2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define ATOM_RATIOS 0x66a
41 #define ATOM_VIDS 0x66b
42 #define ATOM_TURBO_RATIOS 0x66c
43 #define ATOM_TURBO_VIDS 0x66d
46 #include <acpi/processor.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x
, int32_t y
)
58 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
61 static inline int32_t div_fp(s64 x
, s64 y
)
63 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
66 static inline int ceiling_fp(int32_t x
)
71 mask
= (1 << FRAC_BITS
) - 1;
77 static inline u64
mul_ext_fp(u64 x
, u64 y
)
79 return (x
* y
) >> EXT_FRAC_BITS
;
82 static inline u64
div_ext_fp(u64 x
, u64 y
)
84 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
88 * struct sample - Store performance sample
89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
90 * performance during last sample period
91 * @busy_scaled: Scaled busy value which is used to calculate next
92 * P state. This can be different than core_avg_perf
93 * to account for cpu idle period
94 * @aperf: Difference of actual performance frequency clock count
95 * read from APERF MSR between last and current sample
96 * @mperf: Difference of maximum performance frequency clock count
97 * read from MPERF MSR between last and current sample
98 * @tsc: Difference of time stamp counter between last and
100 * @time: Current time from scheduler
102 * This structure is used in the cpudata structure to store performance sample
103 * data for choosing next P State.
106 int32_t core_avg_perf
;
115 * struct pstate_data - Store P state data
116 * @current_pstate: Current requested P state
117 * @min_pstate: Min P state possible for this platform
118 * @max_pstate: Max P state possible for this platform
119 * @max_pstate_physical:This is physical Max P state for a processor
120 * This can be higher than the max_pstate which can
121 * be limited by platform thermal design power limits
122 * @scaling: Scaling factor to convert frequency to cpufreq
124 * @turbo_pstate: Max Turbo P state possible for this platform
126 * Stores the per cpu model P state limits and current P state.
132 int max_pstate_physical
;
138 * struct vid_data - Stores voltage information data
139 * @min: VID data for this platform corresponding to
141 * @max: VID data corresponding to the highest P State.
142 * @turbo: VID data for turbo P state
143 * @ratio: Ratio of (vid max - vid min) /
144 * (max P state - Min P State)
146 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
147 * This data is used in Atom platforms, where in addition to target P state,
148 * the voltage data needs to be specified to select next P State.
158 * struct _pid - Stores PID data
159 * @setpoint: Target set point for busyness or performance
160 * @integral: Storage for accumulated error values
161 * @p_gain: PID proportional gain
162 * @i_gain: PID integral gain
163 * @d_gain: PID derivative gain
164 * @deadband: PID deadband
165 * @last_err: Last error storage for integral part of PID calculation
167 * Stores PID coefficients and last error for PID controller.
180 * struct cpudata - Per CPU instance data storage
181 * @cpu: CPU number for this instance data
182 * @policy: CPUFreq policy value
183 * @update_util: CPUFreq utility callback information
184 * @update_util_set: CPUFreq utility callback is set
185 * @iowait_boost: iowait-related boost fraction
186 * @last_update: Time of the last update.
187 * @pstate: Stores P state limits for this CPU
188 * @vid: Stores VID limits for this CPU
189 * @pid: Stores PID parameters for this CPU
190 * @last_sample_time: Last Sample time
191 * @prev_aperf: Last APERF value read from APERF MSR
192 * @prev_mperf: Last MPERF value read from MPERF MSR
193 * @prev_tsc: Last timestamp counter (TSC) value
194 * @prev_cummulative_iowait: IO Wait time difference from last and
196 * @sample: Storage for storing last Sample data
197 * @acpi_perf_data: Stores ACPI perf information read from _PSS
198 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
200 * This structure stores per CPU instance data for all CPUs.
206 struct update_util_data update_util
;
207 bool update_util_set
;
209 struct pstate_data pstate
;
214 u64 last_sample_time
;
218 u64 prev_cummulative_iowait
;
219 struct sample sample
;
221 struct acpi_processor_performance acpi_perf_data
;
222 bool valid_pss_table
;
224 unsigned int iowait_boost
;
227 static struct cpudata
**all_cpu_data
;
230 * struct pstate_adjust_policy - Stores static PID configuration data
231 * @sample_rate_ms: PID calculation sample rate in ms
232 * @sample_rate_ns: Sample rate calculation in ns
233 * @deadband: PID deadband
234 * @setpoint: PID Setpoint
235 * @p_gain_pct: PID proportional gain
236 * @i_gain_pct: PID integral gain
237 * @d_gain_pct: PID derivative gain
238 * @boost_iowait: Whether or not to use iowait boosting.
240 * Stores per CPU model static PID configuration data.
242 struct pstate_adjust_policy
{
254 * struct pstate_funcs - Per CPU model specific callbacks
255 * @get_max: Callback to get maximum non turbo effective P state
256 * @get_max_physical: Callback to get maximum non turbo physical P state
257 * @get_min: Callback to get minimum P state
258 * @get_turbo: Callback to get turbo P state
259 * @get_scaling: Callback to get frequency scaling factor
260 * @get_val: Callback to convert P state to actual MSR write value
261 * @get_vid: Callback to get VID data for Atom platforms
262 * @get_target_pstate: Callback to a function to calculate next P state to use
264 * Core and Atom CPU models have different way to get P State limits. This
265 * structure is used to store those callbacks.
267 struct pstate_funcs
{
268 int (*get_max
)(void);
269 int (*get_max_physical
)(void);
270 int (*get_min
)(void);
271 int (*get_turbo
)(void);
272 int (*get_scaling
)(void);
273 u64 (*get_val
)(struct cpudata
*, int pstate
);
274 void (*get_vid
)(struct cpudata
*);
275 int32_t (*get_target_pstate
)(struct cpudata
*);
279 * struct cpu_defaults- Per CPU model default config data
280 * @pid_policy: PID config data
281 * @funcs: Callback function data
283 struct cpu_defaults
{
284 struct pstate_adjust_policy pid_policy
;
285 struct pstate_funcs funcs
;
288 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
289 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
291 static struct pstate_adjust_policy pid_params __read_mostly
;
292 static struct pstate_funcs pstate_funcs __read_mostly
;
293 static int hwp_active __read_mostly
;
296 static bool acpi_ppc
;
300 * struct perf_limits - Store user and policy limits
301 * @no_turbo: User requested turbo state from intel_pstate sysfs
302 * @turbo_disabled: Platform turbo status either from msr
303 * MSR_IA32_MISC_ENABLE or when maximum available pstate
304 * matches the maximum turbo pstate
305 * @max_perf_pct: Effective maximum performance limit in percentage, this
306 * is minimum of either limits enforced by cpufreq policy
307 * or limits from user set limits via intel_pstate sysfs
308 * @min_perf_pct: Effective minimum performance limit in percentage, this
309 * is maximum of either limits enforced by cpufreq policy
310 * or limits from user set limits via intel_pstate sysfs
311 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
312 * This value is used to limit max pstate
313 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
314 * This value is used to limit min pstate
315 * @max_policy_pct: The maximum performance in percentage enforced by
316 * cpufreq setpolicy interface
317 * @max_sysfs_pct: The maximum performance in percentage enforced by
318 * intel pstate sysfs interface
319 * @min_policy_pct: The minimum performance in percentage enforced by
320 * cpufreq setpolicy interface
321 * @min_sysfs_pct: The minimum performance in percentage enforced by
322 * intel pstate sysfs interface
324 * Storage for user and policy defined limits.
339 static struct perf_limits performance_limits
= {
343 .max_perf
= int_tofp(1),
345 .min_perf
= int_tofp(1),
346 .max_policy_pct
= 100,
347 .max_sysfs_pct
= 100,
352 static struct perf_limits powersave_limits
= {
356 .max_perf
= int_tofp(1),
359 .max_policy_pct
= 100,
360 .max_sysfs_pct
= 100,
365 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
366 static struct perf_limits
*limits
= &performance_limits
;
368 static struct perf_limits
*limits
= &powersave_limits
;
373 static bool intel_pstate_get_ppc_enable_status(void)
375 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
376 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
382 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
391 if (!intel_pstate_get_ppc_enable_status())
394 cpu
= all_cpu_data
[policy
->cpu
];
396 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
402 * Check if the control value in _PSS is for PERF_CTL MSR, which should
403 * guarantee that the states returned by it map to the states in our
406 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
407 ACPI_ADR_SPACE_FIXED_HARDWARE
)
411 * If there is only one entry _PSS, simply ignore _PSS and continue as
412 * usual without taking _PSS into account
414 if (cpu
->acpi_perf_data
.state_count
< 2)
417 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
418 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
419 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
420 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
421 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
422 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
423 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
427 * The _PSS table doesn't contain whole turbo frequency range.
428 * This just contains +1 MHZ above the max non turbo frequency,
429 * with control value corresponding to max turbo ratio. But
430 * when cpufreq set policy is called, it will call with this
431 * max frequency, which will cause a reduced performance as
432 * this driver uses real max turbo frequency as the max
433 * frequency. So correct this frequency in _PSS table to
434 * correct max turbo frequency based on the turbo state.
435 * Also need to convert to MHz as _PSS freq is in MHz.
437 if (!limits
->turbo_disabled
)
438 cpu
->acpi_perf_data
.states
[0].core_frequency
=
439 policy
->cpuinfo
.max_freq
/ 1000;
440 cpu
->valid_pss_table
= true;
441 pr_debug("_PPC limits will be enforced\n");
446 cpu
->valid_pss_table
= false;
447 acpi_processor_unregister_performance(policy
->cpu
);
450 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
454 cpu
= all_cpu_data
[policy
->cpu
];
455 if (!cpu
->valid_pss_table
)
458 acpi_processor_unregister_performance(policy
->cpu
);
462 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
466 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
471 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
472 int deadband
, int integral
) {
473 pid
->setpoint
= int_tofp(setpoint
);
474 pid
->deadband
= int_tofp(deadband
);
475 pid
->integral
= int_tofp(integral
);
476 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
479 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
481 pid
->p_gain
= div_fp(percent
, 100);
484 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
486 pid
->i_gain
= div_fp(percent
, 100);
489 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
491 pid
->d_gain
= div_fp(percent
, 100);
494 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
497 int32_t pterm
, dterm
, fp_error
;
498 int32_t integral_limit
;
500 fp_error
= pid
->setpoint
- busy
;
502 if (abs(fp_error
) <= pid
->deadband
)
505 pterm
= mul_fp(pid
->p_gain
, fp_error
);
507 pid
->integral
+= fp_error
;
510 * We limit the integral here so that it will never
511 * get higher than 30. This prevents it from becoming
512 * too large an input over long periods of time and allows
513 * it to get factored out sooner.
515 * The value of 30 was chosen through experimentation.
517 integral_limit
= int_tofp(30);
518 if (pid
->integral
> integral_limit
)
519 pid
->integral
= integral_limit
;
520 if (pid
->integral
< -integral_limit
)
521 pid
->integral
= -integral_limit
;
523 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
524 pid
->last_err
= fp_error
;
526 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
527 result
= result
+ (1 << (FRAC_BITS
-1));
528 return (signed int)fp_toint(result
);
531 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
533 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
534 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
535 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
537 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
540 static inline void intel_pstate_reset_all_pid(void)
544 for_each_online_cpu(cpu
) {
545 if (all_cpu_data
[cpu
])
546 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
550 static inline void update_turbo_state(void)
555 cpu
= all_cpu_data
[0];
556 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
557 limits
->turbo_disabled
=
558 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
559 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
562 static void intel_pstate_hwp_set(const struct cpumask
*cpumask
)
564 int min
, hw_min
, max
, hw_max
, cpu
, range
, adj_range
;
567 for_each_cpu(cpu
, cpumask
) {
568 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
569 hw_min
= HWP_LOWEST_PERF(cap
);
570 hw_max
= HWP_HIGHEST_PERF(cap
);
571 range
= hw_max
- hw_min
;
573 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
574 adj_range
= limits
->min_perf_pct
* range
/ 100;
575 min
= hw_min
+ adj_range
;
576 value
&= ~HWP_MIN_PERF(~0L);
577 value
|= HWP_MIN_PERF(min
);
579 adj_range
= limits
->max_perf_pct
* range
/ 100;
580 max
= hw_min
+ adj_range
;
581 if (limits
->no_turbo
) {
582 hw_max
= HWP_GUARANTEED_PERF(cap
);
587 value
&= ~HWP_MAX_PERF(~0L);
588 value
|= HWP_MAX_PERF(max
);
589 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
593 static int intel_pstate_hwp_set_policy(struct cpufreq_policy
*policy
)
596 intel_pstate_hwp_set(policy
->cpus
);
601 static void intel_pstate_hwp_set_online_cpus(void)
604 intel_pstate_hwp_set(cpu_online_mask
);
608 /************************** debugfs begin ************************/
609 static int pid_param_set(void *data
, u64 val
)
612 intel_pstate_reset_all_pid();
616 static int pid_param_get(void *data
, u64
*val
)
621 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
628 static struct pid_param pid_files
[] = {
629 {"sample_rate_ms", &pid_params
.sample_rate_ms
},
630 {"d_gain_pct", &pid_params
.d_gain_pct
},
631 {"i_gain_pct", &pid_params
.i_gain_pct
},
632 {"deadband", &pid_params
.deadband
},
633 {"setpoint", &pid_params
.setpoint
},
634 {"p_gain_pct", &pid_params
.p_gain_pct
},
638 static void __init
intel_pstate_debug_expose_params(void)
640 struct dentry
*debugfs_parent
;
645 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
646 if (IS_ERR_OR_NULL(debugfs_parent
))
648 while (pid_files
[i
].name
) {
649 debugfs_create_file(pid_files
[i
].name
, 0660,
650 debugfs_parent
, pid_files
[i
].value
,
656 /************************** debugfs end ************************/
658 /************************** sysfs begin ************************/
659 #define show_one(file_name, object) \
660 static ssize_t show_##file_name \
661 (struct kobject *kobj, struct attribute *attr, char *buf) \
663 return sprintf(buf, "%u\n", limits->object); \
666 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
667 struct attribute
*attr
, char *buf
)
670 int total
, no_turbo
, turbo_pct
;
673 cpu
= all_cpu_data
[0];
675 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
676 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
677 turbo_fp
= div_fp(no_turbo
, total
);
678 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
679 return sprintf(buf
, "%u\n", turbo_pct
);
682 static ssize_t
show_num_pstates(struct kobject
*kobj
,
683 struct attribute
*attr
, char *buf
)
688 cpu
= all_cpu_data
[0];
689 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
690 return sprintf(buf
, "%u\n", total
);
693 static ssize_t
show_no_turbo(struct kobject
*kobj
,
694 struct attribute
*attr
, char *buf
)
698 update_turbo_state();
699 if (limits
->turbo_disabled
)
700 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
702 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
707 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
708 const char *buf
, size_t count
)
713 ret
= sscanf(buf
, "%u", &input
);
717 update_turbo_state();
718 if (limits
->turbo_disabled
) {
719 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
723 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
726 intel_pstate_hwp_set_online_cpus();
731 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
732 const char *buf
, size_t count
)
737 ret
= sscanf(buf
, "%u", &input
);
741 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
742 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
743 limits
->max_sysfs_pct
);
744 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
745 limits
->max_perf_pct
);
746 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
747 limits
->max_perf_pct
);
748 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
751 intel_pstate_hwp_set_online_cpus();
755 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
756 const char *buf
, size_t count
)
761 ret
= sscanf(buf
, "%u", &input
);
765 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
766 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
767 limits
->min_sysfs_pct
);
768 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
769 limits
->min_perf_pct
);
770 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
771 limits
->min_perf_pct
);
772 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
775 intel_pstate_hwp_set_online_cpus();
779 show_one(max_perf_pct
, max_perf_pct
);
780 show_one(min_perf_pct
, min_perf_pct
);
782 define_one_global_rw(no_turbo
);
783 define_one_global_rw(max_perf_pct
);
784 define_one_global_rw(min_perf_pct
);
785 define_one_global_ro(turbo_pct
);
786 define_one_global_ro(num_pstates
);
788 static struct attribute
*intel_pstate_attributes
[] = {
797 static struct attribute_group intel_pstate_attr_group
= {
798 .attrs
= intel_pstate_attributes
,
801 static void __init
intel_pstate_sysfs_expose_params(void)
803 struct kobject
*intel_pstate_kobject
;
806 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
807 &cpu_subsys
.dev_root
->kobj
);
808 BUG_ON(!intel_pstate_kobject
);
809 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
812 /************************** sysfs end ************************/
814 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
816 /* First disable HWP notification interrupt as we don't process them */
817 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
818 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
820 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
823 static int atom_get_min_pstate(void)
827 rdmsrl(ATOM_RATIOS
, value
);
828 return (value
>> 8) & 0x7F;
831 static int atom_get_max_pstate(void)
835 rdmsrl(ATOM_RATIOS
, value
);
836 return (value
>> 16) & 0x7F;
839 static int atom_get_turbo_pstate(void)
843 rdmsrl(ATOM_TURBO_RATIOS
, value
);
847 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
853 val
= (u64
)pstate
<< 8;
854 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
857 vid_fp
= cpudata
->vid
.min
+ mul_fp(
858 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
861 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
862 vid
= ceiling_fp(vid_fp
);
864 if (pstate
> cpudata
->pstate
.max_pstate
)
865 vid
= cpudata
->vid
.turbo
;
870 static int silvermont_get_scaling(void)
874 /* Defined in Table 35-6 from SDM (Sept 2015) */
875 static int silvermont_freq_table
[] = {
876 83300, 100000, 133300, 116700, 80000};
878 rdmsrl(MSR_FSB_FREQ
, value
);
882 return silvermont_freq_table
[i
];
885 static int airmont_get_scaling(void)
889 /* Defined in Table 35-10 from SDM (Sept 2015) */
890 static int airmont_freq_table
[] = {
891 83300, 100000, 133300, 116700, 80000,
892 93300, 90000, 88900, 87500};
894 rdmsrl(MSR_FSB_FREQ
, value
);
898 return airmont_freq_table
[i
];
901 static void atom_get_vid(struct cpudata
*cpudata
)
905 rdmsrl(ATOM_VIDS
, value
);
906 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
907 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
908 cpudata
->vid
.ratio
= div_fp(
909 cpudata
->vid
.max
- cpudata
->vid
.min
,
910 int_tofp(cpudata
->pstate
.max_pstate
-
911 cpudata
->pstate
.min_pstate
));
913 rdmsrl(ATOM_TURBO_VIDS
, value
);
914 cpudata
->vid
.turbo
= value
& 0x7f;
917 static int core_get_min_pstate(void)
921 rdmsrl(MSR_PLATFORM_INFO
, value
);
922 return (value
>> 40) & 0xFF;
925 static int core_get_max_pstate_physical(void)
929 rdmsrl(MSR_PLATFORM_INFO
, value
);
930 return (value
>> 8) & 0xFF;
933 static int core_get_max_pstate(void)
940 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
941 max_pstate
= (plat_info
>> 8) & 0xFF;
943 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
945 /* Do some sanity checking for safety */
946 if (plat_info
& 0x600000000) {
951 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
955 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x3);
956 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
960 /* For level 1 and 2, bits[23:16] contain the ratio */
964 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
965 if (tdp_ratio
- 1 == tar
) {
967 pr_debug("max_pstate=TAC %x\n", max_pstate
);
978 static int core_get_turbo_pstate(void)
983 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
984 nont
= core_get_max_pstate();
991 static inline int core_get_scaling(void)
996 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1000 val
= (u64
)pstate
<< 8;
1001 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1002 val
|= (u64
)1 << 32;
1007 static int knl_get_turbo_pstate(void)
1012 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1013 nont
= core_get_max_pstate();
1014 ret
= (((value
) >> 8) & 0xFF);
1020 static struct cpu_defaults core_params
= {
1022 .sample_rate_ms
= 10,
1030 .get_max
= core_get_max_pstate
,
1031 .get_max_physical
= core_get_max_pstate_physical
,
1032 .get_min
= core_get_min_pstate
,
1033 .get_turbo
= core_get_turbo_pstate
,
1034 .get_scaling
= core_get_scaling
,
1035 .get_val
= core_get_val
,
1036 .get_target_pstate
= get_target_pstate_use_performance
,
1040 static const struct cpu_defaults silvermont_params
= {
1042 .sample_rate_ms
= 10,
1048 .boost_iowait
= true,
1051 .get_max
= atom_get_max_pstate
,
1052 .get_max_physical
= atom_get_max_pstate
,
1053 .get_min
= atom_get_min_pstate
,
1054 .get_turbo
= atom_get_turbo_pstate
,
1055 .get_val
= atom_get_val
,
1056 .get_scaling
= silvermont_get_scaling
,
1057 .get_vid
= atom_get_vid
,
1058 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1062 static const struct cpu_defaults airmont_params
= {
1064 .sample_rate_ms
= 10,
1070 .boost_iowait
= true,
1073 .get_max
= atom_get_max_pstate
,
1074 .get_max_physical
= atom_get_max_pstate
,
1075 .get_min
= atom_get_min_pstate
,
1076 .get_turbo
= atom_get_turbo_pstate
,
1077 .get_val
= atom_get_val
,
1078 .get_scaling
= airmont_get_scaling
,
1079 .get_vid
= atom_get_vid
,
1080 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1084 static const struct cpu_defaults knl_params
= {
1086 .sample_rate_ms
= 10,
1094 .get_max
= core_get_max_pstate
,
1095 .get_max_physical
= core_get_max_pstate_physical
,
1096 .get_min
= core_get_min_pstate
,
1097 .get_turbo
= knl_get_turbo_pstate
,
1098 .get_scaling
= core_get_scaling
,
1099 .get_val
= core_get_val
,
1100 .get_target_pstate
= get_target_pstate_use_performance
,
1104 static const struct cpu_defaults bxt_params
= {
1106 .sample_rate_ms
= 10,
1112 .boost_iowait
= true,
1115 .get_max
= core_get_max_pstate
,
1116 .get_max_physical
= core_get_max_pstate_physical
,
1117 .get_min
= core_get_min_pstate
,
1118 .get_turbo
= core_get_turbo_pstate
,
1119 .get_scaling
= core_get_scaling
,
1120 .get_val
= core_get_val
,
1121 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1125 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
1127 int max_perf
= cpu
->pstate
.turbo_pstate
;
1131 if (limits
->no_turbo
|| limits
->turbo_disabled
)
1132 max_perf
= cpu
->pstate
.max_pstate
;
1135 * performance can be limited by user through sysfs, by cpufreq
1136 * policy, or by cpu specific default values determined through
1139 max_perf_adj
= fp_toint(max_perf
* limits
->max_perf
);
1140 *max
= clamp_t(int, max_perf_adj
,
1141 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
1143 min_perf
= fp_toint(max_perf
* limits
->min_perf
);
1144 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
1147 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1149 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1150 cpu
->pstate
.current_pstate
= pstate
;
1152 * Generally, there is no guarantee that this code will always run on
1153 * the CPU being updated, so force the register update to run on the
1156 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1157 pstate_funcs
.get_val(cpu
, pstate
));
1160 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1162 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1165 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1167 int min_pstate
, max_pstate
;
1169 update_turbo_state();
1170 intel_pstate_get_min_max(cpu
, &min_pstate
, &max_pstate
);
1171 intel_pstate_set_pstate(cpu
, max_pstate
);
1174 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1176 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1177 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1178 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1179 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1180 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1182 if (pstate_funcs
.get_vid
)
1183 pstate_funcs
.get_vid(cpu
);
1185 intel_pstate_set_min_pstate(cpu
);
1188 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1190 struct sample
*sample
= &cpu
->sample
;
1192 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1195 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1198 unsigned long flags
;
1201 local_irq_save(flags
);
1202 rdmsrl(MSR_IA32_APERF
, aperf
);
1203 rdmsrl(MSR_IA32_MPERF
, mperf
);
1205 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1206 local_irq_restore(flags
);
1209 local_irq_restore(flags
);
1211 cpu
->last_sample_time
= cpu
->sample
.time
;
1212 cpu
->sample
.time
= time
;
1213 cpu
->sample
.aperf
= aperf
;
1214 cpu
->sample
.mperf
= mperf
;
1215 cpu
->sample
.tsc
= tsc
;
1216 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1217 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1218 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1220 cpu
->prev_aperf
= aperf
;
1221 cpu
->prev_mperf
= mperf
;
1222 cpu
->prev_tsc
= tsc
;
1224 * First time this function is invoked in a given cycle, all of the
1225 * previous sample data fields are equal to zero or stale and they must
1226 * be populated with meaningful numbers for things to work, so assume
1227 * that sample.time will always be reset before setting the utilization
1228 * update hook and make the caller skip the sample then.
1230 return !!cpu
->last_sample_time
;
1233 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1235 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1236 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1239 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1241 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1242 cpu
->sample
.core_avg_perf
);
1245 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1247 struct sample
*sample
= &cpu
->sample
;
1248 int32_t busy_frac
, boost
;
1249 int target
, avg_pstate
;
1251 busy_frac
= div_fp(sample
->mperf
, sample
->tsc
);
1253 boost
= cpu
->iowait_boost
;
1254 cpu
->iowait_boost
>>= 1;
1256 if (busy_frac
< boost
)
1259 sample
->busy_scaled
= busy_frac
* 100;
1261 target
= limits
->no_turbo
|| limits
->turbo_disabled
?
1262 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1263 target
+= target
>> 2;
1264 target
= mul_fp(target
, busy_frac
);
1265 if (target
< cpu
->pstate
.min_pstate
)
1266 target
= cpu
->pstate
.min_pstate
;
1269 * If the average P-state during the previous cycle was higher than the
1270 * current target, add 50% of the difference to the target to reduce
1271 * possible performance oscillations and offset possible performance
1272 * loss related to moving the workload from one CPU to another within
1275 avg_pstate
= get_avg_pstate(cpu
);
1276 if (avg_pstate
> target
)
1277 target
+= (avg_pstate
- target
) >> 1;
1282 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1284 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1288 * perf_scaled is the ratio of the average P-state during the last
1289 * sampling period to the P-state requested last time (in percent).
1291 * That measures the system's response to the previous P-state
1294 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1295 current_pstate
= cpu
->pstate
.current_pstate
;
1296 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1297 div_fp(100 * max_pstate
, current_pstate
));
1300 * Since our utilization update callback will not run unless we are
1301 * in C0, check if the actual elapsed time is significantly greater (3x)
1302 * than our sample interval. If it is, then we were idle for a long
1303 * enough period of time to adjust our performance metric.
1305 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1306 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1307 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1308 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1310 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1311 if (sample_ratio
< int_tofp(1))
1315 cpu
->sample
.busy_scaled
= perf_scaled
;
1316 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1319 static inline void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1321 int max_perf
, min_perf
;
1323 update_turbo_state();
1325 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1326 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1327 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1328 if (pstate
== cpu
->pstate
.current_pstate
)
1331 cpu
->pstate
.current_pstate
= pstate
;
1332 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1335 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1337 int from
, target_pstate
;
1338 struct sample
*sample
;
1340 from
= cpu
->pstate
.current_pstate
;
1342 target_pstate
= cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
?
1343 cpu
->pstate
.turbo_pstate
: pstate_funcs
.get_target_pstate(cpu
);
1345 intel_pstate_update_pstate(cpu
, target_pstate
);
1347 sample
= &cpu
->sample
;
1348 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1349 fp_toint(sample
->busy_scaled
),
1351 cpu
->pstate
.current_pstate
,
1355 get_avg_frequency(cpu
),
1356 fp_toint(cpu
->iowait_boost
* 100));
1359 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1362 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1365 if (pid_params
.boost_iowait
) {
1366 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1367 cpu
->iowait_boost
= int_tofp(1);
1368 } else if (cpu
->iowait_boost
) {
1369 /* Clear iowait_boost if the CPU may have been idle. */
1370 delta_ns
= time
- cpu
->last_update
;
1371 if (delta_ns
> TICK_NSEC
)
1372 cpu
->iowait_boost
= 0;
1374 cpu
->last_update
= time
;
1377 delta_ns
= time
- cpu
->sample
.time
;
1378 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1379 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1382 intel_pstate_calc_avg_perf(cpu
);
1384 intel_pstate_adjust_busy_pstate(cpu
);
1389 #define ICPU(model, policy) \
1390 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1391 (unsigned long)&policy }
1393 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1394 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_params
),
1395 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_params
),
1396 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_params
),
1397 ICPU(INTEL_FAM6_IVYBRIDGE
, core_params
),
1398 ICPU(INTEL_FAM6_HASWELL_CORE
, core_params
),
1399 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_params
),
1400 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_params
),
1401 ICPU(INTEL_FAM6_HASWELL_X
, core_params
),
1402 ICPU(INTEL_FAM6_HASWELL_ULT
, core_params
),
1403 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_params
),
1404 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_params
),
1405 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_params
),
1406 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_params
),
1407 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1408 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_params
),
1409 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1410 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_params
),
1411 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_params
),
1414 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1416 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1417 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1418 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1419 ICPU(INTEL_FAM6_SKYLAKE_X
, core_params
),
1423 static int intel_pstate_init_cpu(unsigned int cpunum
)
1425 struct cpudata
*cpu
;
1427 if (!all_cpu_data
[cpunum
])
1428 all_cpu_data
[cpunum
] = kzalloc(sizeof(struct cpudata
),
1430 if (!all_cpu_data
[cpunum
])
1433 cpu
= all_cpu_data
[cpunum
];
1438 intel_pstate_hwp_enable(cpu
);
1439 pid_params
.sample_rate_ms
= 50;
1440 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
1443 intel_pstate_get_cpu_pstates(cpu
);
1445 intel_pstate_busy_pid_reset(cpu
);
1447 pr_debug("controlling: cpu %d\n", cpunum
);
1452 static unsigned int intel_pstate_get(unsigned int cpu_num
)
1454 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1456 return cpu
? get_avg_frequency(cpu
) : 0;
1459 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
1461 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1463 if (cpu
->update_util_set
)
1466 /* Prevent intel_pstate_update_util() from using stale data. */
1467 cpu
->sample
.time
= 0;
1468 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
1469 intel_pstate_update_util
);
1470 cpu
->update_util_set
= true;
1473 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
1475 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
1477 if (!cpu_data
->update_util_set
)
1480 cpufreq_remove_update_util_hook(cpu
);
1481 cpu_data
->update_util_set
= false;
1482 synchronize_sched();
1485 static void intel_pstate_set_performance_limits(struct perf_limits
*limits
)
1487 limits
->no_turbo
= 0;
1488 limits
->turbo_disabled
= 0;
1489 limits
->max_perf_pct
= 100;
1490 limits
->max_perf
= int_tofp(1);
1491 limits
->min_perf_pct
= 100;
1492 limits
->min_perf
= int_tofp(1);
1493 limits
->max_policy_pct
= 100;
1494 limits
->max_sysfs_pct
= 100;
1495 limits
->min_policy_pct
= 0;
1496 limits
->min_sysfs_pct
= 0;
1499 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
1501 struct cpudata
*cpu
;
1503 if (!policy
->cpuinfo
.max_freq
)
1506 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1507 policy
->cpuinfo
.max_freq
, policy
->max
);
1509 cpu
= all_cpu_data
[policy
->cpu
];
1510 cpu
->policy
= policy
->policy
;
1512 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
1513 policy
->max
< policy
->cpuinfo
.max_freq
&&
1514 policy
->max
> cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
) {
1515 pr_debug("policy->max > max non turbo frequency\n");
1516 policy
->max
= policy
->cpuinfo
.max_freq
;
1519 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
1520 limits
= &performance_limits
;
1521 if (policy
->max
>= policy
->cpuinfo
.max_freq
) {
1522 pr_debug("set performance\n");
1523 intel_pstate_set_performance_limits(limits
);
1527 pr_debug("set powersave\n");
1528 limits
= &powersave_limits
;
1531 limits
->min_policy_pct
= (policy
->min
* 100) / policy
->cpuinfo
.max_freq
;
1532 limits
->min_policy_pct
= clamp_t(int, limits
->min_policy_pct
, 0 , 100);
1533 limits
->max_policy_pct
= DIV_ROUND_UP(policy
->max
* 100,
1534 policy
->cpuinfo
.max_freq
);
1535 limits
->max_policy_pct
= clamp_t(int, limits
->max_policy_pct
, 0 , 100);
1537 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1538 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1539 limits
->min_sysfs_pct
);
1540 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1541 limits
->min_perf_pct
);
1542 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1543 limits
->max_sysfs_pct
);
1544 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1545 limits
->max_perf_pct
);
1547 /* Make sure min_perf_pct <= max_perf_pct */
1548 limits
->min_perf_pct
= min(limits
->max_perf_pct
, limits
->min_perf_pct
);
1550 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
1551 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
1552 limits
->max_perf
= round_up(limits
->max_perf
, FRAC_BITS
);
1555 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
1557 * NOHZ_FULL CPUs need this as the governor callback may not
1558 * be invoked on them.
1560 intel_pstate_clear_update_util_hook(policy
->cpu
);
1561 intel_pstate_max_within_limits(cpu
);
1564 intel_pstate_set_update_util_hook(policy
->cpu
);
1566 intel_pstate_hwp_set_policy(policy
);
1571 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
1573 cpufreq_verify_within_cpu_limits(policy
);
1575 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
1576 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
1582 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
1584 int cpu_num
= policy
->cpu
;
1585 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1587 pr_debug("CPU %d exiting\n", cpu_num
);
1589 intel_pstate_clear_update_util_hook(cpu_num
);
1594 intel_pstate_set_min_pstate(cpu
);
1597 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
1599 struct cpudata
*cpu
;
1602 rc
= intel_pstate_init_cpu(policy
->cpu
);
1606 cpu
= all_cpu_data
[policy
->cpu
];
1608 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
1609 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
1611 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
1613 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1614 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1616 /* cpuinfo and default policy values */
1617 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1618 update_turbo_state();
1619 policy
->cpuinfo
.max_freq
= limits
->turbo_disabled
?
1620 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1621 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
1623 intel_pstate_init_acpi_perf_limits(policy
);
1624 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
1625 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
1630 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
1632 intel_pstate_exit_perf_limits(policy
);
1637 static struct cpufreq_driver intel_pstate_driver
= {
1638 .flags
= CPUFREQ_CONST_LOOPS
,
1639 .verify
= intel_pstate_verify_policy
,
1640 .setpolicy
= intel_pstate_set_policy
,
1641 .resume
= intel_pstate_hwp_set_policy
,
1642 .get
= intel_pstate_get
,
1643 .init
= intel_pstate_cpu_init
,
1644 .exit
= intel_pstate_cpu_exit
,
1645 .stop_cpu
= intel_pstate_stop_cpu
,
1646 .name
= "intel_pstate",
1649 static int no_load __initdata
;
1650 static int no_hwp __initdata
;
1651 static int hwp_only __initdata
;
1652 static unsigned int force_load __initdata
;
1654 static int __init
intel_pstate_msrs_not_valid(void)
1656 if (!pstate_funcs
.get_max() ||
1657 !pstate_funcs
.get_min() ||
1658 !pstate_funcs
.get_turbo())
1664 static void __init
copy_pid_params(struct pstate_adjust_policy
*policy
)
1666 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
1667 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
1668 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
1669 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
1670 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
1671 pid_params
.deadband
= policy
->deadband
;
1672 pid_params
.setpoint
= policy
->setpoint
;
1675 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
1677 pstate_funcs
.get_max
= funcs
->get_max
;
1678 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
1679 pstate_funcs
.get_min
= funcs
->get_min
;
1680 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
1681 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
1682 pstate_funcs
.get_val
= funcs
->get_val
;
1683 pstate_funcs
.get_vid
= funcs
->get_vid
;
1684 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
1690 static bool __init
intel_pstate_no_acpi_pss(void)
1694 for_each_possible_cpu(i
) {
1696 union acpi_object
*pss
;
1697 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1698 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1703 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
1704 if (ACPI_FAILURE(status
))
1707 pss
= buffer
.pointer
;
1708 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
1719 static bool __init
intel_pstate_has_acpi_ppc(void)
1723 for_each_possible_cpu(i
) {
1724 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1728 if (acpi_has_method(pr
->handle
, "_PPC"))
1739 struct hw_vendor_info
{
1741 char oem_id
[ACPI_OEM_ID_SIZE
];
1742 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
1746 /* Hardware vendor-specific info that has its own power management modes */
1747 static struct hw_vendor_info vendor_info
[] __initdata
= {
1748 {1, "HP ", "ProLiant", PSS
},
1749 {1, "ORACLE", "X4-2 ", PPC
},
1750 {1, "ORACLE", "X4-2L ", PPC
},
1751 {1, "ORACLE", "X4-2B ", PPC
},
1752 {1, "ORACLE", "X3-2 ", PPC
},
1753 {1, "ORACLE", "X3-2L ", PPC
},
1754 {1, "ORACLE", "X3-2B ", PPC
},
1755 {1, "ORACLE", "X4470M2 ", PPC
},
1756 {1, "ORACLE", "X4270M3 ", PPC
},
1757 {1, "ORACLE", "X4270M2 ", PPC
},
1758 {1, "ORACLE", "X4170M2 ", PPC
},
1759 {1, "ORACLE", "X4170 M3", PPC
},
1760 {1, "ORACLE", "X4275 M3", PPC
},
1761 {1, "ORACLE", "X6-2 ", PPC
},
1762 {1, "ORACLE", "Sudbury ", PPC
},
1766 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
1768 struct acpi_table_header hdr
;
1769 struct hw_vendor_info
*v_info
;
1770 const struct x86_cpu_id
*id
;
1773 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
1775 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
1776 if ( misc_pwr
& (1 << 8))
1780 if (acpi_disabled
||
1781 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
1784 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
1785 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
1786 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
1787 ACPI_OEM_TABLE_ID_SIZE
))
1788 switch (v_info
->oem_pwr_table
) {
1790 return intel_pstate_no_acpi_pss();
1792 return intel_pstate_has_acpi_ppc() &&
1799 #else /* CONFIG_ACPI not enabled */
1800 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1801 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1802 #endif /* CONFIG_ACPI */
1804 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
1805 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
1809 static int __init
intel_pstate_init(void)
1812 const struct x86_cpu_id
*id
;
1813 struct cpu_defaults
*cpu_def
;
1818 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
1819 copy_cpu_funcs(&core_params
.funcs
);
1821 goto hwp_cpu_matched
;
1824 id
= x86_match_cpu(intel_pstate_cpu_ids
);
1828 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
1830 copy_pid_params(&cpu_def
->pid_policy
);
1831 copy_cpu_funcs(&cpu_def
->funcs
);
1833 if (intel_pstate_msrs_not_valid())
1838 * The Intel pstate driver will be ignored if the platform
1839 * firmware has its own power management modes.
1841 if (intel_pstate_platform_pwr_mgmt_exists())
1844 pr_info("Intel P-state driver initializing\n");
1846 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
1850 if (!hwp_active
&& hwp_only
)
1853 rc
= cpufreq_register_driver(&intel_pstate_driver
);
1857 intel_pstate_debug_expose_params();
1858 intel_pstate_sysfs_expose_params();
1861 pr_info("HWP enabled\n");
1866 for_each_online_cpu(cpu
) {
1867 if (all_cpu_data
[cpu
]) {
1868 intel_pstate_clear_update_util_hook(cpu
);
1869 kfree(all_cpu_data
[cpu
]);
1874 vfree(all_cpu_data
);
1877 device_initcall(intel_pstate_init
);
1879 static int __init
intel_pstate_setup(char *str
)
1884 if (!strcmp(str
, "disable"))
1886 if (!strcmp(str
, "no_hwp")) {
1887 pr_info("HWP disabled\n");
1890 if (!strcmp(str
, "force"))
1892 if (!strcmp(str
, "hwp_only"))
1896 if (!strcmp(str
, "support_acpi_ppc"))
1902 early_param("intel_pstate", intel_pstate_setup
);
1904 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1905 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1906 MODULE_LICENSE("GPL");