2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x
, int32_t y
)
58 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
61 static inline int32_t div_fp(s64 x
, s64 y
)
63 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
66 static inline int ceiling_fp(int32_t x
)
71 mask
= (1 << FRAC_BITS
) - 1;
77 static inline u64
mul_ext_fp(u64 x
, u64 y
)
79 return (x
* y
) >> EXT_FRAC_BITS
;
82 static inline u64
div_ext_fp(u64 x
, u64 y
)
84 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
87 static inline int32_t percent_ext_fp(int percent
)
89 return div_ext_fp(percent
, 100);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf
;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @scaling: Scaling factor to convert frequency to cpufreq
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical
;
142 unsigned int max_freq
;
143 unsigned int turbo_freq
;
147 * struct vid_data - Stores voltage information data
148 * @min: VID data for this platform corresponding to
150 * @max: VID data corresponding to the highest P State.
151 * @turbo: VID data for turbo P state
152 * @ratio: Ratio of (vid max - vid min) /
153 * (max P state - Min P State)
155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156 * This data is used in Atom platforms, where in addition to target P state,
157 * the voltage data needs to be specified to select next P State.
167 * struct _pid - Stores PID data
168 * @setpoint: Target set point for busyness or performance
169 * @integral: Storage for accumulated error values
170 * @p_gain: PID proportional gain
171 * @i_gain: PID integral gain
172 * @d_gain: PID derivative gain
173 * @deadband: PID deadband
174 * @last_err: Last error storage for integral part of PID calculation
176 * Stores PID coefficients and last error for PID controller.
189 * struct perf_limits - Store user and policy limits
190 * @no_turbo: User requested turbo state from intel_pstate sysfs
191 * @turbo_disabled: Platform turbo status either from msr
192 * MSR_IA32_MISC_ENABLE or when maximum available pstate
193 * matches the maximum turbo pstate
194 * @max_perf_pct: Effective maximum performance limit in percentage, this
195 * is minimum of either limits enforced by cpufreq policy
196 * or limits from user set limits via intel_pstate sysfs
197 * @min_perf_pct: Effective minimum performance limit in percentage, this
198 * is maximum of either limits enforced by cpufreq policy
199 * or limits from user set limits via intel_pstate sysfs
200 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
201 * This value is used to limit max pstate
202 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
203 * This value is used to limit min pstate
204 * @max_policy_pct: The maximum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @max_sysfs_pct: The maximum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
209 * @min_policy_pct: The minimum performance in percentage enforced by
210 * cpufreq setpolicy interface
211 * @min_sysfs_pct: The minimum performance in percentage enforced by
212 * intel pstate sysfs interface, unused when per cpu
213 * controls are enforced
215 * Storage for user and policy defined limits.
231 * struct cpudata - Per CPU instance data storage
232 * @cpu: CPU number for this instance data
233 * @policy: CPUFreq policy value
234 * @update_util: CPUFreq utility callback information
235 * @update_util_set: CPUFreq utility callback is set
236 * @iowait_boost: iowait-related boost fraction
237 * @last_update: Time of the last update.
238 * @pstate: Stores P state limits for this CPU
239 * @vid: Stores VID limits for this CPU
240 * @pid: Stores PID parameters for this CPU
241 * @last_sample_time: Last Sample time
242 * @prev_aperf: Last APERF value read from APERF MSR
243 * @prev_mperf: Last MPERF value read from MPERF MSR
244 * @prev_tsc: Last timestamp counter (TSC) value
245 * @prev_cummulative_iowait: IO Wait time difference from last and
247 * @sample: Storage for storing last Sample data
248 * @perf_limits: Pointer to perf_limit unique to this CPU
249 * Not all field in the structure are applicable
250 * when per cpu controls are enforced
251 * @acpi_perf_data: Stores ACPI perf information read from _PSS
252 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
253 * @epp_powersave: Last saved HWP energy performance preference
254 * (EPP) or energy performance bias (EPB),
255 * when policy switched to performance
256 * @epp_policy: Last saved policy used to set EPP/EPB
257 * @epp_default: Power on default HWP energy performance
259 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
262 * This structure stores per CPU instance data for all CPUs.
268 struct update_util_data update_util
;
269 bool update_util_set
;
271 struct pstate_data pstate
;
276 u64 last_sample_time
;
280 u64 prev_cummulative_iowait
;
281 struct sample sample
;
282 struct perf_limits
*perf_limits
;
284 struct acpi_processor_performance acpi_perf_data
;
285 bool valid_pss_table
;
287 unsigned int iowait_boost
;
294 static struct cpudata
**all_cpu_data
;
297 * struct pstate_adjust_policy - Stores static PID configuration data
298 * @sample_rate_ms: PID calculation sample rate in ms
299 * @sample_rate_ns: Sample rate calculation in ns
300 * @deadband: PID deadband
301 * @setpoint: PID Setpoint
302 * @p_gain_pct: PID proportional gain
303 * @i_gain_pct: PID integral gain
304 * @d_gain_pct: PID derivative gain
306 * Stores per CPU model static PID configuration data.
308 struct pstate_adjust_policy
{
319 * struct pstate_funcs - Per CPU model specific callbacks
320 * @get_max: Callback to get maximum non turbo effective P state
321 * @get_max_physical: Callback to get maximum non turbo physical P state
322 * @get_min: Callback to get minimum P state
323 * @get_turbo: Callback to get turbo P state
324 * @get_scaling: Callback to get frequency scaling factor
325 * @get_val: Callback to convert P state to actual MSR write value
326 * @get_vid: Callback to get VID data for Atom platforms
327 * @get_target_pstate: Callback to a function to calculate next P state to use
329 * Core and Atom CPU models have different way to get P State limits. This
330 * structure is used to store those callbacks.
332 struct pstate_funcs
{
333 int (*get_max
)(void);
334 int (*get_max_physical
)(void);
335 int (*get_min
)(void);
336 int (*get_turbo
)(void);
337 int (*get_scaling
)(void);
338 u64 (*get_val
)(struct cpudata
*, int pstate
);
339 void (*get_vid
)(struct cpudata
*);
340 int32_t (*get_target_pstate
)(struct cpudata
*);
344 * struct cpu_defaults- Per CPU model default config data
345 * @pid_policy: PID config data
346 * @funcs: Callback function data
348 struct cpu_defaults
{
349 struct pstate_adjust_policy pid_policy
;
350 struct pstate_funcs funcs
;
353 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
356 static struct pstate_adjust_policy pid_params __read_mostly
;
357 static struct pstate_funcs pstate_funcs __read_mostly
;
358 static int hwp_active __read_mostly
;
359 static bool per_cpu_limits __read_mostly
;
361 static bool driver_registered __read_mostly
;
364 static bool acpi_ppc
;
367 static struct perf_limits performance_limits
;
368 static struct perf_limits powersave_limits
;
369 static struct perf_limits
*limits
;
371 static void intel_pstate_init_limits(struct perf_limits
*limits
)
373 memset(limits
, 0, sizeof(*limits
));
374 limits
->max_perf_pct
= 100;
375 limits
->max_perf
= int_ext_tofp(1);
376 limits
->max_policy_pct
= 100;
377 limits
->max_sysfs_pct
= 100;
380 static void intel_pstate_set_performance_limits(struct perf_limits
*limits
)
382 intel_pstate_init_limits(limits
);
383 limits
->min_perf_pct
= 100;
384 limits
->min_perf
= int_ext_tofp(1);
385 limits
->min_sysfs_pct
= 100;
388 static DEFINE_MUTEX(intel_pstate_driver_lock
);
389 static DEFINE_MUTEX(intel_pstate_limits_lock
);
393 static bool intel_pstate_get_ppc_enable_status(void)
395 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
396 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
402 #ifdef CONFIG_ACPI_CPPC_LIB
404 /* The work item is needed to avoid CPU hotplug locking issues */
405 static void intel_pstste_sched_itmt_work_fn(struct work_struct
*work
)
407 sched_set_itmt_support();
410 static DECLARE_WORK(sched_itmt_work
, intel_pstste_sched_itmt_work_fn
);
412 static void intel_pstate_set_itmt_prio(int cpu
)
414 struct cppc_perf_caps cppc_perf
;
415 static u32 max_highest_perf
= 0, min_highest_perf
= U32_MAX
;
418 ret
= cppc_get_perf_caps(cpu
, &cppc_perf
);
423 * The priorities can be set regardless of whether or not
424 * sched_set_itmt_support(true) has been called and it is valid to
425 * update them at any time after it has been called.
427 sched_set_itmt_core_prio(cppc_perf
.highest_perf
, cpu
);
429 if (max_highest_perf
<= min_highest_perf
) {
430 if (cppc_perf
.highest_perf
> max_highest_perf
)
431 max_highest_perf
= cppc_perf
.highest_perf
;
433 if (cppc_perf
.highest_perf
< min_highest_perf
)
434 min_highest_perf
= cppc_perf
.highest_perf
;
436 if (max_highest_perf
> min_highest_perf
) {
438 * This code can be run during CPU online under the
439 * CPU hotplug locks, so sched_set_itmt_support()
440 * cannot be called from here. Queue up a work item
443 schedule_work(&sched_itmt_work
);
448 static void intel_pstate_set_itmt_prio(int cpu
)
453 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
460 intel_pstate_set_itmt_prio(policy
->cpu
);
464 if (!intel_pstate_get_ppc_enable_status())
467 cpu
= all_cpu_data
[policy
->cpu
];
469 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
475 * Check if the control value in _PSS is for PERF_CTL MSR, which should
476 * guarantee that the states returned by it map to the states in our
479 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
480 ACPI_ADR_SPACE_FIXED_HARDWARE
)
484 * If there is only one entry _PSS, simply ignore _PSS and continue as
485 * usual without taking _PSS into account
487 if (cpu
->acpi_perf_data
.state_count
< 2)
490 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
491 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
492 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
493 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
494 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
495 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
496 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
500 * The _PSS table doesn't contain whole turbo frequency range.
501 * This just contains +1 MHZ above the max non turbo frequency,
502 * with control value corresponding to max turbo ratio. But
503 * when cpufreq set policy is called, it will call with this
504 * max frequency, which will cause a reduced performance as
505 * this driver uses real max turbo frequency as the max
506 * frequency. So correct this frequency in _PSS table to
507 * correct max turbo frequency based on the turbo state.
508 * Also need to convert to MHz as _PSS freq is in MHz.
510 if (!limits
->turbo_disabled
)
511 cpu
->acpi_perf_data
.states
[0].core_frequency
=
512 policy
->cpuinfo
.max_freq
/ 1000;
513 cpu
->valid_pss_table
= true;
514 pr_debug("_PPC limits will be enforced\n");
519 cpu
->valid_pss_table
= false;
520 acpi_processor_unregister_performance(policy
->cpu
);
523 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
527 cpu
= all_cpu_data
[policy
->cpu
];
528 if (!cpu
->valid_pss_table
)
531 acpi_processor_unregister_performance(policy
->cpu
);
534 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
538 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
543 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
544 int deadband
, int integral
) {
545 pid
->setpoint
= int_tofp(setpoint
);
546 pid
->deadband
= int_tofp(deadband
);
547 pid
->integral
= int_tofp(integral
);
548 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
551 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
553 pid
->p_gain
= div_fp(percent
, 100);
556 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
558 pid
->i_gain
= div_fp(percent
, 100);
561 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
563 pid
->d_gain
= div_fp(percent
, 100);
566 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
569 int32_t pterm
, dterm
, fp_error
;
570 int32_t integral_limit
;
572 fp_error
= pid
->setpoint
- busy
;
574 if (abs(fp_error
) <= pid
->deadband
)
577 pterm
= mul_fp(pid
->p_gain
, fp_error
);
579 pid
->integral
+= fp_error
;
582 * We limit the integral here so that it will never
583 * get higher than 30. This prevents it from becoming
584 * too large an input over long periods of time and allows
585 * it to get factored out sooner.
587 * The value of 30 was chosen through experimentation.
589 integral_limit
= int_tofp(30);
590 if (pid
->integral
> integral_limit
)
591 pid
->integral
= integral_limit
;
592 if (pid
->integral
< -integral_limit
)
593 pid
->integral
= -integral_limit
;
595 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
596 pid
->last_err
= fp_error
;
598 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
599 result
= result
+ (1 << (FRAC_BITS
-1));
600 return (signed int)fp_toint(result
);
603 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
605 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
606 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
607 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
609 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
612 static inline void intel_pstate_reset_all_pid(void)
616 for_each_online_cpu(cpu
) {
617 if (all_cpu_data
[cpu
])
618 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
622 static inline void update_turbo_state(void)
627 cpu
= all_cpu_data
[0];
628 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
629 limits
->turbo_disabled
=
630 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
631 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
634 static s16
intel_pstate_get_epb(struct cpudata
*cpu_data
)
639 if (!static_cpu_has(X86_FEATURE_EPB
))
642 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
646 return (s16
)(epb
& 0x0f);
649 static s16
intel_pstate_get_epp(struct cpudata
*cpu_data
, u64 hwp_req_data
)
653 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
655 * When hwp_req_data is 0, means that caller didn't read
656 * MSR_HWP_REQUEST, so need to read and get EPP.
659 epp
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
,
664 epp
= (hwp_req_data
>> 24) & 0xff;
666 /* When there is no EPP present, HWP uses EPB settings */
667 epp
= intel_pstate_get_epb(cpu_data
);
673 static int intel_pstate_set_epb(int cpu
, s16 pref
)
678 if (!static_cpu_has(X86_FEATURE_EPB
))
681 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
685 epb
= (epb
& ~0x0f) | pref
;
686 wrmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, epb
);
692 * EPP/EPB display strings corresponding to EPP index in the
693 * energy_perf_strings[]
695 *-------------------------------------
698 * 2 balance_performance
702 static const char * const energy_perf_strings
[] = {
705 "balance_performance",
711 static int intel_pstate_get_energy_pref_index(struct cpudata
*cpu_data
)
716 epp
= intel_pstate_get_epp(cpu_data
, 0);
720 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
723 * 0x00-0x3F : Performance
724 * 0x40-0x7F : Balance performance
725 * 0x80-0xBF : Balance power
727 * The EPP is a 8 bit value, but our ranges restrict the
728 * value which can be set. Here only using top two bits
731 index
= (epp
>> 6) + 1;
732 } else if (static_cpu_has(X86_FEATURE_EPB
)) {
735 * 0x00-0x03 : Performance
736 * 0x04-0x07 : Balance performance
737 * 0x08-0x0B : Balance power
739 * The EPB is a 4 bit value, but our ranges restrict the
740 * value which can be set. Here only using top two bits
743 index
= (epp
>> 2) + 1;
749 static int intel_pstate_set_energy_pref_index(struct cpudata
*cpu_data
,
756 epp
= cpu_data
->epp_default
;
758 mutex_lock(&intel_pstate_limits_lock
);
760 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
763 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, &value
);
767 value
&= ~GENMASK_ULL(31, 24);
770 * If epp is not default, convert from index into
771 * energy_perf_strings to epp value, by shifting 6
772 * bits left to use only top two bits in epp.
773 * The resultant epp need to shifted by 24 bits to
774 * epp position in MSR_HWP_REQUEST.
777 epp
= (pref_index
- 1) << 6;
779 value
|= (u64
)epp
<< 24;
780 ret
= wrmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, value
);
783 epp
= (pref_index
- 1) << 2;
784 ret
= intel_pstate_set_epb(cpu_data
->cpu
, epp
);
787 mutex_unlock(&intel_pstate_limits_lock
);
792 static ssize_t
show_energy_performance_available_preferences(
793 struct cpufreq_policy
*policy
, char *buf
)
798 while (energy_perf_strings
[i
] != NULL
)
799 ret
+= sprintf(&buf
[ret
], "%s ", energy_perf_strings
[i
++]);
801 ret
+= sprintf(&buf
[ret
], "\n");
806 cpufreq_freq_attr_ro(energy_performance_available_preferences
);
808 static ssize_t
store_energy_performance_preference(
809 struct cpufreq_policy
*policy
, const char *buf
, size_t count
)
811 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
812 char str_preference
[21];
815 ret
= sscanf(buf
, "%20s", str_preference
);
819 while (energy_perf_strings
[i
] != NULL
) {
820 if (!strcmp(str_preference
, energy_perf_strings
[i
])) {
821 intel_pstate_set_energy_pref_index(cpu_data
, i
);
830 static ssize_t
show_energy_performance_preference(
831 struct cpufreq_policy
*policy
, char *buf
)
833 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
836 preference
= intel_pstate_get_energy_pref_index(cpu_data
);
840 return sprintf(buf
, "%s\n", energy_perf_strings
[preference
]);
843 cpufreq_freq_attr_rw(energy_performance_preference
);
845 static struct freq_attr
*hwp_cpufreq_attrs
[] = {
846 &energy_performance_preference
,
847 &energy_performance_available_preferences
,
851 static void intel_pstate_hwp_set(struct cpufreq_policy
*policy
)
853 int min
, hw_min
, max
, hw_max
, cpu
;
854 struct perf_limits
*perf_limits
= limits
;
857 for_each_cpu(cpu
, policy
->cpus
) {
858 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
862 perf_limits
= all_cpu_data
[cpu
]->perf_limits
;
864 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
865 hw_min
= HWP_LOWEST_PERF(cap
);
866 if (limits
->no_turbo
)
867 hw_max
= HWP_GUARANTEED_PERF(cap
);
869 hw_max
= HWP_HIGHEST_PERF(cap
);
871 min
= fp_ext_toint(hw_max
* perf_limits
->min_perf
);
873 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
875 value
&= ~HWP_MIN_PERF(~0L);
876 value
|= HWP_MIN_PERF(min
);
878 max
= fp_ext_toint(hw_max
* perf_limits
->max_perf
);
879 value
&= ~HWP_MAX_PERF(~0L);
880 value
|= HWP_MAX_PERF(max
);
882 if (cpu_data
->epp_policy
== cpu_data
->policy
)
885 cpu_data
->epp_policy
= cpu_data
->policy
;
887 if (cpu_data
->epp_saved
>= 0) {
888 epp
= cpu_data
->epp_saved
;
889 cpu_data
->epp_saved
= -EINVAL
;
893 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
894 epp
= intel_pstate_get_epp(cpu_data
, value
);
895 cpu_data
->epp_powersave
= epp
;
896 /* If EPP read was failed, then don't try to write */
903 /* skip setting EPP, when saved value is invalid */
904 if (cpu_data
->epp_powersave
< 0)
908 * No need to restore EPP when it is not zero. This
910 * - Policy is not changed
911 * - user has manually changed
912 * - Error reading EPB
914 epp
= intel_pstate_get_epp(cpu_data
, value
);
918 epp
= cpu_data
->epp_powersave
;
921 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
922 value
&= ~GENMASK_ULL(31, 24);
923 value
|= (u64
)epp
<< 24;
925 intel_pstate_set_epb(cpu
, epp
);
928 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
932 static int intel_pstate_hwp_set_policy(struct cpufreq_policy
*policy
)
935 intel_pstate_hwp_set(policy
);
940 static int intel_pstate_hwp_save_state(struct cpufreq_policy
*policy
)
942 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
947 cpu_data
->epp_saved
= intel_pstate_get_epp(cpu_data
, 0);
952 static int intel_pstate_resume(struct cpufreq_policy
*policy
)
959 mutex_lock(&intel_pstate_limits_lock
);
961 all_cpu_data
[policy
->cpu
]->epp_policy
= 0;
963 ret
= intel_pstate_hwp_set_policy(policy
);
965 mutex_unlock(&intel_pstate_limits_lock
);
970 static void intel_pstate_update_policies(void)
971 __releases(&intel_pstate_limits_lock
)
972 __acquires(&intel_pstate_limits_lock
)
974 struct perf_limits
*saved_limits
= limits
;
977 mutex_unlock(&intel_pstate_limits_lock
);
979 for_each_possible_cpu(cpu
)
980 cpufreq_update_policy(cpu
);
982 mutex_lock(&intel_pstate_limits_lock
);
984 limits
= saved_limits
;
987 /************************** debugfs begin ************************/
988 static int pid_param_set(void *data
, u64 val
)
991 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
992 intel_pstate_reset_all_pid();
996 static int pid_param_get(void *data
, u64
*val
)
1001 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
1003 static struct dentry
*debugfs_parent
;
1008 struct dentry
*dentry
;
1011 static struct pid_param pid_files
[] = {
1012 {"sample_rate_ms", &pid_params
.sample_rate_ms
, },
1013 {"d_gain_pct", &pid_params
.d_gain_pct
, },
1014 {"i_gain_pct", &pid_params
.i_gain_pct
, },
1015 {"deadband", &pid_params
.deadband
, },
1016 {"setpoint", &pid_params
.setpoint
, },
1017 {"p_gain_pct", &pid_params
.p_gain_pct
, },
1021 static void intel_pstate_debug_expose_params(void)
1025 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
1026 if (IS_ERR_OR_NULL(debugfs_parent
))
1029 for (i
= 0; pid_files
[i
].name
; i
++) {
1030 struct dentry
*dentry
;
1032 dentry
= debugfs_create_file(pid_files
[i
].name
, 0660,
1033 debugfs_parent
, pid_files
[i
].value
,
1035 if (!IS_ERR(dentry
))
1036 pid_files
[i
].dentry
= dentry
;
1040 static void intel_pstate_debug_hide_params(void)
1044 if (IS_ERR_OR_NULL(debugfs_parent
))
1047 for (i
= 0; pid_files
[i
].name
; i
++) {
1048 debugfs_remove(pid_files
[i
].dentry
);
1049 pid_files
[i
].dentry
= NULL
;
1052 debugfs_remove(debugfs_parent
);
1053 debugfs_parent
= NULL
;
1056 /************************** debugfs end ************************/
1058 /************************** sysfs begin ************************/
1059 #define show_one(file_name, object) \
1060 static ssize_t show_##file_name \
1061 (struct kobject *kobj, struct attribute *attr, char *buf) \
1063 return sprintf(buf, "%u\n", limits->object); \
1066 static ssize_t
intel_pstate_show_status(char *buf
);
1067 static int intel_pstate_update_status(const char *buf
, size_t size
);
1069 static ssize_t
show_status(struct kobject
*kobj
,
1070 struct attribute
*attr
, char *buf
)
1074 mutex_lock(&intel_pstate_driver_lock
);
1075 ret
= intel_pstate_show_status(buf
);
1076 mutex_unlock(&intel_pstate_driver_lock
);
1081 static ssize_t
store_status(struct kobject
*a
, struct attribute
*b
,
1082 const char *buf
, size_t count
)
1084 char *p
= memchr(buf
, '\n', count
);
1087 mutex_lock(&intel_pstate_driver_lock
);
1088 ret
= intel_pstate_update_status(buf
, p
? p
- buf
: count
);
1089 mutex_unlock(&intel_pstate_driver_lock
);
1091 return ret
< 0 ? ret
: count
;
1094 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
1095 struct attribute
*attr
, char *buf
)
1097 struct cpudata
*cpu
;
1098 int total
, no_turbo
, turbo_pct
;
1101 mutex_lock(&intel_pstate_driver_lock
);
1103 if (!driver_registered
) {
1104 mutex_unlock(&intel_pstate_driver_lock
);
1108 cpu
= all_cpu_data
[0];
1110 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1111 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
1112 turbo_fp
= div_fp(no_turbo
, total
);
1113 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
1115 mutex_unlock(&intel_pstate_driver_lock
);
1117 return sprintf(buf
, "%u\n", turbo_pct
);
1120 static ssize_t
show_num_pstates(struct kobject
*kobj
,
1121 struct attribute
*attr
, char *buf
)
1123 struct cpudata
*cpu
;
1126 mutex_lock(&intel_pstate_driver_lock
);
1128 if (!driver_registered
) {
1129 mutex_unlock(&intel_pstate_driver_lock
);
1133 cpu
= all_cpu_data
[0];
1134 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1136 mutex_unlock(&intel_pstate_driver_lock
);
1138 return sprintf(buf
, "%u\n", total
);
1141 static ssize_t
show_no_turbo(struct kobject
*kobj
,
1142 struct attribute
*attr
, char *buf
)
1146 mutex_lock(&intel_pstate_driver_lock
);
1148 if (!driver_registered
) {
1149 mutex_unlock(&intel_pstate_driver_lock
);
1153 update_turbo_state();
1154 if (limits
->turbo_disabled
)
1155 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
1157 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
1159 mutex_unlock(&intel_pstate_driver_lock
);
1164 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
1165 const char *buf
, size_t count
)
1170 ret
= sscanf(buf
, "%u", &input
);
1174 mutex_lock(&intel_pstate_driver_lock
);
1176 if (!driver_registered
) {
1177 mutex_unlock(&intel_pstate_driver_lock
);
1181 mutex_lock(&intel_pstate_limits_lock
);
1183 update_turbo_state();
1184 if (limits
->turbo_disabled
) {
1185 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1186 mutex_unlock(&intel_pstate_limits_lock
);
1187 mutex_unlock(&intel_pstate_driver_lock
);
1191 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
1193 intel_pstate_update_policies();
1195 mutex_unlock(&intel_pstate_limits_lock
);
1197 mutex_unlock(&intel_pstate_driver_lock
);
1202 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
1203 const char *buf
, size_t count
)
1208 ret
= sscanf(buf
, "%u", &input
);
1212 mutex_lock(&intel_pstate_driver_lock
);
1214 if (!driver_registered
) {
1215 mutex_unlock(&intel_pstate_driver_lock
);
1219 mutex_lock(&intel_pstate_limits_lock
);
1221 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1222 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1223 limits
->max_sysfs_pct
);
1224 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1225 limits
->max_perf_pct
);
1226 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
1227 limits
->max_perf_pct
);
1228 limits
->max_perf
= percent_ext_fp(limits
->max_perf_pct
);
1230 intel_pstate_update_policies();
1232 mutex_unlock(&intel_pstate_limits_lock
);
1234 mutex_unlock(&intel_pstate_driver_lock
);
1239 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
1240 const char *buf
, size_t count
)
1245 ret
= sscanf(buf
, "%u", &input
);
1249 mutex_lock(&intel_pstate_driver_lock
);
1251 if (!driver_registered
) {
1252 mutex_unlock(&intel_pstate_driver_lock
);
1256 mutex_lock(&intel_pstate_limits_lock
);
1258 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1259 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1260 limits
->min_sysfs_pct
);
1261 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1262 limits
->min_perf_pct
);
1263 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
1264 limits
->min_perf_pct
);
1265 limits
->min_perf
= percent_ext_fp(limits
->min_perf_pct
);
1267 intel_pstate_update_policies();
1269 mutex_unlock(&intel_pstate_limits_lock
);
1271 mutex_unlock(&intel_pstate_driver_lock
);
1276 show_one(max_perf_pct
, max_perf_pct
);
1277 show_one(min_perf_pct
, min_perf_pct
);
1279 define_one_global_rw(status
);
1280 define_one_global_rw(no_turbo
);
1281 define_one_global_rw(max_perf_pct
);
1282 define_one_global_rw(min_perf_pct
);
1283 define_one_global_ro(turbo_pct
);
1284 define_one_global_ro(num_pstates
);
1286 static struct attribute
*intel_pstate_attributes
[] = {
1294 static struct attribute_group intel_pstate_attr_group
= {
1295 .attrs
= intel_pstate_attributes
,
1298 static void __init
intel_pstate_sysfs_expose_params(void)
1300 struct kobject
*intel_pstate_kobject
;
1303 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
1304 &cpu_subsys
.dev_root
->kobj
);
1305 if (WARN_ON(!intel_pstate_kobject
))
1308 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
1313 * If per cpu limits are enforced there are no global limits, so
1314 * return without creating max/min_perf_pct attributes
1319 rc
= sysfs_create_file(intel_pstate_kobject
, &max_perf_pct
.attr
);
1322 rc
= sysfs_create_file(intel_pstate_kobject
, &min_perf_pct
.attr
);
1326 /************************** sysfs end ************************/
1328 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
1330 /* First disable HWP notification interrupt as we don't process them */
1331 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
1332 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
1334 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
1335 cpudata
->epp_policy
= 0;
1336 if (cpudata
->epp_default
== -EINVAL
)
1337 cpudata
->epp_default
= intel_pstate_get_epp(cpudata
, 0);
1340 #define MSR_IA32_POWER_CTL_BIT_EE 19
1342 /* Disable energy efficiency optimization */
1343 static void intel_pstate_disable_ee(int cpu
)
1348 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, &power_ctl
);
1352 if (!(power_ctl
& BIT(MSR_IA32_POWER_CTL_BIT_EE
))) {
1353 pr_info("Disabling energy efficiency optimization\n");
1354 power_ctl
|= BIT(MSR_IA32_POWER_CTL_BIT_EE
);
1355 wrmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, power_ctl
);
1359 static int atom_get_min_pstate(void)
1363 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1364 return (value
>> 8) & 0x7F;
1367 static int atom_get_max_pstate(void)
1371 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1372 return (value
>> 16) & 0x7F;
1375 static int atom_get_turbo_pstate(void)
1379 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS
, value
);
1380 return value
& 0x7F;
1383 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
1389 val
= (u64
)pstate
<< 8;
1390 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1391 val
|= (u64
)1 << 32;
1393 vid_fp
= cpudata
->vid
.min
+ mul_fp(
1394 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
1395 cpudata
->vid
.ratio
);
1397 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
1398 vid
= ceiling_fp(vid_fp
);
1400 if (pstate
> cpudata
->pstate
.max_pstate
)
1401 vid
= cpudata
->vid
.turbo
;
1406 static int silvermont_get_scaling(void)
1410 /* Defined in Table 35-6 from SDM (Sept 2015) */
1411 static int silvermont_freq_table
[] = {
1412 83300, 100000, 133300, 116700, 80000};
1414 rdmsrl(MSR_FSB_FREQ
, value
);
1418 return silvermont_freq_table
[i
];
1421 static int airmont_get_scaling(void)
1425 /* Defined in Table 35-10 from SDM (Sept 2015) */
1426 static int airmont_freq_table
[] = {
1427 83300, 100000, 133300, 116700, 80000,
1428 93300, 90000, 88900, 87500};
1430 rdmsrl(MSR_FSB_FREQ
, value
);
1434 return airmont_freq_table
[i
];
1437 static void atom_get_vid(struct cpudata
*cpudata
)
1441 rdmsrl(MSR_ATOM_CORE_VIDS
, value
);
1442 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
1443 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
1444 cpudata
->vid
.ratio
= div_fp(
1445 cpudata
->vid
.max
- cpudata
->vid
.min
,
1446 int_tofp(cpudata
->pstate
.max_pstate
-
1447 cpudata
->pstate
.min_pstate
));
1449 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS
, value
);
1450 cpudata
->vid
.turbo
= value
& 0x7f;
1453 static int core_get_min_pstate(void)
1457 rdmsrl(MSR_PLATFORM_INFO
, value
);
1458 return (value
>> 40) & 0xFF;
1461 static int core_get_max_pstate_physical(void)
1465 rdmsrl(MSR_PLATFORM_INFO
, value
);
1466 return (value
>> 8) & 0xFF;
1469 static int core_get_tdp_ratio(u64 plat_info
)
1471 /* Check how many TDP levels present */
1472 if (plat_info
& 0x600000000) {
1478 /* Get the TDP level (0, 1, 2) to get ratios */
1479 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
1483 /* TDP MSR are continuous starting at 0x648 */
1484 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x03);
1485 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
1489 /* For level 1 and 2, bits[23:16] contain the ratio */
1490 if (tdp_ctrl
& 0x03)
1493 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
1494 pr_debug("tdp_ratio %x\n", (int)tdp_ratio
);
1496 return (int)tdp_ratio
;
1502 static int core_get_max_pstate(void)
1510 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
1511 max_pstate
= (plat_info
>> 8) & 0xFF;
1513 tdp_ratio
= core_get_tdp_ratio(plat_info
);
1518 /* Turbo activation ratio is not used on HWP platforms */
1522 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
1526 /* Do some sanity checking for safety */
1527 tar_levels
= tar
& 0xff;
1528 if (tdp_ratio
- 1 == tar_levels
) {
1529 max_pstate
= tar_levels
;
1530 pr_debug("max_pstate=TAC %x\n", max_pstate
);
1537 static int core_get_turbo_pstate(void)
1542 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1543 nont
= core_get_max_pstate();
1544 ret
= (value
) & 255;
1550 static inline int core_get_scaling(void)
1555 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1559 val
= (u64
)pstate
<< 8;
1560 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1561 val
|= (u64
)1 << 32;
1566 static int knl_get_turbo_pstate(void)
1571 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1572 nont
= core_get_max_pstate();
1573 ret
= (((value
) >> 8) & 0xFF);
1579 static struct cpu_defaults core_params
= {
1581 .sample_rate_ms
= 10,
1589 .get_max
= core_get_max_pstate
,
1590 .get_max_physical
= core_get_max_pstate_physical
,
1591 .get_min
= core_get_min_pstate
,
1592 .get_turbo
= core_get_turbo_pstate
,
1593 .get_scaling
= core_get_scaling
,
1594 .get_val
= core_get_val
,
1595 .get_target_pstate
= get_target_pstate_use_performance
,
1599 static const struct cpu_defaults silvermont_params
= {
1601 .sample_rate_ms
= 10,
1609 .get_max
= atom_get_max_pstate
,
1610 .get_max_physical
= atom_get_max_pstate
,
1611 .get_min
= atom_get_min_pstate
,
1612 .get_turbo
= atom_get_turbo_pstate
,
1613 .get_val
= atom_get_val
,
1614 .get_scaling
= silvermont_get_scaling
,
1615 .get_vid
= atom_get_vid
,
1616 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1620 static const struct cpu_defaults airmont_params
= {
1622 .sample_rate_ms
= 10,
1630 .get_max
= atom_get_max_pstate
,
1631 .get_max_physical
= atom_get_max_pstate
,
1632 .get_min
= atom_get_min_pstate
,
1633 .get_turbo
= atom_get_turbo_pstate
,
1634 .get_val
= atom_get_val
,
1635 .get_scaling
= airmont_get_scaling
,
1636 .get_vid
= atom_get_vid
,
1637 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1641 static const struct cpu_defaults knl_params
= {
1643 .sample_rate_ms
= 10,
1651 .get_max
= core_get_max_pstate
,
1652 .get_max_physical
= core_get_max_pstate_physical
,
1653 .get_min
= core_get_min_pstate
,
1654 .get_turbo
= knl_get_turbo_pstate
,
1655 .get_scaling
= core_get_scaling
,
1656 .get_val
= core_get_val
,
1657 .get_target_pstate
= get_target_pstate_use_performance
,
1661 static const struct cpu_defaults bxt_params
= {
1663 .sample_rate_ms
= 10,
1671 .get_max
= core_get_max_pstate
,
1672 .get_max_physical
= core_get_max_pstate_physical
,
1673 .get_min
= core_get_min_pstate
,
1674 .get_turbo
= core_get_turbo_pstate
,
1675 .get_scaling
= core_get_scaling
,
1676 .get_val
= core_get_val
,
1677 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1681 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
1683 int max_perf
= cpu
->pstate
.turbo_pstate
;
1686 struct perf_limits
*perf_limits
= limits
;
1688 if (limits
->no_turbo
|| limits
->turbo_disabled
)
1689 max_perf
= cpu
->pstate
.max_pstate
;
1692 perf_limits
= cpu
->perf_limits
;
1695 * performance can be limited by user through sysfs, by cpufreq
1696 * policy, or by cpu specific default values determined through
1699 max_perf_adj
= fp_ext_toint(max_perf
* perf_limits
->max_perf
);
1700 *max
= clamp_t(int, max_perf_adj
,
1701 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
1703 min_perf
= fp_ext_toint(max_perf
* perf_limits
->min_perf
);
1704 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
1707 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1709 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1710 cpu
->pstate
.current_pstate
= pstate
;
1712 * Generally, there is no guarantee that this code will always run on
1713 * the CPU being updated, so force the register update to run on the
1716 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1717 pstate_funcs
.get_val(cpu
, pstate
));
1720 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1722 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1725 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1727 int min_pstate
, max_pstate
;
1729 update_turbo_state();
1730 intel_pstate_get_min_max(cpu
, &min_pstate
, &max_pstate
);
1731 intel_pstate_set_pstate(cpu
, max_pstate
);
1734 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1736 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1737 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1738 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1739 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1740 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1741 cpu
->pstate
.max_freq
= cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
;
1742 cpu
->pstate
.turbo_freq
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1744 if (pstate_funcs
.get_vid
)
1745 pstate_funcs
.get_vid(cpu
);
1747 intel_pstate_set_min_pstate(cpu
);
1750 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1752 struct sample
*sample
= &cpu
->sample
;
1754 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1757 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1760 unsigned long flags
;
1763 local_irq_save(flags
);
1764 rdmsrl(MSR_IA32_APERF
, aperf
);
1765 rdmsrl(MSR_IA32_MPERF
, mperf
);
1767 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1768 local_irq_restore(flags
);
1771 local_irq_restore(flags
);
1773 cpu
->last_sample_time
= cpu
->sample
.time
;
1774 cpu
->sample
.time
= time
;
1775 cpu
->sample
.aperf
= aperf
;
1776 cpu
->sample
.mperf
= mperf
;
1777 cpu
->sample
.tsc
= tsc
;
1778 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1779 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1780 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1782 cpu
->prev_aperf
= aperf
;
1783 cpu
->prev_mperf
= mperf
;
1784 cpu
->prev_tsc
= tsc
;
1786 * First time this function is invoked in a given cycle, all of the
1787 * previous sample data fields are equal to zero or stale and they must
1788 * be populated with meaningful numbers for things to work, so assume
1789 * that sample.time will always be reset before setting the utilization
1790 * update hook and make the caller skip the sample then.
1792 return !!cpu
->last_sample_time
;
1795 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1797 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1798 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1801 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1803 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1804 cpu
->sample
.core_avg_perf
);
1807 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1809 struct sample
*sample
= &cpu
->sample
;
1810 int32_t busy_frac
, boost
;
1811 int target
, avg_pstate
;
1813 busy_frac
= div_fp(sample
->mperf
, sample
->tsc
);
1815 boost
= cpu
->iowait_boost
;
1816 cpu
->iowait_boost
>>= 1;
1818 if (busy_frac
< boost
)
1821 sample
->busy_scaled
= busy_frac
* 100;
1823 target
= limits
->no_turbo
|| limits
->turbo_disabled
?
1824 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1825 target
+= target
>> 2;
1826 target
= mul_fp(target
, busy_frac
);
1827 if (target
< cpu
->pstate
.min_pstate
)
1828 target
= cpu
->pstate
.min_pstate
;
1831 * If the average P-state during the previous cycle was higher than the
1832 * current target, add 50% of the difference to the target to reduce
1833 * possible performance oscillations and offset possible performance
1834 * loss related to moving the workload from one CPU to another within
1837 avg_pstate
= get_avg_pstate(cpu
);
1838 if (avg_pstate
> target
)
1839 target
+= (avg_pstate
- target
) >> 1;
1844 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1846 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1850 * perf_scaled is the ratio of the average P-state during the last
1851 * sampling period to the P-state requested last time (in percent).
1853 * That measures the system's response to the previous P-state
1856 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1857 current_pstate
= cpu
->pstate
.current_pstate
;
1858 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1859 div_fp(100 * max_pstate
, current_pstate
));
1862 * Since our utilization update callback will not run unless we are
1863 * in C0, check if the actual elapsed time is significantly greater (3x)
1864 * than our sample interval. If it is, then we were idle for a long
1865 * enough period of time to adjust our performance metric.
1867 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1868 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1869 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1870 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1872 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1873 if (sample_ratio
< int_tofp(1))
1877 cpu
->sample
.busy_scaled
= perf_scaled
;
1878 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1881 static int intel_pstate_prepare_request(struct cpudata
*cpu
, int pstate
)
1883 int max_perf
, min_perf
;
1885 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1886 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1890 static void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1892 if (pstate
== cpu
->pstate
.current_pstate
)
1895 cpu
->pstate
.current_pstate
= pstate
;
1896 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1899 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1901 int from
, target_pstate
;
1902 struct sample
*sample
;
1904 from
= cpu
->pstate
.current_pstate
;
1906 target_pstate
= cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
?
1907 cpu
->pstate
.turbo_pstate
: pstate_funcs
.get_target_pstate(cpu
);
1909 update_turbo_state();
1911 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
1912 trace_cpu_frequency(target_pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1913 intel_pstate_update_pstate(cpu
, target_pstate
);
1915 sample
= &cpu
->sample
;
1916 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1917 fp_toint(sample
->busy_scaled
),
1919 cpu
->pstate
.current_pstate
,
1923 get_avg_frequency(cpu
),
1924 fp_toint(cpu
->iowait_boost
* 100));
1927 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1930 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1933 if (pstate_funcs
.get_target_pstate
== get_target_pstate_use_cpu_load
) {
1934 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1935 cpu
->iowait_boost
= int_tofp(1);
1936 } else if (cpu
->iowait_boost
) {
1937 /* Clear iowait_boost if the CPU may have been idle. */
1938 delta_ns
= time
- cpu
->last_update
;
1939 if (delta_ns
> TICK_NSEC
)
1940 cpu
->iowait_boost
= 0;
1942 cpu
->last_update
= time
;
1945 delta_ns
= time
- cpu
->sample
.time
;
1946 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1947 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1950 intel_pstate_calc_avg_perf(cpu
);
1952 intel_pstate_adjust_busy_pstate(cpu
);
1957 #define ICPU(model, policy) \
1958 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1959 (unsigned long)&policy }
1961 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1962 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_params
),
1963 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_params
),
1964 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_params
),
1965 ICPU(INTEL_FAM6_IVYBRIDGE
, core_params
),
1966 ICPU(INTEL_FAM6_HASWELL_CORE
, core_params
),
1967 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_params
),
1968 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_params
),
1969 ICPU(INTEL_FAM6_HASWELL_X
, core_params
),
1970 ICPU(INTEL_FAM6_HASWELL_ULT
, core_params
),
1971 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_params
),
1972 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_params
),
1973 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_params
),
1974 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_params
),
1975 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1976 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_params
),
1977 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1978 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_params
),
1979 ICPU(INTEL_FAM6_XEON_PHI_KNM
, knl_params
),
1980 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_params
),
1983 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1985 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1986 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1987 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1988 ICPU(INTEL_FAM6_SKYLAKE_X
, core_params
),
1992 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids
[] = {
1993 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP
, core_params
),
1997 static int intel_pstate_init_cpu(unsigned int cpunum
)
1999 struct cpudata
*cpu
;
2001 cpu
= all_cpu_data
[cpunum
];
2004 unsigned int size
= sizeof(struct cpudata
);
2007 size
+= sizeof(struct perf_limits
);
2009 cpu
= kzalloc(size
, GFP_KERNEL
);
2013 all_cpu_data
[cpunum
] = cpu
;
2015 cpu
->perf_limits
= (struct perf_limits
*)(cpu
+ 1);
2017 cpu
->epp_default
= -EINVAL
;
2018 cpu
->epp_powersave
= -EINVAL
;
2019 cpu
->epp_saved
= -EINVAL
;
2022 cpu
= all_cpu_data
[cpunum
];
2027 const struct x86_cpu_id
*id
;
2029 id
= x86_match_cpu(intel_pstate_cpu_ee_disable_ids
);
2031 intel_pstate_disable_ee(cpunum
);
2033 intel_pstate_hwp_enable(cpu
);
2034 pid_params
.sample_rate_ms
= 50;
2035 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
2038 intel_pstate_get_cpu_pstates(cpu
);
2040 intel_pstate_busy_pid_reset(cpu
);
2042 pr_debug("controlling: cpu %d\n", cpunum
);
2047 static unsigned int intel_pstate_get(unsigned int cpu_num
)
2049 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2051 return cpu
? get_avg_frequency(cpu
) : 0;
2054 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
2056 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2058 if (cpu
->update_util_set
)
2061 /* Prevent intel_pstate_update_util() from using stale data. */
2062 cpu
->sample
.time
= 0;
2063 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
2064 intel_pstate_update_util
);
2065 cpu
->update_util_set
= true;
2068 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
2070 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
2072 if (!cpu_data
->update_util_set
)
2075 cpufreq_remove_update_util_hook(cpu
);
2076 cpu_data
->update_util_set
= false;
2077 synchronize_sched();
2080 static void intel_pstate_update_perf_limits(struct cpufreq_policy
*policy
,
2081 struct perf_limits
*limits
)
2083 int32_t max_policy_perf
, min_policy_perf
;
2085 max_policy_perf
= div_ext_fp(policy
->max
, policy
->cpuinfo
.max_freq
);
2086 max_policy_perf
= clamp_t(int32_t, max_policy_perf
, 0, int_ext_tofp(1));
2087 if (policy
->max
== policy
->min
) {
2088 min_policy_perf
= max_policy_perf
;
2090 min_policy_perf
= div_ext_fp(policy
->min
,
2091 policy
->cpuinfo
.max_freq
);
2092 min_policy_perf
= clamp_t(int32_t, min_policy_perf
,
2093 0, max_policy_perf
);
2096 /* Normalize user input to [min_perf, max_perf] */
2097 limits
->min_perf
= max(min_policy_perf
,
2098 percent_ext_fp(limits
->min_sysfs_pct
));
2099 limits
->min_perf
= min(limits
->min_perf
, max_policy_perf
);
2100 limits
->max_perf
= min(max_policy_perf
,
2101 percent_ext_fp(limits
->max_sysfs_pct
));
2102 limits
->max_perf
= max(min_policy_perf
, limits
->max_perf
);
2104 /* Make sure min_perf <= max_perf */
2105 limits
->min_perf
= min(limits
->min_perf
, limits
->max_perf
);
2107 limits
->max_perf
= round_up(limits
->max_perf
, EXT_FRAC_BITS
);
2108 limits
->min_perf
= round_up(limits
->min_perf
, EXT_FRAC_BITS
);
2109 limits
->max_perf_pct
= fp_ext_toint(limits
->max_perf
* 100);
2110 limits
->min_perf_pct
= fp_ext_toint(limits
->min_perf
* 100);
2112 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy
->cpu
,
2113 limits
->max_perf_pct
, limits
->min_perf_pct
);
2116 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
2118 struct cpudata
*cpu
;
2119 struct perf_limits
*perf_limits
= NULL
;
2121 if (!policy
->cpuinfo
.max_freq
)
2124 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2125 policy
->cpuinfo
.max_freq
, policy
->max
);
2127 cpu
= all_cpu_data
[policy
->cpu
];
2128 cpu
->policy
= policy
->policy
;
2130 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
2131 policy
->max
< policy
->cpuinfo
.max_freq
&&
2132 policy
->max
> cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
) {
2133 pr_debug("policy->max > max non turbo frequency\n");
2134 policy
->max
= policy
->cpuinfo
.max_freq
;
2138 perf_limits
= cpu
->perf_limits
;
2140 mutex_lock(&intel_pstate_limits_lock
);
2142 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2143 pr_debug("set performance\n");
2145 limits
= &performance_limits
;
2146 perf_limits
= limits
;
2149 pr_debug("set powersave\n");
2151 limits
= &powersave_limits
;
2152 perf_limits
= limits
;
2157 intel_pstate_update_perf_limits(policy
, perf_limits
);
2159 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2161 * NOHZ_FULL CPUs need this as the governor callback may not
2162 * be invoked on them.
2164 intel_pstate_clear_update_util_hook(policy
->cpu
);
2165 intel_pstate_max_within_limits(cpu
);
2168 intel_pstate_set_update_util_hook(policy
->cpu
);
2170 intel_pstate_hwp_set_policy(policy
);
2172 mutex_unlock(&intel_pstate_limits_lock
);
2177 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
2179 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2180 struct perf_limits
*perf_limits
;
2182 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
2183 perf_limits
= &performance_limits
;
2185 perf_limits
= &powersave_limits
;
2187 update_turbo_state();
2188 policy
->cpuinfo
.max_freq
= perf_limits
->turbo_disabled
||
2189 perf_limits
->no_turbo
?
2190 cpu
->pstate
.max_freq
:
2191 cpu
->pstate
.turbo_freq
;
2193 cpufreq_verify_within_cpu_limits(policy
);
2195 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
2196 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
2199 /* When per-CPU limits are used, sysfs limits are not used */
2200 if (!per_cpu_limits
) {
2201 unsigned int max_freq
, min_freq
;
2203 max_freq
= policy
->cpuinfo
.max_freq
*
2204 perf_limits
->max_sysfs_pct
/ 100;
2205 min_freq
= policy
->cpuinfo
.max_freq
*
2206 perf_limits
->min_sysfs_pct
/ 100;
2207 cpufreq_verify_within_limits(policy
, min_freq
, max_freq
);
2213 static void intel_cpufreq_stop_cpu(struct cpufreq_policy
*policy
)
2215 intel_pstate_set_min_pstate(all_cpu_data
[policy
->cpu
]);
2218 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
2220 pr_debug("CPU %d exiting\n", policy
->cpu
);
2222 intel_pstate_clear_update_util_hook(policy
->cpu
);
2224 intel_pstate_hwp_save_state(policy
);
2226 intel_cpufreq_stop_cpu(policy
);
2229 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
2231 intel_pstate_exit_perf_limits(policy
);
2233 policy
->fast_switch_possible
= false;
2238 static int __intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2240 struct cpudata
*cpu
;
2243 rc
= intel_pstate_init_cpu(policy
->cpu
);
2247 cpu
= all_cpu_data
[policy
->cpu
];
2250 intel_pstate_init_limits(cpu
->perf_limits
);
2252 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2253 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
2255 /* cpuinfo and default policy values */
2256 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2257 update_turbo_state();
2258 policy
->cpuinfo
.max_freq
= limits
->turbo_disabled
?
2259 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
2260 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
2262 intel_pstate_init_acpi_perf_limits(policy
);
2263 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
2265 policy
->fast_switch_possible
= true;
2270 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2272 int ret
= __intel_pstate_cpu_init(policy
);
2277 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
2278 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
2279 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
2281 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
2286 static struct cpufreq_driver intel_pstate
= {
2287 .flags
= CPUFREQ_CONST_LOOPS
,
2288 .verify
= intel_pstate_verify_policy
,
2289 .setpolicy
= intel_pstate_set_policy
,
2290 .suspend
= intel_pstate_hwp_save_state
,
2291 .resume
= intel_pstate_resume
,
2292 .get
= intel_pstate_get
,
2293 .init
= intel_pstate_cpu_init
,
2294 .exit
= intel_pstate_cpu_exit
,
2295 .stop_cpu
= intel_pstate_stop_cpu
,
2296 .name
= "intel_pstate",
2299 static int intel_cpufreq_verify_policy(struct cpufreq_policy
*policy
)
2301 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2303 update_turbo_state();
2304 policy
->cpuinfo
.max_freq
= limits
->turbo_disabled
?
2305 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
2307 cpufreq_verify_within_cpu_limits(policy
);
2312 static unsigned int intel_cpufreq_turbo_update(struct cpudata
*cpu
,
2313 struct cpufreq_policy
*policy
,
2314 unsigned int target_freq
)
2316 unsigned int max_freq
;
2318 update_turbo_state();
2320 max_freq
= limits
->no_turbo
|| limits
->turbo_disabled
?
2321 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
2322 policy
->cpuinfo
.max_freq
= max_freq
;
2323 if (policy
->max
> max_freq
)
2324 policy
->max
= max_freq
;
2326 if (target_freq
> max_freq
)
2327 target_freq
= max_freq
;
2332 static int intel_cpufreq_target(struct cpufreq_policy
*policy
,
2333 unsigned int target_freq
,
2334 unsigned int relation
)
2336 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2337 struct cpufreq_freqs freqs
;
2340 freqs
.old
= policy
->cur
;
2341 freqs
.new = intel_cpufreq_turbo_update(cpu
, policy
, target_freq
);
2343 cpufreq_freq_transition_begin(policy
, &freqs
);
2345 case CPUFREQ_RELATION_L
:
2346 target_pstate
= DIV_ROUND_UP(freqs
.new, cpu
->pstate
.scaling
);
2348 case CPUFREQ_RELATION_H
:
2349 target_pstate
= freqs
.new / cpu
->pstate
.scaling
;
2352 target_pstate
= DIV_ROUND_CLOSEST(freqs
.new, cpu
->pstate
.scaling
);
2355 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2356 if (target_pstate
!= cpu
->pstate
.current_pstate
) {
2357 cpu
->pstate
.current_pstate
= target_pstate
;
2358 wrmsrl_on_cpu(policy
->cpu
, MSR_IA32_PERF_CTL
,
2359 pstate_funcs
.get_val(cpu
, target_pstate
));
2361 freqs
.new = target_pstate
* cpu
->pstate
.scaling
;
2362 cpufreq_freq_transition_end(policy
, &freqs
, false);
2367 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy
*policy
,
2368 unsigned int target_freq
)
2370 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2373 target_freq
= intel_cpufreq_turbo_update(cpu
, policy
, target_freq
);
2374 target_pstate
= DIV_ROUND_UP(target_freq
, cpu
->pstate
.scaling
);
2375 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2376 intel_pstate_update_pstate(cpu
, target_pstate
);
2377 return target_pstate
* cpu
->pstate
.scaling
;
2380 static int intel_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
2382 int ret
= __intel_pstate_cpu_init(policy
);
2387 policy
->cpuinfo
.transition_latency
= INTEL_CPUFREQ_TRANSITION_LATENCY
;
2388 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2389 policy
->cur
= policy
->cpuinfo
.min_freq
;
2394 static struct cpufreq_driver intel_cpufreq
= {
2395 .flags
= CPUFREQ_CONST_LOOPS
,
2396 .verify
= intel_cpufreq_verify_policy
,
2397 .target
= intel_cpufreq_target
,
2398 .fast_switch
= intel_cpufreq_fast_switch
,
2399 .init
= intel_cpufreq_cpu_init
,
2400 .exit
= intel_pstate_cpu_exit
,
2401 .stop_cpu
= intel_cpufreq_stop_cpu
,
2402 .name
= "intel_cpufreq",
2405 static struct cpufreq_driver
*intel_pstate_driver
= &intel_pstate
;
2407 static void intel_pstate_driver_cleanup(void)
2412 for_each_online_cpu(cpu
) {
2413 if (all_cpu_data
[cpu
]) {
2414 if (intel_pstate_driver
== &intel_pstate
)
2415 intel_pstate_clear_update_util_hook(cpu
);
2417 kfree(all_cpu_data
[cpu
]);
2418 all_cpu_data
[cpu
] = NULL
;
2424 static int intel_pstate_register_driver(void)
2428 intel_pstate_init_limits(&powersave_limits
);
2429 intel_pstate_set_performance_limits(&performance_limits
);
2430 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
) &&
2431 intel_pstate_driver
== &intel_pstate
)
2432 limits
= &performance_limits
;
2434 limits
= &powersave_limits
;
2436 ret
= cpufreq_register_driver(intel_pstate_driver
);
2438 intel_pstate_driver_cleanup();
2442 mutex_lock(&intel_pstate_limits_lock
);
2443 driver_registered
= true;
2444 mutex_unlock(&intel_pstate_limits_lock
);
2446 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2447 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2448 intel_pstate_debug_expose_params();
2453 static int intel_pstate_unregister_driver(void)
2458 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2459 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2460 intel_pstate_debug_hide_params();
2462 mutex_lock(&intel_pstate_limits_lock
);
2463 driver_registered
= false;
2464 mutex_unlock(&intel_pstate_limits_lock
);
2466 cpufreq_unregister_driver(intel_pstate_driver
);
2467 intel_pstate_driver_cleanup();
2472 static ssize_t
intel_pstate_show_status(char *buf
)
2474 if (!driver_registered
)
2475 return sprintf(buf
, "off\n");
2477 return sprintf(buf
, "%s\n", intel_pstate_driver
== &intel_pstate
?
2478 "active" : "passive");
2481 static int intel_pstate_update_status(const char *buf
, size_t size
)
2485 if (size
== 3 && !strncmp(buf
, "off", size
))
2486 return driver_registered
?
2487 intel_pstate_unregister_driver() : -EINVAL
;
2489 if (size
== 6 && !strncmp(buf
, "active", size
)) {
2490 if (driver_registered
) {
2491 if (intel_pstate_driver
== &intel_pstate
)
2494 ret
= intel_pstate_unregister_driver();
2499 intel_pstate_driver
= &intel_pstate
;
2500 return intel_pstate_register_driver();
2503 if (size
== 7 && !strncmp(buf
, "passive", size
)) {
2504 if (driver_registered
) {
2505 if (intel_pstate_driver
!= &intel_pstate
)
2508 ret
= intel_pstate_unregister_driver();
2513 intel_pstate_driver
= &intel_cpufreq
;
2514 return intel_pstate_register_driver();
2520 static int no_load __initdata
;
2521 static int no_hwp __initdata
;
2522 static int hwp_only __initdata
;
2523 static unsigned int force_load __initdata
;
2525 static int __init
intel_pstate_msrs_not_valid(void)
2527 if (!pstate_funcs
.get_max() ||
2528 !pstate_funcs
.get_min() ||
2529 !pstate_funcs
.get_turbo())
2535 static void __init
copy_pid_params(struct pstate_adjust_policy
*policy
)
2537 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
2538 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
2539 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
2540 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
2541 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
2542 pid_params
.deadband
= policy
->deadband
;
2543 pid_params
.setpoint
= policy
->setpoint
;
2547 static void intel_pstate_use_acpi_profile(void)
2549 if (acpi_gbl_FADT
.preferred_profile
== PM_MOBILE
)
2550 pstate_funcs
.get_target_pstate
=
2551 get_target_pstate_use_cpu_load
;
2554 static void intel_pstate_use_acpi_profile(void)
2559 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
2561 pstate_funcs
.get_max
= funcs
->get_max
;
2562 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
2563 pstate_funcs
.get_min
= funcs
->get_min
;
2564 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
2565 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
2566 pstate_funcs
.get_val
= funcs
->get_val
;
2567 pstate_funcs
.get_vid
= funcs
->get_vid
;
2568 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
2570 intel_pstate_use_acpi_profile();
2575 static bool __init
intel_pstate_no_acpi_pss(void)
2579 for_each_possible_cpu(i
) {
2581 union acpi_object
*pss
;
2582 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
2583 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2588 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
2589 if (ACPI_FAILURE(status
))
2592 pss
= buffer
.pointer
;
2593 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
2604 static bool __init
intel_pstate_has_acpi_ppc(void)
2608 for_each_possible_cpu(i
) {
2609 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2613 if (acpi_has_method(pr
->handle
, "_PPC"))
2624 struct hw_vendor_info
{
2626 char oem_id
[ACPI_OEM_ID_SIZE
];
2627 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
2631 /* Hardware vendor-specific info that has its own power management modes */
2632 static struct hw_vendor_info vendor_info
[] __initdata
= {
2633 {1, "HP ", "ProLiant", PSS
},
2634 {1, "ORACLE", "X4-2 ", PPC
},
2635 {1, "ORACLE", "X4-2L ", PPC
},
2636 {1, "ORACLE", "X4-2B ", PPC
},
2637 {1, "ORACLE", "X3-2 ", PPC
},
2638 {1, "ORACLE", "X3-2L ", PPC
},
2639 {1, "ORACLE", "X3-2B ", PPC
},
2640 {1, "ORACLE", "X4470M2 ", PPC
},
2641 {1, "ORACLE", "X4270M3 ", PPC
},
2642 {1, "ORACLE", "X4270M2 ", PPC
},
2643 {1, "ORACLE", "X4170M2 ", PPC
},
2644 {1, "ORACLE", "X4170 M3", PPC
},
2645 {1, "ORACLE", "X4275 M3", PPC
},
2646 {1, "ORACLE", "X6-2 ", PPC
},
2647 {1, "ORACLE", "Sudbury ", PPC
},
2651 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
2653 struct acpi_table_header hdr
;
2654 struct hw_vendor_info
*v_info
;
2655 const struct x86_cpu_id
*id
;
2658 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
2660 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
2661 if ( misc_pwr
& (1 << 8))
2665 if (acpi_disabled
||
2666 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
2669 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
2670 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
2671 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
2672 ACPI_OEM_TABLE_ID_SIZE
))
2673 switch (v_info
->oem_pwr_table
) {
2675 return intel_pstate_no_acpi_pss();
2677 return intel_pstate_has_acpi_ppc() &&
2685 static void intel_pstate_request_control_from_smm(void)
2688 * It may be unsafe to request P-states control from SMM if _PPC support
2689 * has not been enabled.
2692 acpi_processor_pstate_control();
2694 #else /* CONFIG_ACPI not enabled */
2695 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2696 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2697 static inline void intel_pstate_request_control_from_smm(void) {}
2698 #endif /* CONFIG_ACPI */
2700 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
2701 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
2705 static int __init
intel_pstate_init(void)
2707 const struct x86_cpu_id
*id
;
2708 struct cpu_defaults
*cpu_def
;
2714 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
2715 copy_cpu_funcs(&core_params
.funcs
);
2717 intel_pstate
.attr
= hwp_cpufreq_attrs
;
2718 goto hwp_cpu_matched
;
2721 id
= x86_match_cpu(intel_pstate_cpu_ids
);
2725 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
2727 copy_pid_params(&cpu_def
->pid_policy
);
2728 copy_cpu_funcs(&cpu_def
->funcs
);
2730 if (intel_pstate_msrs_not_valid())
2735 * The Intel pstate driver will be ignored if the platform
2736 * firmware has its own power management modes.
2738 if (intel_pstate_platform_pwr_mgmt_exists())
2741 if (!hwp_active
&& hwp_only
)
2744 pr_info("Intel P-state driver initializing\n");
2746 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
2750 intel_pstate_request_control_from_smm();
2752 intel_pstate_sysfs_expose_params();
2754 mutex_lock(&intel_pstate_driver_lock
);
2755 rc
= intel_pstate_register_driver();
2756 mutex_unlock(&intel_pstate_driver_lock
);
2761 pr_info("HWP enabled\n");
2765 device_initcall(intel_pstate_init
);
2767 static int __init
intel_pstate_setup(char *str
)
2772 if (!strcmp(str
, "disable")) {
2774 } else if (!strcmp(str
, "passive")) {
2775 pr_info("Passive mode enabled\n");
2776 intel_pstate_driver
= &intel_cpufreq
;
2779 if (!strcmp(str
, "no_hwp")) {
2780 pr_info("HWP disabled\n");
2783 if (!strcmp(str
, "force"))
2785 if (!strcmp(str
, "hwp_only"))
2787 if (!strcmp(str
, "per_cpu_perf_limits"))
2788 per_cpu_limits
= true;
2791 if (!strcmp(str
, "support_acpi_ppc"))
2797 early_param("intel_pstate", intel_pstate_setup
);
2799 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2800 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2801 MODULE_LICENSE("GPL");