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cpufreq: intel_pstate: Use locking in intel_pstate_resume()
[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / intel_pstate.c
1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
33
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41
42 #define ATOM_RATIOS 0x66a
43 #define ATOM_VIDS 0x66b
44 #define ATOM_TURBO_RATIOS 0x66c
45 #define ATOM_TURBO_VIDS 0x66d
46
47 #ifdef CONFIG_ACPI
48 #include <acpi/processor.h>
49 #endif
50
51 #define FRAC_BITS 8
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
70 static inline int ceiling_fp(int32_t x)
71 {
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79 }
80
81 static inline u64 mul_ext_fp(u64 x, u64 y)
82 {
83 return (x * y) >> EXT_FRAC_BITS;
84 }
85
86 static inline u64 div_ext_fp(u64 x, u64 y)
87 {
88 return div64_u64(x << EXT_FRAC_BITS, y);
89 }
90
91 /**
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
103 * current sample
104 * @time: Current time from scheduler
105 *
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
108 */
109 struct sample {
110 int32_t core_avg_perf;
111 int32_t busy_scaled;
112 u64 aperf;
113 u64 mperf;
114 u64 tsc;
115 u64 time;
116 };
117
118 /**
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @scaling: Scaling factor to convert frequency to cpufreq
127 * frequency units
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @max_freq: @max_pstate frequency in cpufreq units
130 * @turbo_freq: @turbo_pstate frequency in cpufreq units
131 *
132 * Stores the per cpu model P state limits and current P state.
133 */
134 struct pstate_data {
135 int current_pstate;
136 int min_pstate;
137 int max_pstate;
138 int max_pstate_physical;
139 int scaling;
140 int turbo_pstate;
141 unsigned int max_freq;
142 unsigned int turbo_freq;
143 };
144
145 /**
146 * struct vid_data - Stores voltage information data
147 * @min: VID data for this platform corresponding to
148 * the lowest P state
149 * @max: VID data corresponding to the highest P State.
150 * @turbo: VID data for turbo P state
151 * @ratio: Ratio of (vid max - vid min) /
152 * (max P state - Min P State)
153 *
154 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
155 * This data is used in Atom platforms, where in addition to target P state,
156 * the voltage data needs to be specified to select next P State.
157 */
158 struct vid_data {
159 int min;
160 int max;
161 int turbo;
162 int32_t ratio;
163 };
164
165 /**
166 * struct _pid - Stores PID data
167 * @setpoint: Target set point for busyness or performance
168 * @integral: Storage for accumulated error values
169 * @p_gain: PID proportional gain
170 * @i_gain: PID integral gain
171 * @d_gain: PID derivative gain
172 * @deadband: PID deadband
173 * @last_err: Last error storage for integral part of PID calculation
174 *
175 * Stores PID coefficients and last error for PID controller.
176 */
177 struct _pid {
178 int setpoint;
179 int32_t integral;
180 int32_t p_gain;
181 int32_t i_gain;
182 int32_t d_gain;
183 int deadband;
184 int32_t last_err;
185 };
186
187 /**
188 * struct perf_limits - Store user and policy limits
189 * @no_turbo: User requested turbo state from intel_pstate sysfs
190 * @turbo_disabled: Platform turbo status either from msr
191 * MSR_IA32_MISC_ENABLE or when maximum available pstate
192 * matches the maximum turbo pstate
193 * @max_perf_pct: Effective maximum performance limit in percentage, this
194 * is minimum of either limits enforced by cpufreq policy
195 * or limits from user set limits via intel_pstate sysfs
196 * @min_perf_pct: Effective minimum performance limit in percentage, this
197 * is maximum of either limits enforced by cpufreq policy
198 * or limits from user set limits via intel_pstate sysfs
199 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
200 * This value is used to limit max pstate
201 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
202 * This value is used to limit min pstate
203 * @max_policy_pct: The maximum performance in percentage enforced by
204 * cpufreq setpolicy interface
205 * @max_sysfs_pct: The maximum performance in percentage enforced by
206 * intel pstate sysfs interface, unused when per cpu
207 * controls are enforced
208 * @min_policy_pct: The minimum performance in percentage enforced by
209 * cpufreq setpolicy interface
210 * @min_sysfs_pct: The minimum performance in percentage enforced by
211 * intel pstate sysfs interface, unused when per cpu
212 * controls are enforced
213 *
214 * Storage for user and policy defined limits.
215 */
216 struct perf_limits {
217 int no_turbo;
218 int turbo_disabled;
219 int max_perf_pct;
220 int min_perf_pct;
221 int32_t max_perf;
222 int32_t min_perf;
223 int max_policy_pct;
224 int max_sysfs_pct;
225 int min_policy_pct;
226 int min_sysfs_pct;
227 };
228
229 /**
230 * struct cpudata - Per CPU instance data storage
231 * @cpu: CPU number for this instance data
232 * @policy: CPUFreq policy value
233 * @update_util: CPUFreq utility callback information
234 * @update_util_set: CPUFreq utility callback is set
235 * @iowait_boost: iowait-related boost fraction
236 * @last_update: Time of the last update.
237 * @pstate: Stores P state limits for this CPU
238 * @vid: Stores VID limits for this CPU
239 * @pid: Stores PID parameters for this CPU
240 * @last_sample_time: Last Sample time
241 * @prev_aperf: Last APERF value read from APERF MSR
242 * @prev_mperf: Last MPERF value read from MPERF MSR
243 * @prev_tsc: Last timestamp counter (TSC) value
244 * @prev_cummulative_iowait: IO Wait time difference from last and
245 * current sample
246 * @sample: Storage for storing last Sample data
247 * @perf_limits: Pointer to perf_limit unique to this CPU
248 * Not all field in the structure are applicable
249 * when per cpu controls are enforced
250 * @acpi_perf_data: Stores ACPI perf information read from _PSS
251 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
252 * @epp_powersave: Last saved HWP energy performance preference
253 * (EPP) or energy performance bias (EPB),
254 * when policy switched to performance
255 * @epp_policy: Last saved policy used to set EPP/EPB
256 * @epp_default: Power on default HWP energy performance
257 * preference/bias
258 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
259 * operation
260 *
261 * This structure stores per CPU instance data for all CPUs.
262 */
263 struct cpudata {
264 int cpu;
265
266 unsigned int policy;
267 struct update_util_data update_util;
268 bool update_util_set;
269
270 struct pstate_data pstate;
271 struct vid_data vid;
272 struct _pid pid;
273
274 u64 last_update;
275 u64 last_sample_time;
276 u64 prev_aperf;
277 u64 prev_mperf;
278 u64 prev_tsc;
279 u64 prev_cummulative_iowait;
280 struct sample sample;
281 struct perf_limits *perf_limits;
282 #ifdef CONFIG_ACPI
283 struct acpi_processor_performance acpi_perf_data;
284 bool valid_pss_table;
285 #endif
286 unsigned int iowait_boost;
287 s16 epp_powersave;
288 s16 epp_policy;
289 s16 epp_default;
290 s16 epp_saved;
291 };
292
293 static struct cpudata **all_cpu_data;
294
295 /**
296 * struct pstate_adjust_policy - Stores static PID configuration data
297 * @sample_rate_ms: PID calculation sample rate in ms
298 * @sample_rate_ns: Sample rate calculation in ns
299 * @deadband: PID deadband
300 * @setpoint: PID Setpoint
301 * @p_gain_pct: PID proportional gain
302 * @i_gain_pct: PID integral gain
303 * @d_gain_pct: PID derivative gain
304 *
305 * Stores per CPU model static PID configuration data.
306 */
307 struct pstate_adjust_policy {
308 int sample_rate_ms;
309 s64 sample_rate_ns;
310 int deadband;
311 int setpoint;
312 int p_gain_pct;
313 int d_gain_pct;
314 int i_gain_pct;
315 };
316
317 /**
318 * struct pstate_funcs - Per CPU model specific callbacks
319 * @get_max: Callback to get maximum non turbo effective P state
320 * @get_max_physical: Callback to get maximum non turbo physical P state
321 * @get_min: Callback to get minimum P state
322 * @get_turbo: Callback to get turbo P state
323 * @get_scaling: Callback to get frequency scaling factor
324 * @get_val: Callback to convert P state to actual MSR write value
325 * @get_vid: Callback to get VID data for Atom platforms
326 * @get_target_pstate: Callback to a function to calculate next P state to use
327 *
328 * Core and Atom CPU models have different way to get P State limits. This
329 * structure is used to store those callbacks.
330 */
331 struct pstate_funcs {
332 int (*get_max)(void);
333 int (*get_max_physical)(void);
334 int (*get_min)(void);
335 int (*get_turbo)(void);
336 int (*get_scaling)(void);
337 u64 (*get_val)(struct cpudata*, int pstate);
338 void (*get_vid)(struct cpudata *);
339 int32_t (*get_target_pstate)(struct cpudata *);
340 };
341
342 /**
343 * struct cpu_defaults- Per CPU model default config data
344 * @pid_policy: PID config data
345 * @funcs: Callback function data
346 */
347 struct cpu_defaults {
348 struct pstate_adjust_policy pid_policy;
349 struct pstate_funcs funcs;
350 };
351
352 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
353 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
354
355 static struct pstate_adjust_policy pid_params __read_mostly;
356 static struct pstate_funcs pstate_funcs __read_mostly;
357 static int hwp_active __read_mostly;
358 static bool per_cpu_limits __read_mostly;
359
360 #ifdef CONFIG_ACPI
361 static bool acpi_ppc;
362 #endif
363
364 static struct perf_limits performance_limits = {
365 .no_turbo = 0,
366 .turbo_disabled = 0,
367 .max_perf_pct = 100,
368 .max_perf = int_ext_tofp(1),
369 .min_perf_pct = 100,
370 .min_perf = int_ext_tofp(1),
371 .max_policy_pct = 100,
372 .max_sysfs_pct = 100,
373 .min_policy_pct = 0,
374 .min_sysfs_pct = 0,
375 };
376
377 static struct perf_limits powersave_limits = {
378 .no_turbo = 0,
379 .turbo_disabled = 0,
380 .max_perf_pct = 100,
381 .max_perf = int_ext_tofp(1),
382 .min_perf_pct = 0,
383 .min_perf = 0,
384 .max_policy_pct = 100,
385 .max_sysfs_pct = 100,
386 .min_policy_pct = 0,
387 .min_sysfs_pct = 0,
388 };
389
390 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
391 static struct perf_limits *limits = &performance_limits;
392 #else
393 static struct perf_limits *limits = &powersave_limits;
394 #endif
395
396 static DEFINE_MUTEX(intel_pstate_limits_lock);
397
398 #ifdef CONFIG_ACPI
399
400 static bool intel_pstate_get_ppc_enable_status(void)
401 {
402 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
403 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
404 return true;
405
406 return acpi_ppc;
407 }
408
409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
410 {
411 struct cpudata *cpu;
412 int ret;
413 int i;
414
415 if (hwp_active)
416 return;
417
418 if (!intel_pstate_get_ppc_enable_status())
419 return;
420
421 cpu = all_cpu_data[policy->cpu];
422
423 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
424 policy->cpu);
425 if (ret)
426 return;
427
428 /*
429 * Check if the control value in _PSS is for PERF_CTL MSR, which should
430 * guarantee that the states returned by it map to the states in our
431 * list directly.
432 */
433 if (cpu->acpi_perf_data.control_register.space_id !=
434 ACPI_ADR_SPACE_FIXED_HARDWARE)
435 goto err;
436
437 /*
438 * If there is only one entry _PSS, simply ignore _PSS and continue as
439 * usual without taking _PSS into account
440 */
441 if (cpu->acpi_perf_data.state_count < 2)
442 goto err;
443
444 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
445 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
446 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
447 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
448 (u32) cpu->acpi_perf_data.states[i].core_frequency,
449 (u32) cpu->acpi_perf_data.states[i].power,
450 (u32) cpu->acpi_perf_data.states[i].control);
451 }
452
453 /*
454 * The _PSS table doesn't contain whole turbo frequency range.
455 * This just contains +1 MHZ above the max non turbo frequency,
456 * with control value corresponding to max turbo ratio. But
457 * when cpufreq set policy is called, it will call with this
458 * max frequency, which will cause a reduced performance as
459 * this driver uses real max turbo frequency as the max
460 * frequency. So correct this frequency in _PSS table to
461 * correct max turbo frequency based on the turbo state.
462 * Also need to convert to MHz as _PSS freq is in MHz.
463 */
464 if (!limits->turbo_disabled)
465 cpu->acpi_perf_data.states[0].core_frequency =
466 policy->cpuinfo.max_freq / 1000;
467 cpu->valid_pss_table = true;
468 pr_debug("_PPC limits will be enforced\n");
469
470 return;
471
472 err:
473 cpu->valid_pss_table = false;
474 acpi_processor_unregister_performance(policy->cpu);
475 }
476
477 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
478 {
479 struct cpudata *cpu;
480
481 cpu = all_cpu_data[policy->cpu];
482 if (!cpu->valid_pss_table)
483 return;
484
485 acpi_processor_unregister_performance(policy->cpu);
486 }
487
488 #else
489 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
490 {
491 }
492
493 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
494 {
495 }
496 #endif
497
498 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
499 int deadband, int integral) {
500 pid->setpoint = int_tofp(setpoint);
501 pid->deadband = int_tofp(deadband);
502 pid->integral = int_tofp(integral);
503 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
504 }
505
506 static inline void pid_p_gain_set(struct _pid *pid, int percent)
507 {
508 pid->p_gain = div_fp(percent, 100);
509 }
510
511 static inline void pid_i_gain_set(struct _pid *pid, int percent)
512 {
513 pid->i_gain = div_fp(percent, 100);
514 }
515
516 static inline void pid_d_gain_set(struct _pid *pid, int percent)
517 {
518 pid->d_gain = div_fp(percent, 100);
519 }
520
521 static signed int pid_calc(struct _pid *pid, int32_t busy)
522 {
523 signed int result;
524 int32_t pterm, dterm, fp_error;
525 int32_t integral_limit;
526
527 fp_error = pid->setpoint - busy;
528
529 if (abs(fp_error) <= pid->deadband)
530 return 0;
531
532 pterm = mul_fp(pid->p_gain, fp_error);
533
534 pid->integral += fp_error;
535
536 /*
537 * We limit the integral here so that it will never
538 * get higher than 30. This prevents it from becoming
539 * too large an input over long periods of time and allows
540 * it to get factored out sooner.
541 *
542 * The value of 30 was chosen through experimentation.
543 */
544 integral_limit = int_tofp(30);
545 if (pid->integral > integral_limit)
546 pid->integral = integral_limit;
547 if (pid->integral < -integral_limit)
548 pid->integral = -integral_limit;
549
550 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
551 pid->last_err = fp_error;
552
553 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
554 result = result + (1 << (FRAC_BITS-1));
555 return (signed int)fp_toint(result);
556 }
557
558 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
559 {
560 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
561 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
562 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
563
564 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
565 }
566
567 static inline void intel_pstate_reset_all_pid(void)
568 {
569 unsigned int cpu;
570
571 for_each_online_cpu(cpu) {
572 if (all_cpu_data[cpu])
573 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
574 }
575 }
576
577 static inline void update_turbo_state(void)
578 {
579 u64 misc_en;
580 struct cpudata *cpu;
581
582 cpu = all_cpu_data[0];
583 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
584 limits->turbo_disabled =
585 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
586 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
587 }
588
589 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
590 {
591 u64 epb;
592 int ret;
593
594 if (!static_cpu_has(X86_FEATURE_EPB))
595 return -ENXIO;
596
597 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
598 if (ret)
599 return (s16)ret;
600
601 return (s16)(epb & 0x0f);
602 }
603
604 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
605 {
606 s16 epp;
607
608 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
609 /*
610 * When hwp_req_data is 0, means that caller didn't read
611 * MSR_HWP_REQUEST, so need to read and get EPP.
612 */
613 if (!hwp_req_data) {
614 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
615 &hwp_req_data);
616 if (epp)
617 return epp;
618 }
619 epp = (hwp_req_data >> 24) & 0xff;
620 } else {
621 /* When there is no EPP present, HWP uses EPB settings */
622 epp = intel_pstate_get_epb(cpu_data);
623 }
624
625 return epp;
626 }
627
628 static int intel_pstate_set_epb(int cpu, s16 pref)
629 {
630 u64 epb;
631 int ret;
632
633 if (!static_cpu_has(X86_FEATURE_EPB))
634 return -ENXIO;
635
636 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
637 if (ret)
638 return ret;
639
640 epb = (epb & ~0x0f) | pref;
641 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
642
643 return 0;
644 }
645
646 /*
647 * EPP/EPB display strings corresponding to EPP index in the
648 * energy_perf_strings[]
649 * index String
650 *-------------------------------------
651 * 0 default
652 * 1 performance
653 * 2 balance_performance
654 * 3 balance_power
655 * 4 power
656 */
657 static const char * const energy_perf_strings[] = {
658 "default",
659 "performance",
660 "balance_performance",
661 "balance_power",
662 "power",
663 NULL
664 };
665
666 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
667 {
668 s16 epp;
669 int index = -EINVAL;
670
671 epp = intel_pstate_get_epp(cpu_data, 0);
672 if (epp < 0)
673 return epp;
674
675 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
676 /*
677 * Range:
678 * 0x00-0x3F : Performance
679 * 0x40-0x7F : Balance performance
680 * 0x80-0xBF : Balance power
681 * 0xC0-0xFF : Power
682 * The EPP is a 8 bit value, but our ranges restrict the
683 * value which can be set. Here only using top two bits
684 * effectively.
685 */
686 index = (epp >> 6) + 1;
687 } else if (static_cpu_has(X86_FEATURE_EPB)) {
688 /*
689 * Range:
690 * 0x00-0x03 : Performance
691 * 0x04-0x07 : Balance performance
692 * 0x08-0x0B : Balance power
693 * 0x0C-0x0F : Power
694 * The EPB is a 4 bit value, but our ranges restrict the
695 * value which can be set. Here only using top two bits
696 * effectively.
697 */
698 index = (epp >> 2) + 1;
699 }
700
701 return index;
702 }
703
704 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
705 int pref_index)
706 {
707 int epp = -EINVAL;
708 int ret;
709
710 if (!pref_index)
711 epp = cpu_data->epp_default;
712
713 mutex_lock(&intel_pstate_limits_lock);
714
715 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
716 u64 value;
717
718 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
719 if (ret)
720 goto return_pref;
721
722 value &= ~GENMASK_ULL(31, 24);
723
724 /*
725 * If epp is not default, convert from index into
726 * energy_perf_strings to epp value, by shifting 6
727 * bits left to use only top two bits in epp.
728 * The resultant epp need to shifted by 24 bits to
729 * epp position in MSR_HWP_REQUEST.
730 */
731 if (epp == -EINVAL)
732 epp = (pref_index - 1) << 6;
733
734 value |= (u64)epp << 24;
735 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
736 } else {
737 if (epp == -EINVAL)
738 epp = (pref_index - 1) << 2;
739 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
740 }
741 return_pref:
742 mutex_unlock(&intel_pstate_limits_lock);
743
744 return ret;
745 }
746
747 static ssize_t show_energy_performance_available_preferences(
748 struct cpufreq_policy *policy, char *buf)
749 {
750 int i = 0;
751 int ret = 0;
752
753 while (energy_perf_strings[i] != NULL)
754 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
755
756 ret += sprintf(&buf[ret], "\n");
757
758 return ret;
759 }
760
761 cpufreq_freq_attr_ro(energy_performance_available_preferences);
762
763 static ssize_t store_energy_performance_preference(
764 struct cpufreq_policy *policy, const char *buf, size_t count)
765 {
766 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
767 char str_preference[21];
768 int ret, i = 0;
769
770 ret = sscanf(buf, "%20s", str_preference);
771 if (ret != 1)
772 return -EINVAL;
773
774 while (energy_perf_strings[i] != NULL) {
775 if (!strcmp(str_preference, energy_perf_strings[i])) {
776 intel_pstate_set_energy_pref_index(cpu_data, i);
777 return count;
778 }
779 ++i;
780 }
781
782 return -EINVAL;
783 }
784
785 static ssize_t show_energy_performance_preference(
786 struct cpufreq_policy *policy, char *buf)
787 {
788 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
789 int preference;
790
791 preference = intel_pstate_get_energy_pref_index(cpu_data);
792 if (preference < 0)
793 return preference;
794
795 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
796 }
797
798 cpufreq_freq_attr_rw(energy_performance_preference);
799
800 static struct freq_attr *hwp_cpufreq_attrs[] = {
801 &energy_performance_preference,
802 &energy_performance_available_preferences,
803 NULL,
804 };
805
806 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
807 {
808 int min, hw_min, max, hw_max, cpu, range, adj_range;
809 struct perf_limits *perf_limits = limits;
810 u64 value, cap;
811
812 for_each_cpu(cpu, cpumask) {
813 int max_perf_pct, min_perf_pct;
814 struct cpudata *cpu_data = all_cpu_data[cpu];
815 s16 epp;
816
817 if (per_cpu_limits)
818 perf_limits = all_cpu_data[cpu]->perf_limits;
819
820 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
821 hw_min = HWP_LOWEST_PERF(cap);
822 hw_max = HWP_HIGHEST_PERF(cap);
823 range = hw_max - hw_min;
824
825 max_perf_pct = perf_limits->max_perf_pct;
826 min_perf_pct = perf_limits->min_perf_pct;
827
828 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
829 adj_range = min_perf_pct * range / 100;
830 min = hw_min + adj_range;
831 value &= ~HWP_MIN_PERF(~0L);
832 value |= HWP_MIN_PERF(min);
833
834 adj_range = max_perf_pct * range / 100;
835 max = hw_min + adj_range;
836 if (limits->no_turbo) {
837 hw_max = HWP_GUARANTEED_PERF(cap);
838 if (hw_max < max)
839 max = hw_max;
840 }
841
842 value &= ~HWP_MAX_PERF(~0L);
843 value |= HWP_MAX_PERF(max);
844
845 if (cpu_data->epp_policy == cpu_data->policy)
846 goto skip_epp;
847
848 cpu_data->epp_policy = cpu_data->policy;
849
850 if (cpu_data->epp_saved >= 0) {
851 epp = cpu_data->epp_saved;
852 cpu_data->epp_saved = -EINVAL;
853 goto update_epp;
854 }
855
856 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
857 epp = intel_pstate_get_epp(cpu_data, value);
858 cpu_data->epp_powersave = epp;
859 /* If EPP read was failed, then don't try to write */
860 if (epp < 0)
861 goto skip_epp;
862
863
864 epp = 0;
865 } else {
866 /* skip setting EPP, when saved value is invalid */
867 if (cpu_data->epp_powersave < 0)
868 goto skip_epp;
869
870 /*
871 * No need to restore EPP when it is not zero. This
872 * means:
873 * - Policy is not changed
874 * - user has manually changed
875 * - Error reading EPB
876 */
877 epp = intel_pstate_get_epp(cpu_data, value);
878 if (epp)
879 goto skip_epp;
880
881 epp = cpu_data->epp_powersave;
882 }
883 update_epp:
884 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
885 value &= ~GENMASK_ULL(31, 24);
886 value |= (u64)epp << 24;
887 } else {
888 intel_pstate_set_epb(cpu, epp);
889 }
890 skip_epp:
891 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
892 }
893 }
894
895 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
896 {
897 if (hwp_active)
898 intel_pstate_hwp_set(policy->cpus);
899
900 return 0;
901 }
902
903 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
904 {
905 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
906
907 if (!hwp_active)
908 return 0;
909
910 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
911
912 return 0;
913 }
914
915 static int intel_pstate_resume(struct cpufreq_policy *policy)
916 {
917 int ret;
918
919 if (!hwp_active)
920 return 0;
921
922 mutex_lock(&intel_pstate_limits_lock);
923
924 all_cpu_data[policy->cpu]->epp_policy = 0;
925
926 ret = intel_pstate_hwp_set_policy(policy);
927
928 mutex_unlock(&intel_pstate_limits_lock);
929
930 return ret;
931 }
932
933 static void intel_pstate_hwp_set_online_cpus(void)
934 {
935 get_online_cpus();
936 intel_pstate_hwp_set(cpu_online_mask);
937 put_online_cpus();
938 }
939
940 /************************** debugfs begin ************************/
941 static int pid_param_set(void *data, u64 val)
942 {
943 *(u32 *)data = val;
944 intel_pstate_reset_all_pid();
945 return 0;
946 }
947
948 static int pid_param_get(void *data, u64 *val)
949 {
950 *val = *(u32 *)data;
951 return 0;
952 }
953 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
954
955 struct pid_param {
956 char *name;
957 void *value;
958 };
959
960 static struct pid_param pid_files[] = {
961 {"sample_rate_ms", &pid_params.sample_rate_ms},
962 {"d_gain_pct", &pid_params.d_gain_pct},
963 {"i_gain_pct", &pid_params.i_gain_pct},
964 {"deadband", &pid_params.deadband},
965 {"setpoint", &pid_params.setpoint},
966 {"p_gain_pct", &pid_params.p_gain_pct},
967 {NULL, NULL}
968 };
969
970 static void __init intel_pstate_debug_expose_params(void)
971 {
972 struct dentry *debugfs_parent;
973 int i = 0;
974
975 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
976 if (IS_ERR_OR_NULL(debugfs_parent))
977 return;
978 while (pid_files[i].name) {
979 debugfs_create_file(pid_files[i].name, 0660,
980 debugfs_parent, pid_files[i].value,
981 &fops_pid_param);
982 i++;
983 }
984 }
985
986 /************************** debugfs end ************************/
987
988 /************************** sysfs begin ************************/
989 #define show_one(file_name, object) \
990 static ssize_t show_##file_name \
991 (struct kobject *kobj, struct attribute *attr, char *buf) \
992 { \
993 return sprintf(buf, "%u\n", limits->object); \
994 }
995
996 static ssize_t show_turbo_pct(struct kobject *kobj,
997 struct attribute *attr, char *buf)
998 {
999 struct cpudata *cpu;
1000 int total, no_turbo, turbo_pct;
1001 uint32_t turbo_fp;
1002
1003 cpu = all_cpu_data[0];
1004
1005 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1006 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1007 turbo_fp = div_fp(no_turbo, total);
1008 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1009 return sprintf(buf, "%u\n", turbo_pct);
1010 }
1011
1012 static ssize_t show_num_pstates(struct kobject *kobj,
1013 struct attribute *attr, char *buf)
1014 {
1015 struct cpudata *cpu;
1016 int total;
1017
1018 cpu = all_cpu_data[0];
1019 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1020 return sprintf(buf, "%u\n", total);
1021 }
1022
1023 static ssize_t show_no_turbo(struct kobject *kobj,
1024 struct attribute *attr, char *buf)
1025 {
1026 ssize_t ret;
1027
1028 update_turbo_state();
1029 if (limits->turbo_disabled)
1030 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1031 else
1032 ret = sprintf(buf, "%u\n", limits->no_turbo);
1033
1034 return ret;
1035 }
1036
1037 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1038 const char *buf, size_t count)
1039 {
1040 unsigned int input;
1041 int ret;
1042
1043 ret = sscanf(buf, "%u", &input);
1044 if (ret != 1)
1045 return -EINVAL;
1046
1047 mutex_lock(&intel_pstate_limits_lock);
1048
1049 update_turbo_state();
1050 if (limits->turbo_disabled) {
1051 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1052 mutex_unlock(&intel_pstate_limits_lock);
1053 return -EPERM;
1054 }
1055
1056 limits->no_turbo = clamp_t(int, input, 0, 1);
1057
1058 if (hwp_active)
1059 intel_pstate_hwp_set_online_cpus();
1060
1061 mutex_unlock(&intel_pstate_limits_lock);
1062
1063 return count;
1064 }
1065
1066 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1067 const char *buf, size_t count)
1068 {
1069 unsigned int input;
1070 int ret;
1071
1072 ret = sscanf(buf, "%u", &input);
1073 if (ret != 1)
1074 return -EINVAL;
1075
1076 mutex_lock(&intel_pstate_limits_lock);
1077
1078 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1079 limits->max_perf_pct = min(limits->max_policy_pct,
1080 limits->max_sysfs_pct);
1081 limits->max_perf_pct = max(limits->min_policy_pct,
1082 limits->max_perf_pct);
1083 limits->max_perf_pct = max(limits->min_perf_pct,
1084 limits->max_perf_pct);
1085 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1086
1087 if (hwp_active)
1088 intel_pstate_hwp_set_online_cpus();
1089
1090 mutex_unlock(&intel_pstate_limits_lock);
1091
1092 return count;
1093 }
1094
1095 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1096 const char *buf, size_t count)
1097 {
1098 unsigned int input;
1099 int ret;
1100
1101 ret = sscanf(buf, "%u", &input);
1102 if (ret != 1)
1103 return -EINVAL;
1104
1105 mutex_lock(&intel_pstate_limits_lock);
1106
1107 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1108 limits->min_perf_pct = max(limits->min_policy_pct,
1109 limits->min_sysfs_pct);
1110 limits->min_perf_pct = min(limits->max_policy_pct,
1111 limits->min_perf_pct);
1112 limits->min_perf_pct = min(limits->max_perf_pct,
1113 limits->min_perf_pct);
1114 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1115
1116 if (hwp_active)
1117 intel_pstate_hwp_set_online_cpus();
1118
1119 mutex_unlock(&intel_pstate_limits_lock);
1120
1121 return count;
1122 }
1123
1124 show_one(max_perf_pct, max_perf_pct);
1125 show_one(min_perf_pct, min_perf_pct);
1126
1127 define_one_global_rw(no_turbo);
1128 define_one_global_rw(max_perf_pct);
1129 define_one_global_rw(min_perf_pct);
1130 define_one_global_ro(turbo_pct);
1131 define_one_global_ro(num_pstates);
1132
1133 static struct attribute *intel_pstate_attributes[] = {
1134 &no_turbo.attr,
1135 &turbo_pct.attr,
1136 &num_pstates.attr,
1137 NULL
1138 };
1139
1140 static struct attribute_group intel_pstate_attr_group = {
1141 .attrs = intel_pstate_attributes,
1142 };
1143
1144 static void __init intel_pstate_sysfs_expose_params(void)
1145 {
1146 struct kobject *intel_pstate_kobject;
1147 int rc;
1148
1149 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1150 &cpu_subsys.dev_root->kobj);
1151 if (WARN_ON(!intel_pstate_kobject))
1152 return;
1153
1154 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1155 if (WARN_ON(rc))
1156 return;
1157
1158 /*
1159 * If per cpu limits are enforced there are no global limits, so
1160 * return without creating max/min_perf_pct attributes
1161 */
1162 if (per_cpu_limits)
1163 return;
1164
1165 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1166 WARN_ON(rc);
1167
1168 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1169 WARN_ON(rc);
1170
1171 }
1172 /************************** sysfs end ************************/
1173
1174 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1175 {
1176 /* First disable HWP notification interrupt as we don't process them */
1177 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1178 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1179
1180 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1181 cpudata->epp_policy = 0;
1182 if (cpudata->epp_default == -EINVAL)
1183 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1184 }
1185
1186 static int atom_get_min_pstate(void)
1187 {
1188 u64 value;
1189
1190 rdmsrl(ATOM_RATIOS, value);
1191 return (value >> 8) & 0x7F;
1192 }
1193
1194 static int atom_get_max_pstate(void)
1195 {
1196 u64 value;
1197
1198 rdmsrl(ATOM_RATIOS, value);
1199 return (value >> 16) & 0x7F;
1200 }
1201
1202 static int atom_get_turbo_pstate(void)
1203 {
1204 u64 value;
1205
1206 rdmsrl(ATOM_TURBO_RATIOS, value);
1207 return value & 0x7F;
1208 }
1209
1210 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1211 {
1212 u64 val;
1213 int32_t vid_fp;
1214 u32 vid;
1215
1216 val = (u64)pstate << 8;
1217 if (limits->no_turbo && !limits->turbo_disabled)
1218 val |= (u64)1 << 32;
1219
1220 vid_fp = cpudata->vid.min + mul_fp(
1221 int_tofp(pstate - cpudata->pstate.min_pstate),
1222 cpudata->vid.ratio);
1223
1224 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1225 vid = ceiling_fp(vid_fp);
1226
1227 if (pstate > cpudata->pstate.max_pstate)
1228 vid = cpudata->vid.turbo;
1229
1230 return val | vid;
1231 }
1232
1233 static int silvermont_get_scaling(void)
1234 {
1235 u64 value;
1236 int i;
1237 /* Defined in Table 35-6 from SDM (Sept 2015) */
1238 static int silvermont_freq_table[] = {
1239 83300, 100000, 133300, 116700, 80000};
1240
1241 rdmsrl(MSR_FSB_FREQ, value);
1242 i = value & 0x7;
1243 WARN_ON(i > 4);
1244
1245 return silvermont_freq_table[i];
1246 }
1247
1248 static int airmont_get_scaling(void)
1249 {
1250 u64 value;
1251 int i;
1252 /* Defined in Table 35-10 from SDM (Sept 2015) */
1253 static int airmont_freq_table[] = {
1254 83300, 100000, 133300, 116700, 80000,
1255 93300, 90000, 88900, 87500};
1256
1257 rdmsrl(MSR_FSB_FREQ, value);
1258 i = value & 0xF;
1259 WARN_ON(i > 8);
1260
1261 return airmont_freq_table[i];
1262 }
1263
1264 static void atom_get_vid(struct cpudata *cpudata)
1265 {
1266 u64 value;
1267
1268 rdmsrl(ATOM_VIDS, value);
1269 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1270 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1271 cpudata->vid.ratio = div_fp(
1272 cpudata->vid.max - cpudata->vid.min,
1273 int_tofp(cpudata->pstate.max_pstate -
1274 cpudata->pstate.min_pstate));
1275
1276 rdmsrl(ATOM_TURBO_VIDS, value);
1277 cpudata->vid.turbo = value & 0x7f;
1278 }
1279
1280 static int core_get_min_pstate(void)
1281 {
1282 u64 value;
1283
1284 rdmsrl(MSR_PLATFORM_INFO, value);
1285 return (value >> 40) & 0xFF;
1286 }
1287
1288 static int core_get_max_pstate_physical(void)
1289 {
1290 u64 value;
1291
1292 rdmsrl(MSR_PLATFORM_INFO, value);
1293 return (value >> 8) & 0xFF;
1294 }
1295
1296 static int core_get_max_pstate(void)
1297 {
1298 u64 tar;
1299 u64 plat_info;
1300 int max_pstate;
1301 int err;
1302
1303 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1304 max_pstate = (plat_info >> 8) & 0xFF;
1305
1306 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1307 if (!err) {
1308 /* Do some sanity checking for safety */
1309 if (plat_info & 0x600000000) {
1310 u64 tdp_ctrl;
1311 u64 tdp_ratio;
1312 int tdp_msr;
1313
1314 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1315 if (err)
1316 goto skip_tar;
1317
1318 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
1319 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1320 if (err)
1321 goto skip_tar;
1322
1323 /* For level 1 and 2, bits[23:16] contain the ratio */
1324 if (tdp_ctrl)
1325 tdp_ratio >>= 16;
1326
1327 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1328 if (tdp_ratio - 1 == tar) {
1329 max_pstate = tar;
1330 pr_debug("max_pstate=TAC %x\n", max_pstate);
1331 } else {
1332 goto skip_tar;
1333 }
1334 }
1335 }
1336
1337 skip_tar:
1338 return max_pstate;
1339 }
1340
1341 static int core_get_turbo_pstate(void)
1342 {
1343 u64 value;
1344 int nont, ret;
1345
1346 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1347 nont = core_get_max_pstate();
1348 ret = (value) & 255;
1349 if (ret <= nont)
1350 ret = nont;
1351 return ret;
1352 }
1353
1354 static inline int core_get_scaling(void)
1355 {
1356 return 100000;
1357 }
1358
1359 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1360 {
1361 u64 val;
1362
1363 val = (u64)pstate << 8;
1364 if (limits->no_turbo && !limits->turbo_disabled)
1365 val |= (u64)1 << 32;
1366
1367 return val;
1368 }
1369
1370 static int knl_get_turbo_pstate(void)
1371 {
1372 u64 value;
1373 int nont, ret;
1374
1375 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1376 nont = core_get_max_pstate();
1377 ret = (((value) >> 8) & 0xFF);
1378 if (ret <= nont)
1379 ret = nont;
1380 return ret;
1381 }
1382
1383 static struct cpu_defaults core_params = {
1384 .pid_policy = {
1385 .sample_rate_ms = 10,
1386 .deadband = 0,
1387 .setpoint = 97,
1388 .p_gain_pct = 20,
1389 .d_gain_pct = 0,
1390 .i_gain_pct = 0,
1391 },
1392 .funcs = {
1393 .get_max = core_get_max_pstate,
1394 .get_max_physical = core_get_max_pstate_physical,
1395 .get_min = core_get_min_pstate,
1396 .get_turbo = core_get_turbo_pstate,
1397 .get_scaling = core_get_scaling,
1398 .get_val = core_get_val,
1399 .get_target_pstate = get_target_pstate_use_performance,
1400 },
1401 };
1402
1403 static const struct cpu_defaults silvermont_params = {
1404 .pid_policy = {
1405 .sample_rate_ms = 10,
1406 .deadband = 0,
1407 .setpoint = 60,
1408 .p_gain_pct = 14,
1409 .d_gain_pct = 0,
1410 .i_gain_pct = 4,
1411 },
1412 .funcs = {
1413 .get_max = atom_get_max_pstate,
1414 .get_max_physical = atom_get_max_pstate,
1415 .get_min = atom_get_min_pstate,
1416 .get_turbo = atom_get_turbo_pstate,
1417 .get_val = atom_get_val,
1418 .get_scaling = silvermont_get_scaling,
1419 .get_vid = atom_get_vid,
1420 .get_target_pstate = get_target_pstate_use_cpu_load,
1421 },
1422 };
1423
1424 static const struct cpu_defaults airmont_params = {
1425 .pid_policy = {
1426 .sample_rate_ms = 10,
1427 .deadband = 0,
1428 .setpoint = 60,
1429 .p_gain_pct = 14,
1430 .d_gain_pct = 0,
1431 .i_gain_pct = 4,
1432 },
1433 .funcs = {
1434 .get_max = atom_get_max_pstate,
1435 .get_max_physical = atom_get_max_pstate,
1436 .get_min = atom_get_min_pstate,
1437 .get_turbo = atom_get_turbo_pstate,
1438 .get_val = atom_get_val,
1439 .get_scaling = airmont_get_scaling,
1440 .get_vid = atom_get_vid,
1441 .get_target_pstate = get_target_pstate_use_cpu_load,
1442 },
1443 };
1444
1445 static const struct cpu_defaults knl_params = {
1446 .pid_policy = {
1447 .sample_rate_ms = 10,
1448 .deadband = 0,
1449 .setpoint = 97,
1450 .p_gain_pct = 20,
1451 .d_gain_pct = 0,
1452 .i_gain_pct = 0,
1453 },
1454 .funcs = {
1455 .get_max = core_get_max_pstate,
1456 .get_max_physical = core_get_max_pstate_physical,
1457 .get_min = core_get_min_pstate,
1458 .get_turbo = knl_get_turbo_pstate,
1459 .get_scaling = core_get_scaling,
1460 .get_val = core_get_val,
1461 .get_target_pstate = get_target_pstate_use_performance,
1462 },
1463 };
1464
1465 static const struct cpu_defaults bxt_params = {
1466 .pid_policy = {
1467 .sample_rate_ms = 10,
1468 .deadband = 0,
1469 .setpoint = 60,
1470 .p_gain_pct = 14,
1471 .d_gain_pct = 0,
1472 .i_gain_pct = 4,
1473 },
1474 .funcs = {
1475 .get_max = core_get_max_pstate,
1476 .get_max_physical = core_get_max_pstate_physical,
1477 .get_min = core_get_min_pstate,
1478 .get_turbo = core_get_turbo_pstate,
1479 .get_scaling = core_get_scaling,
1480 .get_val = core_get_val,
1481 .get_target_pstate = get_target_pstate_use_cpu_load,
1482 },
1483 };
1484
1485 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1486 {
1487 int max_perf = cpu->pstate.turbo_pstate;
1488 int max_perf_adj;
1489 int min_perf;
1490 struct perf_limits *perf_limits = limits;
1491
1492 if (limits->no_turbo || limits->turbo_disabled)
1493 max_perf = cpu->pstate.max_pstate;
1494
1495 if (per_cpu_limits)
1496 perf_limits = cpu->perf_limits;
1497
1498 /*
1499 * performance can be limited by user through sysfs, by cpufreq
1500 * policy, or by cpu specific default values determined through
1501 * experimentation.
1502 */
1503 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1504 *max = clamp_t(int, max_perf_adj,
1505 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1506
1507 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1508 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1509 }
1510
1511 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1512 {
1513 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1514 cpu->pstate.current_pstate = pstate;
1515 /*
1516 * Generally, there is no guarantee that this code will always run on
1517 * the CPU being updated, so force the register update to run on the
1518 * right CPU.
1519 */
1520 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1521 pstate_funcs.get_val(cpu, pstate));
1522 }
1523
1524 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1525 {
1526 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1527 }
1528
1529 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1530 {
1531 int min_pstate, max_pstate;
1532
1533 update_turbo_state();
1534 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1535 intel_pstate_set_pstate(cpu, max_pstate);
1536 }
1537
1538 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1539 {
1540 cpu->pstate.min_pstate = pstate_funcs.get_min();
1541 cpu->pstate.max_pstate = pstate_funcs.get_max();
1542 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1543 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1544 cpu->pstate.scaling = pstate_funcs.get_scaling();
1545 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1546 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1547
1548 if (pstate_funcs.get_vid)
1549 pstate_funcs.get_vid(cpu);
1550
1551 intel_pstate_set_min_pstate(cpu);
1552 }
1553
1554 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1555 {
1556 struct sample *sample = &cpu->sample;
1557
1558 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1559 }
1560
1561 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1562 {
1563 u64 aperf, mperf;
1564 unsigned long flags;
1565 u64 tsc;
1566
1567 local_irq_save(flags);
1568 rdmsrl(MSR_IA32_APERF, aperf);
1569 rdmsrl(MSR_IA32_MPERF, mperf);
1570 tsc = rdtsc();
1571 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1572 local_irq_restore(flags);
1573 return false;
1574 }
1575 local_irq_restore(flags);
1576
1577 cpu->last_sample_time = cpu->sample.time;
1578 cpu->sample.time = time;
1579 cpu->sample.aperf = aperf;
1580 cpu->sample.mperf = mperf;
1581 cpu->sample.tsc = tsc;
1582 cpu->sample.aperf -= cpu->prev_aperf;
1583 cpu->sample.mperf -= cpu->prev_mperf;
1584 cpu->sample.tsc -= cpu->prev_tsc;
1585
1586 cpu->prev_aperf = aperf;
1587 cpu->prev_mperf = mperf;
1588 cpu->prev_tsc = tsc;
1589 /*
1590 * First time this function is invoked in a given cycle, all of the
1591 * previous sample data fields are equal to zero or stale and they must
1592 * be populated with meaningful numbers for things to work, so assume
1593 * that sample.time will always be reset before setting the utilization
1594 * update hook and make the caller skip the sample then.
1595 */
1596 return !!cpu->last_sample_time;
1597 }
1598
1599 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1600 {
1601 return mul_ext_fp(cpu->sample.core_avg_perf,
1602 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1603 }
1604
1605 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1606 {
1607 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1608 cpu->sample.core_avg_perf);
1609 }
1610
1611 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1612 {
1613 struct sample *sample = &cpu->sample;
1614 int32_t busy_frac, boost;
1615 int target, avg_pstate;
1616
1617 busy_frac = div_fp(sample->mperf, sample->tsc);
1618
1619 boost = cpu->iowait_boost;
1620 cpu->iowait_boost >>= 1;
1621
1622 if (busy_frac < boost)
1623 busy_frac = boost;
1624
1625 sample->busy_scaled = busy_frac * 100;
1626
1627 target = limits->no_turbo || limits->turbo_disabled ?
1628 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1629 target += target >> 2;
1630 target = mul_fp(target, busy_frac);
1631 if (target < cpu->pstate.min_pstate)
1632 target = cpu->pstate.min_pstate;
1633
1634 /*
1635 * If the average P-state during the previous cycle was higher than the
1636 * current target, add 50% of the difference to the target to reduce
1637 * possible performance oscillations and offset possible performance
1638 * loss related to moving the workload from one CPU to another within
1639 * a package/module.
1640 */
1641 avg_pstate = get_avg_pstate(cpu);
1642 if (avg_pstate > target)
1643 target += (avg_pstate - target) >> 1;
1644
1645 return target;
1646 }
1647
1648 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1649 {
1650 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1651 u64 duration_ns;
1652
1653 /*
1654 * perf_scaled is the ratio of the average P-state during the last
1655 * sampling period to the P-state requested last time (in percent).
1656 *
1657 * That measures the system's response to the previous P-state
1658 * selection.
1659 */
1660 max_pstate = cpu->pstate.max_pstate_physical;
1661 current_pstate = cpu->pstate.current_pstate;
1662 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1663 div_fp(100 * max_pstate, current_pstate));
1664
1665 /*
1666 * Since our utilization update callback will not run unless we are
1667 * in C0, check if the actual elapsed time is significantly greater (3x)
1668 * than our sample interval. If it is, then we were idle for a long
1669 * enough period of time to adjust our performance metric.
1670 */
1671 duration_ns = cpu->sample.time - cpu->last_sample_time;
1672 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1673 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1674 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1675 } else {
1676 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1677 if (sample_ratio < int_tofp(1))
1678 perf_scaled = 0;
1679 }
1680
1681 cpu->sample.busy_scaled = perf_scaled;
1682 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1683 }
1684
1685 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1686 {
1687 int max_perf, min_perf;
1688
1689 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1690 pstate = clamp_t(int, pstate, min_perf, max_perf);
1691 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1692 return pstate;
1693 }
1694
1695 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1696 {
1697 pstate = intel_pstate_prepare_request(cpu, pstate);
1698 if (pstate == cpu->pstate.current_pstate)
1699 return;
1700
1701 cpu->pstate.current_pstate = pstate;
1702 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1703 }
1704
1705 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1706 {
1707 int from, target_pstate;
1708 struct sample *sample;
1709
1710 from = cpu->pstate.current_pstate;
1711
1712 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1713 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1714
1715 update_turbo_state();
1716
1717 intel_pstate_update_pstate(cpu, target_pstate);
1718
1719 sample = &cpu->sample;
1720 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1721 fp_toint(sample->busy_scaled),
1722 from,
1723 cpu->pstate.current_pstate,
1724 sample->mperf,
1725 sample->aperf,
1726 sample->tsc,
1727 get_avg_frequency(cpu),
1728 fp_toint(cpu->iowait_boost * 100));
1729 }
1730
1731 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1732 unsigned int flags)
1733 {
1734 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1735 u64 delta_ns;
1736
1737 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1738 if (flags & SCHED_CPUFREQ_IOWAIT) {
1739 cpu->iowait_boost = int_tofp(1);
1740 } else if (cpu->iowait_boost) {
1741 /* Clear iowait_boost if the CPU may have been idle. */
1742 delta_ns = time - cpu->last_update;
1743 if (delta_ns > TICK_NSEC)
1744 cpu->iowait_boost = 0;
1745 }
1746 cpu->last_update = time;
1747 }
1748
1749 delta_ns = time - cpu->sample.time;
1750 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1751 bool sample_taken = intel_pstate_sample(cpu, time);
1752
1753 if (sample_taken) {
1754 intel_pstate_calc_avg_perf(cpu);
1755 if (!hwp_active)
1756 intel_pstate_adjust_busy_pstate(cpu);
1757 }
1758 }
1759 }
1760
1761 #define ICPU(model, policy) \
1762 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1763 (unsigned long)&policy }
1764
1765 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1766 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1767 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1768 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1769 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1770 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1771 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1772 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1773 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1774 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1775 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1776 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1777 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1778 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1779 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1780 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1781 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1782 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
1783 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
1784 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
1785 {}
1786 };
1787 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1788
1789 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1790 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1791 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1792 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1793 {}
1794 };
1795
1796 static int intel_pstate_init_cpu(unsigned int cpunum)
1797 {
1798 struct cpudata *cpu;
1799
1800 cpu = all_cpu_data[cpunum];
1801
1802 if (!cpu) {
1803 unsigned int size = sizeof(struct cpudata);
1804
1805 if (per_cpu_limits)
1806 size += sizeof(struct perf_limits);
1807
1808 cpu = kzalloc(size, GFP_KERNEL);
1809 if (!cpu)
1810 return -ENOMEM;
1811
1812 all_cpu_data[cpunum] = cpu;
1813 if (per_cpu_limits)
1814 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1815
1816 cpu->epp_default = -EINVAL;
1817 cpu->epp_powersave = -EINVAL;
1818 cpu->epp_saved = -EINVAL;
1819 }
1820
1821 cpu = all_cpu_data[cpunum];
1822
1823 cpu->cpu = cpunum;
1824
1825 if (hwp_active) {
1826 intel_pstate_hwp_enable(cpu);
1827 pid_params.sample_rate_ms = 50;
1828 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1829 }
1830
1831 intel_pstate_get_cpu_pstates(cpu);
1832
1833 intel_pstate_busy_pid_reset(cpu);
1834
1835 pr_debug("controlling: cpu %d\n", cpunum);
1836
1837 return 0;
1838 }
1839
1840 static unsigned int intel_pstate_get(unsigned int cpu_num)
1841 {
1842 struct cpudata *cpu = all_cpu_data[cpu_num];
1843
1844 return cpu ? get_avg_frequency(cpu) : 0;
1845 }
1846
1847 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1848 {
1849 struct cpudata *cpu = all_cpu_data[cpu_num];
1850
1851 if (cpu->update_util_set)
1852 return;
1853
1854 /* Prevent intel_pstate_update_util() from using stale data. */
1855 cpu->sample.time = 0;
1856 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1857 intel_pstate_update_util);
1858 cpu->update_util_set = true;
1859 }
1860
1861 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1862 {
1863 struct cpudata *cpu_data = all_cpu_data[cpu];
1864
1865 if (!cpu_data->update_util_set)
1866 return;
1867
1868 cpufreq_remove_update_util_hook(cpu);
1869 cpu_data->update_util_set = false;
1870 synchronize_sched();
1871 }
1872
1873 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1874 {
1875 limits->no_turbo = 0;
1876 limits->turbo_disabled = 0;
1877 limits->max_perf_pct = 100;
1878 limits->max_perf = int_ext_tofp(1);
1879 limits->min_perf_pct = 100;
1880 limits->min_perf = int_ext_tofp(1);
1881 limits->max_policy_pct = 100;
1882 limits->max_sysfs_pct = 100;
1883 limits->min_policy_pct = 0;
1884 limits->min_sysfs_pct = 0;
1885 }
1886
1887 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1888 struct perf_limits *limits)
1889 {
1890
1891 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1892 policy->cpuinfo.max_freq);
1893 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
1894 if (policy->max == policy->min) {
1895 limits->min_policy_pct = limits->max_policy_pct;
1896 } else {
1897 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
1898 policy->cpuinfo.max_freq);
1899 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1900 0, 100);
1901 }
1902
1903 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1904 limits->min_perf_pct = max(limits->min_policy_pct,
1905 limits->min_sysfs_pct);
1906 limits->min_perf_pct = min(limits->max_policy_pct,
1907 limits->min_perf_pct);
1908 limits->max_perf_pct = min(limits->max_policy_pct,
1909 limits->max_sysfs_pct);
1910 limits->max_perf_pct = max(limits->min_policy_pct,
1911 limits->max_perf_pct);
1912
1913 /* Make sure min_perf_pct <= max_perf_pct */
1914 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1915
1916 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1917 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1918 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
1919 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
1920
1921 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
1922 limits->max_perf_pct, limits->min_perf_pct);
1923 }
1924
1925 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1926 {
1927 struct cpudata *cpu;
1928 struct perf_limits *perf_limits = NULL;
1929
1930 if (!policy->cpuinfo.max_freq)
1931 return -ENODEV;
1932
1933 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1934 policy->cpuinfo.max_freq, policy->max);
1935
1936 cpu = all_cpu_data[policy->cpu];
1937 cpu->policy = policy->policy;
1938
1939 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1940 policy->max < policy->cpuinfo.max_freq &&
1941 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1942 pr_debug("policy->max > max non turbo frequency\n");
1943 policy->max = policy->cpuinfo.max_freq;
1944 }
1945
1946 if (per_cpu_limits)
1947 perf_limits = cpu->perf_limits;
1948
1949 mutex_lock(&intel_pstate_limits_lock);
1950
1951 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1952 if (!perf_limits) {
1953 limits = &performance_limits;
1954 perf_limits = limits;
1955 }
1956 if (policy->max >= policy->cpuinfo.max_freq) {
1957 pr_debug("set performance\n");
1958 intel_pstate_set_performance_limits(perf_limits);
1959 goto out;
1960 }
1961 } else {
1962 pr_debug("set powersave\n");
1963 if (!perf_limits) {
1964 limits = &powersave_limits;
1965 perf_limits = limits;
1966 }
1967
1968 }
1969
1970 intel_pstate_update_perf_limits(policy, perf_limits);
1971 out:
1972 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1973 /*
1974 * NOHZ_FULL CPUs need this as the governor callback may not
1975 * be invoked on them.
1976 */
1977 intel_pstate_clear_update_util_hook(policy->cpu);
1978 intel_pstate_max_within_limits(cpu);
1979 }
1980
1981 intel_pstate_set_update_util_hook(policy->cpu);
1982
1983 intel_pstate_hwp_set_policy(policy);
1984
1985 mutex_unlock(&intel_pstate_limits_lock);
1986
1987 return 0;
1988 }
1989
1990 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1991 {
1992 cpufreq_verify_within_cpu_limits(policy);
1993
1994 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1995 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1996 return -EINVAL;
1997
1998 return 0;
1999 }
2000
2001 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2002 {
2003 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2004 }
2005
2006 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2007 {
2008 pr_debug("CPU %d exiting\n", policy->cpu);
2009
2010 intel_pstate_clear_update_util_hook(policy->cpu);
2011 if (hwp_active)
2012 intel_pstate_hwp_save_state(policy);
2013 else
2014 intel_cpufreq_stop_cpu(policy);
2015 }
2016
2017 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2018 {
2019 intel_pstate_exit_perf_limits(policy);
2020
2021 policy->fast_switch_possible = false;
2022
2023 return 0;
2024 }
2025
2026 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2027 {
2028 struct cpudata *cpu;
2029 int rc;
2030
2031 rc = intel_pstate_init_cpu(policy->cpu);
2032 if (rc)
2033 return rc;
2034
2035 cpu = all_cpu_data[policy->cpu];
2036
2037 /*
2038 * We need sane value in the cpu->perf_limits, so inherit from global
2039 * perf_limits limits, which are seeded with values based on the
2040 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2041 */
2042 if (per_cpu_limits)
2043 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2044
2045 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2046 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2047
2048 /* cpuinfo and default policy values */
2049 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2050 update_turbo_state();
2051 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2052 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2053 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2054
2055 intel_pstate_init_acpi_perf_limits(policy);
2056 cpumask_set_cpu(policy->cpu, policy->cpus);
2057
2058 policy->fast_switch_possible = true;
2059
2060 return 0;
2061 }
2062
2063 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2064 {
2065 int ret = __intel_pstate_cpu_init(policy);
2066
2067 if (ret)
2068 return ret;
2069
2070 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2071 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2072 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2073 else
2074 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2075
2076 return 0;
2077 }
2078
2079 static struct cpufreq_driver intel_pstate = {
2080 .flags = CPUFREQ_CONST_LOOPS,
2081 .verify = intel_pstate_verify_policy,
2082 .setpolicy = intel_pstate_set_policy,
2083 .suspend = intel_pstate_hwp_save_state,
2084 .resume = intel_pstate_resume,
2085 .get = intel_pstate_get,
2086 .init = intel_pstate_cpu_init,
2087 .exit = intel_pstate_cpu_exit,
2088 .stop_cpu = intel_pstate_stop_cpu,
2089 .name = "intel_pstate",
2090 };
2091
2092 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2093 {
2094 struct cpudata *cpu = all_cpu_data[policy->cpu];
2095 struct perf_limits *perf_limits = limits;
2096
2097 update_turbo_state();
2098 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2099 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2100
2101 cpufreq_verify_within_cpu_limits(policy);
2102
2103 if (per_cpu_limits)
2104 perf_limits = cpu->perf_limits;
2105
2106 intel_pstate_update_perf_limits(policy, perf_limits);
2107
2108 return 0;
2109 }
2110
2111 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2112 struct cpufreq_policy *policy,
2113 unsigned int target_freq)
2114 {
2115 unsigned int max_freq;
2116
2117 update_turbo_state();
2118
2119 max_freq = limits->no_turbo || limits->turbo_disabled ?
2120 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2121 policy->cpuinfo.max_freq = max_freq;
2122 if (policy->max > max_freq)
2123 policy->max = max_freq;
2124
2125 if (target_freq > max_freq)
2126 target_freq = max_freq;
2127
2128 return target_freq;
2129 }
2130
2131 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2132 unsigned int target_freq,
2133 unsigned int relation)
2134 {
2135 struct cpudata *cpu = all_cpu_data[policy->cpu];
2136 struct cpufreq_freqs freqs;
2137 int target_pstate;
2138
2139 freqs.old = policy->cur;
2140 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2141
2142 cpufreq_freq_transition_begin(policy, &freqs);
2143 switch (relation) {
2144 case CPUFREQ_RELATION_L:
2145 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2146 break;
2147 case CPUFREQ_RELATION_H:
2148 target_pstate = freqs.new / cpu->pstate.scaling;
2149 break;
2150 default:
2151 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2152 break;
2153 }
2154 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2155 if (target_pstate != cpu->pstate.current_pstate) {
2156 cpu->pstate.current_pstate = target_pstate;
2157 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2158 pstate_funcs.get_val(cpu, target_pstate));
2159 }
2160 cpufreq_freq_transition_end(policy, &freqs, false);
2161
2162 return 0;
2163 }
2164
2165 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2166 unsigned int target_freq)
2167 {
2168 struct cpudata *cpu = all_cpu_data[policy->cpu];
2169 int target_pstate;
2170
2171 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2172 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2173 intel_pstate_update_pstate(cpu, target_pstate);
2174 return target_freq;
2175 }
2176
2177 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2178 {
2179 int ret = __intel_pstate_cpu_init(policy);
2180
2181 if (ret)
2182 return ret;
2183
2184 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2185 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2186 policy->cur = policy->cpuinfo.min_freq;
2187
2188 return 0;
2189 }
2190
2191 static struct cpufreq_driver intel_cpufreq = {
2192 .flags = CPUFREQ_CONST_LOOPS,
2193 .verify = intel_cpufreq_verify_policy,
2194 .target = intel_cpufreq_target,
2195 .fast_switch = intel_cpufreq_fast_switch,
2196 .init = intel_cpufreq_cpu_init,
2197 .exit = intel_pstate_cpu_exit,
2198 .stop_cpu = intel_cpufreq_stop_cpu,
2199 .name = "intel_cpufreq",
2200 };
2201
2202 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2203
2204 static int no_load __initdata;
2205 static int no_hwp __initdata;
2206 static int hwp_only __initdata;
2207 static unsigned int force_load __initdata;
2208
2209 static int __init intel_pstate_msrs_not_valid(void)
2210 {
2211 if (!pstate_funcs.get_max() ||
2212 !pstate_funcs.get_min() ||
2213 !pstate_funcs.get_turbo())
2214 return -ENODEV;
2215
2216 return 0;
2217 }
2218
2219 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2220 {
2221 pid_params.sample_rate_ms = policy->sample_rate_ms;
2222 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2223 pid_params.p_gain_pct = policy->p_gain_pct;
2224 pid_params.i_gain_pct = policy->i_gain_pct;
2225 pid_params.d_gain_pct = policy->d_gain_pct;
2226 pid_params.deadband = policy->deadband;
2227 pid_params.setpoint = policy->setpoint;
2228 }
2229
2230 #ifdef CONFIG_ACPI
2231 static void intel_pstate_use_acpi_profile(void)
2232 {
2233 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2234 pstate_funcs.get_target_pstate =
2235 get_target_pstate_use_cpu_load;
2236 }
2237 #else
2238 static void intel_pstate_use_acpi_profile(void)
2239 {
2240 }
2241 #endif
2242
2243 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2244 {
2245 pstate_funcs.get_max = funcs->get_max;
2246 pstate_funcs.get_max_physical = funcs->get_max_physical;
2247 pstate_funcs.get_min = funcs->get_min;
2248 pstate_funcs.get_turbo = funcs->get_turbo;
2249 pstate_funcs.get_scaling = funcs->get_scaling;
2250 pstate_funcs.get_val = funcs->get_val;
2251 pstate_funcs.get_vid = funcs->get_vid;
2252 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2253
2254 intel_pstate_use_acpi_profile();
2255 }
2256
2257 #ifdef CONFIG_ACPI
2258
2259 static bool __init intel_pstate_no_acpi_pss(void)
2260 {
2261 int i;
2262
2263 for_each_possible_cpu(i) {
2264 acpi_status status;
2265 union acpi_object *pss;
2266 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2267 struct acpi_processor *pr = per_cpu(processors, i);
2268
2269 if (!pr)
2270 continue;
2271
2272 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2273 if (ACPI_FAILURE(status))
2274 continue;
2275
2276 pss = buffer.pointer;
2277 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2278 kfree(pss);
2279 return false;
2280 }
2281
2282 kfree(pss);
2283 }
2284
2285 return true;
2286 }
2287
2288 static bool __init intel_pstate_has_acpi_ppc(void)
2289 {
2290 int i;
2291
2292 for_each_possible_cpu(i) {
2293 struct acpi_processor *pr = per_cpu(processors, i);
2294
2295 if (!pr)
2296 continue;
2297 if (acpi_has_method(pr->handle, "_PPC"))
2298 return true;
2299 }
2300 return false;
2301 }
2302
2303 enum {
2304 PSS,
2305 PPC,
2306 };
2307
2308 struct hw_vendor_info {
2309 u16 valid;
2310 char oem_id[ACPI_OEM_ID_SIZE];
2311 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2312 int oem_pwr_table;
2313 };
2314
2315 /* Hardware vendor-specific info that has its own power management modes */
2316 static struct hw_vendor_info vendor_info[] __initdata = {
2317 {1, "HP ", "ProLiant", PSS},
2318 {1, "ORACLE", "X4-2 ", PPC},
2319 {1, "ORACLE", "X4-2L ", PPC},
2320 {1, "ORACLE", "X4-2B ", PPC},
2321 {1, "ORACLE", "X3-2 ", PPC},
2322 {1, "ORACLE", "X3-2L ", PPC},
2323 {1, "ORACLE", "X3-2B ", PPC},
2324 {1, "ORACLE", "X4470M2 ", PPC},
2325 {1, "ORACLE", "X4270M3 ", PPC},
2326 {1, "ORACLE", "X4270M2 ", PPC},
2327 {1, "ORACLE", "X4170M2 ", PPC},
2328 {1, "ORACLE", "X4170 M3", PPC},
2329 {1, "ORACLE", "X4275 M3", PPC},
2330 {1, "ORACLE", "X6-2 ", PPC},
2331 {1, "ORACLE", "Sudbury ", PPC},
2332 {0, "", ""},
2333 };
2334
2335 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2336 {
2337 struct acpi_table_header hdr;
2338 struct hw_vendor_info *v_info;
2339 const struct x86_cpu_id *id;
2340 u64 misc_pwr;
2341
2342 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2343 if (id) {
2344 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2345 if ( misc_pwr & (1 << 8))
2346 return true;
2347 }
2348
2349 if (acpi_disabled ||
2350 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2351 return false;
2352
2353 for (v_info = vendor_info; v_info->valid; v_info++) {
2354 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2355 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2356 ACPI_OEM_TABLE_ID_SIZE))
2357 switch (v_info->oem_pwr_table) {
2358 case PSS:
2359 return intel_pstate_no_acpi_pss();
2360 case PPC:
2361 return intel_pstate_has_acpi_ppc() &&
2362 (!force_load);
2363 }
2364 }
2365
2366 return false;
2367 }
2368
2369 static void intel_pstate_request_control_from_smm(void)
2370 {
2371 /*
2372 * It may be unsafe to request P-states control from SMM if _PPC support
2373 * has not been enabled.
2374 */
2375 if (acpi_ppc)
2376 acpi_processor_pstate_control();
2377 }
2378 #else /* CONFIG_ACPI not enabled */
2379 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2380 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2381 static inline void intel_pstate_request_control_from_smm(void) {}
2382 #endif /* CONFIG_ACPI */
2383
2384 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2385 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2386 {}
2387 };
2388
2389 static int __init intel_pstate_init(void)
2390 {
2391 int cpu, rc = 0;
2392 const struct x86_cpu_id *id;
2393 struct cpu_defaults *cpu_def;
2394
2395 if (no_load)
2396 return -ENODEV;
2397
2398 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2399 copy_cpu_funcs(&core_params.funcs);
2400 hwp_active++;
2401 intel_pstate.attr = hwp_cpufreq_attrs;
2402 goto hwp_cpu_matched;
2403 }
2404
2405 id = x86_match_cpu(intel_pstate_cpu_ids);
2406 if (!id)
2407 return -ENODEV;
2408
2409 cpu_def = (struct cpu_defaults *)id->driver_data;
2410
2411 copy_pid_params(&cpu_def->pid_policy);
2412 copy_cpu_funcs(&cpu_def->funcs);
2413
2414 if (intel_pstate_msrs_not_valid())
2415 return -ENODEV;
2416
2417 hwp_cpu_matched:
2418 /*
2419 * The Intel pstate driver will be ignored if the platform
2420 * firmware has its own power management modes.
2421 */
2422 if (intel_pstate_platform_pwr_mgmt_exists())
2423 return -ENODEV;
2424
2425 pr_info("Intel P-state driver initializing\n");
2426
2427 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2428 if (!all_cpu_data)
2429 return -ENOMEM;
2430
2431 if (!hwp_active && hwp_only)
2432 goto out;
2433
2434 intel_pstate_request_control_from_smm();
2435
2436 rc = cpufreq_register_driver(intel_pstate_driver);
2437 if (rc)
2438 goto out;
2439
2440 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2441 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2442 intel_pstate_debug_expose_params();
2443
2444 intel_pstate_sysfs_expose_params();
2445
2446 if (hwp_active)
2447 pr_info("HWP enabled\n");
2448
2449 return rc;
2450 out:
2451 get_online_cpus();
2452 for_each_online_cpu(cpu) {
2453 if (all_cpu_data[cpu]) {
2454 if (intel_pstate_driver == &intel_pstate)
2455 intel_pstate_clear_update_util_hook(cpu);
2456
2457 kfree(all_cpu_data[cpu]);
2458 }
2459 }
2460
2461 put_online_cpus();
2462 vfree(all_cpu_data);
2463 return -ENODEV;
2464 }
2465 device_initcall(intel_pstate_init);
2466
2467 static int __init intel_pstate_setup(char *str)
2468 {
2469 if (!str)
2470 return -EINVAL;
2471
2472 if (!strcmp(str, "disable")) {
2473 no_load = 1;
2474 } else if (!strcmp(str, "passive")) {
2475 pr_info("Passive mode enabled\n");
2476 intel_pstate_driver = &intel_cpufreq;
2477 no_hwp = 1;
2478 }
2479 if (!strcmp(str, "no_hwp")) {
2480 pr_info("HWP disabled\n");
2481 no_hwp = 1;
2482 }
2483 if (!strcmp(str, "force"))
2484 force_load = 1;
2485 if (!strcmp(str, "hwp_only"))
2486 hwp_only = 1;
2487 if (!strcmp(str, "per_cpu_perf_limits"))
2488 per_cpu_limits = true;
2489
2490 #ifdef CONFIG_ACPI
2491 if (!strcmp(str, "support_acpi_ppc"))
2492 acpi_ppc = true;
2493 #endif
2494
2495 return 0;
2496 }
2497 early_param("intel_pstate", intel_pstate_setup);
2498
2499 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2500 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2501 MODULE_LICENSE("GPL");
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