2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x
, int32_t y
)
58 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
61 static inline int32_t div_fp(s64 x
, s64 y
)
63 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
66 static inline int ceiling_fp(int32_t x
)
71 mask
= (1 << FRAC_BITS
) - 1;
77 static inline u64
mul_ext_fp(u64 x
, u64 y
)
79 return (x
* y
) >> EXT_FRAC_BITS
;
82 static inline u64
div_ext_fp(u64 x
, u64 y
)
84 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
88 * struct sample - Store performance sample
89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
90 * performance during last sample period
91 * @busy_scaled: Scaled busy value which is used to calculate next
92 * P state. This can be different than core_avg_perf
93 * to account for cpu idle period
94 * @aperf: Difference of actual performance frequency clock count
95 * read from APERF MSR between last and current sample
96 * @mperf: Difference of maximum performance frequency clock count
97 * read from MPERF MSR between last and current sample
98 * @tsc: Difference of time stamp counter between last and
100 * @time: Current time from scheduler
102 * This structure is used in the cpudata structure to store performance sample
103 * data for choosing next P State.
106 int32_t core_avg_perf
;
115 * struct pstate_data - Store P state data
116 * @current_pstate: Current requested P state
117 * @min_pstate: Min P state possible for this platform
118 * @max_pstate: Max P state possible for this platform
119 * @max_pstate_physical:This is physical Max P state for a processor
120 * This can be higher than the max_pstate which can
121 * be limited by platform thermal design power limits
122 * @scaling: Scaling factor to convert frequency to cpufreq
124 * @turbo_pstate: Max Turbo P state possible for this platform
125 * @max_freq: @max_pstate frequency in cpufreq units
126 * @turbo_freq: @turbo_pstate frequency in cpufreq units
128 * Stores the per cpu model P state limits and current P state.
134 int max_pstate_physical
;
137 unsigned int max_freq
;
138 unsigned int turbo_freq
;
142 * struct vid_data - Stores voltage information data
143 * @min: VID data for this platform corresponding to
145 * @max: VID data corresponding to the highest P State.
146 * @turbo: VID data for turbo P state
147 * @ratio: Ratio of (vid max - vid min) /
148 * (max P state - Min P State)
150 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
151 * This data is used in Atom platforms, where in addition to target P state,
152 * the voltage data needs to be specified to select next P State.
162 * struct _pid - Stores PID data
163 * @setpoint: Target set point for busyness or performance
164 * @integral: Storage for accumulated error values
165 * @p_gain: PID proportional gain
166 * @i_gain: PID integral gain
167 * @d_gain: PID derivative gain
168 * @deadband: PID deadband
169 * @last_err: Last error storage for integral part of PID calculation
171 * Stores PID coefficients and last error for PID controller.
184 * struct perf_limits - Store user and policy limits
185 * @no_turbo: User requested turbo state from intel_pstate sysfs
186 * @turbo_disabled: Platform turbo status either from msr
187 * MSR_IA32_MISC_ENABLE or when maximum available pstate
188 * matches the maximum turbo pstate
189 * @max_perf_pct: Effective maximum performance limit in percentage, this
190 * is minimum of either limits enforced by cpufreq policy
191 * or limits from user set limits via intel_pstate sysfs
192 * @min_perf_pct: Effective minimum performance limit in percentage, this
193 * is maximum of either limits enforced by cpufreq policy
194 * or limits from user set limits via intel_pstate sysfs
195 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
196 * This value is used to limit max pstate
197 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
198 * This value is used to limit min pstate
199 * @max_policy_pct: The maximum performance in percentage enforced by
200 * cpufreq setpolicy interface
201 * @max_sysfs_pct: The maximum performance in percentage enforced by
202 * intel pstate sysfs interface, unused when per cpu
203 * controls are enforced
204 * @min_policy_pct: The minimum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @min_sysfs_pct: The minimum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
210 * Storage for user and policy defined limits.
226 * struct cpudata - Per CPU instance data storage
227 * @cpu: CPU number for this instance data
228 * @policy: CPUFreq policy value
229 * @update_util: CPUFreq utility callback information
230 * @update_util_set: CPUFreq utility callback is set
231 * @iowait_boost: iowait-related boost fraction
232 * @last_update: Time of the last update.
233 * @pstate: Stores P state limits for this CPU
234 * @vid: Stores VID limits for this CPU
235 * @pid: Stores PID parameters for this CPU
236 * @last_sample_time: Last Sample time
237 * @prev_aperf: Last APERF value read from APERF MSR
238 * @prev_mperf: Last MPERF value read from MPERF MSR
239 * @prev_tsc: Last timestamp counter (TSC) value
240 * @prev_cummulative_iowait: IO Wait time difference from last and
242 * @sample: Storage for storing last Sample data
243 * @perf_limits: Pointer to perf_limit unique to this CPU
244 * Not all field in the structure are applicable
245 * when per cpu controls are enforced
246 * @acpi_perf_data: Stores ACPI perf information read from _PSS
247 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
248 * @epp_powersave: Last saved HWP energy performance preference
249 * (EPP) or energy performance bias (EPB),
250 * when policy switched to performance
251 * @epp_policy: Last saved policy used to set EPP/EPB
252 * @epp_default: Power on default HWP energy performance
254 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
257 * This structure stores per CPU instance data for all CPUs.
263 struct update_util_data update_util
;
264 bool update_util_set
;
266 struct pstate_data pstate
;
271 u64 last_sample_time
;
275 u64 prev_cummulative_iowait
;
276 struct sample sample
;
277 struct perf_limits
*perf_limits
;
279 struct acpi_processor_performance acpi_perf_data
;
280 bool valid_pss_table
;
282 unsigned int iowait_boost
;
289 static struct cpudata
**all_cpu_data
;
292 * struct pstate_adjust_policy - Stores static PID configuration data
293 * @sample_rate_ms: PID calculation sample rate in ms
294 * @sample_rate_ns: Sample rate calculation in ns
295 * @deadband: PID deadband
296 * @setpoint: PID Setpoint
297 * @p_gain_pct: PID proportional gain
298 * @i_gain_pct: PID integral gain
299 * @d_gain_pct: PID derivative gain
301 * Stores per CPU model static PID configuration data.
303 struct pstate_adjust_policy
{
314 * struct pstate_funcs - Per CPU model specific callbacks
315 * @get_max: Callback to get maximum non turbo effective P state
316 * @get_max_physical: Callback to get maximum non turbo physical P state
317 * @get_min: Callback to get minimum P state
318 * @get_turbo: Callback to get turbo P state
319 * @get_scaling: Callback to get frequency scaling factor
320 * @get_val: Callback to convert P state to actual MSR write value
321 * @get_vid: Callback to get VID data for Atom platforms
322 * @get_target_pstate: Callback to a function to calculate next P state to use
324 * Core and Atom CPU models have different way to get P State limits. This
325 * structure is used to store those callbacks.
327 struct pstate_funcs
{
328 int (*get_max
)(void);
329 int (*get_max_physical
)(void);
330 int (*get_min
)(void);
331 int (*get_turbo
)(void);
332 int (*get_scaling
)(void);
333 u64 (*get_val
)(struct cpudata
*, int pstate
);
334 void (*get_vid
)(struct cpudata
*);
335 int32_t (*get_target_pstate
)(struct cpudata
*);
339 * struct cpu_defaults- Per CPU model default config data
340 * @pid_policy: PID config data
341 * @funcs: Callback function data
343 struct cpu_defaults
{
344 struct pstate_adjust_policy pid_policy
;
345 struct pstate_funcs funcs
;
348 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
349 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
351 static struct pstate_adjust_policy pid_params __read_mostly
;
352 static struct pstate_funcs pstate_funcs __read_mostly
;
353 static int hwp_active __read_mostly
;
354 static bool per_cpu_limits __read_mostly
;
356 static bool driver_registered __read_mostly
;
359 static bool acpi_ppc
;
362 static struct perf_limits performance_limits
;
363 static struct perf_limits powersave_limits
;
364 static struct perf_limits
*limits
;
366 static void intel_pstate_init_limits(struct perf_limits
*limits
)
368 memset(limits
, 0, sizeof(*limits
));
369 limits
->max_perf_pct
= 100;
370 limits
->max_perf
= int_ext_tofp(1);
371 limits
->max_policy_pct
= 100;
372 limits
->max_sysfs_pct
= 100;
375 static void intel_pstate_set_performance_limits(struct perf_limits
*limits
)
377 intel_pstate_init_limits(limits
);
378 limits
->min_perf_pct
= 100;
379 limits
->min_perf
= int_ext_tofp(1);
382 static DEFINE_MUTEX(intel_pstate_driver_lock
);
383 static DEFINE_MUTEX(intel_pstate_limits_lock
);
387 static bool intel_pstate_get_ppc_enable_status(void)
389 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
390 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
396 #ifdef CONFIG_ACPI_CPPC_LIB
398 /* The work item is needed to avoid CPU hotplug locking issues */
399 static void intel_pstste_sched_itmt_work_fn(struct work_struct
*work
)
401 sched_set_itmt_support();
404 static DECLARE_WORK(sched_itmt_work
, intel_pstste_sched_itmt_work_fn
);
406 static void intel_pstate_set_itmt_prio(int cpu
)
408 struct cppc_perf_caps cppc_perf
;
409 static u32 max_highest_perf
= 0, min_highest_perf
= U32_MAX
;
412 ret
= cppc_get_perf_caps(cpu
, &cppc_perf
);
417 * The priorities can be set regardless of whether or not
418 * sched_set_itmt_support(true) has been called and it is valid to
419 * update them at any time after it has been called.
421 sched_set_itmt_core_prio(cppc_perf
.highest_perf
, cpu
);
423 if (max_highest_perf
<= min_highest_perf
) {
424 if (cppc_perf
.highest_perf
> max_highest_perf
)
425 max_highest_perf
= cppc_perf
.highest_perf
;
427 if (cppc_perf
.highest_perf
< min_highest_perf
)
428 min_highest_perf
= cppc_perf
.highest_perf
;
430 if (max_highest_perf
> min_highest_perf
) {
432 * This code can be run during CPU online under the
433 * CPU hotplug locks, so sched_set_itmt_support()
434 * cannot be called from here. Queue up a work item
437 schedule_work(&sched_itmt_work
);
442 static void intel_pstate_set_itmt_prio(int cpu
)
447 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
454 intel_pstate_set_itmt_prio(policy
->cpu
);
458 if (!intel_pstate_get_ppc_enable_status())
461 cpu
= all_cpu_data
[policy
->cpu
];
463 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
469 * Check if the control value in _PSS is for PERF_CTL MSR, which should
470 * guarantee that the states returned by it map to the states in our
473 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
474 ACPI_ADR_SPACE_FIXED_HARDWARE
)
478 * If there is only one entry _PSS, simply ignore _PSS and continue as
479 * usual without taking _PSS into account
481 if (cpu
->acpi_perf_data
.state_count
< 2)
484 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
485 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
486 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
487 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
488 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
489 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
490 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
494 * The _PSS table doesn't contain whole turbo frequency range.
495 * This just contains +1 MHZ above the max non turbo frequency,
496 * with control value corresponding to max turbo ratio. But
497 * when cpufreq set policy is called, it will call with this
498 * max frequency, which will cause a reduced performance as
499 * this driver uses real max turbo frequency as the max
500 * frequency. So correct this frequency in _PSS table to
501 * correct max turbo frequency based on the turbo state.
502 * Also need to convert to MHz as _PSS freq is in MHz.
504 if (!limits
->turbo_disabled
)
505 cpu
->acpi_perf_data
.states
[0].core_frequency
=
506 policy
->cpuinfo
.max_freq
/ 1000;
507 cpu
->valid_pss_table
= true;
508 pr_debug("_PPC limits will be enforced\n");
513 cpu
->valid_pss_table
= false;
514 acpi_processor_unregister_performance(policy
->cpu
);
517 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
521 cpu
= all_cpu_data
[policy
->cpu
];
522 if (!cpu
->valid_pss_table
)
525 acpi_processor_unregister_performance(policy
->cpu
);
528 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
532 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
537 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
538 int deadband
, int integral
) {
539 pid
->setpoint
= int_tofp(setpoint
);
540 pid
->deadband
= int_tofp(deadband
);
541 pid
->integral
= int_tofp(integral
);
542 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
545 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
547 pid
->p_gain
= div_fp(percent
, 100);
550 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
552 pid
->i_gain
= div_fp(percent
, 100);
555 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
557 pid
->d_gain
= div_fp(percent
, 100);
560 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
563 int32_t pterm
, dterm
, fp_error
;
564 int32_t integral_limit
;
566 fp_error
= pid
->setpoint
- busy
;
568 if (abs(fp_error
) <= pid
->deadband
)
571 pterm
= mul_fp(pid
->p_gain
, fp_error
);
573 pid
->integral
+= fp_error
;
576 * We limit the integral here so that it will never
577 * get higher than 30. This prevents it from becoming
578 * too large an input over long periods of time and allows
579 * it to get factored out sooner.
581 * The value of 30 was chosen through experimentation.
583 integral_limit
= int_tofp(30);
584 if (pid
->integral
> integral_limit
)
585 pid
->integral
= integral_limit
;
586 if (pid
->integral
< -integral_limit
)
587 pid
->integral
= -integral_limit
;
589 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
590 pid
->last_err
= fp_error
;
592 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
593 result
= result
+ (1 << (FRAC_BITS
-1));
594 return (signed int)fp_toint(result
);
597 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
599 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
600 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
601 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
603 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
606 static inline void intel_pstate_reset_all_pid(void)
610 for_each_online_cpu(cpu
) {
611 if (all_cpu_data
[cpu
])
612 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
616 static inline void update_turbo_state(void)
621 cpu
= all_cpu_data
[0];
622 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
623 limits
->turbo_disabled
=
624 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
625 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
628 static s16
intel_pstate_get_epb(struct cpudata
*cpu_data
)
633 if (!static_cpu_has(X86_FEATURE_EPB
))
636 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
640 return (s16
)(epb
& 0x0f);
643 static s16
intel_pstate_get_epp(struct cpudata
*cpu_data
, u64 hwp_req_data
)
647 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
649 * When hwp_req_data is 0, means that caller didn't read
650 * MSR_HWP_REQUEST, so need to read and get EPP.
653 epp
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
,
658 epp
= (hwp_req_data
>> 24) & 0xff;
660 /* When there is no EPP present, HWP uses EPB settings */
661 epp
= intel_pstate_get_epb(cpu_data
);
667 static int intel_pstate_set_epb(int cpu
, s16 pref
)
672 if (!static_cpu_has(X86_FEATURE_EPB
))
675 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
679 epb
= (epb
& ~0x0f) | pref
;
680 wrmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, epb
);
686 * EPP/EPB display strings corresponding to EPP index in the
687 * energy_perf_strings[]
689 *-------------------------------------
692 * 2 balance_performance
696 static const char * const energy_perf_strings
[] = {
699 "balance_performance",
705 static int intel_pstate_get_energy_pref_index(struct cpudata
*cpu_data
)
710 epp
= intel_pstate_get_epp(cpu_data
, 0);
714 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
717 * 0x00-0x3F : Performance
718 * 0x40-0x7F : Balance performance
719 * 0x80-0xBF : Balance power
721 * The EPP is a 8 bit value, but our ranges restrict the
722 * value which can be set. Here only using top two bits
725 index
= (epp
>> 6) + 1;
726 } else if (static_cpu_has(X86_FEATURE_EPB
)) {
729 * 0x00-0x03 : Performance
730 * 0x04-0x07 : Balance performance
731 * 0x08-0x0B : Balance power
733 * The EPB is a 4 bit value, but our ranges restrict the
734 * value which can be set. Here only using top two bits
737 index
= (epp
>> 2) + 1;
743 static int intel_pstate_set_energy_pref_index(struct cpudata
*cpu_data
,
750 epp
= cpu_data
->epp_default
;
752 mutex_lock(&intel_pstate_limits_lock
);
754 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
757 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, &value
);
761 value
&= ~GENMASK_ULL(31, 24);
764 * If epp is not default, convert from index into
765 * energy_perf_strings to epp value, by shifting 6
766 * bits left to use only top two bits in epp.
767 * The resultant epp need to shifted by 24 bits to
768 * epp position in MSR_HWP_REQUEST.
771 epp
= (pref_index
- 1) << 6;
773 value
|= (u64
)epp
<< 24;
774 ret
= wrmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, value
);
777 epp
= (pref_index
- 1) << 2;
778 ret
= intel_pstate_set_epb(cpu_data
->cpu
, epp
);
781 mutex_unlock(&intel_pstate_limits_lock
);
786 static ssize_t
show_energy_performance_available_preferences(
787 struct cpufreq_policy
*policy
, char *buf
)
792 while (energy_perf_strings
[i
] != NULL
)
793 ret
+= sprintf(&buf
[ret
], "%s ", energy_perf_strings
[i
++]);
795 ret
+= sprintf(&buf
[ret
], "\n");
800 cpufreq_freq_attr_ro(energy_performance_available_preferences
);
802 static ssize_t
store_energy_performance_preference(
803 struct cpufreq_policy
*policy
, const char *buf
, size_t count
)
805 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
806 char str_preference
[21];
809 ret
= sscanf(buf
, "%20s", str_preference
);
813 while (energy_perf_strings
[i
] != NULL
) {
814 if (!strcmp(str_preference
, energy_perf_strings
[i
])) {
815 intel_pstate_set_energy_pref_index(cpu_data
, i
);
824 static ssize_t
show_energy_performance_preference(
825 struct cpufreq_policy
*policy
, char *buf
)
827 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
830 preference
= intel_pstate_get_energy_pref_index(cpu_data
);
834 return sprintf(buf
, "%s\n", energy_perf_strings
[preference
]);
837 cpufreq_freq_attr_rw(energy_performance_preference
);
839 static struct freq_attr
*hwp_cpufreq_attrs
[] = {
840 &energy_performance_preference
,
841 &energy_performance_available_preferences
,
845 static void intel_pstate_hwp_set(struct cpufreq_policy
*policy
)
847 int min
, hw_min
, max
, hw_max
, cpu
, range
, adj_range
;
848 struct perf_limits
*perf_limits
= limits
;
851 for_each_cpu(cpu
, policy
->cpus
) {
852 int max_perf_pct
, min_perf_pct
;
853 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
857 perf_limits
= all_cpu_data
[cpu
]->perf_limits
;
859 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
860 hw_min
= HWP_LOWEST_PERF(cap
);
861 if (limits
->no_turbo
)
862 hw_max
= HWP_GUARANTEED_PERF(cap
);
864 hw_max
= HWP_HIGHEST_PERF(cap
);
865 range
= hw_max
- hw_min
;
867 max_perf_pct
= perf_limits
->max_perf_pct
;
868 min_perf_pct
= perf_limits
->min_perf_pct
;
870 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
871 adj_range
= min_perf_pct
* range
/ 100;
872 min
= hw_min
+ adj_range
;
873 value
&= ~HWP_MIN_PERF(~0L);
874 value
|= HWP_MIN_PERF(min
);
876 adj_range
= max_perf_pct
* range
/ 100;
877 max
= hw_min
+ adj_range
;
879 value
&= ~HWP_MAX_PERF(~0L);
880 value
|= HWP_MAX_PERF(max
);
882 if (cpu_data
->epp_policy
== cpu_data
->policy
)
885 cpu_data
->epp_policy
= cpu_data
->policy
;
887 if (cpu_data
->epp_saved
>= 0) {
888 epp
= cpu_data
->epp_saved
;
889 cpu_data
->epp_saved
= -EINVAL
;
893 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
894 epp
= intel_pstate_get_epp(cpu_data
, value
);
895 cpu_data
->epp_powersave
= epp
;
896 /* If EPP read was failed, then don't try to write */
903 /* skip setting EPP, when saved value is invalid */
904 if (cpu_data
->epp_powersave
< 0)
908 * No need to restore EPP when it is not zero. This
910 * - Policy is not changed
911 * - user has manually changed
912 * - Error reading EPB
914 epp
= intel_pstate_get_epp(cpu_data
, value
);
918 epp
= cpu_data
->epp_powersave
;
921 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
922 value
&= ~GENMASK_ULL(31, 24);
923 value
|= (u64
)epp
<< 24;
925 intel_pstate_set_epb(cpu
, epp
);
928 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
932 static int intel_pstate_hwp_set_policy(struct cpufreq_policy
*policy
)
935 intel_pstate_hwp_set(policy
);
940 static int intel_pstate_hwp_save_state(struct cpufreq_policy
*policy
)
942 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
947 cpu_data
->epp_saved
= intel_pstate_get_epp(cpu_data
, 0);
952 static int intel_pstate_resume(struct cpufreq_policy
*policy
)
959 mutex_lock(&intel_pstate_limits_lock
);
961 all_cpu_data
[policy
->cpu
]->epp_policy
= 0;
963 ret
= intel_pstate_hwp_set_policy(policy
);
965 mutex_unlock(&intel_pstate_limits_lock
);
970 static void intel_pstate_update_policies(void)
974 for_each_possible_cpu(cpu
)
975 cpufreq_update_policy(cpu
);
978 /************************** debugfs begin ************************/
979 static int pid_param_set(void *data
, u64 val
)
982 intel_pstate_reset_all_pid();
986 static int pid_param_get(void *data
, u64
*val
)
991 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
993 static struct dentry
*debugfs_parent
;
998 struct dentry
*dentry
;
1001 static struct pid_param pid_files
[] = {
1002 {"sample_rate_ms", &pid_params
.sample_rate_ms
, },
1003 {"d_gain_pct", &pid_params
.d_gain_pct
, },
1004 {"i_gain_pct", &pid_params
.i_gain_pct
, },
1005 {"deadband", &pid_params
.deadband
, },
1006 {"setpoint", &pid_params
.setpoint
, },
1007 {"p_gain_pct", &pid_params
.p_gain_pct
, },
1011 static void intel_pstate_debug_expose_params(void)
1015 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
1016 if (IS_ERR_OR_NULL(debugfs_parent
))
1019 for (i
= 0; pid_files
[i
].name
; i
++) {
1020 struct dentry
*dentry
;
1022 dentry
= debugfs_create_file(pid_files
[i
].name
, 0660,
1023 debugfs_parent
, pid_files
[i
].value
,
1025 if (!IS_ERR(dentry
))
1026 pid_files
[i
].dentry
= dentry
;
1030 static void intel_pstate_debug_hide_params(void)
1034 if (IS_ERR_OR_NULL(debugfs_parent
))
1037 for (i
= 0; pid_files
[i
].name
; i
++) {
1038 debugfs_remove(pid_files
[i
].dentry
);
1039 pid_files
[i
].dentry
= NULL
;
1042 debugfs_remove(debugfs_parent
);
1043 debugfs_parent
= NULL
;
1046 /************************** debugfs end ************************/
1048 /************************** sysfs begin ************************/
1049 #define show_one(file_name, object) \
1050 static ssize_t show_##file_name \
1051 (struct kobject *kobj, struct attribute *attr, char *buf) \
1053 return sprintf(buf, "%u\n", limits->object); \
1056 static ssize_t
intel_pstate_show_status(char *buf
);
1057 static int intel_pstate_update_status(const char *buf
, size_t size
);
1059 static ssize_t
show_status(struct kobject
*kobj
,
1060 struct attribute
*attr
, char *buf
)
1064 mutex_lock(&intel_pstate_driver_lock
);
1065 ret
= intel_pstate_show_status(buf
);
1066 mutex_unlock(&intel_pstate_driver_lock
);
1071 static ssize_t
store_status(struct kobject
*a
, struct attribute
*b
,
1072 const char *buf
, size_t count
)
1074 char *p
= memchr(buf
, '\n', count
);
1077 mutex_lock(&intel_pstate_driver_lock
);
1078 ret
= intel_pstate_update_status(buf
, p
? p
- buf
: count
);
1079 mutex_unlock(&intel_pstate_driver_lock
);
1081 return ret
< 0 ? ret
: count
;
1084 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
1085 struct attribute
*attr
, char *buf
)
1087 struct cpudata
*cpu
;
1088 int total
, no_turbo
, turbo_pct
;
1091 mutex_lock(&intel_pstate_driver_lock
);
1093 if (!driver_registered
) {
1094 mutex_unlock(&intel_pstate_driver_lock
);
1098 cpu
= all_cpu_data
[0];
1100 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1101 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
1102 turbo_fp
= div_fp(no_turbo
, total
);
1103 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
1105 mutex_unlock(&intel_pstate_driver_lock
);
1107 return sprintf(buf
, "%u\n", turbo_pct
);
1110 static ssize_t
show_num_pstates(struct kobject
*kobj
,
1111 struct attribute
*attr
, char *buf
)
1113 struct cpudata
*cpu
;
1116 mutex_lock(&intel_pstate_driver_lock
);
1118 if (!driver_registered
) {
1119 mutex_unlock(&intel_pstate_driver_lock
);
1123 cpu
= all_cpu_data
[0];
1124 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1126 mutex_unlock(&intel_pstate_driver_lock
);
1128 return sprintf(buf
, "%u\n", total
);
1131 static ssize_t
show_no_turbo(struct kobject
*kobj
,
1132 struct attribute
*attr
, char *buf
)
1136 mutex_lock(&intel_pstate_driver_lock
);
1138 if (!driver_registered
) {
1139 mutex_unlock(&intel_pstate_driver_lock
);
1143 update_turbo_state();
1144 if (limits
->turbo_disabled
)
1145 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
1147 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
1149 mutex_unlock(&intel_pstate_driver_lock
);
1154 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
1155 const char *buf
, size_t count
)
1160 ret
= sscanf(buf
, "%u", &input
);
1164 mutex_lock(&intel_pstate_driver_lock
);
1166 if (!driver_registered
) {
1167 mutex_unlock(&intel_pstate_driver_lock
);
1171 mutex_lock(&intel_pstate_limits_lock
);
1173 update_turbo_state();
1174 if (limits
->turbo_disabled
) {
1175 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1176 mutex_unlock(&intel_pstate_limits_lock
);
1177 mutex_unlock(&intel_pstate_driver_lock
);
1181 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
1183 mutex_unlock(&intel_pstate_limits_lock
);
1185 intel_pstate_update_policies();
1187 mutex_unlock(&intel_pstate_driver_lock
);
1192 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
1193 const char *buf
, size_t count
)
1198 ret
= sscanf(buf
, "%u", &input
);
1202 mutex_lock(&intel_pstate_driver_lock
);
1204 if (!driver_registered
) {
1205 mutex_unlock(&intel_pstate_driver_lock
);
1209 mutex_lock(&intel_pstate_limits_lock
);
1211 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1212 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1213 limits
->max_sysfs_pct
);
1214 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1215 limits
->max_perf_pct
);
1216 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
1217 limits
->max_perf_pct
);
1218 limits
->max_perf
= div_ext_fp(limits
->max_perf_pct
, 100);
1220 mutex_unlock(&intel_pstate_limits_lock
);
1222 intel_pstate_update_policies();
1224 mutex_unlock(&intel_pstate_driver_lock
);
1229 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
1230 const char *buf
, size_t count
)
1235 ret
= sscanf(buf
, "%u", &input
);
1239 mutex_lock(&intel_pstate_driver_lock
);
1241 if (!driver_registered
) {
1242 mutex_unlock(&intel_pstate_driver_lock
);
1246 mutex_lock(&intel_pstate_limits_lock
);
1248 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
1249 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1250 limits
->min_sysfs_pct
);
1251 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1252 limits
->min_perf_pct
);
1253 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
1254 limits
->min_perf_pct
);
1255 limits
->min_perf
= div_ext_fp(limits
->min_perf_pct
, 100);
1257 mutex_unlock(&intel_pstate_limits_lock
);
1259 intel_pstate_update_policies();
1261 mutex_unlock(&intel_pstate_driver_lock
);
1266 show_one(max_perf_pct
, max_perf_pct
);
1267 show_one(min_perf_pct
, min_perf_pct
);
1269 define_one_global_rw(status
);
1270 define_one_global_rw(no_turbo
);
1271 define_one_global_rw(max_perf_pct
);
1272 define_one_global_rw(min_perf_pct
);
1273 define_one_global_ro(turbo_pct
);
1274 define_one_global_ro(num_pstates
);
1276 static struct attribute
*intel_pstate_attributes
[] = {
1284 static struct attribute_group intel_pstate_attr_group
= {
1285 .attrs
= intel_pstate_attributes
,
1288 static void __init
intel_pstate_sysfs_expose_params(void)
1290 struct kobject
*intel_pstate_kobject
;
1293 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
1294 &cpu_subsys
.dev_root
->kobj
);
1295 if (WARN_ON(!intel_pstate_kobject
))
1298 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
1303 * If per cpu limits are enforced there are no global limits, so
1304 * return without creating max/min_perf_pct attributes
1309 rc
= sysfs_create_file(intel_pstate_kobject
, &max_perf_pct
.attr
);
1312 rc
= sysfs_create_file(intel_pstate_kobject
, &min_perf_pct
.attr
);
1316 /************************** sysfs end ************************/
1318 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
1320 /* First disable HWP notification interrupt as we don't process them */
1321 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
1322 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
1324 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
1325 cpudata
->epp_policy
= 0;
1326 if (cpudata
->epp_default
== -EINVAL
)
1327 cpudata
->epp_default
= intel_pstate_get_epp(cpudata
, 0);
1330 #define MSR_IA32_POWER_CTL_BIT_EE 19
1332 /* Disable energy efficiency optimization */
1333 static void intel_pstate_disable_ee(int cpu
)
1338 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, &power_ctl
);
1342 if (!(power_ctl
& BIT(MSR_IA32_POWER_CTL_BIT_EE
))) {
1343 pr_info("Disabling energy efficiency optimization\n");
1344 power_ctl
|= BIT(MSR_IA32_POWER_CTL_BIT_EE
);
1345 wrmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, power_ctl
);
1349 static int atom_get_min_pstate(void)
1353 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1354 return (value
>> 8) & 0x7F;
1357 static int atom_get_max_pstate(void)
1361 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1362 return (value
>> 16) & 0x7F;
1365 static int atom_get_turbo_pstate(void)
1369 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS
, value
);
1370 return value
& 0x7F;
1373 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
1379 val
= (u64
)pstate
<< 8;
1380 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1381 val
|= (u64
)1 << 32;
1383 vid_fp
= cpudata
->vid
.min
+ mul_fp(
1384 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
1385 cpudata
->vid
.ratio
);
1387 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
1388 vid
= ceiling_fp(vid_fp
);
1390 if (pstate
> cpudata
->pstate
.max_pstate
)
1391 vid
= cpudata
->vid
.turbo
;
1396 static int silvermont_get_scaling(void)
1400 /* Defined in Table 35-6 from SDM (Sept 2015) */
1401 static int silvermont_freq_table
[] = {
1402 83300, 100000, 133300, 116700, 80000};
1404 rdmsrl(MSR_FSB_FREQ
, value
);
1408 return silvermont_freq_table
[i
];
1411 static int airmont_get_scaling(void)
1415 /* Defined in Table 35-10 from SDM (Sept 2015) */
1416 static int airmont_freq_table
[] = {
1417 83300, 100000, 133300, 116700, 80000,
1418 93300, 90000, 88900, 87500};
1420 rdmsrl(MSR_FSB_FREQ
, value
);
1424 return airmont_freq_table
[i
];
1427 static void atom_get_vid(struct cpudata
*cpudata
)
1431 rdmsrl(MSR_ATOM_CORE_VIDS
, value
);
1432 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
1433 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
1434 cpudata
->vid
.ratio
= div_fp(
1435 cpudata
->vid
.max
- cpudata
->vid
.min
,
1436 int_tofp(cpudata
->pstate
.max_pstate
-
1437 cpudata
->pstate
.min_pstate
));
1439 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS
, value
);
1440 cpudata
->vid
.turbo
= value
& 0x7f;
1443 static int core_get_min_pstate(void)
1447 rdmsrl(MSR_PLATFORM_INFO
, value
);
1448 return (value
>> 40) & 0xFF;
1451 static int core_get_max_pstate_physical(void)
1455 rdmsrl(MSR_PLATFORM_INFO
, value
);
1456 return (value
>> 8) & 0xFF;
1459 static int core_get_tdp_ratio(u64 plat_info
)
1461 /* Check how many TDP levels present */
1462 if (plat_info
& 0x600000000) {
1468 /* Get the TDP level (0, 1, 2) to get ratios */
1469 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
1473 /* TDP MSR are continuous starting at 0x648 */
1474 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x03);
1475 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
1479 /* For level 1 and 2, bits[23:16] contain the ratio */
1480 if (tdp_ctrl
& 0x03)
1483 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
1484 pr_debug("tdp_ratio %x\n", (int)tdp_ratio
);
1486 return (int)tdp_ratio
;
1492 static int core_get_max_pstate(void)
1500 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
1501 max_pstate
= (plat_info
>> 8) & 0xFF;
1503 tdp_ratio
= core_get_tdp_ratio(plat_info
);
1508 /* Turbo activation ratio is not used on HWP platforms */
1512 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
1516 /* Do some sanity checking for safety */
1517 tar_levels
= tar
& 0xff;
1518 if (tdp_ratio
- 1 == tar_levels
) {
1519 max_pstate
= tar_levels
;
1520 pr_debug("max_pstate=TAC %x\n", max_pstate
);
1527 static int core_get_turbo_pstate(void)
1532 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1533 nont
= core_get_max_pstate();
1534 ret
= (value
) & 255;
1540 static inline int core_get_scaling(void)
1545 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1549 val
= (u64
)pstate
<< 8;
1550 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1551 val
|= (u64
)1 << 32;
1556 static int knl_get_turbo_pstate(void)
1561 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1562 nont
= core_get_max_pstate();
1563 ret
= (((value
) >> 8) & 0xFF);
1569 static struct cpu_defaults core_params
= {
1571 .sample_rate_ms
= 10,
1579 .get_max
= core_get_max_pstate
,
1580 .get_max_physical
= core_get_max_pstate_physical
,
1581 .get_min
= core_get_min_pstate
,
1582 .get_turbo
= core_get_turbo_pstate
,
1583 .get_scaling
= core_get_scaling
,
1584 .get_val
= core_get_val
,
1585 .get_target_pstate
= get_target_pstate_use_performance
,
1589 static const struct cpu_defaults silvermont_params
= {
1591 .sample_rate_ms
= 10,
1599 .get_max
= atom_get_max_pstate
,
1600 .get_max_physical
= atom_get_max_pstate
,
1601 .get_min
= atom_get_min_pstate
,
1602 .get_turbo
= atom_get_turbo_pstate
,
1603 .get_val
= atom_get_val
,
1604 .get_scaling
= silvermont_get_scaling
,
1605 .get_vid
= atom_get_vid
,
1606 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1610 static const struct cpu_defaults airmont_params
= {
1612 .sample_rate_ms
= 10,
1620 .get_max
= atom_get_max_pstate
,
1621 .get_max_physical
= atom_get_max_pstate
,
1622 .get_min
= atom_get_min_pstate
,
1623 .get_turbo
= atom_get_turbo_pstate
,
1624 .get_val
= atom_get_val
,
1625 .get_scaling
= airmont_get_scaling
,
1626 .get_vid
= atom_get_vid
,
1627 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1631 static const struct cpu_defaults knl_params
= {
1633 .sample_rate_ms
= 10,
1641 .get_max
= core_get_max_pstate
,
1642 .get_max_physical
= core_get_max_pstate_physical
,
1643 .get_min
= core_get_min_pstate
,
1644 .get_turbo
= knl_get_turbo_pstate
,
1645 .get_scaling
= core_get_scaling
,
1646 .get_val
= core_get_val
,
1647 .get_target_pstate
= get_target_pstate_use_performance
,
1651 static const struct cpu_defaults bxt_params
= {
1653 .sample_rate_ms
= 10,
1661 .get_max
= core_get_max_pstate
,
1662 .get_max_physical
= core_get_max_pstate_physical
,
1663 .get_min
= core_get_min_pstate
,
1664 .get_turbo
= core_get_turbo_pstate
,
1665 .get_scaling
= core_get_scaling
,
1666 .get_val
= core_get_val
,
1667 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1671 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
1673 int max_perf
= cpu
->pstate
.turbo_pstate
;
1676 struct perf_limits
*perf_limits
= limits
;
1678 if (limits
->no_turbo
|| limits
->turbo_disabled
)
1679 max_perf
= cpu
->pstate
.max_pstate
;
1682 perf_limits
= cpu
->perf_limits
;
1685 * performance can be limited by user through sysfs, by cpufreq
1686 * policy, or by cpu specific default values determined through
1689 max_perf_adj
= fp_ext_toint(max_perf
* perf_limits
->max_perf
);
1690 *max
= clamp_t(int, max_perf_adj
,
1691 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
1693 min_perf
= fp_ext_toint(max_perf
* perf_limits
->min_perf
);
1694 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
1697 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1699 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1700 cpu
->pstate
.current_pstate
= pstate
;
1702 * Generally, there is no guarantee that this code will always run on
1703 * the CPU being updated, so force the register update to run on the
1706 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1707 pstate_funcs
.get_val(cpu
, pstate
));
1710 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1712 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1715 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1717 int min_pstate
, max_pstate
;
1719 update_turbo_state();
1720 intel_pstate_get_min_max(cpu
, &min_pstate
, &max_pstate
);
1721 intel_pstate_set_pstate(cpu
, max_pstate
);
1724 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1726 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1727 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1728 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1729 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1730 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1731 cpu
->pstate
.max_freq
= cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
;
1732 cpu
->pstate
.turbo_freq
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1734 if (pstate_funcs
.get_vid
)
1735 pstate_funcs
.get_vid(cpu
);
1737 intel_pstate_set_min_pstate(cpu
);
1740 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1742 struct sample
*sample
= &cpu
->sample
;
1744 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1747 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1750 unsigned long flags
;
1753 local_irq_save(flags
);
1754 rdmsrl(MSR_IA32_APERF
, aperf
);
1755 rdmsrl(MSR_IA32_MPERF
, mperf
);
1757 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1758 local_irq_restore(flags
);
1761 local_irq_restore(flags
);
1763 cpu
->last_sample_time
= cpu
->sample
.time
;
1764 cpu
->sample
.time
= time
;
1765 cpu
->sample
.aperf
= aperf
;
1766 cpu
->sample
.mperf
= mperf
;
1767 cpu
->sample
.tsc
= tsc
;
1768 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1769 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1770 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1772 cpu
->prev_aperf
= aperf
;
1773 cpu
->prev_mperf
= mperf
;
1774 cpu
->prev_tsc
= tsc
;
1776 * First time this function is invoked in a given cycle, all of the
1777 * previous sample data fields are equal to zero or stale and they must
1778 * be populated with meaningful numbers for things to work, so assume
1779 * that sample.time will always be reset before setting the utilization
1780 * update hook and make the caller skip the sample then.
1782 return !!cpu
->last_sample_time
;
1785 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1787 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1788 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1791 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1793 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1794 cpu
->sample
.core_avg_perf
);
1797 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1799 struct sample
*sample
= &cpu
->sample
;
1800 int32_t busy_frac
, boost
;
1801 int target
, avg_pstate
;
1803 busy_frac
= div_fp(sample
->mperf
, sample
->tsc
);
1805 boost
= cpu
->iowait_boost
;
1806 cpu
->iowait_boost
>>= 1;
1808 if (busy_frac
< boost
)
1811 sample
->busy_scaled
= busy_frac
* 100;
1813 target
= limits
->no_turbo
|| limits
->turbo_disabled
?
1814 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1815 target
+= target
>> 2;
1816 target
= mul_fp(target
, busy_frac
);
1817 if (target
< cpu
->pstate
.min_pstate
)
1818 target
= cpu
->pstate
.min_pstate
;
1821 * If the average P-state during the previous cycle was higher than the
1822 * current target, add 50% of the difference to the target to reduce
1823 * possible performance oscillations and offset possible performance
1824 * loss related to moving the workload from one CPU to another within
1827 avg_pstate
= get_avg_pstate(cpu
);
1828 if (avg_pstate
> target
)
1829 target
+= (avg_pstate
- target
) >> 1;
1834 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1836 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1840 * perf_scaled is the ratio of the average P-state during the last
1841 * sampling period to the P-state requested last time (in percent).
1843 * That measures the system's response to the previous P-state
1846 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1847 current_pstate
= cpu
->pstate
.current_pstate
;
1848 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1849 div_fp(100 * max_pstate
, current_pstate
));
1852 * Since our utilization update callback will not run unless we are
1853 * in C0, check if the actual elapsed time is significantly greater (3x)
1854 * than our sample interval. If it is, then we were idle for a long
1855 * enough period of time to adjust our performance metric.
1857 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1858 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1859 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1860 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1862 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1863 if (sample_ratio
< int_tofp(1))
1867 cpu
->sample
.busy_scaled
= perf_scaled
;
1868 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1871 static int intel_pstate_prepare_request(struct cpudata
*cpu
, int pstate
)
1873 int max_perf
, min_perf
;
1875 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1876 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1877 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1881 static void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1883 pstate
= intel_pstate_prepare_request(cpu
, pstate
);
1884 if (pstate
== cpu
->pstate
.current_pstate
)
1887 cpu
->pstate
.current_pstate
= pstate
;
1888 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1891 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1893 int from
, target_pstate
;
1894 struct sample
*sample
;
1896 from
= cpu
->pstate
.current_pstate
;
1898 target_pstate
= cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
?
1899 cpu
->pstate
.turbo_pstate
: pstate_funcs
.get_target_pstate(cpu
);
1901 update_turbo_state();
1903 intel_pstate_update_pstate(cpu
, target_pstate
);
1905 sample
= &cpu
->sample
;
1906 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1907 fp_toint(sample
->busy_scaled
),
1909 cpu
->pstate
.current_pstate
,
1913 get_avg_frequency(cpu
),
1914 fp_toint(cpu
->iowait_boost
* 100));
1917 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1920 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1923 if (pstate_funcs
.get_target_pstate
== get_target_pstate_use_cpu_load
) {
1924 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1925 cpu
->iowait_boost
= int_tofp(1);
1926 } else if (cpu
->iowait_boost
) {
1927 /* Clear iowait_boost if the CPU may have been idle. */
1928 delta_ns
= time
- cpu
->last_update
;
1929 if (delta_ns
> TICK_NSEC
)
1930 cpu
->iowait_boost
= 0;
1932 cpu
->last_update
= time
;
1935 delta_ns
= time
- cpu
->sample
.time
;
1936 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1937 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1940 intel_pstate_calc_avg_perf(cpu
);
1942 intel_pstate_adjust_busy_pstate(cpu
);
1947 #define ICPU(model, policy) \
1948 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1949 (unsigned long)&policy }
1951 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1952 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_params
),
1953 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_params
),
1954 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_params
),
1955 ICPU(INTEL_FAM6_IVYBRIDGE
, core_params
),
1956 ICPU(INTEL_FAM6_HASWELL_CORE
, core_params
),
1957 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_params
),
1958 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_params
),
1959 ICPU(INTEL_FAM6_HASWELL_X
, core_params
),
1960 ICPU(INTEL_FAM6_HASWELL_ULT
, core_params
),
1961 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_params
),
1962 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_params
),
1963 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_params
),
1964 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_params
),
1965 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1966 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_params
),
1967 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1968 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_params
),
1969 ICPU(INTEL_FAM6_XEON_PHI_KNM
, knl_params
),
1970 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_params
),
1973 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1975 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1976 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_params
),
1977 ICPU(INTEL_FAM6_BROADWELL_X
, core_params
),
1978 ICPU(INTEL_FAM6_SKYLAKE_X
, core_params
),
1982 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids
[] = {
1983 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP
, core_params
),
1987 static int intel_pstate_init_cpu(unsigned int cpunum
)
1989 struct cpudata
*cpu
;
1991 cpu
= all_cpu_data
[cpunum
];
1994 unsigned int size
= sizeof(struct cpudata
);
1997 size
+= sizeof(struct perf_limits
);
1999 cpu
= kzalloc(size
, GFP_KERNEL
);
2003 all_cpu_data
[cpunum
] = cpu
;
2005 cpu
->perf_limits
= (struct perf_limits
*)(cpu
+ 1);
2007 cpu
->epp_default
= -EINVAL
;
2008 cpu
->epp_powersave
= -EINVAL
;
2009 cpu
->epp_saved
= -EINVAL
;
2012 cpu
= all_cpu_data
[cpunum
];
2017 const struct x86_cpu_id
*id
;
2019 id
= x86_match_cpu(intel_pstate_cpu_ee_disable_ids
);
2021 intel_pstate_disable_ee(cpunum
);
2023 intel_pstate_hwp_enable(cpu
);
2024 pid_params
.sample_rate_ms
= 50;
2025 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
2028 intel_pstate_get_cpu_pstates(cpu
);
2030 intel_pstate_busy_pid_reset(cpu
);
2032 pr_debug("controlling: cpu %d\n", cpunum
);
2037 static unsigned int intel_pstate_get(unsigned int cpu_num
)
2039 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2041 return cpu
? get_avg_frequency(cpu
) : 0;
2044 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
2046 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
2048 if (cpu
->update_util_set
)
2051 /* Prevent intel_pstate_update_util() from using stale data. */
2052 cpu
->sample
.time
= 0;
2053 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
2054 intel_pstate_update_util
);
2055 cpu
->update_util_set
= true;
2058 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
2060 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
2062 if (!cpu_data
->update_util_set
)
2065 cpufreq_remove_update_util_hook(cpu
);
2066 cpu_data
->update_util_set
= false;
2067 synchronize_sched();
2070 static void intel_pstate_update_perf_limits(struct cpufreq_policy
*policy
,
2071 struct perf_limits
*limits
)
2074 limits
->max_policy_pct
= DIV_ROUND_UP(policy
->max
* 100,
2075 policy
->cpuinfo
.max_freq
);
2076 limits
->max_policy_pct
= clamp_t(int, limits
->max_policy_pct
, 0, 100);
2077 if (policy
->max
== policy
->min
) {
2078 limits
->min_policy_pct
= limits
->max_policy_pct
;
2080 limits
->min_policy_pct
= DIV_ROUND_UP(policy
->min
* 100,
2081 policy
->cpuinfo
.max_freq
);
2082 limits
->min_policy_pct
= clamp_t(int, limits
->min_policy_pct
,
2086 /* Normalize user input to [min_policy_pct, max_policy_pct] */
2087 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
2088 limits
->min_sysfs_pct
);
2089 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
2090 limits
->min_perf_pct
);
2091 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
2092 limits
->max_sysfs_pct
);
2093 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
2094 limits
->max_perf_pct
);
2096 /* Make sure min_perf_pct <= max_perf_pct */
2097 limits
->min_perf_pct
= min(limits
->max_perf_pct
, limits
->min_perf_pct
);
2099 limits
->min_perf
= div_ext_fp(limits
->min_perf_pct
, 100);
2100 limits
->max_perf
= div_ext_fp(limits
->max_perf_pct
, 100);
2101 limits
->max_perf
= round_up(limits
->max_perf
, EXT_FRAC_BITS
);
2102 limits
->min_perf
= round_up(limits
->min_perf
, EXT_FRAC_BITS
);
2104 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy
->cpu
,
2105 limits
->max_perf_pct
, limits
->min_perf_pct
);
2108 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
2110 struct cpudata
*cpu
;
2111 struct perf_limits
*perf_limits
= NULL
;
2113 if (!policy
->cpuinfo
.max_freq
)
2116 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2117 policy
->cpuinfo
.max_freq
, policy
->max
);
2119 cpu
= all_cpu_data
[policy
->cpu
];
2120 cpu
->policy
= policy
->policy
;
2122 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
2123 policy
->max
< policy
->cpuinfo
.max_freq
&&
2124 policy
->max
> cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
) {
2125 pr_debug("policy->max > max non turbo frequency\n");
2126 policy
->max
= policy
->cpuinfo
.max_freq
;
2130 perf_limits
= cpu
->perf_limits
;
2132 mutex_lock(&intel_pstate_limits_lock
);
2134 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2136 limits
= &performance_limits
;
2137 perf_limits
= limits
;
2139 if (policy
->max
>= policy
->cpuinfo
.max_freq
&&
2140 !limits
->no_turbo
) {
2141 pr_debug("set performance\n");
2142 intel_pstate_set_performance_limits(perf_limits
);
2146 pr_debug("set powersave\n");
2148 limits
= &powersave_limits
;
2149 perf_limits
= limits
;
2154 intel_pstate_update_perf_limits(policy
, perf_limits
);
2156 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2158 * NOHZ_FULL CPUs need this as the governor callback may not
2159 * be invoked on them.
2161 intel_pstate_clear_update_util_hook(policy
->cpu
);
2162 intel_pstate_max_within_limits(cpu
);
2165 intel_pstate_set_update_util_hook(policy
->cpu
);
2167 intel_pstate_hwp_set_policy(policy
);
2169 mutex_unlock(&intel_pstate_limits_lock
);
2174 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
2176 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2177 struct perf_limits
*perf_limits
;
2179 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
2180 perf_limits
= &performance_limits
;
2182 perf_limits
= &powersave_limits
;
2184 update_turbo_state();
2185 policy
->cpuinfo
.max_freq
= perf_limits
->turbo_disabled
||
2186 perf_limits
->no_turbo
?
2187 cpu
->pstate
.max_freq
:
2188 cpu
->pstate
.turbo_freq
;
2190 cpufreq_verify_within_cpu_limits(policy
);
2192 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
2193 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
2196 /* When per-CPU limits are used, sysfs limits are not used */
2197 if (!per_cpu_limits
) {
2198 unsigned int max_freq
, min_freq
;
2200 max_freq
= policy
->cpuinfo
.max_freq
*
2201 limits
->max_sysfs_pct
/ 100;
2202 min_freq
= policy
->cpuinfo
.max_freq
*
2203 limits
->min_sysfs_pct
/ 100;
2204 cpufreq_verify_within_limits(policy
, min_freq
, max_freq
);
2210 static void intel_cpufreq_stop_cpu(struct cpufreq_policy
*policy
)
2212 intel_pstate_set_min_pstate(all_cpu_data
[policy
->cpu
]);
2215 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
2217 pr_debug("CPU %d exiting\n", policy
->cpu
);
2219 intel_pstate_clear_update_util_hook(policy
->cpu
);
2221 intel_pstate_hwp_save_state(policy
);
2223 intel_cpufreq_stop_cpu(policy
);
2226 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
2228 intel_pstate_exit_perf_limits(policy
);
2230 policy
->fast_switch_possible
= false;
2235 static int __intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2237 struct cpudata
*cpu
;
2240 rc
= intel_pstate_init_cpu(policy
->cpu
);
2244 cpu
= all_cpu_data
[policy
->cpu
];
2247 * We need sane value in the cpu->perf_limits, so inherit from global
2248 * perf_limits limits, which are seeded with values based on the
2249 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2252 memcpy(cpu
->perf_limits
, limits
, sizeof(struct perf_limits
));
2254 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2255 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
2257 /* cpuinfo and default policy values */
2258 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2259 update_turbo_state();
2260 policy
->cpuinfo
.max_freq
= limits
->turbo_disabled
?
2261 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
2262 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
2264 intel_pstate_init_acpi_perf_limits(policy
);
2265 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
2267 policy
->fast_switch_possible
= true;
2272 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2274 int ret
= __intel_pstate_cpu_init(policy
);
2279 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
2280 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
2281 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
2283 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
2288 static struct cpufreq_driver intel_pstate
= {
2289 .flags
= CPUFREQ_CONST_LOOPS
,
2290 .verify
= intel_pstate_verify_policy
,
2291 .setpolicy
= intel_pstate_set_policy
,
2292 .suspend
= intel_pstate_hwp_save_state
,
2293 .resume
= intel_pstate_resume
,
2294 .get
= intel_pstate_get
,
2295 .init
= intel_pstate_cpu_init
,
2296 .exit
= intel_pstate_cpu_exit
,
2297 .stop_cpu
= intel_pstate_stop_cpu
,
2298 .name
= "intel_pstate",
2301 static int intel_cpufreq_verify_policy(struct cpufreq_policy
*policy
)
2303 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2304 struct perf_limits
*perf_limits
= limits
;
2306 update_turbo_state();
2307 policy
->cpuinfo
.max_freq
= limits
->turbo_disabled
?
2308 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
2310 cpufreq_verify_within_cpu_limits(policy
);
2313 perf_limits
= cpu
->perf_limits
;
2315 mutex_lock(&intel_pstate_limits_lock
);
2317 intel_pstate_update_perf_limits(policy
, perf_limits
);
2319 mutex_unlock(&intel_pstate_limits_lock
);
2324 static unsigned int intel_cpufreq_turbo_update(struct cpudata
*cpu
,
2325 struct cpufreq_policy
*policy
,
2326 unsigned int target_freq
)
2328 unsigned int max_freq
;
2330 update_turbo_state();
2332 max_freq
= limits
->no_turbo
|| limits
->turbo_disabled
?
2333 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
2334 policy
->cpuinfo
.max_freq
= max_freq
;
2335 if (policy
->max
> max_freq
)
2336 policy
->max
= max_freq
;
2338 if (target_freq
> max_freq
)
2339 target_freq
= max_freq
;
2344 static int intel_cpufreq_target(struct cpufreq_policy
*policy
,
2345 unsigned int target_freq
,
2346 unsigned int relation
)
2348 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2349 struct cpufreq_freqs freqs
;
2352 freqs
.old
= policy
->cur
;
2353 freqs
.new = intel_cpufreq_turbo_update(cpu
, policy
, target_freq
);
2355 cpufreq_freq_transition_begin(policy
, &freqs
);
2357 case CPUFREQ_RELATION_L
:
2358 target_pstate
= DIV_ROUND_UP(freqs
.new, cpu
->pstate
.scaling
);
2360 case CPUFREQ_RELATION_H
:
2361 target_pstate
= freqs
.new / cpu
->pstate
.scaling
;
2364 target_pstate
= DIV_ROUND_CLOSEST(freqs
.new, cpu
->pstate
.scaling
);
2367 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2368 if (target_pstate
!= cpu
->pstate
.current_pstate
) {
2369 cpu
->pstate
.current_pstate
= target_pstate
;
2370 wrmsrl_on_cpu(policy
->cpu
, MSR_IA32_PERF_CTL
,
2371 pstate_funcs
.get_val(cpu
, target_pstate
));
2373 cpufreq_freq_transition_end(policy
, &freqs
, false);
2378 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy
*policy
,
2379 unsigned int target_freq
)
2381 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2384 target_freq
= intel_cpufreq_turbo_update(cpu
, policy
, target_freq
);
2385 target_pstate
= DIV_ROUND_UP(target_freq
, cpu
->pstate
.scaling
);
2386 intel_pstate_update_pstate(cpu
, target_pstate
);
2390 static int intel_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
2392 int ret
= __intel_pstate_cpu_init(policy
);
2397 policy
->cpuinfo
.transition_latency
= INTEL_CPUFREQ_TRANSITION_LATENCY
;
2398 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2399 policy
->cur
= policy
->cpuinfo
.min_freq
;
2404 static struct cpufreq_driver intel_cpufreq
= {
2405 .flags
= CPUFREQ_CONST_LOOPS
,
2406 .verify
= intel_cpufreq_verify_policy
,
2407 .target
= intel_cpufreq_target
,
2408 .fast_switch
= intel_cpufreq_fast_switch
,
2409 .init
= intel_cpufreq_cpu_init
,
2410 .exit
= intel_pstate_cpu_exit
,
2411 .stop_cpu
= intel_cpufreq_stop_cpu
,
2412 .name
= "intel_cpufreq",
2415 static struct cpufreq_driver
*intel_pstate_driver
= &intel_pstate
;
2417 static void intel_pstate_driver_cleanup(void)
2422 for_each_online_cpu(cpu
) {
2423 if (all_cpu_data
[cpu
]) {
2424 if (intel_pstate_driver
== &intel_pstate
)
2425 intel_pstate_clear_update_util_hook(cpu
);
2427 kfree(all_cpu_data
[cpu
]);
2428 all_cpu_data
[cpu
] = NULL
;
2434 static int intel_pstate_register_driver(void)
2438 intel_pstate_init_limits(&powersave_limits
);
2439 intel_pstate_set_performance_limits(&performance_limits
);
2440 limits
= IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
) ?
2441 &performance_limits
: &powersave_limits
;
2443 ret
= cpufreq_register_driver(intel_pstate_driver
);
2445 intel_pstate_driver_cleanup();
2449 mutex_lock(&intel_pstate_limits_lock
);
2450 driver_registered
= true;
2451 mutex_unlock(&intel_pstate_limits_lock
);
2453 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2454 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2455 intel_pstate_debug_expose_params();
2460 static int intel_pstate_unregister_driver(void)
2465 if (intel_pstate_driver
== &intel_pstate
&& !hwp_active
&&
2466 pstate_funcs
.get_target_pstate
!= get_target_pstate_use_cpu_load
)
2467 intel_pstate_debug_hide_params();
2469 mutex_lock(&intel_pstate_limits_lock
);
2470 driver_registered
= false;
2471 mutex_unlock(&intel_pstate_limits_lock
);
2473 cpufreq_unregister_driver(intel_pstate_driver
);
2474 intel_pstate_driver_cleanup();
2479 static ssize_t
intel_pstate_show_status(char *buf
)
2481 if (!driver_registered
)
2482 return sprintf(buf
, "off\n");
2484 return sprintf(buf
, "%s\n", intel_pstate_driver
== &intel_pstate
?
2485 "active" : "passive");
2488 static int intel_pstate_update_status(const char *buf
, size_t size
)
2492 if (size
== 3 && !strncmp(buf
, "off", size
))
2493 return driver_registered
?
2494 intel_pstate_unregister_driver() : -EINVAL
;
2496 if (size
== 6 && !strncmp(buf
, "active", size
)) {
2497 if (driver_registered
) {
2498 if (intel_pstate_driver
== &intel_pstate
)
2501 ret
= intel_pstate_unregister_driver();
2506 intel_pstate_driver
= &intel_pstate
;
2507 return intel_pstate_register_driver();
2510 if (size
== 7 && !strncmp(buf
, "passive", size
)) {
2511 if (driver_registered
) {
2512 if (intel_pstate_driver
!= &intel_pstate
)
2515 ret
= intel_pstate_unregister_driver();
2520 intel_pstate_driver
= &intel_cpufreq
;
2521 return intel_pstate_register_driver();
2527 static int no_load __initdata
;
2528 static int no_hwp __initdata
;
2529 static int hwp_only __initdata
;
2530 static unsigned int force_load __initdata
;
2532 static int __init
intel_pstate_msrs_not_valid(void)
2534 if (!pstate_funcs
.get_max() ||
2535 !pstate_funcs
.get_min() ||
2536 !pstate_funcs
.get_turbo())
2542 static void __init
copy_pid_params(struct pstate_adjust_policy
*policy
)
2544 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
2545 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
2546 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
2547 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
2548 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
2549 pid_params
.deadband
= policy
->deadband
;
2550 pid_params
.setpoint
= policy
->setpoint
;
2554 static void intel_pstate_use_acpi_profile(void)
2556 if (acpi_gbl_FADT
.preferred_profile
== PM_MOBILE
)
2557 pstate_funcs
.get_target_pstate
=
2558 get_target_pstate_use_cpu_load
;
2561 static void intel_pstate_use_acpi_profile(void)
2566 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
2568 pstate_funcs
.get_max
= funcs
->get_max
;
2569 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
2570 pstate_funcs
.get_min
= funcs
->get_min
;
2571 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
2572 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
2573 pstate_funcs
.get_val
= funcs
->get_val
;
2574 pstate_funcs
.get_vid
= funcs
->get_vid
;
2575 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
2577 intel_pstate_use_acpi_profile();
2582 static bool __init
intel_pstate_no_acpi_pss(void)
2586 for_each_possible_cpu(i
) {
2588 union acpi_object
*pss
;
2589 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
2590 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2595 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
2596 if (ACPI_FAILURE(status
))
2599 pss
= buffer
.pointer
;
2600 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
2611 static bool __init
intel_pstate_has_acpi_ppc(void)
2615 for_each_possible_cpu(i
) {
2616 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2620 if (acpi_has_method(pr
->handle
, "_PPC"))
2631 struct hw_vendor_info
{
2633 char oem_id
[ACPI_OEM_ID_SIZE
];
2634 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
2638 /* Hardware vendor-specific info that has its own power management modes */
2639 static struct hw_vendor_info vendor_info
[] __initdata
= {
2640 {1, "HP ", "ProLiant", PSS
},
2641 {1, "ORACLE", "X4-2 ", PPC
},
2642 {1, "ORACLE", "X4-2L ", PPC
},
2643 {1, "ORACLE", "X4-2B ", PPC
},
2644 {1, "ORACLE", "X3-2 ", PPC
},
2645 {1, "ORACLE", "X3-2L ", PPC
},
2646 {1, "ORACLE", "X3-2B ", PPC
},
2647 {1, "ORACLE", "X4470M2 ", PPC
},
2648 {1, "ORACLE", "X4270M3 ", PPC
},
2649 {1, "ORACLE", "X4270M2 ", PPC
},
2650 {1, "ORACLE", "X4170M2 ", PPC
},
2651 {1, "ORACLE", "X4170 M3", PPC
},
2652 {1, "ORACLE", "X4275 M3", PPC
},
2653 {1, "ORACLE", "X6-2 ", PPC
},
2654 {1, "ORACLE", "Sudbury ", PPC
},
2658 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
2660 struct acpi_table_header hdr
;
2661 struct hw_vendor_info
*v_info
;
2662 const struct x86_cpu_id
*id
;
2665 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
2667 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
2668 if ( misc_pwr
& (1 << 8))
2672 if (acpi_disabled
||
2673 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
2676 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
2677 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
2678 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
2679 ACPI_OEM_TABLE_ID_SIZE
))
2680 switch (v_info
->oem_pwr_table
) {
2682 return intel_pstate_no_acpi_pss();
2684 return intel_pstate_has_acpi_ppc() &&
2692 static void intel_pstate_request_control_from_smm(void)
2695 * It may be unsafe to request P-states control from SMM if _PPC support
2696 * has not been enabled.
2699 acpi_processor_pstate_control();
2701 #else /* CONFIG_ACPI not enabled */
2702 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2703 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2704 static inline void intel_pstate_request_control_from_smm(void) {}
2705 #endif /* CONFIG_ACPI */
2707 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
2708 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
2712 static int __init
intel_pstate_init(void)
2714 const struct x86_cpu_id
*id
;
2715 struct cpu_defaults
*cpu_def
;
2721 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
2722 copy_cpu_funcs(&core_params
.funcs
);
2724 intel_pstate
.attr
= hwp_cpufreq_attrs
;
2725 goto hwp_cpu_matched
;
2728 id
= x86_match_cpu(intel_pstate_cpu_ids
);
2732 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
2734 copy_pid_params(&cpu_def
->pid_policy
);
2735 copy_cpu_funcs(&cpu_def
->funcs
);
2737 if (intel_pstate_msrs_not_valid())
2742 * The Intel pstate driver will be ignored if the platform
2743 * firmware has its own power management modes.
2745 if (intel_pstate_platform_pwr_mgmt_exists())
2748 if (!hwp_active
&& hwp_only
)
2751 pr_info("Intel P-state driver initializing\n");
2753 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
2757 intel_pstate_request_control_from_smm();
2759 intel_pstate_sysfs_expose_params();
2761 mutex_lock(&intel_pstate_driver_lock
);
2762 rc
= intel_pstate_register_driver();
2763 mutex_unlock(&intel_pstate_driver_lock
);
2768 pr_info("HWP enabled\n");
2772 device_initcall(intel_pstate_init
);
2774 static int __init
intel_pstate_setup(char *str
)
2779 if (!strcmp(str
, "disable")) {
2781 } else if (!strcmp(str
, "passive")) {
2782 pr_info("Passive mode enabled\n");
2783 intel_pstate_driver
= &intel_cpufreq
;
2786 if (!strcmp(str
, "no_hwp")) {
2787 pr_info("HWP disabled\n");
2790 if (!strcmp(str
, "force"))
2792 if (!strcmp(str
, "hwp_only"))
2794 if (!strcmp(str
, "per_cpu_perf_limits"))
2795 per_cpu_limits
= true;
2798 if (!strcmp(str
, "support_acpi_ppc"))
2804 early_param("intel_pstate", intel_pstate_setup
);
2806 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2807 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2808 MODULE_LICENSE("GPL");