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1 /*
2 * Copyright (C) 2002,2003 Intrinsyc Software
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * History:
19 * 31-Jul-2002 : Initial version [FB]
20 * 29-Jan-2003 : added PXA255 support [FB]
21 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
22 *
23 * Note:
24 * This driver may change the memory bus clock rate, but will not do any
25 * platform specific access timing changes... for example if you have flash
26 * memory connected to CS0, you will need to register a platform specific
27 * notifier which will adjust the memory access strobes to maintain a
28 * minimum strobe width.
29 *
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/sched.h>
37 #include <linux/init.h>
38 #include <linux/cpufreq.h>
39 #include <linux/err.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/io.h>
42
43 #include <mach/pxa2xx-regs.h>
44 #include <mach/smemc.h>
45
46 #ifdef DEBUG
47 static unsigned int freq_debug;
48 module_param(freq_debug, uint, 0);
49 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
50 #else
51 #define freq_debug 0
52 #endif
53
54 static struct regulator *vcc_core;
55
56 static unsigned int pxa27x_maxfreq;
57 module_param(pxa27x_maxfreq, uint, 0);
58 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
59 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
60
61 struct pxa_cpufreq_data {
62 struct clk *clk_core;
63 };
64 static struct pxa_cpufreq_data pxa_cpufreq_data;
65
66 struct pxa_freqs {
67 unsigned int khz;
68 int vmin;
69 int vmax;
70 };
71
72 /*
73 * PXA255 definitions
74 */
75 static const struct pxa_freqs pxa255_run_freqs[] =
76 {
77 /* CPU MEMBUS run turbo PXbus SDRAM */
78 { 99500, -1, -1}, /* 99, 99, 50, 50 */
79 {132700, -1, -1}, /* 133, 133, 66, 66 */
80 {199100, -1, -1}, /* 199, 199, 99, 99 */
81 {265400, -1, -1}, /* 265, 265, 133, 66 */
82 {331800, -1, -1}, /* 331, 331, 166, 83 */
83 {398100, -1, -1}, /* 398, 398, 196, 99 */
84 };
85
86 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
87 static const struct pxa_freqs pxa255_turbo_freqs[] =
88 {
89 /* CPU run turbo PXbus SDRAM */
90 { 99500, -1, -1}, /* 99, 99, 50, 50 */
91 {199100, -1, -1}, /* 99, 199, 50, 99 */
92 {298500, -1, -1}, /* 99, 287, 50, 99 */
93 {298600, -1, -1}, /* 199, 287, 99, 99 */
94 {398100, -1, -1}, /* 199, 398, 99, 99 */
95 };
96
97 #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
98 #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
99
100 static struct cpufreq_frequency_table
101 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
102 static struct cpufreq_frequency_table
103 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
104
105 static unsigned int pxa255_turbo_table;
106 module_param(pxa255_turbo_table, uint, 0);
107 MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
108
109 static struct pxa_freqs pxa27x_freqs[] = {
110 {104000, 900000, 1705000 },
111 {156000, 1000000, 1705000 },
112 {208000, 1180000, 1705000 },
113 {312000, 1250000, 1705000 },
114 {416000, 1350000, 1705000 },
115 {520000, 1450000, 1705000 },
116 {624000, 1550000, 1705000 }
117 };
118
119 #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
120 static struct cpufreq_frequency_table
121 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
122
123 extern unsigned get_clk_frequency_khz(int info);
124
125 #ifdef CONFIG_REGULATOR
126
127 static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
128 {
129 int ret = 0;
130 int vmin, vmax;
131
132 if (!cpu_is_pxa27x())
133 return 0;
134
135 vmin = pxa_freq->vmin;
136 vmax = pxa_freq->vmax;
137 if ((vmin == -1) || (vmax == -1))
138 return 0;
139
140 ret = regulator_set_voltage(vcc_core, vmin, vmax);
141 if (ret)
142 pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
143 return ret;
144 }
145
146 static void __init pxa_cpufreq_init_voltages(void)
147 {
148 vcc_core = regulator_get(NULL, "vcc_core");
149 if (IS_ERR(vcc_core)) {
150 pr_info("Didn't find vcc_core regulator\n");
151 vcc_core = NULL;
152 } else {
153 pr_info("Found vcc_core regulator\n");
154 }
155 }
156 #else
157 static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
158 {
159 return 0;
160 }
161
162 static void __init pxa_cpufreq_init_voltages(void) { }
163 #endif
164
165 static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
166 const struct pxa_freqs **pxa_freqs)
167 {
168 if (cpu_is_pxa25x()) {
169 if (!pxa255_turbo_table) {
170 *pxa_freqs = pxa255_run_freqs;
171 *freq_table = pxa255_run_freq_table;
172 } else {
173 *pxa_freqs = pxa255_turbo_freqs;
174 *freq_table = pxa255_turbo_freq_table;
175 }
176 } else if (cpu_is_pxa27x()) {
177 *pxa_freqs = pxa27x_freqs;
178 *freq_table = pxa27x_freq_table;
179 } else {
180 BUG();
181 }
182 }
183
184 static void pxa27x_guess_max_freq(void)
185 {
186 if (!pxa27x_maxfreq) {
187 pxa27x_maxfreq = 416000;
188 pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
189 pxa27x_maxfreq);
190 } else {
191 pxa27x_maxfreq *= 1000;
192 }
193 }
194
195 static unsigned int pxa_cpufreq_get(unsigned int cpu)
196 {
197 struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
198
199 return (unsigned int) clk_get_rate(data->clk_core) / 1000;
200 }
201
202 static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
203 {
204 struct cpufreq_frequency_table *pxa_freqs_table;
205 const struct pxa_freqs *pxa_freq_settings;
206 struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
207 unsigned int new_freq_cpu;
208 int ret = 0;
209
210 /* Get the current policy */
211 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
212
213 new_freq_cpu = pxa_freq_settings[idx].khz;
214
215 if (freq_debug)
216 pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
217 policy->cur / 1000, new_freq_cpu / 1000);
218
219 if (vcc_core && new_freq_cpu > policy->cur) {
220 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
221 if (ret)
222 return ret;
223 }
224
225 clk_set_rate(data->clk_core, new_freq_cpu * 1000);
226
227 /*
228 * Even if voltage setting fails, we don't report it, as the frequency
229 * change succeeded. The voltage reduction is not a critical failure,
230 * only power savings will suffer from this.
231 *
232 * Note: if the voltage change fails, and a return value is returned, a
233 * bug is triggered (seems a deadlock). Should anybody find out where,
234 * the "return 0" should become a "return ret".
235 */
236 if (vcc_core && new_freq_cpu < policy->cur)
237 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
238
239 return 0;
240 }
241
242 static int pxa_cpufreq_init(struct cpufreq_policy *policy)
243 {
244 int i;
245 unsigned int freq;
246 struct cpufreq_frequency_table *pxa255_freq_table;
247 const struct pxa_freqs *pxa255_freqs;
248
249 /* try to guess pxa27x cpu */
250 if (cpu_is_pxa27x())
251 pxa27x_guess_max_freq();
252
253 pxa_cpufreq_init_voltages();
254
255 /* set default policy and cpuinfo */
256 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
257
258 /* Generate pxa25x the run cpufreq_frequency_table struct */
259 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
260 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
261 pxa255_run_freq_table[i].driver_data = i;
262 }
263 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
264
265 /* Generate pxa25x the turbo cpufreq_frequency_table struct */
266 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
267 pxa255_turbo_freq_table[i].frequency =
268 pxa255_turbo_freqs[i].khz;
269 pxa255_turbo_freq_table[i].driver_data = i;
270 }
271 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
272
273 pxa255_turbo_table = !!pxa255_turbo_table;
274
275 /* Generate the pxa27x cpufreq_frequency_table struct */
276 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
277 freq = pxa27x_freqs[i].khz;
278 if (freq > pxa27x_maxfreq)
279 break;
280 pxa27x_freq_table[i].frequency = freq;
281 pxa27x_freq_table[i].driver_data = i;
282 }
283 pxa27x_freq_table[i].driver_data = i;
284 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
285
286 /*
287 * Set the policy's minimum and maximum frequencies from the tables
288 * just constructed. This sets cpuinfo.mxx_freq, min and max.
289 */
290 if (cpu_is_pxa25x()) {
291 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
292 pr_info("using %s frequency table\n",
293 pxa255_turbo_table ? "turbo" : "run");
294
295 cpufreq_table_validate_and_show(policy, pxa255_freq_table);
296 }
297 else if (cpu_is_pxa27x()) {
298 cpufreq_table_validate_and_show(policy, pxa27x_freq_table);
299 }
300
301 pr_info("frequency change support initialized\n");
302
303 return 0;
304 }
305
306 static struct cpufreq_driver pxa_cpufreq_driver = {
307 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
308 .verify = cpufreq_generic_frequency_table_verify,
309 .target_index = pxa_set_target,
310 .init = pxa_cpufreq_init,
311 .get = pxa_cpufreq_get,
312 .name = "PXA2xx",
313 .driver_data = &pxa_cpufreq_data,
314 };
315
316 static int __init pxa_cpu_init(void)
317 {
318 int ret = -ENODEV;
319
320 pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
321 if (IS_ERR(pxa_cpufreq_data.clk_core))
322 return PTR_ERR(pxa_cpufreq_data.clk_core);
323
324 if (cpu_is_pxa25x() || cpu_is_pxa27x())
325 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
326 return ret;
327 }
328
329 static void __exit pxa_cpu_exit(void)
330 {
331 cpufreq_unregister_driver(&pxa_cpufreq_driver);
332 }
333
334
335 MODULE_AUTHOR("Intrinsyc Software Inc.");
336 MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
337 MODULE_LICENSE("GPL");
338 module_init(pxa_cpu_init);
339 module_exit(pxa_cpu_exit);