2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * CPU frequency scaling for S5PC110/S5PV210
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/cpufreq.h>
21 #include <mach/regs-clock.h>
23 static struct clk
*cpu_clk
;
24 static struct clk
*dmc0_clk
;
25 static struct clk
*dmc1_clk
;
26 static struct cpufreq_freqs freqs
;
28 /* APLL M,P,S values for 1G/800Mhz */
29 #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
30 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
33 * DRAM configurations to calculate refresh counter for changing
34 * frequency of memory.
37 unsigned long freq
; /* HZ */
38 unsigned long refresh
; /* DRAM refresh counter * 1000 */
41 /* DRAM configuration (DMC0 and DMC1) */
42 static struct dram_conf s5pv210_dram_conf
[2];
48 enum s5pv210_mem_type
{
54 enum s5pv210_dmc_port
{
59 static struct cpufreq_frequency_table s5pv210_freq_table
[] = {
65 {0, CPUFREQ_TABLE_END
},
68 static u32 clkdiv_val
[5][11] = {
70 * Clock divider value for following
71 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
72 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
76 /* L0 : [1000/200/100][166/83][133/66][200/200] */
77 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
79 /* L1 : [800/200/100][166/83][133/66][200/200] */
80 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
82 /* L2 : [400/200/100][166/83][133/66][200/200] */
83 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
85 /* L3 : [200/200/100][166/83][133/66][200/200] */
86 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
88 /* L4 : [100/100/100][83/83][66/66][100/100] */
89 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
93 * This function set DRAM refresh counter
94 * accoriding to operating frequency of DRAM
95 * ch: DMC port number 0 or 1
96 * freq: Operating frequency of DRAM(KHz)
98 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch
, unsigned long freq
)
100 unsigned long tmp
, tmp1
;
101 void __iomem
*reg
= NULL
;
104 reg
= (S5P_VA_DMC0
+ 0x30);
105 } else if (ch
== DMC1
) {
106 reg
= (S5P_VA_DMC1
+ 0x30);
108 printk(KERN_ERR
"Cannot find DMC port\n");
112 /* Find current DRAM frequency */
113 tmp
= s5pv210_dram_conf
[ch
].freq
;
117 tmp1
= s5pv210_dram_conf
[ch
].refresh
;
121 __raw_writel(tmp1
, reg
);
124 int s5pv210_verify_speed(struct cpufreq_policy
*policy
)
129 return cpufreq_frequency_table_verify(policy
, s5pv210_freq_table
);
132 unsigned int s5pv210_getspeed(unsigned int cpu
)
137 return clk_get_rate(cpu_clk
) / 1000;
140 static int s5pv210_target(struct cpufreq_policy
*policy
,
141 unsigned int target_freq
,
142 unsigned int relation
)
145 unsigned int index
, priv_index
;
146 unsigned int pll_changing
= 0;
147 unsigned int bus_speed_changing
= 0;
149 freqs
.old
= s5pv210_getspeed(0);
151 if (cpufreq_frequency_table_target(policy
, s5pv210_freq_table
,
152 target_freq
, relation
, &index
))
155 freqs
.new = s5pv210_freq_table
[index
].frequency
;
158 if (freqs
.new == freqs
.old
)
161 /* Finding current running level index */
162 if (cpufreq_frequency_table_target(policy
, s5pv210_freq_table
,
163 freqs
.old
, relation
, &priv_index
))
166 cpufreq_notify_transition(&freqs
, CPUFREQ_PRECHANGE
);
168 if (freqs
.new > freqs
.old
) {
169 /* Voltage up: will be implemented */
172 /* Check if there need to change PLL */
173 if ((index
== L0
) || (priv_index
== L0
))
176 /* Check if there need to change System bus clock */
177 if ((index
== L4
) || (priv_index
== L4
))
178 bus_speed_changing
= 1;
180 if (bus_speed_changing
) {
182 * Reconfigure DRAM refresh counter value for minimum
183 * temporary clock while changing divider.
184 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
187 s5pv210_set_refresh(DMC1
, 83000);
189 s5pv210_set_refresh(DMC1
, 100000);
191 s5pv210_set_refresh(DMC0
, 83000);
195 * APLL should be changed in this level
196 * APLL -> MPLL(for stable transition) -> APLL
197 * Some clock source's clock API are not prepared.
198 * Do not use clock API in below code.
202 * 1. Temporary Change divider for MFC and G3D
203 * SCLKA2M(200/1=200)->(200/4=50)Mhz
205 reg
= __raw_readl(S5P_CLK_DIV2
);
206 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
207 reg
|= (3 << S5P_CLKDIV2_G3D_SHIFT
) |
208 (3 << S5P_CLKDIV2_MFC_SHIFT
);
209 __raw_writel(reg
, S5P_CLK_DIV2
);
211 /* For MFC, G3D dividing */
213 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
214 } while (reg
& ((1 << 16) | (1 << 17)));
217 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
218 * (200/4=50)->(667/4=166)Mhz
220 reg
= __raw_readl(S5P_CLK_SRC2
);
221 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
222 reg
|= (1 << S5P_CLKSRC2_G3D_SHIFT
) |
223 (1 << S5P_CLKSRC2_MFC_SHIFT
);
224 __raw_writel(reg
, S5P_CLK_SRC2
);
227 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
228 } while (reg
& ((1 << 7) | (1 << 3)));
231 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
232 * true refresh counter is already programed in upper
235 if (!bus_speed_changing
)
236 s5pv210_set_refresh(DMC1
, 133000);
238 /* 4. SCLKAPLL -> SCLKMPLL */
239 reg
= __raw_readl(S5P_CLK_SRC0
);
240 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
241 reg
|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT
);
242 __raw_writel(reg
, S5P_CLK_SRC0
);
245 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
246 } while (reg
& (0x1 << 18));
251 reg
= __raw_readl(S5P_CLK_DIV0
);
253 reg
&= ~(S5P_CLKDIV0_APLL_MASK
| S5P_CLKDIV0_A2M_MASK
|
254 S5P_CLKDIV0_HCLK200_MASK
| S5P_CLKDIV0_PCLK100_MASK
|
255 S5P_CLKDIV0_HCLK166_MASK
| S5P_CLKDIV0_PCLK83_MASK
|
256 S5P_CLKDIV0_HCLK133_MASK
| S5P_CLKDIV0_PCLK66_MASK
);
258 reg
|= ((clkdiv_val
[index
][0] << S5P_CLKDIV0_APLL_SHIFT
) |
259 (clkdiv_val
[index
][1] << S5P_CLKDIV0_A2M_SHIFT
) |
260 (clkdiv_val
[index
][2] << S5P_CLKDIV0_HCLK200_SHIFT
) |
261 (clkdiv_val
[index
][3] << S5P_CLKDIV0_PCLK100_SHIFT
) |
262 (clkdiv_val
[index
][4] << S5P_CLKDIV0_HCLK166_SHIFT
) |
263 (clkdiv_val
[index
][5] << S5P_CLKDIV0_PCLK83_SHIFT
) |
264 (clkdiv_val
[index
][6] << S5P_CLKDIV0_HCLK133_SHIFT
) |
265 (clkdiv_val
[index
][7] << S5P_CLKDIV0_PCLK66_SHIFT
));
267 __raw_writel(reg
, S5P_CLK_DIV0
);
270 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
271 } while (reg
& 0xff);
273 /* ARM MCS value changed */
274 reg
= __raw_readl(S5P_ARM_MCS_CON
);
281 __raw_writel(reg
, S5P_ARM_MCS_CON
);
284 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
285 __raw_writel(0x2cf, S5P_APLL_LOCK
);
289 * 6-1. Set PMS values
290 * 6-2. Wait untile the PLL is locked
293 __raw_writel(APLL_VAL_1000
, S5P_APLL_CON
);
295 __raw_writel(APLL_VAL_800
, S5P_APLL_CON
);
298 reg
= __raw_readl(S5P_APLL_CON
);
299 } while (!(reg
& (0x1 << 29)));
302 * 7. Change souce clock from SCLKMPLL(667Mhz)
303 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
304 * (667/4=166)->(200/4=50)Mhz
306 reg
= __raw_readl(S5P_CLK_SRC2
);
307 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
308 reg
|= (0 << S5P_CLKSRC2_G3D_SHIFT
) |
309 (0 << S5P_CLKSRC2_MFC_SHIFT
);
310 __raw_writel(reg
, S5P_CLK_SRC2
);
313 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
314 } while (reg
& ((1 << 7) | (1 << 3)));
317 * 8. Change divider for MFC and G3D
318 * (200/4=50)->(200/1=200)Mhz
320 reg
= __raw_readl(S5P_CLK_DIV2
);
321 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
322 reg
|= (clkdiv_val
[index
][10] << S5P_CLKDIV2_G3D_SHIFT
) |
323 (clkdiv_val
[index
][9] << S5P_CLKDIV2_MFC_SHIFT
);
324 __raw_writel(reg
, S5P_CLK_DIV2
);
326 /* For MFC, G3D dividing */
328 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
329 } while (reg
& ((1 << 16) | (1 << 17)));
331 /* 9. Change MPLL to APLL in MSYS_MUX */
332 reg
= __raw_readl(S5P_CLK_SRC0
);
333 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
334 reg
|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT
);
335 __raw_writel(reg
, S5P_CLK_SRC0
);
338 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
339 } while (reg
& (0x1 << 18));
342 * 10. DMC1 refresh counter
343 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
344 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
346 if (!bus_speed_changing
)
347 s5pv210_set_refresh(DMC1
, 200000);
351 * L4 level need to change memory bus speed, hence onedram clock divier
352 * and memory refresh parameter should be changed
354 if (bus_speed_changing
) {
355 reg
= __raw_readl(S5P_CLK_DIV6
);
356 reg
&= ~S5P_CLKDIV6_ONEDRAM_MASK
;
357 reg
|= (clkdiv_val
[index
][8] << S5P_CLKDIV6_ONEDRAM_SHIFT
);
358 __raw_writel(reg
, S5P_CLK_DIV6
);
361 reg
= __raw_readl(S5P_CLKDIV_STAT1
);
362 } while (reg
& (1 << 15));
364 /* Reconfigure DRAM refresh counter value */
370 s5pv210_set_refresh(DMC0
, 166000);
371 s5pv210_set_refresh(DMC1
, 200000);
377 s5pv210_set_refresh(DMC0
, 83000);
378 s5pv210_set_refresh(DMC1
, 100000);
382 if (freqs
.new < freqs
.old
) {
383 /* Voltage down: will be implemented */
386 cpufreq_notify_transition(&freqs
, CPUFREQ_POSTCHANGE
);
388 printk(KERN_DEBUG
"Perf changed[L%d]\n", index
);
394 static int s5pv210_cpufreq_suspend(struct cpufreq_policy
*policy
)
399 static int s5pv210_cpufreq_resume(struct cpufreq_policy
*policy
)
405 static int check_mem_type(void __iomem
*dmc_reg
)
409 val
= __raw_readl(dmc_reg
+ 0x4);
410 val
= (val
& (0xf << 8));
415 static int __init
s5pv210_cpu_init(struct cpufreq_policy
*policy
)
417 unsigned long mem_type
;
419 cpu_clk
= clk_get(NULL
, "armclk");
421 return PTR_ERR(cpu_clk
);
423 dmc0_clk
= clk_get(NULL
, "sclk_dmc0");
424 if (IS_ERR(dmc0_clk
)) {
426 return PTR_ERR(dmc0_clk
);
429 dmc1_clk
= clk_get(NULL
, "hclk_msys");
430 if (IS_ERR(dmc1_clk
)) {
433 return PTR_ERR(dmc1_clk
);
436 if (policy
->cpu
!= 0)
440 * check_mem_type : This driver only support LPDDR & LPDDR2.
441 * other memory type is not supported.
443 mem_type
= check_mem_type(S5P_VA_DMC0
);
445 if ((mem_type
!= LPDDR
) && (mem_type
!= LPDDR2
)) {
446 printk(KERN_ERR
"CPUFreq doesn't support this memory type\n");
450 /* Find current refresh counter and frequency each DMC */
451 s5pv210_dram_conf
[0].refresh
= (__raw_readl(S5P_VA_DMC0
+ 0x30) * 1000);
452 s5pv210_dram_conf
[0].freq
= clk_get_rate(dmc0_clk
);
454 s5pv210_dram_conf
[1].refresh
= (__raw_readl(S5P_VA_DMC1
+ 0x30) * 1000);
455 s5pv210_dram_conf
[1].freq
= clk_get_rate(dmc1_clk
);
457 policy
->cur
= policy
->min
= policy
->max
= s5pv210_getspeed(0);
459 cpufreq_frequency_table_get_attr(s5pv210_freq_table
, policy
->cpu
);
461 policy
->cpuinfo
.transition_latency
= 40000;
463 return cpufreq_frequency_table_cpuinfo(policy
, s5pv210_freq_table
);
466 static struct cpufreq_driver s5pv210_driver
= {
467 .flags
= CPUFREQ_STICKY
,
468 .verify
= s5pv210_verify_speed
,
469 .target
= s5pv210_target
,
470 .get
= s5pv210_getspeed
,
471 .init
= s5pv210_cpu_init
,
474 .suspend
= s5pv210_cpufreq_suspend
,
475 .resume
= s5pv210_cpufreq_resume
,
479 static int __init
s5pv210_cpufreq_init(void)
481 return cpufreq_register_driver(&s5pv210_driver
);
484 late_initcall(s5pv210_cpufreq_init
);