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[mirror_ubuntu-bionic-kernel.git] / drivers / crypto / atmel-aes.c
1 /*
2 * Cryptographic API.
3 *
4 * Support for ATMEL AES HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-aes.c driver.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <crypto/gcm.h>
40 #include <crypto/xts.h>
41 #include <crypto/internal/aead.h>
42 #include <linux/platform_data/crypto-atmel.h>
43 #include <dt-bindings/dma/at91.h>
44 #include "atmel-aes-regs.h"
45 #include "atmel-authenc.h"
46
47 #define ATMEL_AES_PRIORITY 300
48
49 #define ATMEL_AES_BUFFER_ORDER 2
50 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
51
52 #define CFB8_BLOCK_SIZE 1
53 #define CFB16_BLOCK_SIZE 2
54 #define CFB32_BLOCK_SIZE 4
55 #define CFB64_BLOCK_SIZE 8
56
57 #define SIZE_IN_WORDS(x) ((x) >> 2)
58
59 /* AES flags */
60 /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */
61 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
62 #define AES_FLAGS_GTAGEN AES_MR_GTAGEN
63 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
64 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
65 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
66 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
67 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
68 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
69 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
70 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
71 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
72 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
73 #define AES_FLAGS_GCM AES_MR_OPMOD_GCM
74 #define AES_FLAGS_XTS AES_MR_OPMOD_XTS
75
76 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
77 AES_FLAGS_ENCRYPT | \
78 AES_FLAGS_GTAGEN)
79
80 #define AES_FLAGS_BUSY BIT(3)
81 #define AES_FLAGS_DUMP_REG BIT(4)
82 #define AES_FLAGS_OWN_SHA BIT(5)
83
84 #define AES_FLAGS_PERSISTENT AES_FLAGS_BUSY
85
86 #define ATMEL_AES_QUEUE_LENGTH 50
87
88 #define ATMEL_AES_DMA_THRESHOLD 256
89
90
91 struct atmel_aes_caps {
92 bool has_dualbuff;
93 bool has_cfb64;
94 bool has_ctr32;
95 bool has_gcm;
96 bool has_xts;
97 bool has_authenc;
98 u32 max_burst_size;
99 };
100
101 struct atmel_aes_dev;
102
103
104 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
105
106
107 struct atmel_aes_base_ctx {
108 struct atmel_aes_dev *dd;
109 atmel_aes_fn_t start;
110 int keylen;
111 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
112 u16 block_size;
113 bool is_aead;
114 };
115
116 struct atmel_aes_ctx {
117 struct atmel_aes_base_ctx base;
118 };
119
120 struct atmel_aes_ctr_ctx {
121 struct atmel_aes_base_ctx base;
122
123 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
124 size_t offset;
125 struct scatterlist src[2];
126 struct scatterlist dst[2];
127 };
128
129 struct atmel_aes_gcm_ctx {
130 struct atmel_aes_base_ctx base;
131
132 struct scatterlist src[2];
133 struct scatterlist dst[2];
134
135 u32 j0[AES_BLOCK_SIZE / sizeof(u32)];
136 u32 tag[AES_BLOCK_SIZE / sizeof(u32)];
137 u32 ghash[AES_BLOCK_SIZE / sizeof(u32)];
138 size_t textlen;
139
140 const u32 *ghash_in;
141 u32 *ghash_out;
142 atmel_aes_fn_t ghash_resume;
143 };
144
145 struct atmel_aes_xts_ctx {
146 struct atmel_aes_base_ctx base;
147
148 u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
149 };
150
151 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
152 struct atmel_aes_authenc_ctx {
153 struct atmel_aes_base_ctx base;
154 struct atmel_sha_authenc_ctx *auth;
155 };
156 #endif
157
158 struct atmel_aes_reqctx {
159 unsigned long mode;
160 u32 lastc[AES_BLOCK_SIZE / sizeof(u32)];
161 };
162
163 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
164 struct atmel_aes_authenc_reqctx {
165 struct atmel_aes_reqctx base;
166
167 struct scatterlist src[2];
168 struct scatterlist dst[2];
169 size_t textlen;
170 u32 digest[SHA512_DIGEST_SIZE / sizeof(u32)];
171
172 /* auth_req MUST be place last. */
173 struct ahash_request auth_req;
174 };
175 #endif
176
177 struct atmel_aes_dma {
178 struct dma_chan *chan;
179 struct scatterlist *sg;
180 int nents;
181 unsigned int remainder;
182 unsigned int sg_len;
183 };
184
185 struct atmel_aes_dev {
186 struct list_head list;
187 unsigned long phys_base;
188 void __iomem *io_base;
189
190 struct crypto_async_request *areq;
191 struct atmel_aes_base_ctx *ctx;
192
193 bool is_async;
194 atmel_aes_fn_t resume;
195 atmel_aes_fn_t cpu_transfer_complete;
196
197 struct device *dev;
198 struct clk *iclk;
199 int irq;
200
201 unsigned long flags;
202
203 spinlock_t lock;
204 struct crypto_queue queue;
205
206 struct tasklet_struct done_task;
207 struct tasklet_struct queue_task;
208
209 size_t total;
210 size_t datalen;
211 u32 *data;
212
213 struct atmel_aes_dma src;
214 struct atmel_aes_dma dst;
215
216 size_t buflen;
217 void *buf;
218 struct scatterlist aligned_sg;
219 struct scatterlist *real_dst;
220
221 struct atmel_aes_caps caps;
222
223 u32 hw_version;
224 };
225
226 struct atmel_aes_drv {
227 struct list_head dev_list;
228 spinlock_t lock;
229 };
230
231 static struct atmel_aes_drv atmel_aes = {
232 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
233 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
234 };
235
236 #ifdef VERBOSE_DEBUG
237 static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
238 {
239 switch (offset) {
240 case AES_CR:
241 return "CR";
242
243 case AES_MR:
244 return "MR";
245
246 case AES_ISR:
247 return "ISR";
248
249 case AES_IMR:
250 return "IMR";
251
252 case AES_IER:
253 return "IER";
254
255 case AES_IDR:
256 return "IDR";
257
258 case AES_KEYWR(0):
259 case AES_KEYWR(1):
260 case AES_KEYWR(2):
261 case AES_KEYWR(3):
262 case AES_KEYWR(4):
263 case AES_KEYWR(5):
264 case AES_KEYWR(6):
265 case AES_KEYWR(7):
266 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2);
267 break;
268
269 case AES_IDATAR(0):
270 case AES_IDATAR(1):
271 case AES_IDATAR(2):
272 case AES_IDATAR(3):
273 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2);
274 break;
275
276 case AES_ODATAR(0):
277 case AES_ODATAR(1):
278 case AES_ODATAR(2):
279 case AES_ODATAR(3):
280 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2);
281 break;
282
283 case AES_IVR(0):
284 case AES_IVR(1):
285 case AES_IVR(2):
286 case AES_IVR(3):
287 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2);
288 break;
289
290 case AES_AADLENR:
291 return "AADLENR";
292
293 case AES_CLENR:
294 return "CLENR";
295
296 case AES_GHASHR(0):
297 case AES_GHASHR(1):
298 case AES_GHASHR(2):
299 case AES_GHASHR(3):
300 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2);
301 break;
302
303 case AES_TAGR(0):
304 case AES_TAGR(1):
305 case AES_TAGR(2):
306 case AES_TAGR(3):
307 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2);
308 break;
309
310 case AES_CTRR:
311 return "CTRR";
312
313 case AES_GCMHR(0):
314 case AES_GCMHR(1):
315 case AES_GCMHR(2):
316 case AES_GCMHR(3):
317 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
318 break;
319
320 case AES_EMR:
321 return "EMR";
322
323 case AES_TWR(0):
324 case AES_TWR(1):
325 case AES_TWR(2):
326 case AES_TWR(3):
327 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
328 break;
329
330 case AES_ALPHAR(0):
331 case AES_ALPHAR(1):
332 case AES_ALPHAR(2):
333 case AES_ALPHAR(3):
334 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
335 break;
336
337 default:
338 snprintf(tmp, sz, "0x%02x", offset);
339 break;
340 }
341
342 return tmp;
343 }
344 #endif /* VERBOSE_DEBUG */
345
346 /* Shared functions */
347
348 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
349 {
350 u32 value = readl_relaxed(dd->io_base + offset);
351
352 #ifdef VERBOSE_DEBUG
353 if (dd->flags & AES_FLAGS_DUMP_REG) {
354 char tmp[16];
355
356 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
357 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
358 }
359 #endif /* VERBOSE_DEBUG */
360
361 return value;
362 }
363
364 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
365 u32 offset, u32 value)
366 {
367 #ifdef VERBOSE_DEBUG
368 if (dd->flags & AES_FLAGS_DUMP_REG) {
369 char tmp[16];
370
371 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
372 atmel_aes_reg_name(offset, tmp, sizeof(tmp)));
373 }
374 #endif /* VERBOSE_DEBUG */
375
376 writel_relaxed(value, dd->io_base + offset);
377 }
378
379 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
380 u32 *value, int count)
381 {
382 for (; count--; value++, offset += 4)
383 *value = atmel_aes_read(dd, offset);
384 }
385
386 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
387 const u32 *value, int count)
388 {
389 for (; count--; value++, offset += 4)
390 atmel_aes_write(dd, offset, *value);
391 }
392
393 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
394 u32 *value)
395 {
396 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
397 }
398
399 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
400 const u32 *value)
401 {
402 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
403 }
404
405 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
406 atmel_aes_fn_t resume)
407 {
408 u32 isr = atmel_aes_read(dd, AES_ISR);
409
410 if (unlikely(isr & AES_INT_DATARDY))
411 return resume(dd);
412
413 dd->resume = resume;
414 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
415 return -EINPROGRESS;
416 }
417
418 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
419 {
420 len &= block_size - 1;
421 return len ? block_size - len : 0;
422 }
423
424 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
425 {
426 struct atmel_aes_dev *aes_dd = NULL;
427 struct atmel_aes_dev *tmp;
428
429 spin_lock_bh(&atmel_aes.lock);
430 if (!ctx->dd) {
431 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
432 aes_dd = tmp;
433 break;
434 }
435 ctx->dd = aes_dd;
436 } else {
437 aes_dd = ctx->dd;
438 }
439
440 spin_unlock_bh(&atmel_aes.lock);
441
442 return aes_dd;
443 }
444
445 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
446 {
447 int err;
448
449 err = clk_enable(dd->iclk);
450 if (err)
451 return err;
452
453 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
454 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
455
456 return 0;
457 }
458
459 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
460 {
461 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
462 }
463
464 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
465 {
466 int err;
467
468 err = atmel_aes_hw_init(dd);
469 if (err)
470 return err;
471
472 dd->hw_version = atmel_aes_get_version(dd);
473
474 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
475
476 clk_disable(dd->iclk);
477 return 0;
478 }
479
480 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
481 const struct atmel_aes_reqctx *rctx)
482 {
483 /* Clear all but persistent flags and set request flags. */
484 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
485 }
486
487 static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
488 {
489 return (dd->flags & AES_FLAGS_ENCRYPT);
490 }
491
492 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
493 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err);
494 #endif
495
496 static void atmel_aes_set_iv_as_last_ciphertext_block(struct atmel_aes_dev *dd)
497 {
498 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
499 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
500 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
501 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
502
503 if (req->nbytes < ivsize)
504 return;
505
506 if (rctx->mode & AES_FLAGS_ENCRYPT) {
507 scatterwalk_map_and_copy(req->info, req->dst,
508 req->nbytes - ivsize, ivsize, 0);
509 } else {
510 if (req->src == req->dst)
511 memcpy(req->info, rctx->lastc, ivsize);
512 else
513 scatterwalk_map_and_copy(req->info, req->src,
514 req->nbytes - ivsize,
515 ivsize, 0);
516 }
517 }
518
519 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
520 {
521 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
522 if (dd->ctx->is_aead)
523 atmel_aes_authenc_complete(dd, err);
524 #endif
525
526 clk_disable(dd->iclk);
527 dd->flags &= ~AES_FLAGS_BUSY;
528
529 if (!dd->ctx->is_aead)
530 atmel_aes_set_iv_as_last_ciphertext_block(dd);
531
532 if (dd->is_async)
533 dd->areq->complete(dd->areq, err);
534
535 tasklet_schedule(&dd->queue_task);
536
537 return err;
538 }
539
540 static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
541 const u32 *iv, const u32 *key, int keylen)
542 {
543 u32 valmr = 0;
544
545 /* MR register must be set before IV registers */
546 if (keylen == AES_KEYSIZE_128)
547 valmr |= AES_MR_KEYSIZE_128;
548 else if (keylen == AES_KEYSIZE_192)
549 valmr |= AES_MR_KEYSIZE_192;
550 else
551 valmr |= AES_MR_KEYSIZE_256;
552
553 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
554
555 if (use_dma) {
556 valmr |= AES_MR_SMOD_IDATAR0;
557 if (dd->caps.has_dualbuff)
558 valmr |= AES_MR_DUALBUFF;
559 } else {
560 valmr |= AES_MR_SMOD_AUTO;
561 }
562
563 atmel_aes_write(dd, AES_MR, valmr);
564
565 atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
566
567 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
568 atmel_aes_write_block(dd, AES_IVR(0), iv);
569 }
570
571 static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
572 const u32 *iv)
573
574 {
575 atmel_aes_write_ctrl_key(dd, use_dma, iv,
576 dd->ctx->key, dd->ctx->keylen);
577 }
578
579 /* CPU transfer */
580
581 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
582 {
583 int err = 0;
584 u32 isr;
585
586 for (;;) {
587 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
588 dd->data += 4;
589 dd->datalen -= AES_BLOCK_SIZE;
590
591 if (dd->datalen < AES_BLOCK_SIZE)
592 break;
593
594 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
595
596 isr = atmel_aes_read(dd, AES_ISR);
597 if (!(isr & AES_INT_DATARDY)) {
598 dd->resume = atmel_aes_cpu_transfer;
599 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
600 return -EINPROGRESS;
601 }
602 }
603
604 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
605 dd->buf, dd->total))
606 err = -EINVAL;
607
608 if (err)
609 return atmel_aes_complete(dd, err);
610
611 return dd->cpu_transfer_complete(dd);
612 }
613
614 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
615 struct scatterlist *src,
616 struct scatterlist *dst,
617 size_t len,
618 atmel_aes_fn_t resume)
619 {
620 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
621
622 if (unlikely(len == 0))
623 return -EINVAL;
624
625 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
626
627 dd->total = len;
628 dd->real_dst = dst;
629 dd->cpu_transfer_complete = resume;
630 dd->datalen = len + padlen;
631 dd->data = (u32 *)dd->buf;
632 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
633 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
634 }
635
636
637 /* DMA transfer */
638
639 static void atmel_aes_dma_callback(void *data);
640
641 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
642 struct scatterlist *sg,
643 size_t len,
644 struct atmel_aes_dma *dma)
645 {
646 int nents;
647
648 if (!IS_ALIGNED(len, dd->ctx->block_size))
649 return false;
650
651 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
652 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
653 return false;
654
655 if (len <= sg->length) {
656 if (!IS_ALIGNED(len, dd->ctx->block_size))
657 return false;
658
659 dma->nents = nents+1;
660 dma->remainder = sg->length - len;
661 sg->length = len;
662 return true;
663 }
664
665 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
666 return false;
667
668 len -= sg->length;
669 }
670
671 return false;
672 }
673
674 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
675 {
676 struct scatterlist *sg = dma->sg;
677 int nents = dma->nents;
678
679 if (!dma->remainder)
680 return;
681
682 while (--nents > 0 && sg)
683 sg = sg_next(sg);
684
685 if (!sg)
686 return;
687
688 sg->length += dma->remainder;
689 }
690
691 static int atmel_aes_map(struct atmel_aes_dev *dd,
692 struct scatterlist *src,
693 struct scatterlist *dst,
694 size_t len)
695 {
696 bool src_aligned, dst_aligned;
697 size_t padlen;
698
699 dd->total = len;
700 dd->src.sg = src;
701 dd->dst.sg = dst;
702 dd->real_dst = dst;
703
704 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
705 if (src == dst)
706 dst_aligned = src_aligned;
707 else
708 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
709 if (!src_aligned || !dst_aligned) {
710 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
711
712 if (dd->buflen < len + padlen)
713 return -ENOMEM;
714
715 if (!src_aligned) {
716 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
717 dd->src.sg = &dd->aligned_sg;
718 dd->src.nents = 1;
719 dd->src.remainder = 0;
720 }
721
722 if (!dst_aligned) {
723 dd->dst.sg = &dd->aligned_sg;
724 dd->dst.nents = 1;
725 dd->dst.remainder = 0;
726 }
727
728 sg_init_table(&dd->aligned_sg, 1);
729 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
730 }
731
732 if (dd->src.sg == dd->dst.sg) {
733 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
734 DMA_BIDIRECTIONAL);
735 dd->dst.sg_len = dd->src.sg_len;
736 if (!dd->src.sg_len)
737 return -EFAULT;
738 } else {
739 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
740 DMA_TO_DEVICE);
741 if (!dd->src.sg_len)
742 return -EFAULT;
743
744 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
745 DMA_FROM_DEVICE);
746 if (!dd->dst.sg_len) {
747 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
748 DMA_TO_DEVICE);
749 return -EFAULT;
750 }
751 }
752
753 return 0;
754 }
755
756 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
757 {
758 if (dd->src.sg == dd->dst.sg) {
759 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
760 DMA_BIDIRECTIONAL);
761
762 if (dd->src.sg != &dd->aligned_sg)
763 atmel_aes_restore_sg(&dd->src);
764 } else {
765 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
766 DMA_FROM_DEVICE);
767
768 if (dd->dst.sg != &dd->aligned_sg)
769 atmel_aes_restore_sg(&dd->dst);
770
771 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
772 DMA_TO_DEVICE);
773
774 if (dd->src.sg != &dd->aligned_sg)
775 atmel_aes_restore_sg(&dd->src);
776 }
777
778 if (dd->dst.sg == &dd->aligned_sg)
779 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
780 dd->buf, dd->total);
781 }
782
783 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
784 enum dma_slave_buswidth addr_width,
785 enum dma_transfer_direction dir,
786 u32 maxburst)
787 {
788 struct dma_async_tx_descriptor *desc;
789 struct dma_slave_config config;
790 dma_async_tx_callback callback;
791 struct atmel_aes_dma *dma;
792 int err;
793
794 memset(&config, 0, sizeof(config));
795 config.direction = dir;
796 config.src_addr_width = addr_width;
797 config.dst_addr_width = addr_width;
798 config.src_maxburst = maxburst;
799 config.dst_maxburst = maxburst;
800
801 switch (dir) {
802 case DMA_MEM_TO_DEV:
803 dma = &dd->src;
804 callback = NULL;
805 config.dst_addr = dd->phys_base + AES_IDATAR(0);
806 break;
807
808 case DMA_DEV_TO_MEM:
809 dma = &dd->dst;
810 callback = atmel_aes_dma_callback;
811 config.src_addr = dd->phys_base + AES_ODATAR(0);
812 break;
813
814 default:
815 return -EINVAL;
816 }
817
818 err = dmaengine_slave_config(dma->chan, &config);
819 if (err)
820 return err;
821
822 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
823 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
824 if (!desc)
825 return -ENOMEM;
826
827 desc->callback = callback;
828 desc->callback_param = dd;
829 dmaengine_submit(desc);
830 dma_async_issue_pending(dma->chan);
831
832 return 0;
833 }
834
835 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
836 enum dma_transfer_direction dir)
837 {
838 struct atmel_aes_dma *dma;
839
840 switch (dir) {
841 case DMA_MEM_TO_DEV:
842 dma = &dd->src;
843 break;
844
845 case DMA_DEV_TO_MEM:
846 dma = &dd->dst;
847 break;
848
849 default:
850 return;
851 }
852
853 dmaengine_terminate_all(dma->chan);
854 }
855
856 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
857 struct scatterlist *src,
858 struct scatterlist *dst,
859 size_t len,
860 atmel_aes_fn_t resume)
861 {
862 enum dma_slave_buswidth addr_width;
863 u32 maxburst;
864 int err;
865
866 switch (dd->ctx->block_size) {
867 case CFB8_BLOCK_SIZE:
868 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
869 maxburst = 1;
870 break;
871
872 case CFB16_BLOCK_SIZE:
873 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
874 maxburst = 1;
875 break;
876
877 case CFB32_BLOCK_SIZE:
878 case CFB64_BLOCK_SIZE:
879 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
880 maxburst = 1;
881 break;
882
883 case AES_BLOCK_SIZE:
884 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
885 maxburst = dd->caps.max_burst_size;
886 break;
887
888 default:
889 err = -EINVAL;
890 goto exit;
891 }
892
893 err = atmel_aes_map(dd, src, dst, len);
894 if (err)
895 goto exit;
896
897 dd->resume = resume;
898
899 /* Set output DMA transfer first */
900 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
901 maxburst);
902 if (err)
903 goto unmap;
904
905 /* Then set input DMA transfer */
906 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
907 maxburst);
908 if (err)
909 goto output_transfer_stop;
910
911 return -EINPROGRESS;
912
913 output_transfer_stop:
914 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
915 unmap:
916 atmel_aes_unmap(dd);
917 exit:
918 return atmel_aes_complete(dd, err);
919 }
920
921 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
922 {
923 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
924 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
925 atmel_aes_unmap(dd);
926 }
927
928 static void atmel_aes_dma_callback(void *data)
929 {
930 struct atmel_aes_dev *dd = data;
931
932 atmel_aes_dma_stop(dd);
933 dd->is_async = true;
934 (void)dd->resume(dd);
935 }
936
937 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
938 struct crypto_async_request *new_areq)
939 {
940 struct crypto_async_request *areq, *backlog;
941 struct atmel_aes_base_ctx *ctx;
942 unsigned long flags;
943 bool start_async;
944 int err, ret = 0;
945
946 spin_lock_irqsave(&dd->lock, flags);
947 if (new_areq)
948 ret = crypto_enqueue_request(&dd->queue, new_areq);
949 if (dd->flags & AES_FLAGS_BUSY) {
950 spin_unlock_irqrestore(&dd->lock, flags);
951 return ret;
952 }
953 backlog = crypto_get_backlog(&dd->queue);
954 areq = crypto_dequeue_request(&dd->queue);
955 if (areq)
956 dd->flags |= AES_FLAGS_BUSY;
957 spin_unlock_irqrestore(&dd->lock, flags);
958
959 if (!areq)
960 return ret;
961
962 if (backlog)
963 backlog->complete(backlog, -EINPROGRESS);
964
965 ctx = crypto_tfm_ctx(areq->tfm);
966
967 dd->areq = areq;
968 dd->ctx = ctx;
969 start_async = (areq != new_areq);
970 dd->is_async = start_async;
971
972 /* WARNING: ctx->start() MAY change dd->is_async. */
973 err = ctx->start(dd);
974 return (start_async) ? ret : err;
975 }
976
977
978 /* AES async block ciphers */
979
980 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
981 {
982 return atmel_aes_complete(dd, 0);
983 }
984
985 static int atmel_aes_start(struct atmel_aes_dev *dd)
986 {
987 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
988 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
989 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
990 dd->ctx->block_size != AES_BLOCK_SIZE);
991 int err;
992
993 atmel_aes_set_mode(dd, rctx);
994
995 err = atmel_aes_hw_init(dd);
996 if (err)
997 return atmel_aes_complete(dd, err);
998
999 atmel_aes_write_ctrl(dd, use_dma, req->info);
1000 if (use_dma)
1001 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1002 atmel_aes_transfer_complete);
1003
1004 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1005 atmel_aes_transfer_complete);
1006 }
1007
1008 static inline struct atmel_aes_ctr_ctx *
1009 atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
1010 {
1011 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
1012 }
1013
1014 static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
1015 {
1016 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1017 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1018 struct scatterlist *src, *dst;
1019 u32 ctr, blocks;
1020 size_t datalen;
1021 bool use_dma, fragmented = false;
1022
1023 /* Check for transfer completion. */
1024 ctx->offset += dd->total;
1025 if (ctx->offset >= req->nbytes)
1026 return atmel_aes_transfer_complete(dd);
1027
1028 /* Compute data length. */
1029 datalen = req->nbytes - ctx->offset;
1030 blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
1031 ctr = be32_to_cpu(ctx->iv[3]);
1032 if (dd->caps.has_ctr32) {
1033 /* Check 32bit counter overflow. */
1034 u32 start = ctr;
1035 u32 end = start + blocks - 1;
1036
1037 if (end < start) {
1038 ctr |= 0xffffffff;
1039 datalen = AES_BLOCK_SIZE * -start;
1040 fragmented = true;
1041 }
1042 } else {
1043 /* Check 16bit counter overflow. */
1044 u16 start = ctr & 0xffff;
1045 u16 end = start + (u16)blocks - 1;
1046
1047 if (blocks >> 16 || end < start) {
1048 ctr |= 0xffff;
1049 datalen = AES_BLOCK_SIZE * (0x10000-start);
1050 fragmented = true;
1051 }
1052 }
1053 use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
1054
1055 /* Jump to offset. */
1056 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
1057 dst = ((req->src == req->dst) ? src :
1058 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
1059
1060 /* Configure hardware. */
1061 atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
1062 if (unlikely(fragmented)) {
1063 /*
1064 * Increment the counter manually to cope with the hardware
1065 * counter overflow.
1066 */
1067 ctx->iv[3] = cpu_to_be32(ctr);
1068 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
1069 }
1070
1071 if (use_dma)
1072 return atmel_aes_dma_start(dd, src, dst, datalen,
1073 atmel_aes_ctr_transfer);
1074
1075 return atmel_aes_cpu_start(dd, src, dst, datalen,
1076 atmel_aes_ctr_transfer);
1077 }
1078
1079 static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
1080 {
1081 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
1082 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1083 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1084 int err;
1085
1086 atmel_aes_set_mode(dd, rctx);
1087
1088 err = atmel_aes_hw_init(dd);
1089 if (err)
1090 return atmel_aes_complete(dd, err);
1091
1092 memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
1093 ctx->offset = 0;
1094 dd->total = 0;
1095 return atmel_aes_ctr_transfer(dd);
1096 }
1097
1098 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
1099 {
1100 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1101 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1102 struct atmel_aes_reqctx *rctx;
1103 struct atmel_aes_dev *dd;
1104
1105 switch (mode & AES_FLAGS_OPMODE_MASK) {
1106 case AES_FLAGS_CFB8:
1107 ctx->block_size = CFB8_BLOCK_SIZE;
1108 break;
1109
1110 case AES_FLAGS_CFB16:
1111 ctx->block_size = CFB16_BLOCK_SIZE;
1112 break;
1113
1114 case AES_FLAGS_CFB32:
1115 ctx->block_size = CFB32_BLOCK_SIZE;
1116 break;
1117
1118 case AES_FLAGS_CFB64:
1119 ctx->block_size = CFB64_BLOCK_SIZE;
1120 break;
1121
1122 default:
1123 ctx->block_size = AES_BLOCK_SIZE;
1124 break;
1125 }
1126 ctx->is_aead = false;
1127
1128 dd = atmel_aes_find_dev(ctx);
1129 if (!dd)
1130 return -ENODEV;
1131
1132 rctx = ablkcipher_request_ctx(req);
1133 rctx->mode = mode;
1134
1135 if (!(mode & AES_FLAGS_ENCRYPT) && (req->src == req->dst)) {
1136 unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
1137
1138 if (req->nbytes >= ivsize)
1139 scatterwalk_map_and_copy(rctx->lastc, req->src,
1140 req->nbytes - ivsize,
1141 ivsize, 0);
1142 }
1143
1144 return atmel_aes_handle_queue(dd, &req->base);
1145 }
1146
1147 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1148 unsigned int keylen)
1149 {
1150 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1151
1152 if (keylen != AES_KEYSIZE_128 &&
1153 keylen != AES_KEYSIZE_192 &&
1154 keylen != AES_KEYSIZE_256) {
1155 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1156 return -EINVAL;
1157 }
1158
1159 memcpy(ctx->key, key, keylen);
1160 ctx->keylen = keylen;
1161
1162 return 0;
1163 }
1164
1165 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
1166 {
1167 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1168 }
1169
1170 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
1171 {
1172 return atmel_aes_crypt(req, AES_FLAGS_ECB);
1173 }
1174
1175 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
1176 {
1177 return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
1178 }
1179
1180 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
1181 {
1182 return atmel_aes_crypt(req, AES_FLAGS_CBC);
1183 }
1184
1185 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
1186 {
1187 return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);
1188 }
1189
1190 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
1191 {
1192 return atmel_aes_crypt(req, AES_FLAGS_OFB);
1193 }
1194
1195 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
1196 {
1197 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
1198 }
1199
1200 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
1201 {
1202 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
1203 }
1204
1205 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
1206 {
1207 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
1208 }
1209
1210 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
1211 {
1212 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
1213 }
1214
1215 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
1216 {
1217 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
1218 }
1219
1220 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
1221 {
1222 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
1223 }
1224
1225 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
1226 {
1227 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
1228 }
1229
1230 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
1231 {
1232 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
1233 }
1234
1235 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
1236 {
1237 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
1238 }
1239
1240 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
1241 {
1242 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
1243 }
1244
1245 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
1246 {
1247 return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);
1248 }
1249
1250 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
1251 {
1252 return atmel_aes_crypt(req, AES_FLAGS_CTR);
1253 }
1254
1255 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
1256 {
1257 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1258
1259 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1260 ctx->base.start = atmel_aes_start;
1261
1262 return 0;
1263 }
1264
1265 static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
1266 {
1267 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
1268
1269 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1270 ctx->base.start = atmel_aes_ctr_start;
1271
1272 return 0;
1273 }
1274
1275 static struct crypto_alg aes_algs[] = {
1276 {
1277 .cra_name = "ecb(aes)",
1278 .cra_driver_name = "atmel-ecb-aes",
1279 .cra_priority = ATMEL_AES_PRIORITY,
1280 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1281 .cra_blocksize = AES_BLOCK_SIZE,
1282 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1283 .cra_alignmask = 0xf,
1284 .cra_type = &crypto_ablkcipher_type,
1285 .cra_module = THIS_MODULE,
1286 .cra_init = atmel_aes_cra_init,
1287 .cra_u.ablkcipher = {
1288 .min_keysize = AES_MIN_KEY_SIZE,
1289 .max_keysize = AES_MAX_KEY_SIZE,
1290 .setkey = atmel_aes_setkey,
1291 .encrypt = atmel_aes_ecb_encrypt,
1292 .decrypt = atmel_aes_ecb_decrypt,
1293 }
1294 },
1295 {
1296 .cra_name = "cbc(aes)",
1297 .cra_driver_name = "atmel-cbc-aes",
1298 .cra_priority = ATMEL_AES_PRIORITY,
1299 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1300 .cra_blocksize = AES_BLOCK_SIZE,
1301 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1302 .cra_alignmask = 0xf,
1303 .cra_type = &crypto_ablkcipher_type,
1304 .cra_module = THIS_MODULE,
1305 .cra_init = atmel_aes_cra_init,
1306 .cra_u.ablkcipher = {
1307 .min_keysize = AES_MIN_KEY_SIZE,
1308 .max_keysize = AES_MAX_KEY_SIZE,
1309 .ivsize = AES_BLOCK_SIZE,
1310 .setkey = atmel_aes_setkey,
1311 .encrypt = atmel_aes_cbc_encrypt,
1312 .decrypt = atmel_aes_cbc_decrypt,
1313 }
1314 },
1315 {
1316 .cra_name = "ofb(aes)",
1317 .cra_driver_name = "atmel-ofb-aes",
1318 .cra_priority = ATMEL_AES_PRIORITY,
1319 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1320 .cra_blocksize = AES_BLOCK_SIZE,
1321 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1322 .cra_alignmask = 0xf,
1323 .cra_type = &crypto_ablkcipher_type,
1324 .cra_module = THIS_MODULE,
1325 .cra_init = atmel_aes_cra_init,
1326 .cra_u.ablkcipher = {
1327 .min_keysize = AES_MIN_KEY_SIZE,
1328 .max_keysize = AES_MAX_KEY_SIZE,
1329 .ivsize = AES_BLOCK_SIZE,
1330 .setkey = atmel_aes_setkey,
1331 .encrypt = atmel_aes_ofb_encrypt,
1332 .decrypt = atmel_aes_ofb_decrypt,
1333 }
1334 },
1335 {
1336 .cra_name = "cfb(aes)",
1337 .cra_driver_name = "atmel-cfb-aes",
1338 .cra_priority = ATMEL_AES_PRIORITY,
1339 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1340 .cra_blocksize = AES_BLOCK_SIZE,
1341 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1342 .cra_alignmask = 0xf,
1343 .cra_type = &crypto_ablkcipher_type,
1344 .cra_module = THIS_MODULE,
1345 .cra_init = atmel_aes_cra_init,
1346 .cra_u.ablkcipher = {
1347 .min_keysize = AES_MIN_KEY_SIZE,
1348 .max_keysize = AES_MAX_KEY_SIZE,
1349 .ivsize = AES_BLOCK_SIZE,
1350 .setkey = atmel_aes_setkey,
1351 .encrypt = atmel_aes_cfb_encrypt,
1352 .decrypt = atmel_aes_cfb_decrypt,
1353 }
1354 },
1355 {
1356 .cra_name = "cfb32(aes)",
1357 .cra_driver_name = "atmel-cfb32-aes",
1358 .cra_priority = ATMEL_AES_PRIORITY,
1359 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1360 .cra_blocksize = CFB32_BLOCK_SIZE,
1361 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1362 .cra_alignmask = 0x3,
1363 .cra_type = &crypto_ablkcipher_type,
1364 .cra_module = THIS_MODULE,
1365 .cra_init = atmel_aes_cra_init,
1366 .cra_u.ablkcipher = {
1367 .min_keysize = AES_MIN_KEY_SIZE,
1368 .max_keysize = AES_MAX_KEY_SIZE,
1369 .ivsize = AES_BLOCK_SIZE,
1370 .setkey = atmel_aes_setkey,
1371 .encrypt = atmel_aes_cfb32_encrypt,
1372 .decrypt = atmel_aes_cfb32_decrypt,
1373 }
1374 },
1375 {
1376 .cra_name = "cfb16(aes)",
1377 .cra_driver_name = "atmel-cfb16-aes",
1378 .cra_priority = ATMEL_AES_PRIORITY,
1379 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1380 .cra_blocksize = CFB16_BLOCK_SIZE,
1381 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1382 .cra_alignmask = 0x1,
1383 .cra_type = &crypto_ablkcipher_type,
1384 .cra_module = THIS_MODULE,
1385 .cra_init = atmel_aes_cra_init,
1386 .cra_u.ablkcipher = {
1387 .min_keysize = AES_MIN_KEY_SIZE,
1388 .max_keysize = AES_MAX_KEY_SIZE,
1389 .ivsize = AES_BLOCK_SIZE,
1390 .setkey = atmel_aes_setkey,
1391 .encrypt = atmel_aes_cfb16_encrypt,
1392 .decrypt = atmel_aes_cfb16_decrypt,
1393 }
1394 },
1395 {
1396 .cra_name = "cfb8(aes)",
1397 .cra_driver_name = "atmel-cfb8-aes",
1398 .cra_priority = ATMEL_AES_PRIORITY,
1399 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1400 .cra_blocksize = CFB8_BLOCK_SIZE,
1401 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1402 .cra_alignmask = 0x0,
1403 .cra_type = &crypto_ablkcipher_type,
1404 .cra_module = THIS_MODULE,
1405 .cra_init = atmel_aes_cra_init,
1406 .cra_u.ablkcipher = {
1407 .min_keysize = AES_MIN_KEY_SIZE,
1408 .max_keysize = AES_MAX_KEY_SIZE,
1409 .ivsize = AES_BLOCK_SIZE,
1410 .setkey = atmel_aes_setkey,
1411 .encrypt = atmel_aes_cfb8_encrypt,
1412 .decrypt = atmel_aes_cfb8_decrypt,
1413 }
1414 },
1415 {
1416 .cra_name = "ctr(aes)",
1417 .cra_driver_name = "atmel-ctr-aes",
1418 .cra_priority = ATMEL_AES_PRIORITY,
1419 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1420 .cra_blocksize = 1,
1421 .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1422 .cra_alignmask = 0xf,
1423 .cra_type = &crypto_ablkcipher_type,
1424 .cra_module = THIS_MODULE,
1425 .cra_init = atmel_aes_ctr_cra_init,
1426 .cra_u.ablkcipher = {
1427 .min_keysize = AES_MIN_KEY_SIZE,
1428 .max_keysize = AES_MAX_KEY_SIZE,
1429 .ivsize = AES_BLOCK_SIZE,
1430 .setkey = atmel_aes_setkey,
1431 .encrypt = atmel_aes_ctr_encrypt,
1432 .decrypt = atmel_aes_ctr_decrypt,
1433 }
1434 },
1435 };
1436
1437 static struct crypto_alg aes_cfb64_alg = {
1438 .cra_name = "cfb64(aes)",
1439 .cra_driver_name = "atmel-cfb64-aes",
1440 .cra_priority = ATMEL_AES_PRIORITY,
1441 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1442 .cra_blocksize = CFB64_BLOCK_SIZE,
1443 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1444 .cra_alignmask = 0x7,
1445 .cra_type = &crypto_ablkcipher_type,
1446 .cra_module = THIS_MODULE,
1447 .cra_init = atmel_aes_cra_init,
1448 .cra_u.ablkcipher = {
1449 .min_keysize = AES_MIN_KEY_SIZE,
1450 .max_keysize = AES_MAX_KEY_SIZE,
1451 .ivsize = AES_BLOCK_SIZE,
1452 .setkey = atmel_aes_setkey,
1453 .encrypt = atmel_aes_cfb64_encrypt,
1454 .decrypt = atmel_aes_cfb64_decrypt,
1455 }
1456 };
1457
1458
1459 /* gcm aead functions */
1460
1461 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1462 const u32 *data, size_t datalen,
1463 const u32 *ghash_in, u32 *ghash_out,
1464 atmel_aes_fn_t resume);
1465 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd);
1466 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd);
1467
1468 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd);
1469 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd);
1470 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd);
1471 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd);
1472 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd);
1473 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd);
1474 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd);
1475
1476 static inline struct atmel_aes_gcm_ctx *
1477 atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx)
1478 {
1479 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1480 }
1481
1482 static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd,
1483 const u32 *data, size_t datalen,
1484 const u32 *ghash_in, u32 *ghash_out,
1485 atmel_aes_fn_t resume)
1486 {
1487 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1488
1489 dd->data = (u32 *)data;
1490 dd->datalen = datalen;
1491 ctx->ghash_in = ghash_in;
1492 ctx->ghash_out = ghash_out;
1493 ctx->ghash_resume = resume;
1494
1495 atmel_aes_write_ctrl(dd, false, NULL);
1496 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init);
1497 }
1498
1499 static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
1500 {
1501 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1502
1503 /* Set the data length. */
1504 atmel_aes_write(dd, AES_AADLENR, dd->total);
1505 atmel_aes_write(dd, AES_CLENR, 0);
1506
1507 /* If needed, overwrite the GCM Intermediate Hash Word Registers */
1508 if (ctx->ghash_in)
1509 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in);
1510
1511 return atmel_aes_gcm_ghash_finalize(dd);
1512 }
1513
1514 static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd)
1515 {
1516 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1517 u32 isr;
1518
1519 /* Write data into the Input Data Registers. */
1520 while (dd->datalen > 0) {
1521 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1522 dd->data += 4;
1523 dd->datalen -= AES_BLOCK_SIZE;
1524
1525 isr = atmel_aes_read(dd, AES_ISR);
1526 if (!(isr & AES_INT_DATARDY)) {
1527 dd->resume = atmel_aes_gcm_ghash_finalize;
1528 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1529 return -EINPROGRESS;
1530 }
1531 }
1532
1533 /* Read the computed hash from GHASHRx. */
1534 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out);
1535
1536 return ctx->ghash_resume(dd);
1537 }
1538
1539
1540 static int atmel_aes_gcm_start(struct atmel_aes_dev *dd)
1541 {
1542 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1543 struct aead_request *req = aead_request_cast(dd->areq);
1544 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1545 struct atmel_aes_reqctx *rctx = aead_request_ctx(req);
1546 size_t ivsize = crypto_aead_ivsize(tfm);
1547 size_t datalen, padlen;
1548 const void *iv = req->iv;
1549 u8 *data = dd->buf;
1550 int err;
1551
1552 atmel_aes_set_mode(dd, rctx);
1553
1554 err = atmel_aes_hw_init(dd);
1555 if (err)
1556 return atmel_aes_complete(dd, err);
1557
1558 if (likely(ivsize == GCM_AES_IV_SIZE)) {
1559 memcpy(ctx->j0, iv, ivsize);
1560 ctx->j0[3] = cpu_to_be32(1);
1561 return atmel_aes_gcm_process(dd);
1562 }
1563
1564 padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE);
1565 datalen = ivsize + padlen + AES_BLOCK_SIZE;
1566 if (datalen > dd->buflen)
1567 return atmel_aes_complete(dd, -EINVAL);
1568
1569 memcpy(data, iv, ivsize);
1570 memset(data + ivsize, 0, padlen + sizeof(u64));
1571 ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8);
1572
1573 return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen,
1574 NULL, ctx->j0, atmel_aes_gcm_process);
1575 }
1576
1577 static int atmel_aes_gcm_process(struct atmel_aes_dev *dd)
1578 {
1579 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1580 struct aead_request *req = aead_request_cast(dd->areq);
1581 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1582 bool enc = atmel_aes_is_encrypt(dd);
1583 u32 authsize;
1584
1585 /* Compute text length. */
1586 authsize = crypto_aead_authsize(tfm);
1587 ctx->textlen = req->cryptlen - (enc ? 0 : authsize);
1588
1589 /*
1590 * According to tcrypt test suite, the GCM Automatic Tag Generation
1591 * fails when both the message and its associated data are empty.
1592 */
1593 if (likely(req->assoclen != 0 || ctx->textlen != 0))
1594 dd->flags |= AES_FLAGS_GTAGEN;
1595
1596 atmel_aes_write_ctrl(dd, false, NULL);
1597 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length);
1598 }
1599
1600 static int atmel_aes_gcm_length(struct atmel_aes_dev *dd)
1601 {
1602 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1603 struct aead_request *req = aead_request_cast(dd->areq);
1604 u32 j0_lsw, *j0 = ctx->j0;
1605 size_t padlen;
1606
1607 /* Write incr32(J0) into IV. */
1608 j0_lsw = j0[3];
1609 j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1);
1610 atmel_aes_write_block(dd, AES_IVR(0), j0);
1611 j0[3] = j0_lsw;
1612
1613 /* Set aad and text lengths. */
1614 atmel_aes_write(dd, AES_AADLENR, req->assoclen);
1615 atmel_aes_write(dd, AES_CLENR, ctx->textlen);
1616
1617 /* Check whether AAD are present. */
1618 if (unlikely(req->assoclen == 0)) {
1619 dd->datalen = 0;
1620 return atmel_aes_gcm_data(dd);
1621 }
1622
1623 /* Copy assoc data and add padding. */
1624 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE);
1625 if (unlikely(req->assoclen + padlen > dd->buflen))
1626 return atmel_aes_complete(dd, -EINVAL);
1627 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen);
1628
1629 /* Write assoc data into the Input Data register. */
1630 dd->data = (u32 *)dd->buf;
1631 dd->datalen = req->assoclen + padlen;
1632 return atmel_aes_gcm_data(dd);
1633 }
1634
1635 static int atmel_aes_gcm_data(struct atmel_aes_dev *dd)
1636 {
1637 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1638 struct aead_request *req = aead_request_cast(dd->areq);
1639 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD);
1640 struct scatterlist *src, *dst;
1641 u32 isr, mr;
1642
1643 /* Write AAD first. */
1644 while (dd->datalen > 0) {
1645 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
1646 dd->data += 4;
1647 dd->datalen -= AES_BLOCK_SIZE;
1648
1649 isr = atmel_aes_read(dd, AES_ISR);
1650 if (!(isr & AES_INT_DATARDY)) {
1651 dd->resume = atmel_aes_gcm_data;
1652 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
1653 return -EINPROGRESS;
1654 }
1655 }
1656
1657 /* GMAC only. */
1658 if (unlikely(ctx->textlen == 0))
1659 return atmel_aes_gcm_tag_init(dd);
1660
1661 /* Prepare src and dst scatter lists to transfer cipher/plain texts */
1662 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen);
1663 dst = ((req->src == req->dst) ? src :
1664 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen));
1665
1666 if (use_dma) {
1667 /* Update the Mode Register for DMA transfers. */
1668 mr = atmel_aes_read(dd, AES_MR);
1669 mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF);
1670 mr |= AES_MR_SMOD_IDATAR0;
1671 if (dd->caps.has_dualbuff)
1672 mr |= AES_MR_DUALBUFF;
1673 atmel_aes_write(dd, AES_MR, mr);
1674
1675 return atmel_aes_dma_start(dd, src, dst, ctx->textlen,
1676 atmel_aes_gcm_tag_init);
1677 }
1678
1679 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen,
1680 atmel_aes_gcm_tag_init);
1681 }
1682
1683 static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd)
1684 {
1685 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1686 struct aead_request *req = aead_request_cast(dd->areq);
1687 u64 *data = dd->buf;
1688
1689 if (likely(dd->flags & AES_FLAGS_GTAGEN)) {
1690 if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) {
1691 dd->resume = atmel_aes_gcm_tag_init;
1692 atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY);
1693 return -EINPROGRESS;
1694 }
1695
1696 return atmel_aes_gcm_finalize(dd);
1697 }
1698
1699 /* Read the GCM Intermediate Hash Word Registers. */
1700 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash);
1701
1702 data[0] = cpu_to_be64(req->assoclen * 8);
1703 data[1] = cpu_to_be64(ctx->textlen * 8);
1704
1705 return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE,
1706 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag);
1707 }
1708
1709 static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd)
1710 {
1711 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1712 unsigned long flags;
1713
1714 /*
1715 * Change mode to CTR to complete the tag generation.
1716 * Use J0 as Initialization Vector.
1717 */
1718 flags = dd->flags;
1719 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN);
1720 dd->flags |= AES_FLAGS_CTR;
1721 atmel_aes_write_ctrl(dd, false, ctx->j0);
1722 dd->flags = flags;
1723
1724 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash);
1725 return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize);
1726 }
1727
1728 static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd)
1729 {
1730 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
1731 struct aead_request *req = aead_request_cast(dd->areq);
1732 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1733 bool enc = atmel_aes_is_encrypt(dd);
1734 u32 offset, authsize, itag[4], *otag = ctx->tag;
1735 int err;
1736
1737 /* Read the computed tag. */
1738 if (likely(dd->flags & AES_FLAGS_GTAGEN))
1739 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag);
1740 else
1741 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag);
1742
1743 offset = req->assoclen + ctx->textlen;
1744 authsize = crypto_aead_authsize(tfm);
1745 if (enc) {
1746 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1);
1747 err = 0;
1748 } else {
1749 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0);
1750 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0;
1751 }
1752
1753 return atmel_aes_complete(dd, err);
1754 }
1755
1756 static int atmel_aes_gcm_crypt(struct aead_request *req,
1757 unsigned long mode)
1758 {
1759 struct atmel_aes_base_ctx *ctx;
1760 struct atmel_aes_reqctx *rctx;
1761 struct atmel_aes_dev *dd;
1762
1763 ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1764 ctx->block_size = AES_BLOCK_SIZE;
1765 ctx->is_aead = true;
1766
1767 dd = atmel_aes_find_dev(ctx);
1768 if (!dd)
1769 return -ENODEV;
1770
1771 rctx = aead_request_ctx(req);
1772 rctx->mode = AES_FLAGS_GCM | mode;
1773
1774 return atmel_aes_handle_queue(dd, &req->base);
1775 }
1776
1777 static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
1778 unsigned int keylen)
1779 {
1780 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
1781
1782 if (keylen != AES_KEYSIZE_256 &&
1783 keylen != AES_KEYSIZE_192 &&
1784 keylen != AES_KEYSIZE_128) {
1785 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1786 return -EINVAL;
1787 }
1788
1789 memcpy(ctx->key, key, keylen);
1790 ctx->keylen = keylen;
1791
1792 return 0;
1793 }
1794
1795 static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm,
1796 unsigned int authsize)
1797 {
1798 /* Same as crypto_gcm_authsize() from crypto/gcm.c */
1799 switch (authsize) {
1800 case 4:
1801 case 8:
1802 case 12:
1803 case 13:
1804 case 14:
1805 case 15:
1806 case 16:
1807 break;
1808 default:
1809 return -EINVAL;
1810 }
1811
1812 return 0;
1813 }
1814
1815 static int atmel_aes_gcm_encrypt(struct aead_request *req)
1816 {
1817 return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT);
1818 }
1819
1820 static int atmel_aes_gcm_decrypt(struct aead_request *req)
1821 {
1822 return atmel_aes_gcm_crypt(req, 0);
1823 }
1824
1825 static int atmel_aes_gcm_init(struct crypto_aead *tfm)
1826 {
1827 struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm);
1828
1829 crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx));
1830 ctx->base.start = atmel_aes_gcm_start;
1831
1832 return 0;
1833 }
1834
1835 static struct aead_alg aes_gcm_alg = {
1836 .setkey = atmel_aes_gcm_setkey,
1837 .setauthsize = atmel_aes_gcm_setauthsize,
1838 .encrypt = atmel_aes_gcm_encrypt,
1839 .decrypt = atmel_aes_gcm_decrypt,
1840 .init = atmel_aes_gcm_init,
1841 .ivsize = GCM_AES_IV_SIZE,
1842 .maxauthsize = AES_BLOCK_SIZE,
1843
1844 .base = {
1845 .cra_name = "gcm(aes)",
1846 .cra_driver_name = "atmel-gcm-aes",
1847 .cra_priority = ATMEL_AES_PRIORITY,
1848 .cra_flags = CRYPTO_ALG_ASYNC,
1849 .cra_blocksize = 1,
1850 .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx),
1851 .cra_alignmask = 0xf,
1852 .cra_module = THIS_MODULE,
1853 },
1854 };
1855
1856
1857 /* xts functions */
1858
1859 static inline struct atmel_aes_xts_ctx *
1860 atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
1861 {
1862 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1863 }
1864
1865 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
1866
1867 static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
1868 {
1869 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
1870 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1871 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
1872 unsigned long flags;
1873 int err;
1874
1875 atmel_aes_set_mode(dd, rctx);
1876
1877 err = atmel_aes_hw_init(dd);
1878 if (err)
1879 return atmel_aes_complete(dd, err);
1880
1881 /* Compute the tweak value from req->info with ecb(aes). */
1882 flags = dd->flags;
1883 dd->flags &= ~AES_FLAGS_MODE_MASK;
1884 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
1885 atmel_aes_write_ctrl_key(dd, false, NULL,
1886 ctx->key2, ctx->base.keylen);
1887 dd->flags = flags;
1888
1889 atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
1890 return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
1891 }
1892
1893 static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
1894 {
1895 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
1896 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
1897 u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
1898 static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
1899 u8 *tweak_bytes = (u8 *)tweak;
1900 int i;
1901
1902 /* Read the computed ciphered tweak value. */
1903 atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
1904 /*
1905 * Hardware quirk:
1906 * the order of the ciphered tweak bytes need to be reversed before
1907 * writing them into the ODATARx registers.
1908 */
1909 for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
1910 u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
1911
1912 tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
1913 tweak_bytes[i] = tmp;
1914 }
1915
1916 /* Process the data. */
1917 atmel_aes_write_ctrl(dd, use_dma, NULL);
1918 atmel_aes_write_block(dd, AES_TWR(0), tweak);
1919 atmel_aes_write_block(dd, AES_ALPHAR(0), one);
1920 if (use_dma)
1921 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
1922 atmel_aes_transfer_complete);
1923
1924 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
1925 atmel_aes_transfer_complete);
1926 }
1927
1928 static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1929 unsigned int keylen)
1930 {
1931 struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
1932 int err;
1933
1934 err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
1935 if (err)
1936 return err;
1937
1938 memcpy(ctx->base.key, key, keylen/2);
1939 memcpy(ctx->key2, key + keylen/2, keylen/2);
1940 ctx->base.keylen = keylen/2;
1941
1942 return 0;
1943 }
1944
1945 static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
1946 {
1947 return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
1948 }
1949
1950 static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
1951 {
1952 return atmel_aes_crypt(req, AES_FLAGS_XTS);
1953 }
1954
1955 static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
1956 {
1957 struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
1958
1959 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
1960 ctx->base.start = atmel_aes_xts_start;
1961
1962 return 0;
1963 }
1964
1965 static struct crypto_alg aes_xts_alg = {
1966 .cra_name = "xts(aes)",
1967 .cra_driver_name = "atmel-xts-aes",
1968 .cra_priority = ATMEL_AES_PRIORITY,
1969 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1970 .cra_blocksize = AES_BLOCK_SIZE,
1971 .cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1972 .cra_alignmask = 0xf,
1973 .cra_type = &crypto_ablkcipher_type,
1974 .cra_module = THIS_MODULE,
1975 .cra_init = atmel_aes_xts_cra_init,
1976 .cra_u.ablkcipher = {
1977 .min_keysize = 2 * AES_MIN_KEY_SIZE,
1978 .max_keysize = 2 * AES_MAX_KEY_SIZE,
1979 .ivsize = AES_BLOCK_SIZE,
1980 .setkey = atmel_aes_xts_setkey,
1981 .encrypt = atmel_aes_xts_encrypt,
1982 .decrypt = atmel_aes_xts_decrypt,
1983 }
1984 };
1985
1986 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
1987 /* authenc aead functions */
1988
1989 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd);
1990 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
1991 bool is_async);
1992 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
1993 bool is_async);
1994 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd);
1995 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
1996 bool is_async);
1997
1998 static void atmel_aes_authenc_complete(struct atmel_aes_dev *dd, int err)
1999 {
2000 struct aead_request *req = aead_request_cast(dd->areq);
2001 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2002
2003 if (err && (dd->flags & AES_FLAGS_OWN_SHA))
2004 atmel_sha_authenc_abort(&rctx->auth_req);
2005 dd->flags &= ~AES_FLAGS_OWN_SHA;
2006 }
2007
2008 static int atmel_aes_authenc_start(struct atmel_aes_dev *dd)
2009 {
2010 struct aead_request *req = aead_request_cast(dd->areq);
2011 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2012 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2013 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2014 int err;
2015
2016 atmel_aes_set_mode(dd, &rctx->base);
2017
2018 err = atmel_aes_hw_init(dd);
2019 if (err)
2020 return atmel_aes_complete(dd, err);
2021
2022 return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth,
2023 atmel_aes_authenc_init, dd);
2024 }
2025
2026 static int atmel_aes_authenc_init(struct atmel_aes_dev *dd, int err,
2027 bool is_async)
2028 {
2029 struct aead_request *req = aead_request_cast(dd->areq);
2030 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2031
2032 if (is_async)
2033 dd->is_async = true;
2034 if (err)
2035 return atmel_aes_complete(dd, err);
2036
2037 /* If here, we've got the ownership of the SHA device. */
2038 dd->flags |= AES_FLAGS_OWN_SHA;
2039
2040 /* Configure the SHA device. */
2041 return atmel_sha_authenc_init(&rctx->auth_req,
2042 req->src, req->assoclen,
2043 rctx->textlen,
2044 atmel_aes_authenc_transfer, dd);
2045 }
2046
2047 static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
2048 bool is_async)
2049 {
2050 struct aead_request *req = aead_request_cast(dd->areq);
2051 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2052 bool enc = atmel_aes_is_encrypt(dd);
2053 struct scatterlist *src, *dst;
2054 u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
2055 u32 emr;
2056
2057 if (is_async)
2058 dd->is_async = true;
2059 if (err)
2060 return atmel_aes_complete(dd, err);
2061
2062 /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */
2063 src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen);
2064 dst = src;
2065
2066 if (req->src != req->dst)
2067 dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen);
2068
2069 /* Configure the AES device. */
2070 memcpy(iv, req->iv, sizeof(iv));
2071
2072 /*
2073 * Here we always set the 2nd parameter of atmel_aes_write_ctrl() to
2074 * 'true' even if the data transfer is actually performed by the CPU (so
2075 * not by the DMA) because we must force the AES_MR_SMOD bitfield to the
2076 * value AES_MR_SMOD_IDATAR0. Indeed, both AES_MR_SMOD and SHA_MR_SMOD
2077 * must be set to *_MR_SMOD_IDATAR0.
2078 */
2079 atmel_aes_write_ctrl(dd, true, iv);
2080 emr = AES_EMR_PLIPEN;
2081 if (!enc)
2082 emr |= AES_EMR_PLIPD;
2083 atmel_aes_write(dd, AES_EMR, emr);
2084
2085 /* Transfer data. */
2086 return atmel_aes_dma_start(dd, src, dst, rctx->textlen,
2087 atmel_aes_authenc_digest);
2088 }
2089
2090 static int atmel_aes_authenc_digest(struct atmel_aes_dev *dd)
2091 {
2092 struct aead_request *req = aead_request_cast(dd->areq);
2093 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2094
2095 /* atmel_sha_authenc_final() releases the SHA device. */
2096 dd->flags &= ~AES_FLAGS_OWN_SHA;
2097 return atmel_sha_authenc_final(&rctx->auth_req,
2098 rctx->digest, sizeof(rctx->digest),
2099 atmel_aes_authenc_final, dd);
2100 }
2101
2102 static int atmel_aes_authenc_final(struct atmel_aes_dev *dd, int err,
2103 bool is_async)
2104 {
2105 struct aead_request *req = aead_request_cast(dd->areq);
2106 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2107 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2108 bool enc = atmel_aes_is_encrypt(dd);
2109 u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest;
2110 u32 offs, authsize;
2111
2112 if (is_async)
2113 dd->is_async = true;
2114 if (err)
2115 goto complete;
2116
2117 offs = req->assoclen + rctx->textlen;
2118 authsize = crypto_aead_authsize(tfm);
2119 if (enc) {
2120 scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1);
2121 } else {
2122 scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0);
2123 if (crypto_memneq(idigest, odigest, authsize))
2124 err = -EBADMSG;
2125 }
2126
2127 complete:
2128 return atmel_aes_complete(dd, err);
2129 }
2130
2131 static int atmel_aes_authenc_setkey(struct crypto_aead *tfm, const u8 *key,
2132 unsigned int keylen)
2133 {
2134 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2135 struct crypto_authenc_keys keys;
2136 u32 flags;
2137 int err;
2138
2139 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
2140 goto badkey;
2141
2142 if (keys.enckeylen > sizeof(ctx->base.key))
2143 goto badkey;
2144
2145 /* Save auth key. */
2146 flags = crypto_aead_get_flags(tfm);
2147 err = atmel_sha_authenc_setkey(ctx->auth,
2148 keys.authkey, keys.authkeylen,
2149 &flags);
2150 crypto_aead_set_flags(tfm, flags & CRYPTO_TFM_RES_MASK);
2151 if (err) {
2152 memzero_explicit(&keys, sizeof(keys));
2153 return err;
2154 }
2155
2156 /* Save enc key. */
2157 ctx->base.keylen = keys.enckeylen;
2158 memcpy(ctx->base.key, keys.enckey, keys.enckeylen);
2159
2160 memzero_explicit(&keys, sizeof(keys));
2161 return 0;
2162
2163 badkey:
2164 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
2165 memzero_explicit(&keys, sizeof(keys));
2166 return -EINVAL;
2167 }
2168
2169 static int atmel_aes_authenc_init_tfm(struct crypto_aead *tfm,
2170 unsigned long auth_mode)
2171 {
2172 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2173 unsigned int auth_reqsize = atmel_sha_authenc_get_reqsize();
2174
2175 ctx->auth = atmel_sha_authenc_spawn(auth_mode);
2176 if (IS_ERR(ctx->auth))
2177 return PTR_ERR(ctx->auth);
2178
2179 crypto_aead_set_reqsize(tfm, (sizeof(struct atmel_aes_authenc_reqctx) +
2180 auth_reqsize));
2181 ctx->base.start = atmel_aes_authenc_start;
2182
2183 return 0;
2184 }
2185
2186 static int atmel_aes_authenc_hmac_sha1_init_tfm(struct crypto_aead *tfm)
2187 {
2188 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA1);
2189 }
2190
2191 static int atmel_aes_authenc_hmac_sha224_init_tfm(struct crypto_aead *tfm)
2192 {
2193 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA224);
2194 }
2195
2196 static int atmel_aes_authenc_hmac_sha256_init_tfm(struct crypto_aead *tfm)
2197 {
2198 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA256);
2199 }
2200
2201 static int atmel_aes_authenc_hmac_sha384_init_tfm(struct crypto_aead *tfm)
2202 {
2203 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA384);
2204 }
2205
2206 static int atmel_aes_authenc_hmac_sha512_init_tfm(struct crypto_aead *tfm)
2207 {
2208 return atmel_aes_authenc_init_tfm(tfm, SHA_FLAGS_HMAC_SHA512);
2209 }
2210
2211 static void atmel_aes_authenc_exit_tfm(struct crypto_aead *tfm)
2212 {
2213 struct atmel_aes_authenc_ctx *ctx = crypto_aead_ctx(tfm);
2214
2215 atmel_sha_authenc_free(ctx->auth);
2216 }
2217
2218 static int atmel_aes_authenc_crypt(struct aead_request *req,
2219 unsigned long mode)
2220 {
2221 struct atmel_aes_authenc_reqctx *rctx = aead_request_ctx(req);
2222 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
2223 struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm);
2224 u32 authsize = crypto_aead_authsize(tfm);
2225 bool enc = (mode & AES_FLAGS_ENCRYPT);
2226 struct atmel_aes_dev *dd;
2227
2228 /* Compute text length. */
2229 if (!enc && req->cryptlen < authsize)
2230 return -EINVAL;
2231 rctx->textlen = req->cryptlen - (enc ? 0 : authsize);
2232
2233 /*
2234 * Currently, empty messages are not supported yet:
2235 * the SHA auto-padding can be used only on non-empty messages.
2236 * Hence a special case needs to be implemented for empty message.
2237 */
2238 if (!rctx->textlen && !req->assoclen)
2239 return -EINVAL;
2240
2241 rctx->base.mode = mode;
2242 ctx->block_size = AES_BLOCK_SIZE;
2243 ctx->is_aead = true;
2244
2245 dd = atmel_aes_find_dev(ctx);
2246 if (!dd)
2247 return -ENODEV;
2248
2249 return atmel_aes_handle_queue(dd, &req->base);
2250 }
2251
2252 static int atmel_aes_authenc_cbc_aes_encrypt(struct aead_request *req)
2253 {
2254 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT);
2255 }
2256
2257 static int atmel_aes_authenc_cbc_aes_decrypt(struct aead_request *req)
2258 {
2259 return atmel_aes_authenc_crypt(req, AES_FLAGS_CBC);
2260 }
2261
2262 static struct aead_alg aes_authenc_algs[] = {
2263 {
2264 .setkey = atmel_aes_authenc_setkey,
2265 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2266 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2267 .init = atmel_aes_authenc_hmac_sha1_init_tfm,
2268 .exit = atmel_aes_authenc_exit_tfm,
2269 .ivsize = AES_BLOCK_SIZE,
2270 .maxauthsize = SHA1_DIGEST_SIZE,
2271
2272 .base = {
2273 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2274 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes",
2275 .cra_priority = ATMEL_AES_PRIORITY,
2276 .cra_flags = CRYPTO_ALG_ASYNC,
2277 .cra_blocksize = AES_BLOCK_SIZE,
2278 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2279 .cra_alignmask = 0xf,
2280 .cra_module = THIS_MODULE,
2281 },
2282 },
2283 {
2284 .setkey = atmel_aes_authenc_setkey,
2285 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2286 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2287 .init = atmel_aes_authenc_hmac_sha224_init_tfm,
2288 .exit = atmel_aes_authenc_exit_tfm,
2289 .ivsize = AES_BLOCK_SIZE,
2290 .maxauthsize = SHA224_DIGEST_SIZE,
2291
2292 .base = {
2293 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2294 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes",
2295 .cra_priority = ATMEL_AES_PRIORITY,
2296 .cra_flags = CRYPTO_ALG_ASYNC,
2297 .cra_blocksize = AES_BLOCK_SIZE,
2298 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2299 .cra_alignmask = 0xf,
2300 .cra_module = THIS_MODULE,
2301 },
2302 },
2303 {
2304 .setkey = atmel_aes_authenc_setkey,
2305 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2306 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2307 .init = atmel_aes_authenc_hmac_sha256_init_tfm,
2308 .exit = atmel_aes_authenc_exit_tfm,
2309 .ivsize = AES_BLOCK_SIZE,
2310 .maxauthsize = SHA256_DIGEST_SIZE,
2311
2312 .base = {
2313 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2314 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes",
2315 .cra_priority = ATMEL_AES_PRIORITY,
2316 .cra_flags = CRYPTO_ALG_ASYNC,
2317 .cra_blocksize = AES_BLOCK_SIZE,
2318 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2319 .cra_alignmask = 0xf,
2320 .cra_module = THIS_MODULE,
2321 },
2322 },
2323 {
2324 .setkey = atmel_aes_authenc_setkey,
2325 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2326 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2327 .init = atmel_aes_authenc_hmac_sha384_init_tfm,
2328 .exit = atmel_aes_authenc_exit_tfm,
2329 .ivsize = AES_BLOCK_SIZE,
2330 .maxauthsize = SHA384_DIGEST_SIZE,
2331
2332 .base = {
2333 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2334 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes",
2335 .cra_priority = ATMEL_AES_PRIORITY,
2336 .cra_flags = CRYPTO_ALG_ASYNC,
2337 .cra_blocksize = AES_BLOCK_SIZE,
2338 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2339 .cra_alignmask = 0xf,
2340 .cra_module = THIS_MODULE,
2341 },
2342 },
2343 {
2344 .setkey = atmel_aes_authenc_setkey,
2345 .encrypt = atmel_aes_authenc_cbc_aes_encrypt,
2346 .decrypt = atmel_aes_authenc_cbc_aes_decrypt,
2347 .init = atmel_aes_authenc_hmac_sha512_init_tfm,
2348 .exit = atmel_aes_authenc_exit_tfm,
2349 .ivsize = AES_BLOCK_SIZE,
2350 .maxauthsize = SHA512_DIGEST_SIZE,
2351
2352 .base = {
2353 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2354 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes",
2355 .cra_priority = ATMEL_AES_PRIORITY,
2356 .cra_flags = CRYPTO_ALG_ASYNC,
2357 .cra_blocksize = AES_BLOCK_SIZE,
2358 .cra_ctxsize = sizeof(struct atmel_aes_authenc_ctx),
2359 .cra_alignmask = 0xf,
2360 .cra_module = THIS_MODULE,
2361 },
2362 },
2363 };
2364 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2365
2366 /* Probe functions */
2367
2368 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
2369 {
2370 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
2371 dd->buflen = ATMEL_AES_BUFFER_SIZE;
2372 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
2373
2374 if (!dd->buf) {
2375 dev_err(dd->dev, "unable to alloc pages.\n");
2376 return -ENOMEM;
2377 }
2378
2379 return 0;
2380 }
2381
2382 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
2383 {
2384 free_page((unsigned long)dd->buf);
2385 }
2386
2387 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
2388 {
2389 struct at_dma_slave *sl = slave;
2390
2391 if (sl && sl->dma_dev == chan->device->dev) {
2392 chan->private = sl;
2393 return true;
2394 } else {
2395 return false;
2396 }
2397 }
2398
2399 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
2400 struct crypto_platform_data *pdata)
2401 {
2402 struct at_dma_slave *slave;
2403 dma_cap_mask_t mask;
2404
2405 dma_cap_zero(mask);
2406 dma_cap_set(DMA_SLAVE, mask);
2407
2408 /* Try to grab 2 DMA channels */
2409 slave = &pdata->dma_slave->rxdata;
2410 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2411 slave, dd->dev, "tx");
2412 if (!dd->src.chan)
2413 goto err_dma_in;
2414
2415 slave = &pdata->dma_slave->txdata;
2416 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
2417 slave, dd->dev, "rx");
2418 if (!dd->dst.chan)
2419 goto err_dma_out;
2420
2421 return 0;
2422
2423 err_dma_out:
2424 dma_release_channel(dd->src.chan);
2425 err_dma_in:
2426 dev_warn(dd->dev, "no DMA channel available\n");
2427 return -ENODEV;
2428 }
2429
2430 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
2431 {
2432 dma_release_channel(dd->dst.chan);
2433 dma_release_channel(dd->src.chan);
2434 }
2435
2436 static void atmel_aes_queue_task(unsigned long data)
2437 {
2438 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2439
2440 atmel_aes_handle_queue(dd, NULL);
2441 }
2442
2443 static void atmel_aes_done_task(unsigned long data)
2444 {
2445 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
2446
2447 dd->is_async = true;
2448 (void)dd->resume(dd);
2449 }
2450
2451 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
2452 {
2453 struct atmel_aes_dev *aes_dd = dev_id;
2454 u32 reg;
2455
2456 reg = atmel_aes_read(aes_dd, AES_ISR);
2457 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
2458 atmel_aes_write(aes_dd, AES_IDR, reg);
2459 if (AES_FLAGS_BUSY & aes_dd->flags)
2460 tasklet_schedule(&aes_dd->done_task);
2461 else
2462 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
2463 return IRQ_HANDLED;
2464 }
2465
2466 return IRQ_NONE;
2467 }
2468
2469 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
2470 {
2471 int i;
2472
2473 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2474 if (dd->caps.has_authenc)
2475 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++)
2476 crypto_unregister_aead(&aes_authenc_algs[i]);
2477 #endif
2478
2479 if (dd->caps.has_xts)
2480 crypto_unregister_alg(&aes_xts_alg);
2481
2482 if (dd->caps.has_gcm)
2483 crypto_unregister_aead(&aes_gcm_alg);
2484
2485 if (dd->caps.has_cfb64)
2486 crypto_unregister_alg(&aes_cfb64_alg);
2487
2488 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
2489 crypto_unregister_alg(&aes_algs[i]);
2490 }
2491
2492 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
2493 {
2494 int err, i, j;
2495
2496 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
2497 err = crypto_register_alg(&aes_algs[i]);
2498 if (err)
2499 goto err_aes_algs;
2500 }
2501
2502 if (dd->caps.has_cfb64) {
2503 err = crypto_register_alg(&aes_cfb64_alg);
2504 if (err)
2505 goto err_aes_cfb64_alg;
2506 }
2507
2508 if (dd->caps.has_gcm) {
2509 err = crypto_register_aead(&aes_gcm_alg);
2510 if (err)
2511 goto err_aes_gcm_alg;
2512 }
2513
2514 if (dd->caps.has_xts) {
2515 err = crypto_register_alg(&aes_xts_alg);
2516 if (err)
2517 goto err_aes_xts_alg;
2518 }
2519
2520 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2521 if (dd->caps.has_authenc) {
2522 for (i = 0; i < ARRAY_SIZE(aes_authenc_algs); i++) {
2523 err = crypto_register_aead(&aes_authenc_algs[i]);
2524 if (err)
2525 goto err_aes_authenc_alg;
2526 }
2527 }
2528 #endif
2529
2530 return 0;
2531
2532 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2533 /* i = ARRAY_SIZE(aes_authenc_algs); */
2534 err_aes_authenc_alg:
2535 for (j = 0; j < i; j++)
2536 crypto_unregister_aead(&aes_authenc_algs[j]);
2537 crypto_unregister_alg(&aes_xts_alg);
2538 #endif
2539 err_aes_xts_alg:
2540 crypto_unregister_aead(&aes_gcm_alg);
2541 err_aes_gcm_alg:
2542 crypto_unregister_alg(&aes_cfb64_alg);
2543 err_aes_cfb64_alg:
2544 i = ARRAY_SIZE(aes_algs);
2545 err_aes_algs:
2546 for (j = 0; j < i; j++)
2547 crypto_unregister_alg(&aes_algs[j]);
2548
2549 return err;
2550 }
2551
2552 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
2553 {
2554 dd->caps.has_dualbuff = 0;
2555 dd->caps.has_cfb64 = 0;
2556 dd->caps.has_ctr32 = 0;
2557 dd->caps.has_gcm = 0;
2558 dd->caps.has_xts = 0;
2559 dd->caps.has_authenc = 0;
2560 dd->caps.max_burst_size = 1;
2561
2562 /* keep only major version number */
2563 switch (dd->hw_version & 0xff0) {
2564 case 0x500:
2565 dd->caps.has_dualbuff = 1;
2566 dd->caps.has_cfb64 = 1;
2567 dd->caps.has_ctr32 = 1;
2568 dd->caps.has_gcm = 1;
2569 dd->caps.has_xts = 1;
2570 dd->caps.has_authenc = 1;
2571 dd->caps.max_burst_size = 4;
2572 break;
2573 case 0x200:
2574 dd->caps.has_dualbuff = 1;
2575 dd->caps.has_cfb64 = 1;
2576 dd->caps.has_ctr32 = 1;
2577 dd->caps.has_gcm = 1;
2578 dd->caps.max_burst_size = 4;
2579 break;
2580 case 0x130:
2581 dd->caps.has_dualbuff = 1;
2582 dd->caps.has_cfb64 = 1;
2583 dd->caps.max_burst_size = 4;
2584 break;
2585 case 0x120:
2586 break;
2587 default:
2588 dev_warn(dd->dev,
2589 "Unmanaged aes version, set minimum capabilities\n");
2590 break;
2591 }
2592 }
2593
2594 #if defined(CONFIG_OF)
2595 static const struct of_device_id atmel_aes_dt_ids[] = {
2596 { .compatible = "atmel,at91sam9g46-aes" },
2597 { /* sentinel */ }
2598 };
2599 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
2600
2601 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2602 {
2603 struct device_node *np = pdev->dev.of_node;
2604 struct crypto_platform_data *pdata;
2605
2606 if (!np) {
2607 dev_err(&pdev->dev, "device node not found\n");
2608 return ERR_PTR(-EINVAL);
2609 }
2610
2611 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2612 if (!pdata) {
2613 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
2614 return ERR_PTR(-ENOMEM);
2615 }
2616
2617 pdata->dma_slave = devm_kzalloc(&pdev->dev,
2618 sizeof(*(pdata->dma_slave)),
2619 GFP_KERNEL);
2620 if (!pdata->dma_slave) {
2621 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
2622 devm_kfree(&pdev->dev, pdata);
2623 return ERR_PTR(-ENOMEM);
2624 }
2625
2626 return pdata;
2627 }
2628 #else
2629 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
2630 {
2631 return ERR_PTR(-EINVAL);
2632 }
2633 #endif
2634
2635 static int atmel_aes_probe(struct platform_device *pdev)
2636 {
2637 struct atmel_aes_dev *aes_dd;
2638 struct crypto_platform_data *pdata;
2639 struct device *dev = &pdev->dev;
2640 struct resource *aes_res;
2641 int err;
2642
2643 pdata = pdev->dev.platform_data;
2644 if (!pdata) {
2645 pdata = atmel_aes_of_init(pdev);
2646 if (IS_ERR(pdata)) {
2647 err = PTR_ERR(pdata);
2648 goto aes_dd_err;
2649 }
2650 }
2651
2652 if (!pdata->dma_slave) {
2653 err = -ENXIO;
2654 goto aes_dd_err;
2655 }
2656
2657 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
2658 if (aes_dd == NULL) {
2659 dev_err(dev, "unable to alloc data struct.\n");
2660 err = -ENOMEM;
2661 goto aes_dd_err;
2662 }
2663
2664 aes_dd->dev = dev;
2665
2666 platform_set_drvdata(pdev, aes_dd);
2667
2668 INIT_LIST_HEAD(&aes_dd->list);
2669 spin_lock_init(&aes_dd->lock);
2670
2671 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
2672 (unsigned long)aes_dd);
2673 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
2674 (unsigned long)aes_dd);
2675
2676 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
2677
2678 /* Get the base address */
2679 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2680 if (!aes_res) {
2681 dev_err(dev, "no MEM resource info\n");
2682 err = -ENODEV;
2683 goto res_err;
2684 }
2685 aes_dd->phys_base = aes_res->start;
2686
2687 /* Get the IRQ */
2688 aes_dd->irq = platform_get_irq(pdev, 0);
2689 if (aes_dd->irq < 0) {
2690 dev_err(dev, "no IRQ resource info\n");
2691 err = aes_dd->irq;
2692 goto res_err;
2693 }
2694
2695 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
2696 IRQF_SHARED, "atmel-aes", aes_dd);
2697 if (err) {
2698 dev_err(dev, "unable to request aes irq.\n");
2699 goto res_err;
2700 }
2701
2702 /* Initializing the clock */
2703 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
2704 if (IS_ERR(aes_dd->iclk)) {
2705 dev_err(dev, "clock initialization failed.\n");
2706 err = PTR_ERR(aes_dd->iclk);
2707 goto res_err;
2708 }
2709
2710 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
2711 if (IS_ERR(aes_dd->io_base)) {
2712 dev_err(dev, "can't ioremap\n");
2713 err = PTR_ERR(aes_dd->io_base);
2714 goto res_err;
2715 }
2716
2717 err = clk_prepare(aes_dd->iclk);
2718 if (err)
2719 goto res_err;
2720
2721 err = atmel_aes_hw_version_init(aes_dd);
2722 if (err)
2723 goto iclk_unprepare;
2724
2725 atmel_aes_get_cap(aes_dd);
2726
2727 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
2728 if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) {
2729 err = -EPROBE_DEFER;
2730 goto iclk_unprepare;
2731 }
2732 #endif
2733
2734 err = atmel_aes_buff_init(aes_dd);
2735 if (err)
2736 goto err_aes_buff;
2737
2738 err = atmel_aes_dma_init(aes_dd, pdata);
2739 if (err)
2740 goto err_aes_dma;
2741
2742 spin_lock(&atmel_aes.lock);
2743 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
2744 spin_unlock(&atmel_aes.lock);
2745
2746 err = atmel_aes_register_algs(aes_dd);
2747 if (err)
2748 goto err_algs;
2749
2750 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
2751 dma_chan_name(aes_dd->src.chan),
2752 dma_chan_name(aes_dd->dst.chan));
2753
2754 return 0;
2755
2756 err_algs:
2757 spin_lock(&atmel_aes.lock);
2758 list_del(&aes_dd->list);
2759 spin_unlock(&atmel_aes.lock);
2760 atmel_aes_dma_cleanup(aes_dd);
2761 err_aes_dma:
2762 atmel_aes_buff_cleanup(aes_dd);
2763 err_aes_buff:
2764 iclk_unprepare:
2765 clk_unprepare(aes_dd->iclk);
2766 res_err:
2767 tasklet_kill(&aes_dd->done_task);
2768 tasklet_kill(&aes_dd->queue_task);
2769 aes_dd_err:
2770 if (err != -EPROBE_DEFER)
2771 dev_err(dev, "initialization failed.\n");
2772
2773 return err;
2774 }
2775
2776 static int atmel_aes_remove(struct platform_device *pdev)
2777 {
2778 struct atmel_aes_dev *aes_dd;
2779
2780 aes_dd = platform_get_drvdata(pdev);
2781 if (!aes_dd)
2782 return -ENODEV;
2783 spin_lock(&atmel_aes.lock);
2784 list_del(&aes_dd->list);
2785 spin_unlock(&atmel_aes.lock);
2786
2787 atmel_aes_unregister_algs(aes_dd);
2788
2789 tasklet_kill(&aes_dd->done_task);
2790 tasklet_kill(&aes_dd->queue_task);
2791
2792 atmel_aes_dma_cleanup(aes_dd);
2793 atmel_aes_buff_cleanup(aes_dd);
2794
2795 clk_unprepare(aes_dd->iclk);
2796
2797 return 0;
2798 }
2799
2800 static struct platform_driver atmel_aes_driver = {
2801 .probe = atmel_aes_probe,
2802 .remove = atmel_aes_remove,
2803 .driver = {
2804 .name = "atmel_aes",
2805 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
2806 },
2807 };
2808
2809 module_platform_driver(atmel_aes_driver);
2810
2811 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
2812 MODULE_LICENSE("GPL v2");
2813 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
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