drivers/crypto/caam/caamalg_qi2.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright 2015-2016 Freescale Semiconductor Inc.
   4  * Copyright 2017-2018 NXP
   5  */
   6
   7 #ifndef _CAAMALG_QI2_H_
   8 #define _CAAMALG_QI2_H_
   9
  10 #include <soc/fsl/dpaa2-io.h>
  11 #include <soc/fsl/dpaa2-fd.h>
  12 #include <linux/threads.h>
  13 #include <linux/netdevice.h>
  14 #include "dpseci.h"
  15 #include "desc_constr.h"
  16 #include <crypto/skcipher.h>
  17
  18 #define DPAA2_CAAM_STORE_SIZE   16
  19 /* NAPI weight *must* be a multiple of the store size. */
  20 #define DPAA2_CAAM_NAPI_WEIGHT  512
  21
  22 /* The congestion entrance threshold was chosen so that on LS2088
  23  * we support the maximum throughput for the available memory
  24  */
  25 #define DPAA2_SEC_CONG_ENTRY_THRESH     (128 * 1024 * 1024)
  26 #define DPAA2_SEC_CONG_EXIT_THRESH      (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
  27
  28 /**
  29  * dpaa2_caam_priv - driver private data
  30  * @dpseci_id: DPSECI object unique ID
  31  * @major_ver: DPSECI major version
  32  * @minor_ver: DPSECI minor version
  33  * @dpseci_attr: DPSECI attributes
  34  * @sec_attr: SEC engine attributes
  35  * @rx_queue_attr: array of Rx queue attributes
  36  * @tx_queue_attr: array of Tx queue attributes
  37  * @cscn_mem: pointer to memory region containing the congestion SCN
  38  *      it's size is larger than to accommodate alignment
  39  * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
  40  *      PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
  41  * @cscn_dma: dma address used by the QMAN to write CSCN messages
  42  * @dev: device associated with the DPSECI object
  43  * @mc_io: pointer to MC portal's I/O object
  44  * @domain: IOMMU domain
  45  * @ppriv: per CPU pointers to privata data
  46  */
  47 struct dpaa2_caam_priv {
  48         int dpsec_id;
  49
  50         u16 major_ver;
  51         u16 minor_ver;
  52
  53         struct dpseci_attr dpseci_attr;
  54         struct dpseci_sec_attr sec_attr;
  55         struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
  56         struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
  57         int num_pairs;
  58
  59         /* congestion */
  60         void *cscn_mem;
  61         void *cscn_mem_aligned;
  62         dma_addr_t cscn_dma;
  63
  64         struct device *dev;
  65         struct fsl_mc_io *mc_io;
  66         struct iommu_domain *domain;
  67
  68         struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
  69         struct dentry *dfs_root;
  70 };
  71
  72 /**
  73  * dpaa2_caam_priv_per_cpu - per CPU private data
  74  * @napi: napi structure
  75  * @net_dev: netdev used by napi
  76  * @req_fqid: (virtual) request (Tx / enqueue) FQID
  77  * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
  78  * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
  79  * @nctx: notification context of response FQ
  80  * @store: where dequeued frames are stored
  81  * @priv: backpointer to dpaa2_caam_priv
  82  * @dpio: portal used for data path operations
  83  */
  84 struct dpaa2_caam_priv_per_cpu {
  85         struct napi_struct napi;
  86         struct net_device net_dev;
  87         int req_fqid;
  88         int rsp_fqid;
  89         int prio;
  90         struct dpaa2_io_notification_ctx nctx;
  91         struct dpaa2_io_store *store;
  92         struct dpaa2_caam_priv *priv;
  93         struct dpaa2_io *dpio;
  94 };
  95
  96 /* Length of a single buffer in the QI driver memory cache */
  97 #define CAAM_QI_MEMCACHE_SIZE   512
  98
  99 /*
 100  * aead_edesc - s/w-extended aead descriptor
 101  * @src_nents: number of segments in input scatterlist
 102  * @dst_nents: number of segments in output scatterlist
 103  * @iv_dma: dma address of iv for checking continuity and link table
 104  * @qm_sg_bytes: length of dma mapped h/w link table
 105  * @qm_sg_dma: bus physical mapped address of h/w link table
 106  * @assoclen: associated data length, in CAAM endianness
 107  * @assoclen_dma: bus physical mapped address of req->assoclen
 108  * @sgt: the h/w link table, followed by IV
 109  */
 110 struct aead_edesc {
 111         int src_nents;
 112         int dst_nents;
 113         dma_addr_t iv_dma;
 114         int qm_sg_bytes;
 115         dma_addr_t qm_sg_dma;
 116         unsigned int assoclen;
 117         dma_addr_t assoclen_dma;
 118         struct dpaa2_sg_entry sgt[];
 119 };
 120
 121 /*
 122  * skcipher_edesc - s/w-extended skcipher descriptor
 123  * @src_nents: number of segments in input scatterlist
 124  * @dst_nents: number of segments in output scatterlist
 125  * @iv_dma: dma address of iv for checking continuity and link table
 126  * @qm_sg_bytes: length of dma mapped qm_sg space
 127  * @qm_sg_dma: I/O virtual address of h/w link table
 128  * @sgt: the h/w link table, followed by IV
 129  */
 130 struct skcipher_edesc {
 131         int src_nents;
 132         int dst_nents;
 133         dma_addr_t iv_dma;
 134         int qm_sg_bytes;
 135         dma_addr_t qm_sg_dma;
 136         struct dpaa2_sg_entry sgt[];
 137 };
 138
 139 /*
 140  * ahash_edesc - s/w-extended ahash descriptor
 141  * @qm_sg_dma: I/O virtual address of h/w link table
 142  * @src_nents: number of segments in input scatterlist
 143  * @qm_sg_bytes: length of dma mapped qm_sg space
 144  * @sgt: pointer to h/w link table
 145  */
 146 struct ahash_edesc {
 147         dma_addr_t qm_sg_dma;
 148         int src_nents;
 149         int qm_sg_bytes;
 150         struct dpaa2_sg_entry sgt[];
 151 };
 152
 153 /**
 154  * caam_flc - Flow Context (FLC)
 155  * @flc: Flow Context options
 156  * @sh_desc: Shared Descriptor
 157  */
 158 struct caam_flc {
 159         u32 flc[16];
 160         u32 sh_desc[MAX_SDLEN];
 161 } ____cacheline_aligned;
 162
 163 enum optype {
 164         ENCRYPT = 0,
 165         DECRYPT,
 166         NUM_OP
 167 };
 168
 169 /**
 170  * caam_request - the request structure the driver application should fill while
 171  *                submitting a job to driver.
 172  * @fd_flt: Frame list table defining input and output
 173  *          fd_flt[0] - FLE pointing to output buffer
 174  *          fd_flt[1] - FLE pointing to input buffer
 175  * @fd_flt_dma: DMA address for the frame list table
 176  * @flc: Flow Context
 177  * @flc_dma: I/O virtual address of Flow Context
 178  * @cbk: Callback function to invoke when job is completed
 179  * @ctx: arbit context attached with request by the application
 180  * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
 181  */
 182 struct caam_request {
 183         struct dpaa2_fl_entry fd_flt[2];
 184         dma_addr_t fd_flt_dma;
 185         struct caam_flc *flc;
 186         dma_addr_t flc_dma;
 187         void (*cbk)(void *ctx, u32 err);
 188         void *ctx;
 189         void *edesc;
 190         struct skcipher_request fallback_req;
 191 };
 192
 193 /**
 194  * dpaa2_caam_enqueue() - enqueue a crypto request
 195  * @dev: device associated with the DPSECI object
 196  * @req: pointer to caam_request
 197  */
 198 int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
 199
 200 #endif  /* _CAAMALG_QI2_H_ */