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1 /*
2 * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
4 *
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 */
7
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
10
11 #include "compat.h"
12 #include "regs.h"
13 #include "intern.h"
14 #include "jr.h"
15 #include "desc_constr.h"
16 #include "error.h"
17 #include "ctrl.h"
18
19 /*
20 * Descriptor to instantiate RNG State Handle 0 in normal mode and
21 * load the JDKEK, TDKEK and TDSK registers
22 */
23 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
24 {
25 u32 *jump_cmd, op_flags;
26
27 init_job_desc(desc, 0);
28
29 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
30 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
31
32 /* INIT RNG in non-test mode */
33 append_operation(desc, op_flags);
34
35 if (!handle && do_sk) {
36 /*
37 * For SH0, Secure Keys must be generated as well
38 */
39
40 /* wait for done */
41 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
42 set_jump_tgt_here(desc, jump_cmd);
43
44 /*
45 * load 1 to clear written reg:
46 * resets the done interrrupt and returns the RNG to idle.
47 */
48 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
49
50 /* Initialize State Handle */
51 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
52 OP_ALG_AAI_RNG4_SK);
53 }
54
55 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
56 }
57
58 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
59 static void build_deinstantiation_desc(u32 *desc, int handle)
60 {
61 init_job_desc(desc, 0);
62
63 /* Uninstantiate State Handle 0 */
64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
65 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
66
67 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
68 }
69
70 /*
71 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
72 * the software (no JR/QI used).
73 * @ctrldev - pointer to device
74 * @status - descriptor status, after being run
75 *
76 * Return: - 0 if no error occurred
77 * - -ENODEV if the DECO couldn't be acquired
78 * - -EAGAIN if an error occurred while executing the descriptor
79 */
80 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
81 u32 *status)
82 {
83 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
84 struct caam_full __iomem *topregs;
85 unsigned int timeout = 100000;
86 u32 deco_dbg_reg, flags;
87 int i;
88
89 /* Set the bit to request direct access to DECO0 */
90 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
91 setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
92
93 while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) &&
94 --timeout)
95 cpu_relax();
96
97 if (!timeout) {
98 dev_err(ctrldev, "failed to acquire DECO 0\n");
99 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
100 return -ENODEV;
101 }
102
103 for (i = 0; i < desc_len(desc); i++)
104 wr_reg32(&topregs->deco.descbuf[i], *(desc + i));
105
106 flags = DECO_JQCR_WHL;
107 /*
108 * If the descriptor length is longer than 4 words, then the
109 * FOUR bit in JRCTRL register must be set.
110 */
111 if (desc_len(desc) >= 4)
112 flags |= DECO_JQCR_FOUR;
113
114 /* Instruct the DECO to execute it */
115 wr_reg32(&topregs->deco.jr_ctl_hi, flags);
116
117 timeout = 10000000;
118 do {
119 deco_dbg_reg = rd_reg32(&topregs->deco.desc_dbg);
120 /*
121 * If an error occured in the descriptor, then
122 * the DECO status field will be set to 0x0D
123 */
124 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
125 DESC_DBG_DECO_STAT_HOST_ERR)
126 break;
127 cpu_relax();
128 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
129
130 *status = rd_reg32(&topregs->deco.op_status_hi) &
131 DECO_OP_STATUS_HI_ERR_MASK;
132
133 /* Mark the DECO as free */
134 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
135
136 if (!timeout)
137 return -EAGAIN;
138
139 return 0;
140 }
141
142 /*
143 * instantiate_rng - builds and executes a descriptor on DECO0,
144 * which initializes the RNG block.
145 * @ctrldev - pointer to device
146 * @state_handle_mask - bitmask containing the instantiation status
147 * for the RNG4 state handles which exist in
148 * the RNG4 block: 1 if it's been instantiated
149 * by an external entry, 0 otherwise.
150 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
151 * Caution: this can be done only once; if the keys need to be
152 * regenerated, a POR is required
153 *
154 * Return: - 0 if no error occurred
155 * - -ENOMEM if there isn't enough memory to allocate the descriptor
156 * - -ENODEV if DECO0 couldn't be acquired
157 * - -EAGAIN if an error occurred when executing the descriptor
158 * f.i. there was a RNG hardware error due to not "good enough"
159 * entropy being aquired.
160 */
161 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
162 int gen_sk)
163 {
164 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
165 struct caam_full __iomem *topregs;
166 struct rng4tst __iomem *r4tst;
167 u32 *desc, status, rdsta_val;
168 int ret = 0, sh_idx;
169
170 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
171 r4tst = &topregs->ctrl.r4tst[0];
172
173 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
174 if (!desc)
175 return -ENOMEM;
176
177 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
178 /*
179 * If the corresponding bit is set, this state handle
180 * was initialized by somebody else, so it's left alone.
181 */
182 if ((1 << sh_idx) & state_handle_mask)
183 continue;
184
185 /* Create the descriptor for instantiating RNG State Handle */
186 build_instantiation_desc(desc, sh_idx, gen_sk);
187
188 /* Try to run it through DECO0 */
189 ret = run_descriptor_deco0(ctrldev, desc, &status);
190
191 /*
192 * If ret is not 0, or descriptor status is not 0, then
193 * something went wrong. No need to try the next state
194 * handle (if available), bail out here.
195 * Also, if for some reason, the State Handle didn't get
196 * instantiated although the descriptor has finished
197 * without any error (HW optimizations for later
198 * CAAM eras), then try again.
199 */
200 rdsta_val =
201 rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IFMASK;
202 if (status || !(rdsta_val & (1 << sh_idx)))
203 ret = -EAGAIN;
204 if (ret)
205 break;
206
207 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
208 /* Clear the contents before recreating the descriptor */
209 memset(desc, 0x00, CAAM_CMD_SZ * 7);
210 }
211
212 kfree(desc);
213
214 return ret;
215 }
216
217 /*
218 * deinstantiate_rng - builds and executes a descriptor on DECO0,
219 * which deinitializes the RNG block.
220 * @ctrldev - pointer to device
221 * @state_handle_mask - bitmask containing the instantiation status
222 * for the RNG4 state handles which exist in
223 * the RNG4 block: 1 if it's been instantiated
224 *
225 * Return: - 0 if no error occurred
226 * - -ENOMEM if there isn't enough memory to allocate the descriptor
227 * - -ENODEV if DECO0 couldn't be acquired
228 * - -EAGAIN if an error occurred when executing the descriptor
229 */
230 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
231 {
232 u32 *desc, status;
233 int sh_idx, ret = 0;
234
235 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
236 if (!desc)
237 return -ENOMEM;
238
239 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
240 /*
241 * If the corresponding bit is set, then it means the state
242 * handle was initialized by us, and thus it needs to be
243 * deintialized as well
244 */
245 if ((1 << sh_idx) & state_handle_mask) {
246 /*
247 * Create the descriptor for deinstantating this state
248 * handle
249 */
250 build_deinstantiation_desc(desc, sh_idx);
251
252 /* Try to run it through DECO0 */
253 ret = run_descriptor_deco0(ctrldev, desc, &status);
254
255 if (ret || status) {
256 dev_err(ctrldev,
257 "Failed to deinstantiate RNG4 SH%d\n",
258 sh_idx);
259 break;
260 }
261 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
262 }
263 }
264
265 kfree(desc);
266
267 return ret;
268 }
269
270 static int caam_remove(struct platform_device *pdev)
271 {
272 struct device *ctrldev;
273 struct caam_drv_private *ctrlpriv;
274 struct caam_full __iomem *topregs;
275 int ring, ret = 0;
276
277 ctrldev = &pdev->dev;
278 ctrlpriv = dev_get_drvdata(ctrldev);
279 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
280
281 /* Remove platform devices for JobRs */
282 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
283 if (ctrlpriv->jrpdev[ring])
284 of_device_unregister(ctrlpriv->jrpdev[ring]);
285 }
286
287 /* De-initialize RNG state handles initialized by this driver. */
288 if (ctrlpriv->rng4_sh_init)
289 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
290
291 /* Shut down debug views */
292 #ifdef CONFIG_DEBUG_FS
293 debugfs_remove_recursive(ctrlpriv->dfs_root);
294 #endif
295
296 /* Unmap controller region */
297 iounmap(&topregs->ctrl);
298
299 kfree(ctrlpriv->jrpdev);
300 kfree(ctrlpriv);
301
302 return ret;
303 }
304
305 /*
306 * kick_trng - sets the various parameters for enabling the initialization
307 * of the RNG4 block in CAAM
308 * @pdev - pointer to the platform device
309 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
310 */
311 static void kick_trng(struct platform_device *pdev, int ent_delay)
312 {
313 struct device *ctrldev = &pdev->dev;
314 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
315 struct caam_full __iomem *topregs;
316 struct rng4tst __iomem *r4tst;
317 u32 val;
318
319 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
320 r4tst = &topregs->ctrl.r4tst[0];
321
322 /* put RNG4 into program mode */
323 setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
324
325 /*
326 * Performance-wise, it does not make sense to
327 * set the delay to a value that is lower
328 * than the last one that worked (i.e. the state handles
329 * were instantiated properly. Thus, instead of wasting
330 * time trying to set the values controlling the sample
331 * frequency, the function simply returns.
332 */
333 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
334 >> RTSDCTL_ENT_DLY_SHIFT;
335 if (ent_delay <= val) {
336 /* put RNG4 into run mode */
337 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
338 return;
339 }
340
341 val = rd_reg32(&r4tst->rtsdctl);
342 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
343 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
344 wr_reg32(&r4tst->rtsdctl, val);
345 /* min. freq. count, equal to 1/4 of the entropy sample length */
346 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
347 /* max. freq. count, equal to 8 times the entropy sample length */
348 wr_reg32(&r4tst->rtfrqmax, ent_delay << 3);
349 /* put RNG4 into run mode */
350 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
351 }
352
353 /**
354 * caam_get_era() - Return the ERA of the SEC on SoC, based
355 * on the SEC_VID register.
356 * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown.
357 * @caam_id - the value of the SEC_VID register
358 **/
359 int caam_get_era(u64 caam_id)
360 {
361 struct sec_vid *sec_vid = (struct sec_vid *)&caam_id;
362 static const struct {
363 u16 ip_id;
364 u8 maj_rev;
365 u8 era;
366 } caam_eras[] = {
367 {0x0A10, 1, 1},
368 {0x0A10, 2, 2},
369 {0x0A12, 1, 3},
370 {0x0A14, 1, 3},
371 {0x0A14, 2, 4},
372 {0x0A16, 1, 4},
373 {0x0A11, 1, 4}
374 };
375 int i;
376
377 for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
378 if (caam_eras[i].ip_id == sec_vid->ip_id &&
379 caam_eras[i].maj_rev == sec_vid->maj_rev)
380 return caam_eras[i].era;
381
382 return -ENOTSUPP;
383 }
384 EXPORT_SYMBOL(caam_get_era);
385
386 /* Probe routine for CAAM top (controller) level */
387 static int caam_probe(struct platform_device *pdev)
388 {
389 int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
390 u64 caam_id;
391 struct device *dev;
392 struct device_node *nprop, *np;
393 struct caam_ctrl __iomem *ctrl;
394 struct caam_full __iomem *topregs;
395 struct caam_drv_private *ctrlpriv;
396 #ifdef CONFIG_DEBUG_FS
397 struct caam_perfmon *perfmon;
398 #endif
399 u64 cha_vid;
400
401 ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
402 if (!ctrlpriv)
403 return -ENOMEM;
404
405 dev = &pdev->dev;
406 dev_set_drvdata(dev, ctrlpriv);
407 ctrlpriv->pdev = pdev;
408 nprop = pdev->dev.of_node;
409
410 /* Get configuration properties from device tree */
411 /* First, get register page */
412 ctrl = of_iomap(nprop, 0);
413 if (ctrl == NULL) {
414 dev_err(dev, "caam: of_iomap() failed\n");
415 return -ENOMEM;
416 }
417 ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
418
419 /* topregs used to derive pointers to CAAM sub-blocks only */
420 topregs = (struct caam_full __iomem *)ctrl;
421
422 /* Get the IRQ of the controller (for security violations only) */
423 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
424
425 /*
426 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
427 * long pointers in master configuration register
428 */
429 setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
430 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
431
432 if (sizeof(dma_addr_t) == sizeof(u64))
433 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
434 dma_set_mask(dev, DMA_BIT_MASK(40));
435 else
436 dma_set_mask(dev, DMA_BIT_MASK(36));
437 else
438 dma_set_mask(dev, DMA_BIT_MASK(32));
439
440 /*
441 * Detect and enable JobRs
442 * First, find out how many ring spec'ed, allocate references
443 * for all, then go probe each one.
444 */
445 rspec = 0;
446 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
447 rspec++;
448 if (!rspec) {
449 /* for backward compatible with device trees */
450 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
451 rspec++;
452 }
453
454 ctrlpriv->jrpdev = kzalloc(sizeof(struct platform_device *) * rspec,
455 GFP_KERNEL);
456 if (ctrlpriv->jrpdev == NULL) {
457 iounmap(&topregs->ctrl);
458 return -ENOMEM;
459 }
460
461 ring = 0;
462 ctrlpriv->total_jobrs = 0;
463 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
464 ctrlpriv->jrpdev[ring] =
465 of_platform_device_create(np, NULL, dev);
466 if (!ctrlpriv->jrpdev[ring]) {
467 pr_warn("JR%d Platform device creation error\n", ring);
468 continue;
469 }
470 ctrlpriv->total_jobrs++;
471 ring++;
472 }
473 if (!ring) {
474 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
475 ctrlpriv->jrpdev[ring] =
476 of_platform_device_create(np, NULL, dev);
477 if (!ctrlpriv->jrpdev[ring]) {
478 pr_warn("JR%d Platform device creation error\n",
479 ring);
480 continue;
481 }
482 ctrlpriv->total_jobrs++;
483 ring++;
484 }
485 }
486
487 /* Check to see if QI present. If so, enable */
488 ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
489 CTPR_QI_MASK);
490 if (ctrlpriv->qi_present) {
491 ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
492 /* This is all that's required to physically enable QI */
493 wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
494 }
495
496 /* If no QI and no rings specified, quit and go home */
497 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
498 dev_err(dev, "no queues configured, terminating\n");
499 caam_remove(pdev);
500 return -ENOMEM;
501 }
502
503 cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id);
504
505 /*
506 * If SEC has RNG version >= 4 and RNG state handle has not been
507 * already instantiated, do RNG instantiation
508 */
509 if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
510 ctrlpriv->rng4_sh_init =
511 rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
512 /*
513 * If the secure keys (TDKEK, JDKEK, TDSK), were already
514 * generated, signal this to the function that is instantiating
515 * the state handles. An error would occur if RNG4 attempts
516 * to regenerate these keys before the next POR.
517 */
518 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
519 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
520 do {
521 int inst_handles =
522 rd_reg32(&topregs->ctrl.r4tst[0].rdsta) &
523 RDSTA_IFMASK;
524 /*
525 * If either SH were instantiated by somebody else
526 * (e.g. u-boot) then it is assumed that the entropy
527 * parameters are properly set and thus the function
528 * setting these (kick_trng(...)) is skipped.
529 * Also, if a handle was instantiated, do not change
530 * the TRNG parameters.
531 */
532 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
533 kick_trng(pdev, ent_delay);
534 ent_delay += 400;
535 }
536 /*
537 * if instantiate_rng(...) fails, the loop will rerun
538 * and the kick_trng(...) function will modfiy the
539 * upper and lower limits of the entropy sampling
540 * interval, leading to a sucessful initialization of
541 * the RNG.
542 */
543 ret = instantiate_rng(dev, inst_handles,
544 gen_sk);
545 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
546 if (ret) {
547 dev_err(dev, "failed to instantiate RNG");
548 caam_remove(pdev);
549 return ret;
550 }
551 /*
552 * Set handles init'ed by this module as the complement of the
553 * already initialized ones
554 */
555 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
556
557 /* Enable RDB bit so that RNG works faster */
558 setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
559 }
560
561 /* NOTE: RTIC detection ought to go here, around Si time */
562
563 caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
564
565 /* Report "alive" for developer to see */
566 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
567 caam_get_era(caam_id));
568 dev_info(dev, "job rings = %d, qi = %d\n",
569 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
570
571 #ifdef CONFIG_DEBUG_FS
572 /*
573 * FIXME: needs better naming distinction, as some amalgamation of
574 * "caam" and nprop->full_name. The OF name isn't distinctive,
575 * but does separate instances
576 */
577 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
578
579 ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL);
580 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
581
582 /* Controller-level - performance monitor counters */
583 ctrlpriv->ctl_rq_dequeued =
584 debugfs_create_u64("rq_dequeued",
585 S_IRUSR | S_IRGRP | S_IROTH,
586 ctrlpriv->ctl, &perfmon->req_dequeued);
587 ctrlpriv->ctl_ob_enc_req =
588 debugfs_create_u64("ob_rq_encrypted",
589 S_IRUSR | S_IRGRP | S_IROTH,
590 ctrlpriv->ctl, &perfmon->ob_enc_req);
591 ctrlpriv->ctl_ib_dec_req =
592 debugfs_create_u64("ib_rq_decrypted",
593 S_IRUSR | S_IRGRP | S_IROTH,
594 ctrlpriv->ctl, &perfmon->ib_dec_req);
595 ctrlpriv->ctl_ob_enc_bytes =
596 debugfs_create_u64("ob_bytes_encrypted",
597 S_IRUSR | S_IRGRP | S_IROTH,
598 ctrlpriv->ctl, &perfmon->ob_enc_bytes);
599 ctrlpriv->ctl_ob_prot_bytes =
600 debugfs_create_u64("ob_bytes_protected",
601 S_IRUSR | S_IRGRP | S_IROTH,
602 ctrlpriv->ctl, &perfmon->ob_prot_bytes);
603 ctrlpriv->ctl_ib_dec_bytes =
604 debugfs_create_u64("ib_bytes_decrypted",
605 S_IRUSR | S_IRGRP | S_IROTH,
606 ctrlpriv->ctl, &perfmon->ib_dec_bytes);
607 ctrlpriv->ctl_ib_valid_bytes =
608 debugfs_create_u64("ib_bytes_validated",
609 S_IRUSR | S_IRGRP | S_IROTH,
610 ctrlpriv->ctl, &perfmon->ib_valid_bytes);
611
612 /* Controller level - global status values */
613 ctrlpriv->ctl_faultaddr =
614 debugfs_create_u64("fault_addr",
615 S_IRUSR | S_IRGRP | S_IROTH,
616 ctrlpriv->ctl, &perfmon->faultaddr);
617 ctrlpriv->ctl_faultdetail =
618 debugfs_create_u32("fault_detail",
619 S_IRUSR | S_IRGRP | S_IROTH,
620 ctrlpriv->ctl, &perfmon->faultdetail);
621 ctrlpriv->ctl_faultstatus =
622 debugfs_create_u32("fault_status",
623 S_IRUSR | S_IRGRP | S_IROTH,
624 ctrlpriv->ctl, &perfmon->status);
625
626 /* Internal covering keys (useful in non-secure mode only) */
627 ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
628 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
629 ctrlpriv->ctl_kek = debugfs_create_blob("kek",
630 S_IRUSR |
631 S_IRGRP | S_IROTH,
632 ctrlpriv->ctl,
633 &ctrlpriv->ctl_kek_wrap);
634
635 ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
636 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
637 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
638 S_IRUSR |
639 S_IRGRP | S_IROTH,
640 ctrlpriv->ctl,
641 &ctrlpriv->ctl_tkek_wrap);
642
643 ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
644 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
645 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
646 S_IRUSR |
647 S_IRGRP | S_IROTH,
648 ctrlpriv->ctl,
649 &ctrlpriv->ctl_tdsk_wrap);
650 #endif
651 return 0;
652 }
653
654 static struct of_device_id caam_match[] = {
655 {
656 .compatible = "fsl,sec-v4.0",
657 },
658 {
659 .compatible = "fsl,sec4.0",
660 },
661 {},
662 };
663 MODULE_DEVICE_TABLE(of, caam_match);
664
665 static struct platform_driver caam_driver = {
666 .driver = {
667 .name = "caam",
668 .owner = THIS_MODULE,
669 .of_match_table = caam_match,
670 },
671 .probe = caam_probe,
672 .remove = caam_remove,
673 };
674
675 module_platform_driver(caam_driver);
676
677 MODULE_LICENSE("GPL");
678 MODULE_DESCRIPTION("FSL CAAM request backend");
679 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");