drivers/crypto/caam/ctrl.c

   1 /* * CAAM control-plane driver backend
   2  * Controller-level driver, kernel property detection, initialization
   3  *
   4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_irq.h>
  10
  11 #include "compat.h"
  12 #include "regs.h"
  13 #include "intern.h"
  14 #include "jr.h"
  15 #include "desc_constr.h"
  16 #include "error.h"
  17 #include "ctrl.h"
  18
  19 bool caam_little_end;
  20 EXPORT_SYMBOL(caam_little_end);
  21
  22 /*
  23  * i.MX targets tend to have clock control subsystems that can
  24  * enable/disable clocking to our device.
  25  */
  26 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
  27 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  28                                                 char *clk_name)
  29 {
  30         return devm_clk_get(dev, clk_name);
  31 }
  32 #else
  33 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  34                                                 char *clk_name)
  35 {
  36         return NULL;
  37 }
  38 #endif
  39
  40 /*
  41  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  42  * load the JDKEK, TDKEK and TDSK registers
  43  */
  44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  45 {
  46         u32 *jump_cmd, op_flags;
  47
  48         init_job_desc(desc, 0);
  49
  50         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  51                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  52
  53         /* INIT RNG in non-test mode */
  54         append_operation(desc, op_flags);
  55
  56         if (!handle && do_sk) {
  57                 /*
  58                  * For SH0, Secure Keys must be generated as well
  59                  */
  60
  61                 /* wait for done */
  62                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  63                 set_jump_tgt_here(desc, jump_cmd);
  64
  65                 /*
  66                  * load 1 to clear written reg:
  67                  * resets the done interrrupt and returns the RNG to idle.
  68                  */
  69                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  70
  71                 /* Initialize State Handle  */
  72                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  73                                  OP_ALG_AAI_RNG4_SK);
  74         }
  75
  76         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  77 }
  78
  79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  80 static void build_deinstantiation_desc(u32 *desc, int handle)
  81 {
  82         init_job_desc(desc, 0);
  83
  84         /* Uninstantiate State Handle 0 */
  85         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  86                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  87
  88         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  89 }
  90
  91 /*
  92  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  93  *                        the software (no JR/QI used).
  94  * @ctrldev - pointer to device
  95  * @status - descriptor status, after being run
  96  *
  97  * Return: - 0 if no error occurred
  98  *         - -ENODEV if the DECO couldn't be acquired
  99  *         - -EAGAIN if an error occurred while executing the descriptor
 100  */
 101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 102                                         u32 *status)
 103 {
 104         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 105         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 106         struct caam_deco __iomem *deco = ctrlpriv->deco;
 107         unsigned int timeout = 100000;
 108         u32 deco_dbg_reg, flags;
 109         int i;
 110
 111
 112         if (ctrlpriv->virt_en == 1) {
 113                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 114
 115                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 116                        --timeout)
 117                         cpu_relax();
 118
 119                 timeout = 100000;
 120         }
 121
 122         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 123
 124         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 125                                                                  --timeout)
 126                 cpu_relax();
 127
 128         if (!timeout) {
 129                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 130                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 131                 return -ENODEV;
 132         }
 133
 134         for (i = 0; i < desc_len(desc); i++)
 135                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 136
 137         flags = DECO_JQCR_WHL;
 138         /*
 139          * If the descriptor length is longer than 4 words, then the
 140          * FOUR bit in JRCTRL register must be set.
 141          */
 142         if (desc_len(desc) >= 4)
 143                 flags |= DECO_JQCR_FOUR;
 144
 145         /* Instruct the DECO to execute it */
 146         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 147
 148         timeout = 10000000;
 149         do {
 150                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 151                 /*
 152                  * If an error occured in the descriptor, then
 153                  * the DECO status field will be set to 0x0D
 154                  */
 155                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
 156                     DESC_DBG_DECO_STAT_HOST_ERR)
 157                         break;
 158                 cpu_relax();
 159         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 160
 161         *status = rd_reg32(&deco->op_status_hi) &
 162                   DECO_OP_STATUS_HI_ERR_MASK;
 163
 164         if (ctrlpriv->virt_en == 1)
 165                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 166
 167         /* Mark the DECO as free */
 168         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 169
 170         if (!timeout)
 171                 return -EAGAIN;
 172
 173         return 0;
 174 }
 175
 176 /*
 177  * instantiate_rng - builds and executes a descriptor on DECO0,
 178  *                   which initializes the RNG block.
 179  * @ctrldev - pointer to device
 180  * @state_handle_mask - bitmask containing the instantiation status
 181  *                      for the RNG4 state handles which exist in
 182  *                      the RNG4 block: 1 if it's been instantiated
 183  *                      by an external entry, 0 otherwise.
 184  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 185  *            Caution: this can be done only once; if the keys need to be
 186  *            regenerated, a POR is required
 187  *
 188  * Return: - 0 if no error occurred
 189  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 190  *         - -ENODEV if DECO0 couldn't be acquired
 191  *         - -EAGAIN if an error occurred when executing the descriptor
 192  *            f.i. there was a RNG hardware error due to not "good enough"
 193  *            entropy being aquired.
 194  */
 195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 196                            int gen_sk)
 197 {
 198         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 199         struct caam_ctrl __iomem *ctrl;
 200         u32 *desc, status = 0, rdsta_val;
 201         int ret = 0, sh_idx;
 202
 203         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 204         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 205         if (!desc)
 206                 return -ENOMEM;
 207
 208         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 209                 /*
 210                  * If the corresponding bit is set, this state handle
 211                  * was initialized by somebody else, so it's left alone.
 212                  */
 213                 if ((1 << sh_idx) & state_handle_mask)
 214                         continue;
 215
 216                 /* Create the descriptor for instantiating RNG State Handle */
 217                 build_instantiation_desc(desc, sh_idx, gen_sk);
 218
 219                 /* Try to run it through DECO0 */
 220                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 221
 222                 /*
 223                  * If ret is not 0, or descriptor status is not 0, then
 224                  * something went wrong. No need to try the next state
 225                  * handle (if available), bail out here.
 226                  * Also, if for some reason, the State Handle didn't get
 227                  * instantiated although the descriptor has finished
 228                  * without any error (HW optimizations for later
 229                  * CAAM eras), then try again.
 230                  */
 231                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 232                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 233                     !(rdsta_val & (1 << sh_idx)))
 234                         ret = -EAGAIN;
 235                 if (ret)
 236                         break;
 237                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 238                 /* Clear the contents before recreating the descriptor */
 239                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 240         }
 241
 242         kfree(desc);
 243
 244         return ret;
 245 }
 246
 247 /*
 248  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 249  *                     which deinitializes the RNG block.
 250  * @ctrldev - pointer to device
 251  * @state_handle_mask - bitmask containing the instantiation status
 252  *                      for the RNG4 state handles which exist in
 253  *                      the RNG4 block: 1 if it's been instantiated
 254  *
 255  * Return: - 0 if no error occurred
 256  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 257  *         - -ENODEV if DECO0 couldn't be acquired
 258  *         - -EAGAIN if an error occurred when executing the descriptor
 259  */
 260 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 261 {
 262         u32 *desc, status;
 263         int sh_idx, ret = 0;
 264
 265         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 266         if (!desc)
 267                 return -ENOMEM;
 268
 269         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 270                 /*
 271                  * If the corresponding bit is set, then it means the state
 272                  * handle was initialized by us, and thus it needs to be
 273                  * deintialized as well
 274                  */
 275                 if ((1 << sh_idx) & state_handle_mask) {
 276                         /*
 277                          * Create the descriptor for deinstantating this state
 278                          * handle
 279                          */
 280                         build_deinstantiation_desc(desc, sh_idx);
 281
 282                         /* Try to run it through DECO0 */
 283                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 284
 285                         if (ret || status) {
 286                                 dev_err(ctrldev,
 287                                         "Failed to deinstantiate RNG4 SH%d\n",
 288                                         sh_idx);
 289                                 break;
 290                         }
 291                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 292                 }
 293         }
 294
 295         kfree(desc);
 296
 297         return ret;
 298 }
 299
 300 static int caam_remove(struct platform_device *pdev)
 301 {
 302         struct device *ctrldev;
 303         struct caam_drv_private *ctrlpriv;
 304         struct caam_ctrl __iomem *ctrl;
 305         int ring;
 306
 307         ctrldev = &pdev->dev;
 308         ctrlpriv = dev_get_drvdata(ctrldev);
 309         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 310
 311         /* Remove platform devices for JobRs */
 312         for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
 313                 if (ctrlpriv->jrpdev[ring])
 314                         of_device_unregister(ctrlpriv->jrpdev[ring]);
 315         }
 316
 317         /* De-initialize RNG state handles initialized by this driver. */
 318         if (ctrlpriv->rng4_sh_init)
 319                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 320
 321         /* Shut down debug views */
 322 #ifdef CONFIG_DEBUG_FS
 323         debugfs_remove_recursive(ctrlpriv->dfs_root);
 324 #endif
 325
 326         /* Unmap controller region */
 327         iounmap(ctrl);
 328
 329         /* shut clocks off before finalizing shutdown */
 330         clk_disable_unprepare(ctrlpriv->caam_ipg);
 331         clk_disable_unprepare(ctrlpriv->caam_mem);
 332         clk_disable_unprepare(ctrlpriv->caam_aclk);
 333         clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * kick_trng - sets the various parameters for enabling the initialization
 340  *             of the RNG4 block in CAAM
 341  * @pdev - pointer to the platform device
 342  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 343  */
 344 static void kick_trng(struct platform_device *pdev, int ent_delay)
 345 {
 346         struct device *ctrldev = &pdev->dev;
 347         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 348         struct caam_ctrl __iomem *ctrl;
 349         struct rng4tst __iomem *r4tst;
 350         u32 val;
 351
 352         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 353         r4tst = &ctrl->r4tst[0];
 354
 355         /* put RNG4 into program mode */
 356         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 357
 358         /*
 359          * Performance-wise, it does not make sense to
 360          * set the delay to a value that is lower
 361          * than the last one that worked (i.e. the state handles
 362          * were instantiated properly. Thus, instead of wasting
 363          * time trying to set the values controlling the sample
 364          * frequency, the function simply returns.
 365          */
 366         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 367               >> RTSDCTL_ENT_DLY_SHIFT;
 368         if (ent_delay <= val) {
 369                 /* put RNG4 into run mode */
 370                 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
 371                 return;
 372         }
 373
 374         val = rd_reg32(&r4tst->rtsdctl);
 375         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 376               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 377         wr_reg32(&r4tst->rtsdctl, val);
 378         /* min. freq. count, equal to 1/4 of the entropy sample length */
 379         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 380         /* disable maximum frequency count */
 381         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 382         /* read the control register */
 383         val = rd_reg32(&r4tst->rtmctl);
 384         /*
 385          * select raw sampling in both entropy shifter
 386          * and statistical checker
 387          */
 388         clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
 389         /* put RNG4 into run mode */
 390         clrsetbits_32(&val, RTMCTL_PRGM, 0);
 391         /* write back the control register */
 392         wr_reg32(&r4tst->rtmctl, val);
 393 }
 394
 395 /**
 396  * caam_get_era() - Return the ERA of the SEC on SoC, based
 397  * on "sec-era" propery in the DTS. This property is updated by u-boot.
 398  **/
 399 int caam_get_era(void)
 400 {
 401         struct device_node *caam_node;
 402         int ret;
 403         u32 prop;
 404
 405         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 406         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 407         of_node_put(caam_node);
 408
 409         return ret ? -ENOTSUPP : prop;
 410 }
 411 EXPORT_SYMBOL(caam_get_era);
 412
 413 #ifdef CONFIG_DEBUG_FS
 414 static int caam_debugfs_u64_get(void *data, u64 *val)
 415 {
 416         *val = caam64_to_cpu(*(u64 *)data);
 417         return 0;
 418 }
 419
 420 static int caam_debugfs_u32_get(void *data, u64 *val)
 421 {
 422         *val = caam32_to_cpu(*(u32 *)data);
 423         return 0;
 424 }
 425
 426 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
 427 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
 428 #endif
 429
 430 /* Probe routine for CAAM top (controller) level */
 431 static int caam_probe(struct platform_device *pdev)
 432 {
 433         int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 434         u64 caam_id;
 435         struct device *dev;
 436         struct device_node *nprop, *np;
 437         struct caam_ctrl __iomem *ctrl;
 438         struct caam_drv_private *ctrlpriv;
 439         struct clk *clk;
 440 #ifdef CONFIG_DEBUG_FS
 441         struct caam_perfmon *perfmon;
 442 #endif
 443         u32 scfgr, comp_params;
 444         u32 cha_vid_ls;
 445         int pg_size;
 446         int BLOCK_OFFSET = 0;
 447
 448         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 449         if (!ctrlpriv)
 450                 return -ENOMEM;
 451
 452         dev = &pdev->dev;
 453         dev_set_drvdata(dev, ctrlpriv);
 454         ctrlpriv->pdev = pdev;
 455         nprop = pdev->dev.of_node;
 456
 457         /* Enable clocking */
 458         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 459         if (IS_ERR(clk)) {
 460                 ret = PTR_ERR(clk);
 461                 dev_err(&pdev->dev,
 462                         "can't identify CAAM ipg clk: %d\n", ret);
 463                 return ret;
 464         }
 465         ctrlpriv->caam_ipg = clk;
 466
 467         clk = caam_drv_identify_clk(&pdev->dev, "mem");
 468         if (IS_ERR(clk)) {
 469                 ret = PTR_ERR(clk);
 470                 dev_err(&pdev->dev,
 471                         "can't identify CAAM mem clk: %d\n", ret);
 472                 return ret;
 473         }
 474         ctrlpriv->caam_mem = clk;
 475
 476         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 477         if (IS_ERR(clk)) {
 478                 ret = PTR_ERR(clk);
 479                 dev_err(&pdev->dev,
 480                         "can't identify CAAM aclk clk: %d\n", ret);
 481                 return ret;
 482         }
 483         ctrlpriv->caam_aclk = clk;
 484
 485         clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 486         if (IS_ERR(clk)) {
 487                 ret = PTR_ERR(clk);
 488                 dev_err(&pdev->dev,
 489                         "can't identify CAAM emi_slow clk: %d\n", ret);
 490                 return ret;
 491         }
 492         ctrlpriv->caam_emi_slow = clk;
 493
 494         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 495         if (ret < 0) {
 496                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 497                 return ret;
 498         }
 499
 500         ret = clk_prepare_enable(ctrlpriv->caam_mem);
 501         if (ret < 0) {
 502                 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 503                         ret);
 504                 goto disable_caam_ipg;
 505         }
 506
 507         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 508         if (ret < 0) {
 509                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 510                 goto disable_caam_mem;
 511         }
 512
 513         ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 514         if (ret < 0) {
 515                 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 516                         ret);
 517                 goto disable_caam_aclk;
 518         }
 519
 520         /* Get configuration properties from device tree */
 521         /* First, get register page */
 522         ctrl = of_iomap(nprop, 0);
 523         if (ctrl == NULL) {
 524                 dev_err(dev, "caam: of_iomap() failed\n");
 525                 ret = -ENOMEM;
 526                 goto disable_caam_emi_slow;
 527         }
 528
 529         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 530                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 531
 532         /* Finding the page size for using the CTPR_MS register */
 533         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 534         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 535
 536         /* Allocating the BLOCK_OFFSET based on the supported page size on
 537          * the platform
 538          */
 539         if (pg_size == 0)
 540                 BLOCK_OFFSET = PG_SIZE_4K;
 541         else
 542                 BLOCK_OFFSET = PG_SIZE_64K;
 543
 544         ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
 545         ctrlpriv->assure = (struct caam_assurance __force *)
 546                            ((uint8_t *)ctrl +
 547                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 548                            );
 549         ctrlpriv->deco = (struct caam_deco __force *)
 550                          ((uint8_t *)ctrl +
 551                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 552                          );
 553
 554         /* Get the IRQ of the controller (for security violations only) */
 555         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 556
 557         /*
 558          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 559          * long pointers in master configuration register
 560          */
 561         clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 562                       MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 563                       MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 564                       (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 565
 566         /*
 567          *  Read the Compile Time paramters and SCFGR to determine
 568          * if Virtualization is enabled for this platform
 569          */
 570         scfgr = rd_reg32(&ctrl->scfgr);
 571
 572         ctrlpriv->virt_en = 0;
 573         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 574                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 575                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 576                  */
 577                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 578                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 579                        (scfgr & SCFGR_VIRT_EN)))
 580                                 ctrlpriv->virt_en = 1;
 581         } else {
 582                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 583                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 584                                 ctrlpriv->virt_en = 1;
 585         }
 586
 587         if (ctrlpriv->virt_en == 1)
 588                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 589                               JRSTART_JR1_START | JRSTART_JR2_START |
 590                               JRSTART_JR3_START);
 591
 592         if (sizeof(dma_addr_t) == sizeof(u64))
 593                 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 594                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 595                 else
 596                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 597         else
 598                 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 599
 600         /*
 601          * Detect and enable JobRs
 602          * First, find out how many ring spec'ed, allocate references
 603          * for all, then go probe each one.
 604          */
 605         rspec = 0;
 606         for_each_available_child_of_node(nprop, np)
 607                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 608                     of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
 609                         rspec++;
 610
 611         ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec,
 612                                         sizeof(*ctrlpriv->jrpdev), GFP_KERNEL);
 613         if (ctrlpriv->jrpdev == NULL) {
 614                 ret = -ENOMEM;
 615                 goto iounmap_ctrl;
 616         }
 617
 618         ring = 0;
 619         ctrlpriv->total_jobrs = 0;
 620         for_each_available_child_of_node(nprop, np)
 621                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 622                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 623                         ctrlpriv->jrpdev[ring] =
 624                                 of_platform_device_create(np, NULL, dev);
 625                         if (!ctrlpriv->jrpdev[ring]) {
 626                                 pr_warn("JR%d Platform device creation error\n",
 627                                         ring);
 628                                 continue;
 629                         }
 630                         ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
 631                                              ((uint8_t *)ctrl +
 632                                              (ring + JR_BLOCK_NUMBER) *
 633                                               BLOCK_OFFSET
 634                                              );
 635                         ctrlpriv->total_jobrs++;
 636                         ring++;
 637         }
 638
 639         /* Check to see if QI present. If so, enable */
 640         ctrlpriv->qi_present =
 641                         !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
 642                            CTPR_MS_QI_MASK);
 643         if (ctrlpriv->qi_present) {
 644                 ctrlpriv->qi = (struct caam_queue_if __force *)
 645                                ((uint8_t *)ctrl +
 646                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 647                                );
 648                 /* This is all that's required to physically enable QI */
 649                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 650         }
 651
 652         /* If no QI and no rings specified, quit and go home */
 653         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 654                 dev_err(dev, "no queues configured, terminating\n");
 655                 ret = -ENOMEM;
 656                 goto caam_remove;
 657         }
 658
 659         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 660
 661         /*
 662          * If SEC has RNG version >= 4 and RNG state handle has not been
 663          * already instantiated, do RNG instantiation
 664          */
 665         if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 666                 ctrlpriv->rng4_sh_init =
 667                         rd_reg32(&ctrl->r4tst[0].rdsta);
 668                 /*
 669                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 670                  * generated, signal this to the function that is instantiating
 671                  * the state handles. An error would occur if RNG4 attempts
 672                  * to regenerate these keys before the next POR.
 673                  */
 674                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 675                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 676                 do {
 677                         int inst_handles =
 678                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 679                                                                 RDSTA_IFMASK;
 680                         /*
 681                          * If either SH were instantiated by somebody else
 682                          * (e.g. u-boot) then it is assumed that the entropy
 683                          * parameters are properly set and thus the function
 684                          * setting these (kick_trng(...)) is skipped.
 685                          * Also, if a handle was instantiated, do not change
 686                          * the TRNG parameters.
 687                          */
 688                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 689                                 dev_info(dev,
 690                                          "Entropy delay = %u\n",
 691                                          ent_delay);
 692                                 kick_trng(pdev, ent_delay);
 693                                 ent_delay += 400;
 694                         }
 695                         /*
 696                          * if instantiate_rng(...) fails, the loop will rerun
 697                          * and the kick_trng(...) function will modfiy the
 698                          * upper and lower limits of the entropy sampling
 699                          * interval, leading to a sucessful initialization of
 700                          * the RNG.
 701                          */
 702                         ret = instantiate_rng(dev, inst_handles,
 703                                               gen_sk);
 704                         if (ret == -EAGAIN)
 705                                 /*
 706                                  * if here, the loop will rerun,
 707                                  * so don't hog the CPU
 708                                  */
 709                                 cpu_relax();
 710                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 711                 if (ret) {
 712                         dev_err(dev, "failed to instantiate RNG");
 713                         goto caam_remove;
 714                 }
 715                 /*
 716                  * Set handles init'ed by this module as the complement of the
 717                  * already initialized ones
 718                  */
 719                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 720
 721                 /* Enable RDB bit so that RNG works faster */
 722                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 723         }
 724
 725         /* NOTE: RTIC detection ought to go here, around Si time */
 726
 727         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 728                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 729
 730         /* Report "alive" for developer to see */
 731         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 732                  caam_get_era());
 733         dev_info(dev, "job rings = %d, qi = %d\n",
 734                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 735
 736 #ifdef CONFIG_DEBUG_FS
 737         /*
 738          * FIXME: needs better naming distinction, as some amalgamation of
 739          * "caam" and nprop->full_name. The OF name isn't distinctive,
 740          * but does separate instances
 741          */
 742         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 743
 744         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 745         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 746
 747         /* Controller-level - performance monitor counters */
 748
 749         ctrlpriv->ctl_rq_dequeued =
 750                 debugfs_create_file("rq_dequeued",
 751                                     S_IRUSR | S_IRGRP | S_IROTH,
 752                                     ctrlpriv->ctl, &perfmon->req_dequeued,
 753                                     &caam_fops_u64_ro);
 754         ctrlpriv->ctl_ob_enc_req =
 755                 debugfs_create_file("ob_rq_encrypted",
 756                                     S_IRUSR | S_IRGRP | S_IROTH,
 757                                     ctrlpriv->ctl, &perfmon->ob_enc_req,
 758                                     &caam_fops_u64_ro);
 759         ctrlpriv->ctl_ib_dec_req =
 760                 debugfs_create_file("ib_rq_decrypted",
 761                                     S_IRUSR | S_IRGRP | S_IROTH,
 762                                     ctrlpriv->ctl, &perfmon->ib_dec_req,
 763                                     &caam_fops_u64_ro);
 764         ctrlpriv->ctl_ob_enc_bytes =
 765                 debugfs_create_file("ob_bytes_encrypted",
 766                                     S_IRUSR | S_IRGRP | S_IROTH,
 767                                     ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 768                                     &caam_fops_u64_ro);
 769         ctrlpriv->ctl_ob_prot_bytes =
 770                 debugfs_create_file("ob_bytes_protected",
 771                                     S_IRUSR | S_IRGRP | S_IROTH,
 772                                     ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 773                                     &caam_fops_u64_ro);
 774         ctrlpriv->ctl_ib_dec_bytes =
 775                 debugfs_create_file("ib_bytes_decrypted",
 776                                     S_IRUSR | S_IRGRP | S_IROTH,
 777                                     ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 778                                     &caam_fops_u64_ro);
 779         ctrlpriv->ctl_ib_valid_bytes =
 780                 debugfs_create_file("ib_bytes_validated",
 781                                     S_IRUSR | S_IRGRP | S_IROTH,
 782                                     ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 783                                     &caam_fops_u64_ro);
 784
 785         /* Controller level - global status values */
 786         ctrlpriv->ctl_faultaddr =
 787                 debugfs_create_file("fault_addr",
 788                                     S_IRUSR | S_IRGRP | S_IROTH,
 789                                     ctrlpriv->ctl, &perfmon->faultaddr,
 790                                     &caam_fops_u32_ro);
 791         ctrlpriv->ctl_faultdetail =
 792                 debugfs_create_file("fault_detail",
 793                                     S_IRUSR | S_IRGRP | S_IROTH,
 794                                     ctrlpriv->ctl, &perfmon->faultdetail,
 795                                     &caam_fops_u32_ro);
 796         ctrlpriv->ctl_faultstatus =
 797                 debugfs_create_file("fault_status",
 798                                     S_IRUSR | S_IRGRP | S_IROTH,
 799                                     ctrlpriv->ctl, &perfmon->status,
 800                                     &caam_fops_u32_ro);
 801
 802         /* Internal covering keys (useful in non-secure mode only) */
 803         ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
 804         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 805         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
 806                                                 S_IRUSR |
 807                                                 S_IRGRP | S_IROTH,
 808                                                 ctrlpriv->ctl,
 809                                                 &ctrlpriv->ctl_kek_wrap);
 810
 811         ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
 812         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 813         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
 814                                                  S_IRUSR |
 815                                                  S_IRGRP | S_IROTH,
 816                                                  ctrlpriv->ctl,
 817                                                  &ctrlpriv->ctl_tkek_wrap);
 818
 819         ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
 820         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 821         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
 822                                                  S_IRUSR |
 823                                                  S_IRGRP | S_IROTH,
 824                                                  ctrlpriv->ctl,
 825                                                  &ctrlpriv->ctl_tdsk_wrap);
 826 #endif
 827         return 0;
 828
 829 caam_remove:
 830         caam_remove(pdev);
 831         return ret;
 832
 833 iounmap_ctrl:
 834         iounmap(ctrl);
 835 disable_caam_emi_slow:
 836         clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 837 disable_caam_aclk:
 838         clk_disable_unprepare(ctrlpriv->caam_aclk);
 839 disable_caam_mem:
 840         clk_disable_unprepare(ctrlpriv->caam_mem);
 841 disable_caam_ipg:
 842         clk_disable_unprepare(ctrlpriv->caam_ipg);
 843         return ret;
 844 }
 845
 846 static struct of_device_id caam_match[] = {
 847         {
 848                 .compatible = "fsl,sec-v4.0",
 849         },
 850         {
 851                 .compatible = "fsl,sec4.0",
 852         },
 853         {},
 854 };
 855 MODULE_DEVICE_TABLE(of, caam_match);
 856
 857 static struct platform_driver caam_driver = {
 858         .driver = {
 859                 .name = "caam",
 860                 .of_match_table = caam_match,
 861         },
 862         .probe       = caam_probe,
 863         .remove      = caam_remove,
 864 };
 865
 866 module_platform_driver(caam_driver);
 867
 868 MODULE_LICENSE("GPL");
 869 MODULE_DESCRIPTION("FSL CAAM request backend");
 870 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");