1 /* * CAAM control-plane driver backend
2 * Controller-level driver, kernel property detection, initialization
4 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
10 #include <linux/sys_soc.h>
16 #include "desc_constr.h"
20 EXPORT_SYMBOL(caam_little_end
);
22 EXPORT_SYMBOL(caam_dpaa2
);
24 EXPORT_SYMBOL(caam_imx
);
31 * i.MX targets tend to have clock control subsystems that can
32 * enable/disable clocking to our device.
34 static inline struct clk
*caam_drv_identify_clk(struct device
*dev
,
37 return caam_imx
? devm_clk_get(dev
, clk_name
) : NULL
;
41 * Descriptor to instantiate RNG State Handle 0 in normal mode and
42 * load the JDKEK, TDKEK and TDSK registers
44 static void build_instantiation_desc(u32
*desc
, int handle
, int do_sk
)
46 u32
*jump_cmd
, op_flags
;
48 init_job_desc(desc
, 0);
50 op_flags
= OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
51 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INIT
;
53 /* INIT RNG in non-test mode */
54 append_operation(desc
, op_flags
);
56 if (!handle
&& do_sk
) {
58 * For SH0, Secure Keys must be generated as well
62 jump_cmd
= append_jump(desc
, JUMP_CLASS_CLASS1
);
63 set_jump_tgt_here(desc
, jump_cmd
);
66 * load 1 to clear written reg:
67 * resets the done interrrupt and returns the RNG to idle.
69 append_load_imm_u32(desc
, 1, LDST_SRCDST_WORD_CLRW
);
71 /* Initialize State Handle */
72 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
76 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
80 static void build_deinstantiation_desc(u32
*desc
, int handle
)
82 init_job_desc(desc
, 0);
84 /* Uninstantiate State Handle 0 */
85 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
86 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INITFINAL
);
88 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
92 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
93 * the software (no JR/QI used).
94 * @ctrldev - pointer to device
95 * @status - descriptor status, after being run
97 * Return: - 0 if no error occurred
98 * - -ENODEV if the DECO couldn't be acquired
99 * - -EAGAIN if an error occurred while executing the descriptor
101 static inline int run_descriptor_deco0(struct device
*ctrldev
, u32
*desc
,
104 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
105 struct caam_ctrl __iomem
*ctrl
= ctrlpriv
->ctrl
;
106 struct caam_deco __iomem
*deco
= ctrlpriv
->deco
;
107 unsigned int timeout
= 100000;
108 u32 deco_dbg_reg
, flags
;
112 if (ctrlpriv
->virt_en
== 1) {
113 clrsetbits_32(&ctrl
->deco_rsr
, 0, DECORSR_JR0
);
115 while (!(rd_reg32(&ctrl
->deco_rsr
) & DECORSR_VALID
) &&
122 clrsetbits_32(&ctrl
->deco_rq
, 0, DECORR_RQD0ENABLE
);
124 while (!(rd_reg32(&ctrl
->deco_rq
) & DECORR_DEN0
) &&
129 dev_err(ctrldev
, "failed to acquire DECO 0\n");
130 clrsetbits_32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
, 0);
134 for (i
= 0; i
< desc_len(desc
); i
++)
135 wr_reg32(&deco
->descbuf
[i
], caam32_to_cpu(*(desc
+ i
)));
137 flags
= DECO_JQCR_WHL
;
139 * If the descriptor length is longer than 4 words, then the
140 * FOUR bit in JRCTRL register must be set.
142 if (desc_len(desc
) >= 4)
143 flags
|= DECO_JQCR_FOUR
;
145 /* Instruct the DECO to execute it */
146 clrsetbits_32(&deco
->jr_ctl_hi
, 0, flags
);
150 deco_dbg_reg
= rd_reg32(&deco
->desc_dbg
);
152 * If an error occured in the descriptor, then
153 * the DECO status field will be set to 0x0D
155 if ((deco_dbg_reg
& DESC_DBG_DECO_STAT_MASK
) ==
156 DESC_DBG_DECO_STAT_HOST_ERR
)
159 } while ((deco_dbg_reg
& DESC_DBG_DECO_STAT_VALID
) && --timeout
);
161 *status
= rd_reg32(&deco
->op_status_hi
) &
162 DECO_OP_STATUS_HI_ERR_MASK
;
164 if (ctrlpriv
->virt_en
== 1)
165 clrsetbits_32(&ctrl
->deco_rsr
, DECORSR_JR0
, 0);
167 /* Mark the DECO as free */
168 clrsetbits_32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
, 0);
177 * instantiate_rng - builds and executes a descriptor on DECO0,
178 * which initializes the RNG block.
179 * @ctrldev - pointer to device
180 * @state_handle_mask - bitmask containing the instantiation status
181 * for the RNG4 state handles which exist in
182 * the RNG4 block: 1 if it's been instantiated
183 * by an external entry, 0 otherwise.
184 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
185 * Caution: this can be done only once; if the keys need to be
186 * regenerated, a POR is required
188 * Return: - 0 if no error occurred
189 * - -ENOMEM if there isn't enough memory to allocate the descriptor
190 * - -ENODEV if DECO0 couldn't be acquired
191 * - -EAGAIN if an error occurred when executing the descriptor
192 * f.i. there was a RNG hardware error due to not "good enough"
193 * entropy being aquired.
195 static int instantiate_rng(struct device
*ctrldev
, int state_handle_mask
,
198 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
199 struct caam_ctrl __iomem
*ctrl
;
200 u32
*desc
, status
= 0, rdsta_val
;
203 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
204 desc
= kmalloc(CAAM_CMD_SZ
* 7, GFP_KERNEL
);
208 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
210 * If the corresponding bit is set, this state handle
211 * was initialized by somebody else, so it's left alone.
213 if ((1 << sh_idx
) & state_handle_mask
)
216 /* Create the descriptor for instantiating RNG State Handle */
217 build_instantiation_desc(desc
, sh_idx
, gen_sk
);
219 /* Try to run it through DECO0 */
220 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
223 * If ret is not 0, or descriptor status is not 0, then
224 * something went wrong. No need to try the next state
225 * handle (if available), bail out here.
226 * Also, if for some reason, the State Handle didn't get
227 * instantiated although the descriptor has finished
228 * without any error (HW optimizations for later
229 * CAAM eras), then try again.
231 rdsta_val
= rd_reg32(&ctrl
->r4tst
[0].rdsta
) & RDSTA_IFMASK
;
232 if ((status
&& status
!= JRSTA_SSRC_JUMP_HALT_CC
) ||
233 !(rdsta_val
& (1 << sh_idx
)))
237 dev_info(ctrldev
, "Instantiated RNG4 SH%d\n", sh_idx
);
238 /* Clear the contents before recreating the descriptor */
239 memset(desc
, 0x00, CAAM_CMD_SZ
* 7);
248 * deinstantiate_rng - builds and executes a descriptor on DECO0,
249 * which deinitializes the RNG block.
250 * @ctrldev - pointer to device
251 * @state_handle_mask - bitmask containing the instantiation status
252 * for the RNG4 state handles which exist in
253 * the RNG4 block: 1 if it's been instantiated
255 * Return: - 0 if no error occurred
256 * - -ENOMEM if there isn't enough memory to allocate the descriptor
257 * - -ENODEV if DECO0 couldn't be acquired
258 * - -EAGAIN if an error occurred when executing the descriptor
260 static int deinstantiate_rng(struct device
*ctrldev
, int state_handle_mask
)
265 desc
= kmalloc(CAAM_CMD_SZ
* 3, GFP_KERNEL
);
269 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
271 * If the corresponding bit is set, then it means the state
272 * handle was initialized by us, and thus it needs to be
273 * deinitialized as well
275 if ((1 << sh_idx
) & state_handle_mask
) {
277 * Create the descriptor for deinstantating this state
280 build_deinstantiation_desc(desc
, sh_idx
);
282 /* Try to run it through DECO0 */
283 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
286 (status
&& status
!= JRSTA_SSRC_JUMP_HALT_CC
)) {
288 "Failed to deinstantiate RNG4 SH%d\n",
292 dev_info(ctrldev
, "Deinstantiated RNG4 SH%d\n", sh_idx
);
301 static int caam_remove(struct platform_device
*pdev
)
303 struct device
*ctrldev
;
304 struct caam_drv_private
*ctrlpriv
;
305 struct caam_ctrl __iomem
*ctrl
;
307 ctrldev
= &pdev
->dev
;
308 ctrlpriv
= dev_get_drvdata(ctrldev
);
309 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
311 /* Remove platform devices under the crypto node */
312 of_platform_depopulate(ctrldev
);
314 #ifdef CONFIG_CAAM_QI
316 caam_qi_shutdown(ctrlpriv
->qidev
);
320 * De-initialize RNG state handles initialized by this driver.
321 * In case of DPAA 2.x, RNG is managed by MC firmware.
323 if (!caam_dpaa2
&& ctrlpriv
->rng4_sh_init
)
324 deinstantiate_rng(ctrldev
, ctrlpriv
->rng4_sh_init
);
326 /* Shut down debug views */
327 #ifdef CONFIG_DEBUG_FS
328 debugfs_remove_recursive(ctrlpriv
->dfs_root
);
331 /* Unmap controller region */
334 /* shut clocks off before finalizing shutdown */
335 clk_disable_unprepare(ctrlpriv
->caam_ipg
);
336 clk_disable_unprepare(ctrlpriv
->caam_mem
);
337 clk_disable_unprepare(ctrlpriv
->caam_aclk
);
338 if (ctrlpriv
->caam_emi_slow
)
339 clk_disable_unprepare(ctrlpriv
->caam_emi_slow
);
344 * kick_trng - sets the various parameters for enabling the initialization
345 * of the RNG4 block in CAAM
346 * @pdev - pointer to the platform device
347 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
349 static void kick_trng(struct platform_device
*pdev
, int ent_delay
)
351 struct device
*ctrldev
= &pdev
->dev
;
352 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
353 struct caam_ctrl __iomem
*ctrl
;
354 struct rng4tst __iomem
*r4tst
;
357 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
358 r4tst
= &ctrl
->r4tst
[0];
360 /* put RNG4 into program mode */
361 clrsetbits_32(&r4tst
->rtmctl
, 0, RTMCTL_PRGM
);
364 * Performance-wise, it does not make sense to
365 * set the delay to a value that is lower
366 * than the last one that worked (i.e. the state handles
367 * were instantiated properly. Thus, instead of wasting
368 * time trying to set the values controlling the sample
369 * frequency, the function simply returns.
371 val
= (rd_reg32(&r4tst
->rtsdctl
) & RTSDCTL_ENT_DLY_MASK
)
372 >> RTSDCTL_ENT_DLY_SHIFT
;
373 if (ent_delay
<= val
)
376 val
= rd_reg32(&r4tst
->rtsdctl
);
377 val
= (val
& ~RTSDCTL_ENT_DLY_MASK
) |
378 (ent_delay
<< RTSDCTL_ENT_DLY_SHIFT
);
379 wr_reg32(&r4tst
->rtsdctl
, val
);
380 /* min. freq. count, equal to 1/4 of the entropy sample length */
381 wr_reg32(&r4tst
->rtfrqmin
, ent_delay
>> 2);
382 /* disable maximum frequency count */
383 wr_reg32(&r4tst
->rtfrqmax
, RTFRQMAX_DISABLE
);
384 /* read the control register */
385 val
= rd_reg32(&r4tst
->rtmctl
);
388 * select raw sampling in both entropy shifter
389 * and statistical checker; ; put RNG4 into run mode
391 clrsetbits_32(&r4tst
->rtmctl
, RTMCTL_PRGM
, RTMCTL_SAMP_MODE_RAW_ES_SC
);
395 * caam_get_era() - Return the ERA of the SEC on SoC, based
396 * on "sec-era" propery in the DTS. This property is updated by u-boot.
398 int caam_get_era(void)
400 struct device_node
*caam_node
;
404 caam_node
= of_find_compatible_node(NULL
, NULL
, "fsl,sec-v4.0");
405 ret
= of_property_read_u32(caam_node
, "fsl,sec-era", &prop
);
406 of_node_put(caam_node
);
408 return ret
? -ENOTSUPP
: prop
;
410 EXPORT_SYMBOL(caam_get_era
);
412 static const struct of_device_id caam_match
[] = {
414 .compatible
= "fsl,sec-v4.0",
417 .compatible
= "fsl,sec4.0",
421 MODULE_DEVICE_TABLE(of
, caam_match
);
423 /* Probe routine for CAAM top (controller) level */
424 static int caam_probe(struct platform_device
*pdev
)
426 int ret
, ring
, gen_sk
, ent_delay
= RTSDCTL_ENT_DLY_MIN
;
428 static const struct soc_device_attribute imx_soc
[] = {
429 {.family
= "Freescale i.MX"},
433 struct device_node
*nprop
, *np
;
434 struct caam_ctrl __iomem
*ctrl
;
435 struct caam_drv_private
*ctrlpriv
;
437 #ifdef CONFIG_DEBUG_FS
438 struct caam_perfmon
*perfmon
;
440 u32 scfgr
, comp_params
;
443 int BLOCK_OFFSET
= 0;
445 ctrlpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*ctrlpriv
), GFP_KERNEL
);
450 dev_set_drvdata(dev
, ctrlpriv
);
451 nprop
= pdev
->dev
.of_node
;
453 caam_imx
= (bool)soc_device_match(imx_soc
);
455 /* Enable clocking */
456 clk
= caam_drv_identify_clk(&pdev
->dev
, "ipg");
460 "can't identify CAAM ipg clk: %d\n", ret
);
463 ctrlpriv
->caam_ipg
= clk
;
465 clk
= caam_drv_identify_clk(&pdev
->dev
, "mem");
469 "can't identify CAAM mem clk: %d\n", ret
);
472 ctrlpriv
->caam_mem
= clk
;
474 clk
= caam_drv_identify_clk(&pdev
->dev
, "aclk");
478 "can't identify CAAM aclk clk: %d\n", ret
);
481 ctrlpriv
->caam_aclk
= clk
;
483 if (!of_machine_is_compatible("fsl,imx6ul")) {
484 clk
= caam_drv_identify_clk(&pdev
->dev
, "emi_slow");
488 "can't identify CAAM emi_slow clk: %d\n", ret
);
491 ctrlpriv
->caam_emi_slow
= clk
;
494 ret
= clk_prepare_enable(ctrlpriv
->caam_ipg
);
496 dev_err(&pdev
->dev
, "can't enable CAAM ipg clock: %d\n", ret
);
500 ret
= clk_prepare_enable(ctrlpriv
->caam_mem
);
502 dev_err(&pdev
->dev
, "can't enable CAAM secure mem clock: %d\n",
504 goto disable_caam_ipg
;
507 ret
= clk_prepare_enable(ctrlpriv
->caam_aclk
);
509 dev_err(&pdev
->dev
, "can't enable CAAM aclk clock: %d\n", ret
);
510 goto disable_caam_mem
;
513 if (ctrlpriv
->caam_emi_slow
) {
514 ret
= clk_prepare_enable(ctrlpriv
->caam_emi_slow
);
516 dev_err(&pdev
->dev
, "can't enable CAAM emi slow clock: %d\n",
518 goto disable_caam_aclk
;
522 /* Get configuration properties from device tree */
523 /* First, get register page */
524 ctrl
= of_iomap(nprop
, 0);
526 dev_err(dev
, "caam: of_iomap() failed\n");
528 goto disable_caam_emi_slow
;
531 caam_little_end
= !(bool)(rd_reg32(&ctrl
->perfmon
.status
) &
532 (CSTA_PLEND
| CSTA_ALT_PLEND
));
534 /* Finding the page size for using the CTPR_MS register */
535 comp_params
= rd_reg32(&ctrl
->perfmon
.comp_parms_ms
);
536 pg_size
= (comp_params
& CTPR_MS_PG_SZ_MASK
) >> CTPR_MS_PG_SZ_SHIFT
;
538 /* Allocating the BLOCK_OFFSET based on the supported page size on
542 BLOCK_OFFSET
= PG_SIZE_4K
;
544 BLOCK_OFFSET
= PG_SIZE_64K
;
546 ctrlpriv
->ctrl
= (struct caam_ctrl __iomem __force
*)ctrl
;
547 ctrlpriv
->assure
= (struct caam_assurance __iomem __force
*)
548 ((__force
uint8_t *)ctrl
+
549 BLOCK_OFFSET
* ASSURE_BLOCK_NUMBER
551 ctrlpriv
->deco
= (struct caam_deco __iomem __force
*)
552 ((__force
uint8_t *)ctrl
+
553 BLOCK_OFFSET
* DECO_BLOCK_NUMBER
556 /* Get the IRQ of the controller (for security violations only) */
557 ctrlpriv
->secvio_irq
= irq_of_parse_and_map(nprop
, 0);
560 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
561 * long pointers in master configuration register.
562 * In case of DPAA 2.x, Management Complex firmware performs
565 caam_dpaa2
= !!(comp_params
& CTPR_MS_DPAA2
);
567 clrsetbits_32(&ctrl
->mcr
, MCFGR_AWCACHE_MASK
| MCFGR_LONG_PTR
,
568 MCFGR_AWCACHE_CACH
| MCFGR_AWCACHE_BUFF
|
569 MCFGR_WDENABLE
| MCFGR_LARGE_BURST
|
570 (sizeof(dma_addr_t
) == sizeof(u64
) ?
571 MCFGR_LONG_PTR
: 0));
574 * Read the Compile Time paramters and SCFGR to determine
575 * if Virtualization is enabled for this platform
577 scfgr
= rd_reg32(&ctrl
->scfgr
);
579 ctrlpriv
->virt_en
= 0;
580 if (comp_params
& CTPR_MS_VIRT_EN_INCL
) {
581 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
582 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
584 if ((comp_params
& CTPR_MS_VIRT_EN_POR
) ||
585 (!(comp_params
& CTPR_MS_VIRT_EN_POR
) &&
586 (scfgr
& SCFGR_VIRT_EN
)))
587 ctrlpriv
->virt_en
= 1;
589 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
590 if (comp_params
& CTPR_MS_VIRT_EN_POR
)
591 ctrlpriv
->virt_en
= 1;
594 if (ctrlpriv
->virt_en
== 1)
595 clrsetbits_32(&ctrl
->jrstart
, 0, JRSTART_JR0_START
|
596 JRSTART_JR1_START
| JRSTART_JR2_START
|
599 if (sizeof(dma_addr_t
) == sizeof(u64
)) {
601 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(49));
602 else if (of_device_is_compatible(nprop
, "fsl,sec-v5.0"))
603 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(40));
605 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(36));
607 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
610 dev_err(dev
, "dma_set_mask_and_coherent failed (%d)\n", ret
);
614 ret
= of_platform_populate(nprop
, caam_match
, NULL
, dev
);
616 dev_err(dev
, "JR platform devices creation error\n");
620 #ifdef CONFIG_DEBUG_FS
622 * FIXME: needs better naming distinction, as some amalgamation of
623 * "caam" and nprop->full_name. The OF name isn't distinctive,
624 * but does separate instances
626 perfmon
= (struct caam_perfmon __force
*)&ctrl
->perfmon
;
628 ctrlpriv
->dfs_root
= debugfs_create_dir(dev_name(dev
), NULL
);
629 ctrlpriv
->ctl
= debugfs_create_dir("ctl", ctrlpriv
->dfs_root
);
633 for_each_available_child_of_node(nprop
, np
)
634 if (of_device_is_compatible(np
, "fsl,sec-v4.0-job-ring") ||
635 of_device_is_compatible(np
, "fsl,sec4.0-job-ring")) {
636 ctrlpriv
->jr
[ring
] = (struct caam_job_ring __iomem __force
*)
637 ((__force
uint8_t *)ctrl
+
638 (ring
+ JR_BLOCK_NUMBER
) *
641 ctrlpriv
->total_jobrs
++;
645 /* Check to see if (DPAA 1.x) QI present. If so, enable */
646 ctrlpriv
->qi_present
= !!(comp_params
& CTPR_MS_QI_MASK
);
647 if (ctrlpriv
->qi_present
&& !caam_dpaa2
) {
648 ctrlpriv
->qi
= (struct caam_queue_if __iomem __force
*)
649 ((__force
uint8_t *)ctrl
+
650 BLOCK_OFFSET
* QI_BLOCK_NUMBER
652 /* This is all that's required to physically enable QI */
653 wr_reg32(&ctrlpriv
->qi
->qi_control_lo
, QICTL_DQEN
);
655 /* If QMAN driver is present, init CAAM-QI backend */
656 #ifdef CONFIG_CAAM_QI
657 ret
= caam_qi_init(pdev
);
659 dev_err(dev
, "caam qi i/f init failed: %d\n", ret
);
663 /* If no QI and no rings specified, quit and go home */
664 if ((!ctrlpriv
->qi_present
) && (!ctrlpriv
->total_jobrs
)) {
665 dev_err(dev
, "no queues configured, terminating\n");
670 cha_vid_ls
= rd_reg32(&ctrl
->perfmon
.cha_id_ls
);
673 * If SEC has RNG version >= 4 and RNG state handle has not been
674 * already instantiated, do RNG instantiation
675 * In case of DPAA 2.x, RNG is managed by MC firmware.
678 (cha_vid_ls
& CHA_ID_LS_RNG_MASK
) >> CHA_ID_LS_RNG_SHIFT
>= 4) {
679 ctrlpriv
->rng4_sh_init
=
680 rd_reg32(&ctrl
->r4tst
[0].rdsta
);
682 * If the secure keys (TDKEK, JDKEK, TDSK), were already
683 * generated, signal this to the function that is instantiating
684 * the state handles. An error would occur if RNG4 attempts
685 * to regenerate these keys before the next POR.
687 gen_sk
= ctrlpriv
->rng4_sh_init
& RDSTA_SKVN
? 0 : 1;
688 ctrlpriv
->rng4_sh_init
&= RDSTA_IFMASK
;
691 rd_reg32(&ctrl
->r4tst
[0].rdsta
) &
694 * If either SH were instantiated by somebody else
695 * (e.g. u-boot) then it is assumed that the entropy
696 * parameters are properly set and thus the function
697 * setting these (kick_trng(...)) is skipped.
698 * Also, if a handle was instantiated, do not change
699 * the TRNG parameters.
701 if (!(ctrlpriv
->rng4_sh_init
|| inst_handles
)) {
703 "Entropy delay = %u\n",
705 kick_trng(pdev
, ent_delay
);
709 * if instantiate_rng(...) fails, the loop will rerun
710 * and the kick_trng(...) function will modfiy the
711 * upper and lower limits of the entropy sampling
712 * interval, leading to a sucessful initialization of
715 ret
= instantiate_rng(dev
, inst_handles
,
719 * if here, the loop will rerun,
720 * so don't hog the CPU
723 } while ((ret
== -EAGAIN
) && (ent_delay
< RTSDCTL_ENT_DLY_MAX
));
725 dev_err(dev
, "failed to instantiate RNG");
729 * Set handles init'ed by this module as the complement of the
730 * already initialized ones
732 ctrlpriv
->rng4_sh_init
= ~ctrlpriv
->rng4_sh_init
& RDSTA_IFMASK
;
734 /* Enable RDB bit so that RNG works faster */
735 clrsetbits_32(&ctrl
->scfgr
, 0, SCFGR_RDBENABLE
);
738 /* NOTE: RTIC detection ought to go here, around Si time */
740 caam_id
= (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ms
) << 32 |
741 (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ls
);
743 /* Report "alive" for developer to see */
744 dev_info(dev
, "device ID = 0x%016llx (Era %d)\n", caam_id
,
746 dev_info(dev
, "job rings = %d, qi = %d, dpaa2 = %s\n",
747 ctrlpriv
->total_jobrs
, ctrlpriv
->qi_present
,
748 caam_dpaa2
? "yes" : "no");
750 #ifdef CONFIG_DEBUG_FS
751 debugfs_create_file("rq_dequeued", S_IRUSR
| S_IRGRP
| S_IROTH
,
752 ctrlpriv
->ctl
, &perfmon
->req_dequeued
,
754 debugfs_create_file("ob_rq_encrypted", S_IRUSR
| S_IRGRP
| S_IROTH
,
755 ctrlpriv
->ctl
, &perfmon
->ob_enc_req
,
757 debugfs_create_file("ib_rq_decrypted", S_IRUSR
| S_IRGRP
| S_IROTH
,
758 ctrlpriv
->ctl
, &perfmon
->ib_dec_req
,
760 debugfs_create_file("ob_bytes_encrypted", S_IRUSR
| S_IRGRP
| S_IROTH
,
761 ctrlpriv
->ctl
, &perfmon
->ob_enc_bytes
,
763 debugfs_create_file("ob_bytes_protected", S_IRUSR
| S_IRGRP
| S_IROTH
,
764 ctrlpriv
->ctl
, &perfmon
->ob_prot_bytes
,
766 debugfs_create_file("ib_bytes_decrypted", S_IRUSR
| S_IRGRP
| S_IROTH
,
767 ctrlpriv
->ctl
, &perfmon
->ib_dec_bytes
,
769 debugfs_create_file("ib_bytes_validated", S_IRUSR
| S_IRGRP
| S_IROTH
,
770 ctrlpriv
->ctl
, &perfmon
->ib_valid_bytes
,
773 /* Controller level - global status values */
774 debugfs_create_file("fault_addr", S_IRUSR
| S_IRGRP
| S_IROTH
,
775 ctrlpriv
->ctl
, &perfmon
->faultaddr
,
777 debugfs_create_file("fault_detail", S_IRUSR
| S_IRGRP
| S_IROTH
,
778 ctrlpriv
->ctl
, &perfmon
->faultdetail
,
780 debugfs_create_file("fault_status", S_IRUSR
| S_IRGRP
| S_IROTH
,
781 ctrlpriv
->ctl
, &perfmon
->status
,
784 /* Internal covering keys (useful in non-secure mode only) */
785 ctrlpriv
->ctl_kek_wrap
.data
= (__force
void *)&ctrlpriv
->ctrl
->kek
[0];
786 ctrlpriv
->ctl_kek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
787 ctrlpriv
->ctl_kek
= debugfs_create_blob("kek",
791 &ctrlpriv
->ctl_kek_wrap
);
793 ctrlpriv
->ctl_tkek_wrap
.data
= (__force
void *)&ctrlpriv
->ctrl
->tkek
[0];
794 ctrlpriv
->ctl_tkek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
795 ctrlpriv
->ctl_tkek
= debugfs_create_blob("tkek",
799 &ctrlpriv
->ctl_tkek_wrap
);
801 ctrlpriv
->ctl_tdsk_wrap
.data
= (__force
void *)&ctrlpriv
->ctrl
->tdsk
[0];
802 ctrlpriv
->ctl_tdsk_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
803 ctrlpriv
->ctl_tdsk
= debugfs_create_blob("tdsk",
807 &ctrlpriv
->ctl_tdsk_wrap
);
812 #ifdef CONFIG_DEBUG_FS
813 debugfs_remove_recursive(ctrlpriv
->dfs_root
);
820 disable_caam_emi_slow
:
821 if (ctrlpriv
->caam_emi_slow
)
822 clk_disable_unprepare(ctrlpriv
->caam_emi_slow
);
824 clk_disable_unprepare(ctrlpriv
->caam_aclk
);
826 clk_disable_unprepare(ctrlpriv
->caam_mem
);
828 clk_disable_unprepare(ctrlpriv
->caam_ipg
);
832 static struct platform_driver caam_driver
= {
835 .of_match_table
= caam_match
,
838 .remove
= caam_remove
,
841 module_platform_driver(caam_driver
);
843 MODULE_LICENSE("GPL");
844 MODULE_DESCRIPTION("FSL CAAM request backend");
845 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");