1 /* * CAAM control-plane driver backend
2 * Controller-level driver, kernel property detection, initialization
4 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
15 #include "desc_constr.h"
19 EXPORT_SYMBOL(caam_little_end
);
22 * i.MX targets tend to have clock control subsystems that can
23 * enable/disable clocking to our device.
25 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
26 static inline struct clk
*caam_drv_identify_clk(struct device
*dev
,
29 return devm_clk_get(dev
, clk_name
);
32 static inline struct clk
*caam_drv_identify_clk(struct device
*dev
,
40 * Descriptor to instantiate RNG State Handle 0 in normal mode and
41 * load the JDKEK, TDKEK and TDSK registers
43 static void build_instantiation_desc(u32
*desc
, int handle
, int do_sk
)
45 u32
*jump_cmd
, op_flags
;
47 init_job_desc(desc
, 0);
49 op_flags
= OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
50 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INIT
;
52 /* INIT RNG in non-test mode */
53 append_operation(desc
, op_flags
);
55 if (!handle
&& do_sk
) {
57 * For SH0, Secure Keys must be generated as well
61 jump_cmd
= append_jump(desc
, JUMP_CLASS_CLASS1
);
62 set_jump_tgt_here(desc
, jump_cmd
);
65 * load 1 to clear written reg:
66 * resets the done interrrupt and returns the RNG to idle.
68 append_load_imm_u32(desc
, 1, LDST_SRCDST_WORD_CLRW
);
70 /* Initialize State Handle */
71 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
75 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
78 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
79 static void build_deinstantiation_desc(u32
*desc
, int handle
)
81 init_job_desc(desc
, 0);
83 /* Uninstantiate State Handle 0 */
84 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
85 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INITFINAL
);
87 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
91 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
92 * the software (no JR/QI used).
93 * @ctrldev - pointer to device
94 * @status - descriptor status, after being run
96 * Return: - 0 if no error occurred
97 * - -ENODEV if the DECO couldn't be acquired
98 * - -EAGAIN if an error occurred while executing the descriptor
100 static inline int run_descriptor_deco0(struct device
*ctrldev
, u32
*desc
,
103 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
104 struct caam_ctrl __iomem
*ctrl
= ctrlpriv
->ctrl
;
105 struct caam_deco __iomem
*deco
= ctrlpriv
->deco
;
106 unsigned int timeout
= 100000;
107 u32 deco_dbg_reg
, flags
;
111 if (ctrlpriv
->virt_en
== 1) {
112 clrsetbits_32(&ctrl
->deco_rsr
, 0, DECORSR_JR0
);
114 while (!(rd_reg32(&ctrl
->deco_rsr
) & DECORSR_VALID
) &&
121 clrsetbits_32(&ctrl
->deco_rq
, 0, DECORR_RQD0ENABLE
);
123 while (!(rd_reg32(&ctrl
->deco_rq
) & DECORR_DEN0
) &&
128 dev_err(ctrldev
, "failed to acquire DECO 0\n");
129 clrsetbits_32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
, 0);
133 for (i
= 0; i
< desc_len(desc
); i
++)
134 wr_reg32(&deco
->descbuf
[i
], caam32_to_cpu(*(desc
+ i
)));
136 flags
= DECO_JQCR_WHL
;
138 * If the descriptor length is longer than 4 words, then the
139 * FOUR bit in JRCTRL register must be set.
141 if (desc_len(desc
) >= 4)
142 flags
|= DECO_JQCR_FOUR
;
144 /* Instruct the DECO to execute it */
145 clrsetbits_32(&deco
->jr_ctl_hi
, 0, flags
);
149 deco_dbg_reg
= rd_reg32(&deco
->desc_dbg
);
151 * If an error occured in the descriptor, then
152 * the DECO status field will be set to 0x0D
154 if ((deco_dbg_reg
& DESC_DBG_DECO_STAT_MASK
) ==
155 DESC_DBG_DECO_STAT_HOST_ERR
)
158 } while ((deco_dbg_reg
& DESC_DBG_DECO_STAT_VALID
) && --timeout
);
160 *status
= rd_reg32(&deco
->op_status_hi
) &
161 DECO_OP_STATUS_HI_ERR_MASK
;
163 if (ctrlpriv
->virt_en
== 1)
164 clrsetbits_32(&ctrl
->deco_rsr
, DECORSR_JR0
, 0);
166 /* Mark the DECO as free */
167 clrsetbits_32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
, 0);
176 * instantiate_rng - builds and executes a descriptor on DECO0,
177 * which initializes the RNG block.
178 * @ctrldev - pointer to device
179 * @state_handle_mask - bitmask containing the instantiation status
180 * for the RNG4 state handles which exist in
181 * the RNG4 block: 1 if it's been instantiated
182 * by an external entry, 0 otherwise.
183 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
184 * Caution: this can be done only once; if the keys need to be
185 * regenerated, a POR is required
187 * Return: - 0 if no error occurred
188 * - -ENOMEM if there isn't enough memory to allocate the descriptor
189 * - -ENODEV if DECO0 couldn't be acquired
190 * - -EAGAIN if an error occurred when executing the descriptor
191 * f.i. there was a RNG hardware error due to not "good enough"
192 * entropy being aquired.
194 static int instantiate_rng(struct device
*ctrldev
, int state_handle_mask
,
197 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
198 struct caam_ctrl __iomem
*ctrl
;
199 u32
*desc
, status
= 0, rdsta_val
;
202 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
203 desc
= kmalloc(CAAM_CMD_SZ
* 7, GFP_KERNEL
);
207 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
209 * If the corresponding bit is set, this state handle
210 * was initialized by somebody else, so it's left alone.
212 if ((1 << sh_idx
) & state_handle_mask
)
215 /* Create the descriptor for instantiating RNG State Handle */
216 build_instantiation_desc(desc
, sh_idx
, gen_sk
);
218 /* Try to run it through DECO0 */
219 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
222 * If ret is not 0, or descriptor status is not 0, then
223 * something went wrong. No need to try the next state
224 * handle (if available), bail out here.
225 * Also, if for some reason, the State Handle didn't get
226 * instantiated although the descriptor has finished
227 * without any error (HW optimizations for later
228 * CAAM eras), then try again.
230 rdsta_val
= rd_reg32(&ctrl
->r4tst
[0].rdsta
) & RDSTA_IFMASK
;
231 if ((status
&& status
!= JRSTA_SSRC_JUMP_HALT_CC
) ||
232 !(rdsta_val
& (1 << sh_idx
)))
236 dev_info(ctrldev
, "Instantiated RNG4 SH%d\n", sh_idx
);
237 /* Clear the contents before recreating the descriptor */
238 memset(desc
, 0x00, CAAM_CMD_SZ
* 7);
247 * deinstantiate_rng - builds and executes a descriptor on DECO0,
248 * which deinitializes the RNG block.
249 * @ctrldev - pointer to device
250 * @state_handle_mask - bitmask containing the instantiation status
251 * for the RNG4 state handles which exist in
252 * the RNG4 block: 1 if it's been instantiated
254 * Return: - 0 if no error occurred
255 * - -ENOMEM if there isn't enough memory to allocate the descriptor
256 * - -ENODEV if DECO0 couldn't be acquired
257 * - -EAGAIN if an error occurred when executing the descriptor
259 static int deinstantiate_rng(struct device
*ctrldev
, int state_handle_mask
)
264 desc
= kmalloc(CAAM_CMD_SZ
* 3, GFP_KERNEL
);
268 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
270 * If the corresponding bit is set, then it means the state
271 * handle was initialized by us, and thus it needs to be
272 * deintialized as well
274 if ((1 << sh_idx
) & state_handle_mask
) {
276 * Create the descriptor for deinstantating this state
279 build_deinstantiation_desc(desc
, sh_idx
);
281 /* Try to run it through DECO0 */
282 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
286 "Failed to deinstantiate RNG4 SH%d\n",
290 dev_info(ctrldev
, "Deinstantiated RNG4 SH%d\n", sh_idx
);
299 static int caam_remove(struct platform_device
*pdev
)
301 struct device
*ctrldev
;
302 struct caam_drv_private
*ctrlpriv
;
303 struct caam_ctrl __iomem
*ctrl
;
306 ctrldev
= &pdev
->dev
;
307 ctrlpriv
= dev_get_drvdata(ctrldev
);
308 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
310 /* Remove platform devices for JobRs */
311 for (ring
= 0; ring
< ctrlpriv
->total_jobrs
; ring
++) {
312 if (ctrlpriv
->jrpdev
[ring
])
313 of_device_unregister(ctrlpriv
->jrpdev
[ring
]);
316 /* De-initialize RNG state handles initialized by this driver. */
317 if (ctrlpriv
->rng4_sh_init
)
318 deinstantiate_rng(ctrldev
, ctrlpriv
->rng4_sh_init
);
320 /* Shut down debug views */
321 #ifdef CONFIG_DEBUG_FS
322 debugfs_remove_recursive(ctrlpriv
->dfs_root
);
325 /* Unmap controller region */
328 /* shut clocks off before finalizing shutdown */
329 clk_disable_unprepare(ctrlpriv
->caam_ipg
);
330 clk_disable_unprepare(ctrlpriv
->caam_mem
);
331 clk_disable_unprepare(ctrlpriv
->caam_aclk
);
332 clk_disable_unprepare(ctrlpriv
->caam_emi_slow
);
338 * kick_trng - sets the various parameters for enabling the initialization
339 * of the RNG4 block in CAAM
340 * @pdev - pointer to the platform device
341 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
343 static void kick_trng(struct platform_device
*pdev
, int ent_delay
)
345 struct device
*ctrldev
= &pdev
->dev
;
346 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
347 struct caam_ctrl __iomem
*ctrl
;
348 struct rng4tst __iomem
*r4tst
;
351 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
352 r4tst
= &ctrl
->r4tst
[0];
354 /* put RNG4 into program mode */
355 clrsetbits_32(&r4tst
->rtmctl
, 0, RTMCTL_PRGM
);
358 * Performance-wise, it does not make sense to
359 * set the delay to a value that is lower
360 * than the last one that worked (i.e. the state handles
361 * were instantiated properly. Thus, instead of wasting
362 * time trying to set the values controlling the sample
363 * frequency, the function simply returns.
365 val
= (rd_reg32(&r4tst
->rtsdctl
) & RTSDCTL_ENT_DLY_MASK
)
366 >> RTSDCTL_ENT_DLY_SHIFT
;
367 if (ent_delay
<= val
) {
368 /* put RNG4 into run mode */
369 clrsetbits_32(&r4tst
->rtmctl
, RTMCTL_PRGM
, 0);
373 val
= rd_reg32(&r4tst
->rtsdctl
);
374 val
= (val
& ~RTSDCTL_ENT_DLY_MASK
) |
375 (ent_delay
<< RTSDCTL_ENT_DLY_SHIFT
);
376 wr_reg32(&r4tst
->rtsdctl
, val
);
377 /* min. freq. count, equal to 1/4 of the entropy sample length */
378 wr_reg32(&r4tst
->rtfrqmin
, ent_delay
>> 2);
379 /* disable maximum frequency count */
380 wr_reg32(&r4tst
->rtfrqmax
, RTFRQMAX_DISABLE
);
381 /* read the control register */
382 val
= rd_reg32(&r4tst
->rtmctl
);
384 * select raw sampling in both entropy shifter
385 * and statistical checker
387 clrsetbits_32(&val
, 0, RTMCTL_SAMP_MODE_RAW_ES_SC
);
388 /* put RNG4 into run mode */
389 clrsetbits_32(&val
, RTMCTL_PRGM
, 0);
390 /* write back the control register */
391 wr_reg32(&r4tst
->rtmctl
, val
);
395 * caam_get_era() - Return the ERA of the SEC on SoC, based
396 * on "sec-era" propery in the DTS. This property is updated by u-boot.
398 int caam_get_era(void)
400 struct device_node
*caam_node
;
404 caam_node
= of_find_compatible_node(NULL
, NULL
, "fsl,sec-v4.0");
405 ret
= of_property_read_u32(caam_node
, "fsl,sec-era", &prop
);
406 of_node_put(caam_node
);
408 return ret
? -ENOTSUPP
: prop
;
410 EXPORT_SYMBOL(caam_get_era
);
412 #ifdef CONFIG_DEBUG_FS
413 static int caam_debugfs_u64_get(void *data
, u64
*val
)
415 *val
= caam64_to_cpu(*(u64
*)data
);
419 static int caam_debugfs_u32_get(void *data
, u64
*val
)
421 *val
= caam32_to_cpu(*(u32
*)data
);
425 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro
, caam_debugfs_u32_get
, NULL
, "%llu\n");
426 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro
, caam_debugfs_u64_get
, NULL
, "%llu\n");
429 /* Probe routine for CAAM top (controller) level */
430 static int caam_probe(struct platform_device
*pdev
)
432 int ret
, ring
, rspec
, gen_sk
, ent_delay
= RTSDCTL_ENT_DLY_MIN
;
435 struct device_node
*nprop
, *np
;
436 struct caam_ctrl __iomem
*ctrl
;
437 struct caam_drv_private
*ctrlpriv
;
439 #ifdef CONFIG_DEBUG_FS
440 struct caam_perfmon
*perfmon
;
442 u32 scfgr
, comp_params
;
445 int BLOCK_OFFSET
= 0;
447 ctrlpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*ctrlpriv
), GFP_KERNEL
);
452 dev_set_drvdata(dev
, ctrlpriv
);
453 ctrlpriv
->pdev
= pdev
;
454 nprop
= pdev
->dev
.of_node
;
456 /* Enable clocking */
457 clk
= caam_drv_identify_clk(&pdev
->dev
, "ipg");
461 "can't identify CAAM ipg clk: %d\n", ret
);
464 ctrlpriv
->caam_ipg
= clk
;
466 clk
= caam_drv_identify_clk(&pdev
->dev
, "mem");
470 "can't identify CAAM mem clk: %d\n", ret
);
473 ctrlpriv
->caam_mem
= clk
;
475 clk
= caam_drv_identify_clk(&pdev
->dev
, "aclk");
479 "can't identify CAAM aclk clk: %d\n", ret
);
482 ctrlpriv
->caam_aclk
= clk
;
484 clk
= caam_drv_identify_clk(&pdev
->dev
, "emi_slow");
488 "can't identify CAAM emi_slow clk: %d\n", ret
);
491 ctrlpriv
->caam_emi_slow
= clk
;
493 ret
= clk_prepare_enable(ctrlpriv
->caam_ipg
);
495 dev_err(&pdev
->dev
, "can't enable CAAM ipg clock: %d\n", ret
);
499 ret
= clk_prepare_enable(ctrlpriv
->caam_mem
);
501 dev_err(&pdev
->dev
, "can't enable CAAM secure mem clock: %d\n",
503 goto disable_caam_ipg
;
506 ret
= clk_prepare_enable(ctrlpriv
->caam_aclk
);
508 dev_err(&pdev
->dev
, "can't enable CAAM aclk clock: %d\n", ret
);
509 goto disable_caam_mem
;
512 ret
= clk_prepare_enable(ctrlpriv
->caam_emi_slow
);
514 dev_err(&pdev
->dev
, "can't enable CAAM emi slow clock: %d\n",
516 goto disable_caam_aclk
;
519 /* Get configuration properties from device tree */
520 /* First, get register page */
521 ctrl
= of_iomap(nprop
, 0);
523 dev_err(dev
, "caam: of_iomap() failed\n");
525 goto disable_caam_emi_slow
;
528 caam_little_end
= !(bool)(rd_reg32(&ctrl
->perfmon
.status
) &
529 (CSTA_PLEND
| CSTA_ALT_PLEND
));
531 /* Finding the page size for using the CTPR_MS register */
532 comp_params
= rd_reg32(&ctrl
->perfmon
.comp_parms_ms
);
533 pg_size
= (comp_params
& CTPR_MS_PG_SZ_MASK
) >> CTPR_MS_PG_SZ_SHIFT
;
535 /* Allocating the BLOCK_OFFSET based on the supported page size on
539 BLOCK_OFFSET
= PG_SIZE_4K
;
541 BLOCK_OFFSET
= PG_SIZE_64K
;
543 ctrlpriv
->ctrl
= (struct caam_ctrl __force
*)ctrl
;
544 ctrlpriv
->assure
= (struct caam_assurance __force
*)
546 BLOCK_OFFSET
* ASSURE_BLOCK_NUMBER
548 ctrlpriv
->deco
= (struct caam_deco __force
*)
550 BLOCK_OFFSET
* DECO_BLOCK_NUMBER
553 /* Get the IRQ of the controller (for security violations only) */
554 ctrlpriv
->secvio_irq
= irq_of_parse_and_map(nprop
, 0);
557 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
558 * long pointers in master configuration register
560 clrsetbits_32(&ctrl
->mcr
, MCFGR_AWCACHE_MASK
, MCFGR_AWCACHE_CACH
|
561 MCFGR_AWCACHE_BUFF
| MCFGR_WDENABLE
| MCFGR_LARGE_BURST
|
562 (sizeof(dma_addr_t
) == sizeof(u64
) ? MCFGR_LONG_PTR
: 0));
565 * Read the Compile Time paramters and SCFGR to determine
566 * if Virtualization is enabled for this platform
568 scfgr
= rd_reg32(&ctrl
->scfgr
);
570 ctrlpriv
->virt_en
= 0;
571 if (comp_params
& CTPR_MS_VIRT_EN_INCL
) {
572 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
573 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
575 if ((comp_params
& CTPR_MS_VIRT_EN_POR
) ||
576 (!(comp_params
& CTPR_MS_VIRT_EN_POR
) &&
577 (scfgr
& SCFGR_VIRT_EN
)))
578 ctrlpriv
->virt_en
= 1;
580 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
581 if (comp_params
& CTPR_MS_VIRT_EN_POR
)
582 ctrlpriv
->virt_en
= 1;
585 if (ctrlpriv
->virt_en
== 1)
586 clrsetbits_32(&ctrl
->jrstart
, 0, JRSTART_JR0_START
|
587 JRSTART_JR1_START
| JRSTART_JR2_START
|
590 if (sizeof(dma_addr_t
) == sizeof(u64
))
591 if (of_device_is_compatible(nprop
, "fsl,sec-v5.0"))
592 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(40));
594 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(36));
596 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
599 * Detect and enable JobRs
600 * First, find out how many ring spec'ed, allocate references
601 * for all, then go probe each one.
604 for_each_available_child_of_node(nprop
, np
)
605 if (of_device_is_compatible(np
, "fsl,sec-v4.0-job-ring") ||
606 of_device_is_compatible(np
, "fsl,sec4.0-job-ring"))
609 ctrlpriv
->jrpdev
= devm_kcalloc(&pdev
->dev
, rspec
,
610 sizeof(*ctrlpriv
->jrpdev
), GFP_KERNEL
);
611 if (ctrlpriv
->jrpdev
== NULL
) {
617 ctrlpriv
->total_jobrs
= 0;
618 for_each_available_child_of_node(nprop
, np
)
619 if (of_device_is_compatible(np
, "fsl,sec-v4.0-job-ring") ||
620 of_device_is_compatible(np
, "fsl,sec4.0-job-ring")) {
621 ctrlpriv
->jrpdev
[ring
] =
622 of_platform_device_create(np
, NULL
, dev
);
623 if (!ctrlpriv
->jrpdev
[ring
]) {
624 pr_warn("JR%d Platform device creation error\n",
628 ctrlpriv
->jr
[ring
] = (struct caam_job_ring __force
*)
630 (ring
+ JR_BLOCK_NUMBER
) *
633 ctrlpriv
->total_jobrs
++;
637 /* Check to see if QI present. If so, enable */
638 ctrlpriv
->qi_present
=
639 !!(rd_reg32(&ctrl
->perfmon
.comp_parms_ms
) &
641 if (ctrlpriv
->qi_present
) {
642 ctrlpriv
->qi
= (struct caam_queue_if __force
*)
644 BLOCK_OFFSET
* QI_BLOCK_NUMBER
646 /* This is all that's required to physically enable QI */
647 wr_reg32(&ctrlpriv
->qi
->qi_control_lo
, QICTL_DQEN
);
650 /* If no QI and no rings specified, quit and go home */
651 if ((!ctrlpriv
->qi_present
) && (!ctrlpriv
->total_jobrs
)) {
652 dev_err(dev
, "no queues configured, terminating\n");
657 cha_vid_ls
= rd_reg32(&ctrl
->perfmon
.cha_id_ls
);
660 * If SEC has RNG version >= 4 and RNG state handle has not been
661 * already instantiated, do RNG instantiation
663 if ((cha_vid_ls
& CHA_ID_LS_RNG_MASK
) >> CHA_ID_LS_RNG_SHIFT
>= 4) {
664 ctrlpriv
->rng4_sh_init
=
665 rd_reg32(&ctrl
->r4tst
[0].rdsta
);
667 * If the secure keys (TDKEK, JDKEK, TDSK), were already
668 * generated, signal this to the function that is instantiating
669 * the state handles. An error would occur if RNG4 attempts
670 * to regenerate these keys before the next POR.
672 gen_sk
= ctrlpriv
->rng4_sh_init
& RDSTA_SKVN
? 0 : 1;
673 ctrlpriv
->rng4_sh_init
&= RDSTA_IFMASK
;
676 rd_reg32(&ctrl
->r4tst
[0].rdsta
) &
679 * If either SH were instantiated by somebody else
680 * (e.g. u-boot) then it is assumed that the entropy
681 * parameters are properly set and thus the function
682 * setting these (kick_trng(...)) is skipped.
683 * Also, if a handle was instantiated, do not change
684 * the TRNG parameters.
686 if (!(ctrlpriv
->rng4_sh_init
|| inst_handles
)) {
688 "Entropy delay = %u\n",
690 kick_trng(pdev
, ent_delay
);
694 * if instantiate_rng(...) fails, the loop will rerun
695 * and the kick_trng(...) function will modfiy the
696 * upper and lower limits of the entropy sampling
697 * interval, leading to a sucessful initialization of
700 ret
= instantiate_rng(dev
, inst_handles
,
704 * if here, the loop will rerun,
705 * so don't hog the CPU
708 } while ((ret
== -EAGAIN
) && (ent_delay
< RTSDCTL_ENT_DLY_MAX
));
710 dev_err(dev
, "failed to instantiate RNG");
714 * Set handles init'ed by this module as the complement of the
715 * already initialized ones
717 ctrlpriv
->rng4_sh_init
= ~ctrlpriv
->rng4_sh_init
& RDSTA_IFMASK
;
719 /* Enable RDB bit so that RNG works faster */
720 clrsetbits_32(&ctrl
->scfgr
, 0, SCFGR_RDBENABLE
);
723 /* NOTE: RTIC detection ought to go here, around Si time */
725 caam_id
= (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ms
) << 32 |
726 (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ls
);
728 /* Report "alive" for developer to see */
729 dev_info(dev
, "device ID = 0x%016llx (Era %d)\n", caam_id
,
731 dev_info(dev
, "job rings = %d, qi = %d\n",
732 ctrlpriv
->total_jobrs
, ctrlpriv
->qi_present
);
734 #ifdef CONFIG_DEBUG_FS
736 * FIXME: needs better naming distinction, as some amalgamation of
737 * "caam" and nprop->full_name. The OF name isn't distinctive,
738 * but does separate instances
740 perfmon
= (struct caam_perfmon __force
*)&ctrl
->perfmon
;
742 ctrlpriv
->dfs_root
= debugfs_create_dir(dev_name(dev
), NULL
);
743 ctrlpriv
->ctl
= debugfs_create_dir("ctl", ctrlpriv
->dfs_root
);
745 /* Controller-level - performance monitor counters */
747 ctrlpriv
->ctl_rq_dequeued
=
748 debugfs_create_file("rq_dequeued",
749 S_IRUSR
| S_IRGRP
| S_IROTH
,
750 ctrlpriv
->ctl
, &perfmon
->req_dequeued
,
752 ctrlpriv
->ctl_ob_enc_req
=
753 debugfs_create_file("ob_rq_encrypted",
754 S_IRUSR
| S_IRGRP
| S_IROTH
,
755 ctrlpriv
->ctl
, &perfmon
->ob_enc_req
,
757 ctrlpriv
->ctl_ib_dec_req
=
758 debugfs_create_file("ib_rq_decrypted",
759 S_IRUSR
| S_IRGRP
| S_IROTH
,
760 ctrlpriv
->ctl
, &perfmon
->ib_dec_req
,
762 ctrlpriv
->ctl_ob_enc_bytes
=
763 debugfs_create_file("ob_bytes_encrypted",
764 S_IRUSR
| S_IRGRP
| S_IROTH
,
765 ctrlpriv
->ctl
, &perfmon
->ob_enc_bytes
,
767 ctrlpriv
->ctl_ob_prot_bytes
=
768 debugfs_create_file("ob_bytes_protected",
769 S_IRUSR
| S_IRGRP
| S_IROTH
,
770 ctrlpriv
->ctl
, &perfmon
->ob_prot_bytes
,
772 ctrlpriv
->ctl_ib_dec_bytes
=
773 debugfs_create_file("ib_bytes_decrypted",
774 S_IRUSR
| S_IRGRP
| S_IROTH
,
775 ctrlpriv
->ctl
, &perfmon
->ib_dec_bytes
,
777 ctrlpriv
->ctl_ib_valid_bytes
=
778 debugfs_create_file("ib_bytes_validated",
779 S_IRUSR
| S_IRGRP
| S_IROTH
,
780 ctrlpriv
->ctl
, &perfmon
->ib_valid_bytes
,
783 /* Controller level - global status values */
784 ctrlpriv
->ctl_faultaddr
=
785 debugfs_create_file("fault_addr",
786 S_IRUSR
| S_IRGRP
| S_IROTH
,
787 ctrlpriv
->ctl
, &perfmon
->faultaddr
,
789 ctrlpriv
->ctl_faultdetail
=
790 debugfs_create_file("fault_detail",
791 S_IRUSR
| S_IRGRP
| S_IROTH
,
792 ctrlpriv
->ctl
, &perfmon
->faultdetail
,
794 ctrlpriv
->ctl_faultstatus
=
795 debugfs_create_file("fault_status",
796 S_IRUSR
| S_IRGRP
| S_IROTH
,
797 ctrlpriv
->ctl
, &perfmon
->status
,
800 /* Internal covering keys (useful in non-secure mode only) */
801 ctrlpriv
->ctl_kek_wrap
.data
= &ctrlpriv
->ctrl
->kek
[0];
802 ctrlpriv
->ctl_kek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
803 ctrlpriv
->ctl_kek
= debugfs_create_blob("kek",
807 &ctrlpriv
->ctl_kek_wrap
);
809 ctrlpriv
->ctl_tkek_wrap
.data
= &ctrlpriv
->ctrl
->tkek
[0];
810 ctrlpriv
->ctl_tkek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
811 ctrlpriv
->ctl_tkek
= debugfs_create_blob("tkek",
815 &ctrlpriv
->ctl_tkek_wrap
);
817 ctrlpriv
->ctl_tdsk_wrap
.data
= &ctrlpriv
->ctrl
->tdsk
[0];
818 ctrlpriv
->ctl_tdsk_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
819 ctrlpriv
->ctl_tdsk
= debugfs_create_blob("tdsk",
823 &ctrlpriv
->ctl_tdsk_wrap
);
831 disable_caam_emi_slow
:
832 clk_disable_unprepare(ctrlpriv
->caam_emi_slow
);
834 clk_disable_unprepare(ctrlpriv
->caam_aclk
);
836 clk_disable_unprepare(ctrlpriv
->caam_mem
);
838 clk_disable_unprepare(ctrlpriv
->caam_ipg
);
842 static struct of_device_id caam_match
[] = {
844 .compatible
= "fsl,sec-v4.0",
847 .compatible
= "fsl,sec4.0",
851 MODULE_DEVICE_TABLE(of
, caam_match
);
853 static struct platform_driver caam_driver
= {
856 .of_match_table
= caam_match
,
859 .remove
= caam_remove
,
862 module_platform_driver(caam_driver
);
864 MODULE_LICENSE("GPL");
865 MODULE_DESCRIPTION("FSL CAAM request backend");
866 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");