drivers/crypto/cavium/nitrox/nitrox_dev.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __NITROX_DEV_H
   3 #define __NITROX_DEV_H
   4
   5 #include <linux/dma-mapping.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/pci.h>
   8
   9 #define VERSION_LEN 32
  10
  11 struct nitrox_cmdq {
  12         /* command queue lock */
  13         spinlock_t cmdq_lock;
  14         /* response list lock */
  15         spinlock_t response_lock;
  16         /* backlog list lock */
  17         spinlock_t backlog_lock;
  18
  19         /* request submitted to chip, in progress */
  20         struct list_head response_head;
  21         /* hw queue full, hold in backlog list */
  22         struct list_head backlog_head;
  23
  24         /* doorbell address */
  25         u8 __iomem *dbell_csr_addr;
  26         /* base address of the queue */
  27         u8 *head;
  28
  29         struct nitrox_device *ndev;
  30         /* flush pending backlog commands */
  31         struct work_struct backlog_qflush;
  32
  33         /* requests posted waiting for completion */
  34         atomic_t pending_count;
  35         /* requests in backlog queues */
  36         atomic_t backlog_count;
  37
  38         /* command size 32B/64B */
  39         u8 instr_size;
  40         u8 qno;
  41         u32 qsize;
  42
  43         /* unaligned addresses */
  44         u8 *head_unaligned;
  45         dma_addr_t dma_unaligned;
  46         /* dma address of the base */
  47         dma_addr_t dma;
  48 };
  49
  50 struct nitrox_hw {
  51         /* firmware version */
  52         char fw_name[VERSION_LEN];
  53
  54         u16 vendor_id;
  55         u16 device_id;
  56         u8 revision_id;
  57
  58         /* CNN55XX cores */
  59         u8 se_cores;
  60         u8 ae_cores;
  61         u8 zip_cores;
  62 };
  63
  64 #define MAX_MSIX_VECTOR_NAME    20
  65 /**
  66  * vectors for queues (64 AE, 64 SE and 64 ZIP) and
  67  * error condition/mailbox.
  68  */
  69 #define MAX_MSIX_VECTORS        192
  70
  71 struct nitrox_msix {
  72         struct msix_entry *entries;
  73         char **names;
  74         DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS);
  75         u32 nr_entries;
  76 };
  77
  78 struct bh_data {
  79         /* slc port completion count address */
  80         u8 __iomem *completion_cnt_csr_addr;
  81
  82         struct nitrox_cmdq *cmdq;
  83         struct tasklet_struct resp_handler;
  84 };
  85
  86 struct nitrox_bh {
  87         struct bh_data *slc;
  88 };
  89
  90 /* NITROX-5 driver state */
  91 #define NITROX_UCODE_LOADED     0
  92 #define NITROX_READY            1
  93
  94 /* command queue size */
  95 #define DEFAULT_CMD_QLEN 2048
  96 /* command timeout in milliseconds */
  97 #define CMD_TIMEOUT 2000
  98
  99 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
 100 #define PF_MODE 0
 101
 102 #define NITROX_CSR_ADDR(ndev, offset) \
 103         ((ndev)->bar_addr + (offset))
 104
 105 /**
 106  * struct nitrox_device - NITROX Device Information.
 107  * @list: pointer to linked list of devices
 108  * @bar_addr: iomap address
 109  * @pdev: PCI device information
 110  * @status: NITROX status
 111  * @timeout: Request timeout in jiffies
 112  * @refcnt: Device usage count
 113  * @idx: device index (0..N)
 114  * @node: NUMA node id attached
 115  * @qlen: Command queue length
 116  * @nr_queues: Number of command queues
 117  * @ctx_pool: DMA pool for crypto context
 118  * @pkt_cmdqs: SE Command queues
 119  * @msix: MSI-X information
 120  * @bh: post processing work
 121  * @hw: hardware information
 122  * @debugfs_dir: debugfs directory
 123  */
 124 struct nitrox_device {
 125         struct list_head list;
 126
 127         u8 __iomem *bar_addr;
 128         struct pci_dev *pdev;
 129
 130         unsigned long status;
 131         unsigned long timeout;
 132         refcount_t refcnt;
 133
 134         u8 idx;
 135         int node;
 136         u16 qlen;
 137         u16 nr_queues;
 138
 139         struct dma_pool *ctx_pool;
 140         struct nitrox_cmdq *pkt_cmdqs;
 141
 142         struct nitrox_msix msix;
 143         struct nitrox_bh bh;
 144
 145         struct nitrox_hw hw;
 146 #if IS_ENABLED(CONFIG_DEBUG_FS)
 147         struct dentry *debugfs_dir;
 148 #endif
 149 };
 150
 151 /**
 152  * nitrox_read_csr - Read from device register
 153  * @ndev: NITROX device
 154  * @offset: offset of the register to read
 155  *
 156  * Returns: value read
 157  */
 158 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
 159 {
 160         return readq(ndev->bar_addr + offset);
 161 }
 162
 163 /**
 164  * nitrox_write_csr - Write to device register
 165  * @ndev: NITROX device
 166  * @offset: offset of the register to write
 167  * @value: value to write
 168  */
 169 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
 170                                     u64 value)
 171 {
 172         writeq(value, (ndev->bar_addr + offset));
 173 }
 174
 175 static inline int nitrox_ready(struct nitrox_device *ndev)
 176 {
 177         return test_bit(NITROX_READY, &ndev->status);
 178 }
 179
 180 #endif /* __NITROX_DEV_H */