2 * AMD Cryptographic Coprocessor (CCP) driver
4 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
6 * Author: Tom Lendacky <thomas.lendacky@amd.com>
7 * Author: Gary R Hook <gary.hook@amd.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
17 #include <linux/device.h>
18 #include <linux/pci.h>
19 #include <linux/spinlock.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/wait.h>
23 #include <linux/dmapool.h>
24 #include <linux/hw_random.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqreturn.h>
28 #include <linux/dmaengine.h>
30 #define MAX_CCP_NAME_LEN 16
31 #define MAX_DMAPOOL_NAME_LEN 32
33 #define MAX_HW_QUEUES 5
34 #define MAX_CMD_QLEN 100
36 #define TRNG_RETRIES 10
38 #define CACHE_NONE 0x00
39 #define CACHE_WB_NO_ALLOC 0xb7
41 /****** Register Mappings ******/
42 #define Q_MASK_REG 0x000
43 #define TRNG_OUT_REG 0x00c
44 #define IRQ_MASK_REG 0x040
45 #define IRQ_STATUS_REG 0x200
47 #define DEL_CMD_Q_JOB 0x124
48 #define DEL_Q_ACTIVE 0x00000200
49 #define DEL_Q_ID_SHIFT 6
51 #define CMD_REQ0 0x180
52 #define CMD_REQ_INCR 0x04
54 #define CMD_Q_STATUS_BASE 0x210
55 #define CMD_Q_INT_STATUS_BASE 0x214
56 #define CMD_Q_STATUS_INCR 0x20
58 #define CMD_Q_CACHE_BASE 0x228
59 #define CMD_Q_CACHE_INC 0x20
61 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
62 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
64 /* ------------------------ CCP Version 5 Specifics ------------------------ */
65 #define CMD5_QUEUE_MASK_OFFSET 0x00
66 #define CMD5_QUEUE_PRIO_OFFSET 0x04
67 #define CMD5_REQID_CONFIG_OFFSET 0x08
68 #define CMD5_CMD_TIMEOUT_OFFSET 0x10
69 #define LSB_PUBLIC_MASK_LO_OFFSET 0x18
70 #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
71 #define LSB_PRIVATE_MASK_LO_OFFSET 0x20
72 #define LSB_PRIVATE_MASK_HI_OFFSET 0x24
73 #define CMD5_PSP_CCP_VERSION 0x100
75 #define CMD5_Q_CONTROL_BASE 0x0000
76 #define CMD5_Q_TAIL_LO_BASE 0x0004
77 #define CMD5_Q_HEAD_LO_BASE 0x0008
78 #define CMD5_Q_INT_ENABLE_BASE 0x000C
79 #define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
81 #define CMD5_Q_STATUS_BASE 0x0100
82 #define CMD5_Q_INT_STATUS_BASE 0x0104
83 #define CMD5_Q_DMA_STATUS_BASE 0x0108
84 #define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
85 #define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
86 #define CMD5_Q_ABORT_BASE 0x0114
87 #define CMD5_Q_AX_CACHE_BASE 0x0118
89 #define CMD5_CONFIG_0_OFFSET 0x6000
90 #define CMD5_TRNG_CTL_OFFSET 0x6008
91 #define CMD5_AES_MASK_OFFSET 0x6010
92 #define CMD5_CLK_GATE_CTL_OFFSET 0x603C
94 /* Address offset between two virtual queue registers */
95 #define CMD5_Q_STATUS_INCR 0x1000
98 #define CMD5_Q_RUN 0x1
99 #define CMD5_Q_HALT 0x2
100 #define CMD5_Q_MEM_LOCATION 0x4
101 #define CMD5_Q_SIZE 0x1F
102 #define CMD5_Q_SHIFT 3
103 #define COMMANDS_PER_QUEUE 16
104 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
106 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
107 #define Q_DESC_SIZE sizeof(struct ccp5_desc)
108 #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
110 #define INT_COMPLETION 0x1
111 #define INT_ERROR 0x2
112 #define INT_QUEUE_STOPPED 0x4
113 #define INT_EMPTY_QUEUE 0x8
114 #define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
116 #define LSB_REGION_WIDTH 5
117 #define MAX_LSB_CNT 8
120 #define LSB_ITEM_SIZE 32
121 #define PLSB_MAP_SIZE (LSB_SIZE)
122 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
124 #define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
126 /* ------------------------ CCP Version 3 Specifics ------------------------ */
127 #define REQ0_WAIT_FOR_WRITE 0x00000004
128 #define REQ0_INT_ON_COMPLETE 0x00000002
129 #define REQ0_STOP_ON_COMPLETE 0x00000001
131 #define REQ0_CMD_Q_SHIFT 9
132 #define REQ0_JOBID_SHIFT 3
134 /****** REQ1 Related Values ******/
135 #define REQ1_PROTECT_SHIFT 27
136 #define REQ1_ENGINE_SHIFT 23
137 #define REQ1_KEY_KSB_SHIFT 2
139 #define REQ1_EOM 0x00000002
140 #define REQ1_INIT 0x00000001
142 /* AES Related Values */
143 #define REQ1_AES_TYPE_SHIFT 21
144 #define REQ1_AES_MODE_SHIFT 18
145 #define REQ1_AES_ACTION_SHIFT 17
146 #define REQ1_AES_CFB_SIZE_SHIFT 10
148 /* XTS-AES Related Values */
149 #define REQ1_XTS_AES_SIZE_SHIFT 10
151 /* SHA Related Values */
152 #define REQ1_SHA_TYPE_SHIFT 21
154 /* RSA Related Values */
155 #define REQ1_RSA_MOD_SIZE_SHIFT 10
157 /* Pass-Through Related Values */
158 #define REQ1_PT_BW_SHIFT 12
159 #define REQ1_PT_BS_SHIFT 10
161 /* ECC Related Values */
162 #define REQ1_ECC_AFFINE_CONVERT 0x00200000
163 #define REQ1_ECC_FUNCTION_SHIFT 18
165 /****** REQ4 Related Values ******/
166 #define REQ4_KSB_SHIFT 18
167 #define REQ4_MEMTYPE_SHIFT 16
169 /****** REQ6 Related Values ******/
170 #define REQ6_MEMTYPE_SHIFT 16
172 /****** Key Storage Block ******/
175 #define KSB_COUNT (KSB_END - KSB_START + 1)
176 #define CCP_SB_BITS 256
178 #define CCP_JOBID_MASK 0x0000003f
180 /* ------------------------ General CCP Defines ------------------------ */
182 #define CCP_DMA_DFLT 0x0
183 #define CCP_DMA_PRIV 0x1
184 #define CCP_DMA_PUB 0x2
186 #define CCP_DMAPOOL_MAX_SIZE 64
187 #define CCP_DMAPOOL_ALIGN BIT(5)
189 #define CCP_REVERSE_BUF_SIZE 64
191 #define CCP_AES_KEY_SB_COUNT 1
192 #define CCP_AES_CTX_SB_COUNT 1
194 #define CCP_XTS_AES_KEY_SB_COUNT 1
195 #define CCP5_XTS_AES_KEY_SB_COUNT 2
196 #define CCP_XTS_AES_CTX_SB_COUNT 1
198 #define CCP_DES3_KEY_SB_COUNT 1
199 #define CCP_DES3_CTX_SB_COUNT 1
201 #define CCP_SHA_SB_COUNT 1
203 #define CCP_RSA_MAX_WIDTH 4096
205 #define CCP_PASSTHRU_BLOCKSIZE 256
206 #define CCP_PASSTHRU_MASKSIZE 32
207 #define CCP_PASSTHRU_SB_COUNT 1
209 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
210 #define CCP_ECC_MAX_OPERANDS 6
211 #define CCP_ECC_MAX_OUTPUTS 3
212 #define CCP_ECC_SRC_BUF_SIZE 448
213 #define CCP_ECC_DST_BUF_SIZE 192
214 #define CCP_ECC_OPERAND_SIZE 64
215 #define CCP_ECC_OUTPUT_SIZE 64
216 #define CCP_ECC_RESULT_OFFSET 60
217 #define CCP_ECC_RESULT_SUCCESS 0x0001
219 #define CCP_SB_BYTES 32
227 struct list_head entry
;
229 struct ccp_cmd ccp_cmd
;
232 struct ccp_dma_desc
{
233 struct list_head entry
;
235 struct ccp_device
*ccp
;
237 struct list_head pending
;
238 struct list_head active
;
240 enum dma_status status
;
241 struct dma_async_tx_descriptor tx_desc
;
245 struct ccp_dma_chan
{
246 struct ccp_device
*ccp
;
249 struct list_head created
;
250 struct list_head pending
;
251 struct list_head active
;
252 struct list_head complete
;
254 struct tasklet_struct cleanup_tasklet
;
256 enum dma_status status
;
257 struct dma_chan dma_chan
;
260 struct ccp_cmd_queue
{
261 struct ccp_device
*ccp
;
263 /* Queue identifier */
267 struct dma_pool
*dma_pool
;
269 /* Queue base address (not neccessarily aligned)*/
270 struct ccp5_desc
*qbase
;
272 /* Aligned queue start address (per requirement) */
273 struct mutex q_mutex ____cacheline_aligned
;
276 /* Version 5 has different requirements for queue memory */
278 dma_addr_t qbase_dma
;
279 dma_addr_t qdma_tail
;
281 /* Per-queue reserved storage block(s) */
285 /* Bitmap of LSBs that can be accessed by this queue */
286 DECLARE_BITMAP(lsbmask
, MAX_LSB_CNT
);
287 /* Private LSB that is assigned to this queue, or -1 if none.
288 * Bitmap for my private LSB, unused otherwise
291 DECLARE_BITMAP(lsbmap
, PLSB_MAP_SIZE
);
293 /* Queue processing thread */
294 struct task_struct
*kthread
;
296 unsigned int suspended
;
298 /* Number of free command slots available */
299 unsigned int free_slots
;
301 /* Interrupt masks */
305 /* Register addresses for queue */
306 void __iomem
*reg_control
;
307 void __iomem
*reg_tail_lo
;
308 void __iomem
*reg_head_lo
;
309 void __iomem
*reg_int_enable
;
310 void __iomem
*reg_interrupt_status
;
311 void __iomem
*reg_status
;
312 void __iomem
*reg_int_status
;
313 void __iomem
*reg_dma_status
;
314 void __iomem
*reg_dma_read_status
;
315 void __iomem
*reg_dma_write_status
;
316 u32 qcontrol
; /* Cached control register */
318 /* Status values from job */
324 /* Interrupt wait queue */
325 wait_queue_head_t int_queue
;
326 unsigned int int_rcvd
;
328 /* Per-queue Statistics */
329 unsigned long total_ops
;
330 unsigned long total_aes_ops
;
331 unsigned long total_xts_aes_ops
;
332 unsigned long total_3des_ops
;
333 unsigned long total_sha_ops
;
334 unsigned long total_rsa_ops
;
335 unsigned long total_pt_ops
;
336 unsigned long total_ecc_ops
;
337 } ____cacheline_aligned
;
340 struct list_head entry
;
342 struct ccp_vdata
*vdata
;
344 char name
[MAX_CCP_NAME_LEN
];
345 char rngname
[MAX_CCP_NAME_LEN
];
349 /* Bus specific device information
352 int (*get_irq
)(struct ccp_device
*ccp
);
353 void (*free_irq
)(struct ccp_device
*ccp
);
357 struct tasklet_struct irq_tasklet
;
359 /* I/O area used for device communication. The register mapping
360 * starts at an offset into the mapped bar.
361 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
362 * need to be protected while a command queue thread is accessing
365 struct mutex req_mutex ____cacheline_aligned
;
366 void __iomem
*io_map
;
367 void __iomem
*io_regs
;
369 /* Master lists that all cmds are queued on. Because there can be
370 * more than one CCP command queue that can process a cmd a separate
371 * backlog list is neeeded so that the backlog completion call
372 * completes before the cmd is available for execution.
374 spinlock_t cmd_lock ____cacheline_aligned
;
375 unsigned int cmd_count
;
376 struct list_head cmd
;
377 struct list_head backlog
;
379 /* The command queues. These represent the queues available on the
380 * CCP that are available for processing cmds
382 struct ccp_cmd_queue cmd_q
[MAX_HW_QUEUES
];
383 unsigned int cmd_q_count
;
385 /* Support for the CCP True RNG
388 unsigned int hwrng_retries
;
390 /* Support for the CCP DMA capabilities
392 struct dma_device dma_dev
;
393 struct ccp_dma_chan
*ccp_dma_chan
;
394 struct kmem_cache
*dma_cmd_cache
;
395 struct kmem_cache
*dma_desc_cache
;
397 /* A counter used to generate job-ids for cmds submitted to the CCP
399 atomic_t current_id ____cacheline_aligned
;
401 /* The v3 CCP uses key storage blocks (SB) to maintain context for
402 * certain operations. To prevent multiple cmds from using the same
403 * SB range a command queue reserves an SB range for the duration of
404 * the cmd. Each queue, will however, reserve 2 SB blocks for
405 * operations that only require single SB entries (eg. AES context/iv
406 * and key) in order to avoid allocation contention. This will reserve
407 * at most 10 SB entries, leaving 40 SB entries available for dynamic
410 * The v5 CCP Local Storage Block (LSB) is broken up into 8
411 * memrory ranges, each of which can be enabled for access by one
412 * or more queues. Device initialization takes this into account,
413 * and attempts to assign one region for exclusive use by each
414 * available queue; the rest are then aggregated as "public" use.
415 * If there are fewer regions than queues, all regions are shared
416 * amongst all queues.
418 struct mutex sb_mutex ____cacheline_aligned
;
419 DECLARE_BITMAP(sb
, KSB_COUNT
);
420 wait_queue_head_t sb_queue
;
421 unsigned int sb_avail
;
422 unsigned int sb_count
;
425 /* Bitmap of shared LSBs, if any */
426 DECLARE_BITMAP(lsbmap
, SLSB_MAP_SIZE
);
428 /* Suspend support */
429 unsigned int suspending
;
430 wait_queue_head_t suspend_queue
;
432 /* DMA caching attribute support */
433 unsigned int axcache
;
435 /* Device Statistics */
436 unsigned long total_interrupts
;
439 struct dentry
*debugfs_instance
;
443 CCP_MEMTYPE_SYSTEM
= 0,
448 #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
451 struct ccp_dma_info
{
455 enum dma_data_direction dir
;
456 } __packed
__aligned(4);
458 struct ccp_dm_workarea
{
460 struct dma_pool
*dma_pool
;
463 struct ccp_dma_info dma
;
467 struct ccp_sg_workarea
{
468 struct scatterlist
*sg
;
470 unsigned int sg_used
;
472 struct scatterlist
*dma_sg
;
473 struct device
*dma_dev
;
474 unsigned int dma_count
;
475 enum dma_data_direction dma_dir
;
481 struct ccp_sg_workarea sg_wa
;
482 struct ccp_dm_workarea dm_wa
;
486 enum ccp_memtype type
;
488 struct ccp_dma_info dma
;
494 enum ccp_aes_type type
;
495 enum ccp_aes_mode mode
;
496 enum ccp_aes_action action
;
500 struct ccp_xts_aes_op
{
501 enum ccp_aes_type type
;
502 enum ccp_aes_action action
;
503 enum ccp_xts_aes_unit_size unit_size
;
507 enum ccp_des3_type type
;
508 enum ccp_des3_mode mode
;
509 enum ccp_des3_action action
;
513 enum ccp_sha_type type
;
522 struct ccp_passthru_op
{
523 enum ccp_passthru_bitwise bit_mod
;
524 enum ccp_passthru_byteswap byte_swap
;
528 enum ccp_ecc_function function
;
532 struct ccp_cmd_queue
*cmd_q
;
547 struct ccp_aes_op aes
;
548 struct ccp_xts_aes_op xts
;
549 struct ccp_des3_op des3
;
550 struct ccp_sha_op sha
;
551 struct ccp_rsa_op rsa
;
552 struct ccp_passthru_op passthru
;
553 struct ccp_ecc_op ecc
;
557 static inline u32
ccp_addr_lo(struct ccp_dma_info
*info
)
559 return lower_32_bits(info
->address
+ info
->offset
);
562 static inline u32
ccp_addr_hi(struct ccp_dma_info
*info
)
564 return upper_32_bits(info
->address
+ info
->offset
) & 0x0000ffff;
568 * descriptor for version 5 CPP commands
570 * word 0: function; engine; control bits
571 * word 1: length of source data
572 * word 2: low 32 bits of source pointer
573 * word 3: upper 16 bits of source pointer; source memory type
574 * word 4: low 32 bits of destination pointer
575 * word 5: upper 16 bits of destination pointer; destination memory type
576 * word 6: low 32 bits of key pointer
577 * word 7: upper 16 bits of key pointer; key memory type
582 unsigned int rsvd1
:1;
584 unsigned int eom
:1; /* AES/SHA only */
585 unsigned int function
:15;
586 unsigned int engine
:4;
588 unsigned int rsvd2
:7;
592 unsigned int src_hi
:16;
593 unsigned int src_mem
:2;
594 unsigned int lsb_cxt_id
:8;
595 unsigned int rsvd1
:5;
596 unsigned int fixed
:1;
600 __le32 dst_lo
; /* NON-SHA */
601 __le32 sha_len_lo
; /* SHA */
606 unsigned int dst_hi
:16;
607 unsigned int dst_mem
:2;
608 unsigned int rsvd1
:13;
609 unsigned int fixed
:1;
615 unsigned int key_hi
:16;
616 unsigned int key_mem
:2;
617 unsigned int rsvd1
:14;
631 int ccp_pci_init(void);
632 void ccp_pci_exit(void);
634 int ccp_platform_init(void);
635 void ccp_platform_exit(void);
637 void ccp_add_device(struct ccp_device
*ccp
);
638 void ccp_del_device(struct ccp_device
*ccp
);
640 extern void ccp_log_error(struct ccp_device
*, int);
642 struct ccp_device
*ccp_alloc_struct(struct device
*dev
);
643 bool ccp_queues_suspended(struct ccp_device
*ccp
);
644 int ccp_cmd_queue_thread(void *data
);
645 int ccp_trng_read(struct hwrng
*rng
, void *data
, size_t max
, bool wait
);
647 int ccp_run_cmd(struct ccp_cmd_queue
*cmd_q
, struct ccp_cmd
*cmd
);
649 int ccp_register_rng(struct ccp_device
*ccp
);
650 void ccp_unregister_rng(struct ccp_device
*ccp
);
651 int ccp_dmaengine_register(struct ccp_device
*ccp
);
652 void ccp_dmaengine_unregister(struct ccp_device
*ccp
);
654 void ccp5_debugfs_setup(struct ccp_device
*ccp
);
655 void ccp5_debugfs_destroy(void);
657 /* Structure for computation functions that are device-specific */
659 int (*aes
)(struct ccp_op
*);
660 int (*xts_aes
)(struct ccp_op
*);
661 int (*des3
)(struct ccp_op
*);
662 int (*sha
)(struct ccp_op
*);
663 int (*rsa
)(struct ccp_op
*);
664 int (*passthru
)(struct ccp_op
*);
665 int (*ecc
)(struct ccp_op
*);
666 u32 (*sballoc
)(struct ccp_cmd_queue
*, unsigned int);
667 void (*sbfree
)(struct ccp_cmd_queue
*, unsigned int, unsigned int);
668 unsigned int (*get_free_slots
)(struct ccp_cmd_queue
*);
669 int (*init
)(struct ccp_device
*);
670 void (*destroy
)(struct ccp_device
*);
671 irqreturn_t (*irqhandler
)(int, void *);
674 /* Structure to hold CCP version-specific values */
676 const unsigned int version
;
677 const unsigned int dma_chan_attr
;
678 void (*setup
)(struct ccp_device
*);
679 const struct ccp_actions
*perform
;
680 const unsigned int bar
;
681 const unsigned int offset
;
684 extern const struct ccp_vdata ccpv3
;
685 extern const struct ccp_vdata ccpv5a
;
686 extern const struct ccp_vdata ccpv5b
;