drivers/crypto/ccp/ccp-dev.h

   1 /*
   2  * AMD Cryptographic Coprocessor (CCP) driver
   3  *
   4  * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
   5  *
   6  * Author: Tom Lendacky <thomas.lendacky@amd.com>
   7  * Author: Gary R Hook <gary.hook@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef __CCP_DEV_H__
  15 #define __CCP_DEV_H__
  16
  17 #include <linux/device.h>
  18 #include <linux/pci.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/mutex.h>
  21 #include <linux/list.h>
  22 #include <linux/wait.h>
  23 #include <linux/dmapool.h>
  24 #include <linux/hw_random.h>
  25 #include <linux/bitops.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irqreturn.h>
  28 #include <linux/dmaengine.h>
  29
  30 #define MAX_CCP_NAME_LEN                16
  31 #define MAX_DMAPOOL_NAME_LEN            32
  32
  33 #define MAX_HW_QUEUES                   5
  34 #define MAX_CMD_QLEN                    100
  35
  36 #define TRNG_RETRIES                    10
  37
  38 #define CACHE_NONE                      0x00
  39 #define CACHE_WB_NO_ALLOC               0xb7
  40
  41 /****** Register Mappings ******/
  42 #define Q_MASK_REG                      0x000
  43 #define TRNG_OUT_REG                    0x00c
  44 #define IRQ_MASK_REG                    0x040
  45 #define IRQ_STATUS_REG                  0x200
  46
  47 #define DEL_CMD_Q_JOB                   0x124
  48 #define DEL_Q_ACTIVE                    0x00000200
  49 #define DEL_Q_ID_SHIFT                  6
  50
  51 #define CMD_REQ0                        0x180
  52 #define CMD_REQ_INCR                    0x04
  53
  54 #define CMD_Q_STATUS_BASE               0x210
  55 #define CMD_Q_INT_STATUS_BASE           0x214
  56 #define CMD_Q_STATUS_INCR               0x20
  57
  58 #define CMD_Q_CACHE_BASE                0x228
  59 #define CMD_Q_CACHE_INC                 0x20
  60
  61 #define CMD_Q_ERROR(__qs)               ((__qs) & 0x0000003f)
  62 #define CMD_Q_DEPTH(__qs)               (((__qs) >> 12) & 0x0000000f)
  63
  64 /* ------------------------ CCP Version 5 Specifics ------------------------ */
  65 #define CMD5_QUEUE_MASK_OFFSET          0x00
  66 #define CMD5_QUEUE_PRIO_OFFSET          0x04
  67 #define CMD5_REQID_CONFIG_OFFSET        0x08
  68 #define CMD5_CMD_TIMEOUT_OFFSET         0x10
  69 #define LSB_PUBLIC_MASK_LO_OFFSET       0x18
  70 #define LSB_PUBLIC_MASK_HI_OFFSET       0x1C
  71 #define LSB_PRIVATE_MASK_LO_OFFSET      0x20
  72 #define LSB_PRIVATE_MASK_HI_OFFSET      0x24
  73
  74 #define CMD5_Q_CONTROL_BASE             0x0000
  75 #define CMD5_Q_TAIL_LO_BASE             0x0004
  76 #define CMD5_Q_HEAD_LO_BASE             0x0008
  77 #define CMD5_Q_INT_ENABLE_BASE          0x000C
  78 #define CMD5_Q_INTERRUPT_STATUS_BASE    0x0010
  79
  80 #define CMD5_Q_STATUS_BASE              0x0100
  81 #define CMD5_Q_INT_STATUS_BASE          0x0104
  82 #define CMD5_Q_DMA_STATUS_BASE          0x0108
  83 #define CMD5_Q_DMA_READ_STATUS_BASE     0x010C
  84 #define CMD5_Q_DMA_WRITE_STATUS_BASE    0x0110
  85 #define CMD5_Q_ABORT_BASE               0x0114
  86 #define CMD5_Q_AX_CACHE_BASE            0x0118
  87
  88 #define CMD5_CONFIG_0_OFFSET            0x6000
  89 #define CMD5_TRNG_CTL_OFFSET            0x6008
  90 #define CMD5_AES_MASK_OFFSET            0x6010
  91 #define CMD5_CLK_GATE_CTL_OFFSET        0x603C
  92
  93 /* Address offset between two virtual queue registers */
  94 #define CMD5_Q_STATUS_INCR              0x1000
  95
  96 /* Bit masks */
  97 #define CMD5_Q_RUN                      0x1
  98 #define CMD5_Q_HALT                     0x2
  99 #define CMD5_Q_MEM_LOCATION             0x4
 100 #define CMD5_Q_SIZE                     0x1F
 101 #define CMD5_Q_SHIFT                    3
 102 #define COMMANDS_PER_QUEUE              16
 103 #define QUEUE_SIZE_VAL                  ((ffs(COMMANDS_PER_QUEUE) - 2) & \
 104                                           CMD5_Q_SIZE)
 105 #define Q_PTR_MASK                      (2 << (QUEUE_SIZE_VAL + 5) - 1)
 106 #define Q_DESC_SIZE                     sizeof(struct ccp5_desc)
 107 #define Q_SIZE(n)                       (COMMANDS_PER_QUEUE*(n))
 108
 109 #define INT_COMPLETION                  0x1
 110 #define INT_ERROR                       0x2
 111 #define INT_QUEUE_STOPPED               0x4
 112 #define ALL_INTERRUPTS                  (INT_COMPLETION| \
 113                                          INT_ERROR| \
 114                                          INT_QUEUE_STOPPED)
 115
 116 #define LSB_REGION_WIDTH                5
 117 #define MAX_LSB_CNT                     8
 118
 119 #define LSB_SIZE                        16
 120 #define LSB_ITEM_SIZE                   32
 121 #define PLSB_MAP_SIZE                   (LSB_SIZE)
 122 #define SLSB_MAP_SIZE                   (MAX_LSB_CNT * LSB_SIZE)
 123
 124 #define LSB_ENTRY_NUMBER(LSB_ADDR)      (LSB_ADDR / LSB_ITEM_SIZE)
 125
 126 /* ------------------------ CCP Version 3 Specifics ------------------------ */
 127 #define REQ0_WAIT_FOR_WRITE             0x00000004
 128 #define REQ0_INT_ON_COMPLETE            0x00000002
 129 #define REQ0_STOP_ON_COMPLETE           0x00000001
 130
 131 #define REQ0_CMD_Q_SHIFT                9
 132 #define REQ0_JOBID_SHIFT                3
 133
 134 /****** REQ1 Related Values ******/
 135 #define REQ1_PROTECT_SHIFT              27
 136 #define REQ1_ENGINE_SHIFT               23
 137 #define REQ1_KEY_KSB_SHIFT              2
 138
 139 #define REQ1_EOM                        0x00000002
 140 #define REQ1_INIT                       0x00000001
 141
 142 /* AES Related Values */
 143 #define REQ1_AES_TYPE_SHIFT             21
 144 #define REQ1_AES_MODE_SHIFT             18
 145 #define REQ1_AES_ACTION_SHIFT           17
 146 #define REQ1_AES_CFB_SIZE_SHIFT         10
 147
 148 /* XTS-AES Related Values */
 149 #define REQ1_XTS_AES_SIZE_SHIFT         10
 150
 151 /* SHA Related Values */
 152 #define REQ1_SHA_TYPE_SHIFT             21
 153
 154 /* RSA Related Values */
 155 #define REQ1_RSA_MOD_SIZE_SHIFT         10
 156
 157 /* Pass-Through Related Values */
 158 #define REQ1_PT_BW_SHIFT                12
 159 #define REQ1_PT_BS_SHIFT                10
 160
 161 /* ECC Related Values */
 162 #define REQ1_ECC_AFFINE_CONVERT         0x00200000
 163 #define REQ1_ECC_FUNCTION_SHIFT         18
 164
 165 /****** REQ4 Related Values ******/
 166 #define REQ4_KSB_SHIFT                  18
 167 #define REQ4_MEMTYPE_SHIFT              16
 168
 169 /****** REQ6 Related Values ******/
 170 #define REQ6_MEMTYPE_SHIFT              16
 171
 172 /****** Key Storage Block ******/
 173 #define KSB_START                       77
 174 #define KSB_END                         127
 175 #define KSB_COUNT                       (KSB_END - KSB_START + 1)
 176 #define CCP_SB_BITS                     256
 177
 178 #define CCP_JOBID_MASK                  0x0000003f
 179
 180 /* ------------------------ General CCP Defines ------------------------ */
 181
 182 #define CCP_DMA_DFLT                    0x0
 183 #define CCP_DMA_PRIV                    0x1
 184 #define CCP_DMA_PUB                     0x2
 185
 186 #define CCP_DMAPOOL_MAX_SIZE            64
 187 #define CCP_DMAPOOL_ALIGN               BIT(5)
 188
 189 #define CCP_REVERSE_BUF_SIZE            64
 190
 191 #define CCP_AES_KEY_SB_COUNT            1
 192 #define CCP_AES_CTX_SB_COUNT            1
 193
 194 #define CCP_XTS_AES_KEY_SB_COUNT        1
 195 #define CCP_XTS_AES_CTX_SB_COUNT        1
 196
 197 #define CCP_SHA_SB_COUNT                1
 198
 199 #define CCP_RSA_MAX_WIDTH               4096
 200
 201 #define CCP_PASSTHRU_BLOCKSIZE          256
 202 #define CCP_PASSTHRU_MASKSIZE           32
 203 #define CCP_PASSTHRU_SB_COUNT           1
 204
 205 #define CCP_ECC_MODULUS_BYTES           48      /* 384-bits */
 206 #define CCP_ECC_MAX_OPERANDS            6
 207 #define CCP_ECC_MAX_OUTPUTS             3
 208 #define CCP_ECC_SRC_BUF_SIZE            448
 209 #define CCP_ECC_DST_BUF_SIZE            192
 210 #define CCP_ECC_OPERAND_SIZE            64
 211 #define CCP_ECC_OUTPUT_SIZE             64
 212 #define CCP_ECC_RESULT_OFFSET           60
 213 #define CCP_ECC_RESULT_SUCCESS          0x0001
 214
 215 #define CCP_SB_BYTES                    32
 216
 217 struct ccp_op;
 218 struct ccp_device;
 219 struct ccp_cmd;
 220 struct ccp_fns;
 221
 222 struct ccp_dma_cmd {
 223         struct list_head entry;
 224
 225         struct ccp_cmd ccp_cmd;
 226 };
 227
 228 struct ccp_dma_desc {
 229         struct list_head entry;
 230
 231         struct ccp_device *ccp;
 232
 233         struct list_head pending;
 234         struct list_head active;
 235
 236         enum dma_status status;
 237         struct dma_async_tx_descriptor tx_desc;
 238         size_t len;
 239 };
 240
 241 struct ccp_dma_chan {
 242         struct ccp_device *ccp;
 243
 244         spinlock_t lock;
 245         struct list_head created;
 246         struct list_head pending;
 247         struct list_head active;
 248         struct list_head complete;
 249
 250         struct tasklet_struct cleanup_tasklet;
 251
 252         enum dma_status status;
 253         struct dma_chan dma_chan;
 254 };
 255
 256 struct ccp_cmd_queue {
 257         struct ccp_device *ccp;
 258
 259         /* Queue identifier */
 260         u32 id;
 261
 262         /* Queue dma pool */
 263         struct dma_pool *dma_pool;
 264
 265         /* Queue base address (not neccessarily aligned)*/
 266         struct ccp5_desc *qbase;
 267
 268         /* Aligned queue start address (per requirement) */
 269         struct mutex q_mutex ____cacheline_aligned;
 270         unsigned int qidx;
 271
 272         /* Version 5 has different requirements for queue memory */
 273         unsigned int qsize;
 274         dma_addr_t qbase_dma;
 275         dma_addr_t qdma_tail;
 276
 277         /* Per-queue reserved storage block(s) */
 278         u32 sb_key;
 279         u32 sb_ctx;
 280
 281         /* Bitmap of LSBs that can be accessed by this queue */
 282         DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
 283         /* Private LSB that is assigned to this queue, or -1 if none.
 284          * Bitmap for my private LSB, unused otherwise
 285          */
 286         int lsb;
 287         DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
 288
 289         /* Queue processing thread */
 290         struct task_struct *kthread;
 291         unsigned int active;
 292         unsigned int suspended;
 293
 294         /* Number of free command slots available */
 295         unsigned int free_slots;
 296
 297         /* Interrupt masks */
 298         u32 int_ok;
 299         u32 int_err;
 300
 301         /* Register addresses for queue */
 302         void __iomem *reg_control;
 303         void __iomem *reg_tail_lo;
 304         void __iomem *reg_head_lo;
 305         void __iomem *reg_int_enable;
 306         void __iomem *reg_interrupt_status;
 307         void __iomem *reg_status;
 308         void __iomem *reg_int_status;
 309         void __iomem *reg_dma_status;
 310         void __iomem *reg_dma_read_status;
 311         void __iomem *reg_dma_write_status;
 312         u32 qcontrol; /* Cached control register */
 313
 314         /* Status values from job */
 315         u32 int_status;
 316         u32 q_status;
 317         u32 q_int_status;
 318         u32 cmd_error;
 319
 320         /* Interrupt wait queue */
 321         wait_queue_head_t int_queue;
 322         unsigned int int_rcvd;
 323 } ____cacheline_aligned;
 324
 325 struct ccp_device {
 326         struct list_head entry;
 327
 328         struct ccp_vdata *vdata;
 329         unsigned int ord;
 330         char name[MAX_CCP_NAME_LEN];
 331         char rngname[MAX_CCP_NAME_LEN];
 332
 333         struct device *dev;
 334
 335         /* Bus specific device information
 336          */
 337         void *dev_specific;
 338         int (*get_irq)(struct ccp_device *ccp);
 339         void (*free_irq)(struct ccp_device *ccp);
 340         unsigned int irq;
 341
 342         /* I/O area used for device communication. The register mapping
 343          * starts at an offset into the mapped bar.
 344          *   The CMD_REQx registers and the Delete_Cmd_Queue_Job register
 345          *   need to be protected while a command queue thread is accessing
 346          *   them.
 347          */
 348         struct mutex req_mutex ____cacheline_aligned;
 349         void __iomem *io_map;
 350         void __iomem *io_regs;
 351
 352         /* Master lists that all cmds are queued on. Because there can be
 353          * more than one CCP command queue that can process a cmd a separate
 354          * backlog list is neeeded so that the backlog completion call
 355          * completes before the cmd is available for execution.
 356          */
 357         spinlock_t cmd_lock ____cacheline_aligned;
 358         unsigned int cmd_count;
 359         struct list_head cmd;
 360         struct list_head backlog;
 361
 362         /* The command queues. These represent the queues available on the
 363          * CCP that are available for processing cmds
 364          */
 365         struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
 366         unsigned int cmd_q_count;
 367
 368         /* Support for the CCP True RNG
 369          */
 370         struct hwrng hwrng;
 371         unsigned int hwrng_retries;
 372
 373         /* Support for the CCP DMA capabilities
 374          */
 375         struct dma_device dma_dev;
 376         struct ccp_dma_chan *ccp_dma_chan;
 377         struct kmem_cache *dma_cmd_cache;
 378         struct kmem_cache *dma_desc_cache;
 379
 380         /* A counter used to generate job-ids for cmds submitted to the CCP
 381          */
 382         atomic_t current_id ____cacheline_aligned;
 383
 384         /* The v3 CCP uses key storage blocks (SB) to maintain context for
 385          * certain operations. To prevent multiple cmds from using the same
 386          * SB range a command queue reserves an SB range for the duration of
 387          * the cmd. Each queue, will however, reserve 2 SB blocks for
 388          * operations that only require single SB entries (eg. AES context/iv
 389          * and key) in order to avoid allocation contention.  This will reserve
 390          * at most 10 SB entries, leaving 40 SB entries available for dynamic
 391          * allocation.
 392          *
 393          * The v5 CCP Local Storage Block (LSB) is broken up into 8
 394          * memrory ranges, each of which can be enabled for access by one
 395          * or more queues. Device initialization takes this into account,
 396          * and attempts to assign one region for exclusive use by each
 397          * available queue; the rest are then aggregated as "public" use.
 398          * If there are fewer regions than queues, all regions are shared
 399          * amongst all queues.
 400          */
 401         struct mutex sb_mutex ____cacheline_aligned;
 402         DECLARE_BITMAP(sb, KSB_COUNT);
 403         wait_queue_head_t sb_queue;
 404         unsigned int sb_avail;
 405         unsigned int sb_count;
 406         u32 sb_start;
 407
 408         /* Bitmap of shared LSBs, if any */
 409         DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
 410
 411         /* Suspend support */
 412         unsigned int suspending;
 413         wait_queue_head_t suspend_queue;
 414
 415         /* DMA caching attribute support */
 416         unsigned int axcache;
 417 };
 418
 419 enum ccp_memtype {
 420         CCP_MEMTYPE_SYSTEM = 0,
 421         CCP_MEMTYPE_SB,
 422         CCP_MEMTYPE_LOCAL,
 423         CCP_MEMTYPE__LAST,
 424 };
 425 #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
 426
 427 struct ccp_dma_info {
 428         dma_addr_t address;
 429         unsigned int offset;
 430         unsigned int length;
 431         enum dma_data_direction dir;
 432 };
 433
 434 struct ccp_dm_workarea {
 435         struct device *dev;
 436         struct dma_pool *dma_pool;
 437         unsigned int length;
 438
 439         u8 *address;
 440         struct ccp_dma_info dma;
 441 };
 442
 443 struct ccp_sg_workarea {
 444         struct scatterlist *sg;
 445         int nents;
 446
 447         struct scatterlist *dma_sg;
 448         struct device *dma_dev;
 449         unsigned int dma_count;
 450         enum dma_data_direction dma_dir;
 451
 452         unsigned int sg_used;
 453
 454         u64 bytes_left;
 455 };
 456
 457 struct ccp_data {
 458         struct ccp_sg_workarea sg_wa;
 459         struct ccp_dm_workarea dm_wa;
 460 };
 461
 462 struct ccp_mem {
 463         enum ccp_memtype type;
 464         union {
 465                 struct ccp_dma_info dma;
 466                 u32 sb;
 467         } u;
 468 };
 469
 470 struct ccp_aes_op {
 471         enum ccp_aes_type type;
 472         enum ccp_aes_mode mode;
 473         enum ccp_aes_action action;
 474         unsigned int size;
 475 };
 476
 477 struct ccp_xts_aes_op {
 478         enum ccp_aes_action action;
 479         enum ccp_xts_aes_unit_size unit_size;
 480 };
 481
 482 struct ccp_sha_op {
 483         enum ccp_sha_type type;
 484         u64 msg_bits;
 485 };
 486
 487 struct ccp_rsa_op {
 488         u32 mod_size;
 489         u32 input_len;
 490 };
 491
 492 struct ccp_passthru_op {
 493         enum ccp_passthru_bitwise bit_mod;
 494         enum ccp_passthru_byteswap byte_swap;
 495 };
 496
 497 struct ccp_ecc_op {
 498         enum ccp_ecc_function function;
 499 };
 500
 501 struct ccp_op {
 502         struct ccp_cmd_queue *cmd_q;
 503
 504         u32 jobid;
 505         u32 ioc;
 506         u32 soc;
 507         u32 sb_key;
 508         u32 sb_ctx;
 509         u32 init;
 510         u32 eom;
 511
 512         struct ccp_mem src;
 513         struct ccp_mem dst;
 514         struct ccp_mem exp;
 515
 516         union {
 517                 struct ccp_aes_op aes;
 518                 struct ccp_xts_aes_op xts;
 519                 struct ccp_sha_op sha;
 520                 struct ccp_rsa_op rsa;
 521                 struct ccp_passthru_op passthru;
 522                 struct ccp_ecc_op ecc;
 523         } u;
 524 };
 525
 526 static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
 527 {
 528         return lower_32_bits(info->address + info->offset);
 529 }
 530
 531 static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
 532 {
 533         return upper_32_bits(info->address + info->offset) & 0x0000ffff;
 534 }
 535
 536 /**
 537  * descriptor for version 5 CPP commands
 538  * 8 32-bit words:
 539  * word 0: function; engine; control bits
 540  * word 1: length of source data
 541  * word 2: low 32 bits of source pointer
 542  * word 3: upper 16 bits of source pointer; source memory type
 543  * word 4: low 32 bits of destination pointer
 544  * word 5: upper 16 bits of destination pointer; destination memory type
 545  * word 6: low 32 bits of key pointer
 546  * word 7: upper 16 bits of key pointer; key memory type
 547  */
 548 struct dword0 {
 549         unsigned int soc:1;
 550         unsigned int ioc:1;
 551         unsigned int rsvd1:1;
 552         unsigned int init:1;
 553         unsigned int eom:1;             /* AES/SHA only */
 554         unsigned int function:15;
 555         unsigned int engine:4;
 556         unsigned int prot:1;
 557         unsigned int rsvd2:7;
 558 };
 559
 560 struct dword3 {
 561         unsigned int  src_hi:16;
 562         unsigned int  src_mem:2;
 563         unsigned int  lsb_cxt_id:8;
 564         unsigned int  rsvd1:5;
 565         unsigned int  fixed:1;
 566 };
 567
 568 union dword4 {
 569         __le32 dst_lo;          /* NON-SHA      */
 570         __le32 sha_len_lo;      /* SHA          */
 571 };
 572
 573 union dword5 {
 574         struct {
 575                 unsigned int  dst_hi:16;
 576                 unsigned int  dst_mem:2;
 577                 unsigned int  rsvd1:13;
 578                 unsigned int  fixed:1;
 579         } fields;
 580         __le32 sha_len_hi;
 581 };
 582
 583 struct dword7 {
 584         unsigned int  key_hi:16;
 585         unsigned int  key_mem:2;
 586         unsigned int  rsvd1:14;
 587 };
 588
 589 struct ccp5_desc {
 590         struct dword0 dw0;
 591         __le32 length;
 592         __le32 src_lo;
 593         struct dword3 dw3;
 594         union dword4 dw4;
 595         union dword5 dw5;
 596         __le32 key_lo;
 597         struct dword7 dw7;
 598 };
 599
 600 int ccp_pci_init(void);
 601 void ccp_pci_exit(void);
 602
 603 int ccp_platform_init(void);
 604 void ccp_platform_exit(void);
 605
 606 void ccp_add_device(struct ccp_device *ccp);
 607 void ccp_del_device(struct ccp_device *ccp);
 608
 609 extern void ccp_log_error(struct ccp_device *, int);
 610
 611 struct ccp_device *ccp_alloc_struct(struct device *dev);
 612 bool ccp_queues_suspended(struct ccp_device *ccp);
 613 int ccp_cmd_queue_thread(void *data);
 614 int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
 615
 616 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
 617
 618 int ccp_register_rng(struct ccp_device *ccp);
 619 void ccp_unregister_rng(struct ccp_device *ccp);
 620 int ccp_dmaengine_register(struct ccp_device *ccp);
 621 void ccp_dmaengine_unregister(struct ccp_device *ccp);
 622
 623 /* Structure for computation functions that are device-specific */
 624 struct ccp_actions {
 625         int (*aes)(struct ccp_op *);
 626         int (*xts_aes)(struct ccp_op *);
 627         int (*sha)(struct ccp_op *);
 628         int (*rsa)(struct ccp_op *);
 629         int (*passthru)(struct ccp_op *);
 630         int (*ecc)(struct ccp_op *);
 631         u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
 632         void (*sbfree)(struct ccp_cmd_queue *, unsigned int,
 633                                unsigned int);
 634         unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
 635         int (*init)(struct ccp_device *);
 636         void (*destroy)(struct ccp_device *);
 637         irqreturn_t (*irqhandler)(int, void *);
 638 };
 639
 640 /* Structure to hold CCP version-specific values */
 641 struct ccp_vdata {
 642         const unsigned int version;
 643         const unsigned int dma_chan_attr;
 644         void (*setup)(struct ccp_device *);
 645         const struct ccp_actions *perform;
 646         const unsigned int bar;
 647         const unsigned int offset;
 648 };
 649
 650 extern const struct ccp_vdata ccpv3;
 651 extern const struct ccp_vdata ccpv5a;
 652 extern const struct ccp_vdata ccpv5b;
 653
 654 #endif