2 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
3 * that can be found on the following platform: Orion, Kirkwood, Armada. This
4 * driver supports the TDMA engine on platforms on which it is available.
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Author: Arnaud Ebalard <arno@natisbad.org>
9 * This work is based on an initial version written by
10 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published
14 * by the Free Software Foundation.
17 #include <linux/delay.h>
18 #include <linux/genalloc.h>
19 #include <linux/interrupt.h>
21 #include <linux/kthread.h>
22 #include <linux/mbus.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/clk.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_irq.h>
34 static int allhwsupport
= !IS_ENABLED(CONFIG_CRYPTO_DEV_MV_CESA
);
35 module_param_named(allhwsupport
, allhwsupport
, int, 0444);
36 MODULE_PARM_DESC(allhwsupport
, "Enable support for all hardware (even it if overlaps with the mv_cesa driver)");
38 struct mv_cesa_dev
*cesa_dev
;
40 static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine
*engine
)
42 struct crypto_async_request
*req
, *backlog
;
43 struct mv_cesa_ctx
*ctx
;
45 spin_lock_bh(&cesa_dev
->lock
);
46 backlog
= crypto_get_backlog(&cesa_dev
->queue
);
47 req
= crypto_dequeue_request(&cesa_dev
->queue
);
49 spin_unlock_bh(&cesa_dev
->lock
);
55 backlog
->complete(backlog
, -EINPROGRESS
);
57 ctx
= crypto_tfm_ctx(req
->tfm
);
58 ctx
->ops
->prepare(req
, engine
);
62 static irqreturn_t
mv_cesa_int(int irq
, void *priv
)
64 struct mv_cesa_engine
*engine
= priv
;
65 struct crypto_async_request
*req
;
66 struct mv_cesa_ctx
*ctx
;
68 irqreturn_t ret
= IRQ_NONE
;
73 mask
= mv_cesa_get_int_mask(engine
);
74 status
= readl(engine
->regs
+ CESA_SA_INT_STATUS
);
80 * TODO: avoid clearing the FPGA_INT_STATUS if this not
81 * relevant on some platforms.
83 writel(~status
, engine
->regs
+ CESA_SA_FPGA_INT_STATUS
);
84 writel(~status
, engine
->regs
+ CESA_SA_INT_STATUS
);
87 spin_lock_bh(&engine
->lock
);
89 spin_unlock_bh(&engine
->lock
);
91 ctx
= crypto_tfm_ctx(req
->tfm
);
92 res
= ctx
->ops
->process(req
, status
& mask
);
93 if (res
!= -EINPROGRESS
) {
94 spin_lock_bh(&engine
->lock
);
96 mv_cesa_dequeue_req_unlocked(engine
);
97 spin_unlock_bh(&engine
->lock
);
98 ctx
->ops
->cleanup(req
);
100 req
->complete(req
, res
);
111 int mv_cesa_queue_req(struct crypto_async_request
*req
)
116 spin_lock_bh(&cesa_dev
->lock
);
117 ret
= crypto_enqueue_request(&cesa_dev
->queue
, req
);
118 spin_unlock_bh(&cesa_dev
->lock
);
120 if (ret
!= -EINPROGRESS
)
123 for (i
= 0; i
< cesa_dev
->caps
->nengines
; i
++) {
124 spin_lock_bh(&cesa_dev
->engines
[i
].lock
);
125 if (!cesa_dev
->engines
[i
].req
)
126 mv_cesa_dequeue_req_unlocked(&cesa_dev
->engines
[i
]);
127 spin_unlock_bh(&cesa_dev
->engines
[i
].lock
);
133 static int mv_cesa_add_algs(struct mv_cesa_dev
*cesa
)
138 for (i
= 0; i
< cesa
->caps
->ncipher_algs
; i
++) {
139 ret
= crypto_register_alg(cesa
->caps
->cipher_algs
[i
]);
141 goto err_unregister_crypto
;
144 for (i
= 0; i
< cesa
->caps
->nahash_algs
; i
++) {
145 ret
= crypto_register_ahash(cesa
->caps
->ahash_algs
[i
]);
147 goto err_unregister_ahash
;
152 err_unregister_ahash
:
153 for (j
= 0; j
< i
; j
++)
154 crypto_unregister_ahash(cesa
->caps
->ahash_algs
[j
]);
155 i
= cesa
->caps
->ncipher_algs
;
157 err_unregister_crypto
:
158 for (j
= 0; j
< i
; j
++)
159 crypto_unregister_alg(cesa
->caps
->cipher_algs
[j
]);
164 static void mv_cesa_remove_algs(struct mv_cesa_dev
*cesa
)
168 for (i
= 0; i
< cesa
->caps
->nahash_algs
; i
++)
169 crypto_unregister_ahash(cesa
->caps
->ahash_algs
[i
]);
171 for (i
= 0; i
< cesa
->caps
->ncipher_algs
; i
++)
172 crypto_unregister_alg(cesa
->caps
->cipher_algs
[i
]);
175 static struct crypto_alg
*orion_cipher_algs
[] = {
176 &mv_cesa_ecb_des_alg
,
177 &mv_cesa_cbc_des_alg
,
178 &mv_cesa_ecb_des3_ede_alg
,
179 &mv_cesa_cbc_des3_ede_alg
,
180 &mv_cesa_ecb_aes_alg
,
181 &mv_cesa_cbc_aes_alg
,
184 static struct ahash_alg
*orion_ahash_algs
[] = {
191 static struct crypto_alg
*armada_370_cipher_algs
[] = {
192 &mv_cesa_ecb_des_alg
,
193 &mv_cesa_cbc_des_alg
,
194 &mv_cesa_ecb_des3_ede_alg
,
195 &mv_cesa_cbc_des3_ede_alg
,
196 &mv_cesa_ecb_aes_alg
,
197 &mv_cesa_cbc_aes_alg
,
200 static struct ahash_alg
*armada_370_ahash_algs
[] = {
206 &mv_ahmac_sha256_alg
,
209 static const struct mv_cesa_caps orion_caps
= {
211 .cipher_algs
= orion_cipher_algs
,
212 .ncipher_algs
= ARRAY_SIZE(orion_cipher_algs
),
213 .ahash_algs
= orion_ahash_algs
,
214 .nahash_algs
= ARRAY_SIZE(orion_ahash_algs
),
218 static const struct mv_cesa_caps kirkwood_caps
= {
220 .cipher_algs
= orion_cipher_algs
,
221 .ncipher_algs
= ARRAY_SIZE(orion_cipher_algs
),
222 .ahash_algs
= orion_ahash_algs
,
223 .nahash_algs
= ARRAY_SIZE(orion_ahash_algs
),
227 static const struct mv_cesa_caps armada_370_caps
= {
229 .cipher_algs
= armada_370_cipher_algs
,
230 .ncipher_algs
= ARRAY_SIZE(armada_370_cipher_algs
),
231 .ahash_algs
= armada_370_ahash_algs
,
232 .nahash_algs
= ARRAY_SIZE(armada_370_ahash_algs
),
236 static const struct mv_cesa_caps armada_xp_caps
= {
238 .cipher_algs
= armada_370_cipher_algs
,
239 .ncipher_algs
= ARRAY_SIZE(armada_370_cipher_algs
),
240 .ahash_algs
= armada_370_ahash_algs
,
241 .nahash_algs
= ARRAY_SIZE(armada_370_ahash_algs
),
245 static const struct of_device_id mv_cesa_of_match_table
[] = {
246 { .compatible
= "marvell,orion-crypto", .data
= &orion_caps
},
247 { .compatible
= "marvell,kirkwood-crypto", .data
= &kirkwood_caps
},
248 { .compatible
= "marvell,dove-crypto", .data
= &kirkwood_caps
},
249 { .compatible
= "marvell,armada-370-crypto", .data
= &armada_370_caps
},
250 { .compatible
= "marvell,armada-xp-crypto", .data
= &armada_xp_caps
},
251 { .compatible
= "marvell,armada-375-crypto", .data
= &armada_xp_caps
},
252 { .compatible
= "marvell,armada-38x-crypto", .data
= &armada_xp_caps
},
255 MODULE_DEVICE_TABLE(of
, mv_cesa_of_match_table
);
258 mv_cesa_conf_mbus_windows(struct mv_cesa_engine
*engine
,
259 const struct mbus_dram_target_info
*dram
)
261 void __iomem
*iobase
= engine
->regs
;
264 for (i
= 0; i
< 4; i
++) {
265 writel(0, iobase
+ CESA_TDMA_WINDOW_CTRL(i
));
266 writel(0, iobase
+ CESA_TDMA_WINDOW_BASE(i
));
269 for (i
= 0; i
< dram
->num_cs
; i
++) {
270 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
272 writel(((cs
->size
- 1) & 0xffff0000) |
273 (cs
->mbus_attr
<< 8) |
274 (dram
->mbus_dram_target_id
<< 4) | 1,
275 iobase
+ CESA_TDMA_WINDOW_CTRL(i
));
276 writel(cs
->base
, iobase
+ CESA_TDMA_WINDOW_BASE(i
));
280 static int mv_cesa_dev_dma_init(struct mv_cesa_dev
*cesa
)
282 struct device
*dev
= cesa
->dev
;
283 struct mv_cesa_dev_dma
*dma
;
285 if (!cesa
->caps
->has_tdma
)
288 dma
= devm_kzalloc(dev
, sizeof(*dma
), GFP_KERNEL
);
292 dma
->tdma_desc_pool
= dmam_pool_create("tdma_desc", dev
,
293 sizeof(struct mv_cesa_tdma_desc
),
295 if (!dma
->tdma_desc_pool
)
298 dma
->op_pool
= dmam_pool_create("cesa_op", dev
,
299 sizeof(struct mv_cesa_op_ctx
), 16, 0);
303 dma
->cache_pool
= dmam_pool_create("cesa_cache", dev
,
304 CESA_MAX_HASH_BLOCK_SIZE
, 1, 0);
305 if (!dma
->cache_pool
)
308 dma
->padding_pool
= dmam_pool_create("cesa_padding", dev
, 72, 1, 0);
309 if (!dma
->cache_pool
)
317 static int mv_cesa_get_sram(struct platform_device
*pdev
, int idx
)
319 struct mv_cesa_dev
*cesa
= platform_get_drvdata(pdev
);
320 struct mv_cesa_engine
*engine
= &cesa
->engines
[idx
];
321 const char *res_name
= "sram";
322 struct resource
*res
;
324 engine
->pool
= of_gen_pool_get(cesa
->dev
->of_node
,
325 "marvell,crypto-srams", idx
);
327 engine
->sram
= gen_pool_dma_alloc(engine
->pool
,
337 if (cesa
->caps
->nengines
> 1) {
344 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
346 if (!res
|| resource_size(res
) < cesa
->sram_size
)
349 engine
->sram
= devm_ioremap_resource(cesa
->dev
, res
);
350 if (IS_ERR(engine
->sram
))
351 return PTR_ERR(engine
->sram
);
353 engine
->sram_dma
= phys_to_dma(cesa
->dev
,
354 (phys_addr_t
)res
->start
);
359 static void mv_cesa_put_sram(struct platform_device
*pdev
, int idx
)
361 struct mv_cesa_dev
*cesa
= platform_get_drvdata(pdev
);
362 struct mv_cesa_engine
*engine
= &cesa
->engines
[idx
];
367 gen_pool_free(engine
->pool
, (unsigned long)engine
->sram
,
371 static int mv_cesa_probe(struct platform_device
*pdev
)
373 const struct mv_cesa_caps
*caps
= &orion_caps
;
374 const struct mbus_dram_target_info
*dram
;
375 const struct of_device_id
*match
;
376 struct device
*dev
= &pdev
->dev
;
377 struct mv_cesa_dev
*cesa
;
378 struct mv_cesa_engine
*engines
;
379 struct resource
*res
;
384 dev_err(&pdev
->dev
, "Only one CESA device authorized\n");
389 match
= of_match_node(mv_cesa_of_match_table
, dev
->of_node
);
390 if (!match
|| !match
->data
)
396 if ((caps
== &orion_caps
|| caps
== &kirkwood_caps
) && !allhwsupport
)
399 cesa
= devm_kzalloc(dev
, sizeof(*cesa
), GFP_KERNEL
);
406 sram_size
= CESA_SA_DEFAULT_SRAM_SIZE
;
407 of_property_read_u32(cesa
->dev
->of_node
, "marvell,crypto-sram-size",
409 if (sram_size
< CESA_SA_MIN_SRAM_SIZE
)
410 sram_size
= CESA_SA_MIN_SRAM_SIZE
;
412 cesa
->sram_size
= sram_size
;
413 cesa
->engines
= devm_kzalloc(dev
, caps
->nengines
* sizeof(*engines
),
418 spin_lock_init(&cesa
->lock
);
419 crypto_init_queue(&cesa
->queue
, 50);
420 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "regs");
421 cesa
->regs
= devm_ioremap_resource(dev
, res
);
422 if (IS_ERR(cesa
->regs
))
425 ret
= mv_cesa_dev_dma_init(cesa
);
429 dram
= mv_mbus_dram_info_nooverlap();
431 platform_set_drvdata(pdev
, cesa
);
433 for (i
= 0; i
< caps
->nengines
; i
++) {
434 struct mv_cesa_engine
*engine
= &cesa
->engines
[i
];
438 spin_lock_init(&engine
->lock
);
440 ret
= mv_cesa_get_sram(pdev
, i
);
444 irq
= platform_get_irq(pdev
, i
);
451 * Not all platforms can gate the CESA clocks: do not complain
452 * if the clock does not exist.
454 snprintf(res_name
, sizeof(res_name
), "cesa%d", i
);
455 engine
->clk
= devm_clk_get(dev
, res_name
);
456 if (IS_ERR(engine
->clk
)) {
457 engine
->clk
= devm_clk_get(dev
, NULL
);
458 if (IS_ERR(engine
->clk
))
462 snprintf(res_name
, sizeof(res_name
), "cesaz%d", i
);
463 engine
->zclk
= devm_clk_get(dev
, res_name
);
464 if (IS_ERR(engine
->zclk
))
467 ret
= clk_prepare_enable(engine
->clk
);
471 ret
= clk_prepare_enable(engine
->zclk
);
475 engine
->regs
= cesa
->regs
+ CESA_ENGINE_OFF(i
);
477 if (dram
&& cesa
->caps
->has_tdma
)
478 mv_cesa_conf_mbus_windows(&cesa
->engines
[i
], dram
);
480 writel(0, cesa
->engines
[i
].regs
+ CESA_SA_INT_STATUS
);
481 writel(CESA_SA_CFG_STOP_DIG_ERR
,
482 cesa
->engines
[i
].regs
+ CESA_SA_CFG
);
483 writel(engine
->sram_dma
& CESA_SA_SRAM_MSK
,
484 cesa
->engines
[i
].regs
+ CESA_SA_DESC_P0
);
486 ret
= devm_request_threaded_irq(dev
, irq
, NULL
, mv_cesa_int
,
488 dev_name(&pdev
->dev
),
496 ret
= mv_cesa_add_algs(cesa
);
502 dev_info(dev
, "CESA device successfully registered\n");
507 for (i
= 0; i
< caps
->nengines
; i
++) {
508 clk_disable_unprepare(cesa
->engines
[i
].zclk
);
509 clk_disable_unprepare(cesa
->engines
[i
].clk
);
510 mv_cesa_put_sram(pdev
, i
);
516 static int mv_cesa_remove(struct platform_device
*pdev
)
518 struct mv_cesa_dev
*cesa
= platform_get_drvdata(pdev
);
521 mv_cesa_remove_algs(cesa
);
523 for (i
= 0; i
< cesa
->caps
->nengines
; i
++) {
524 clk_disable_unprepare(cesa
->engines
[i
].zclk
);
525 clk_disable_unprepare(cesa
->engines
[i
].clk
);
526 mv_cesa_put_sram(pdev
, i
);
532 static struct platform_driver marvell_cesa
= {
533 .probe
= mv_cesa_probe
,
534 .remove
= mv_cesa_remove
,
536 .owner
= THIS_MODULE
,
537 .name
= "marvell-cesa",
538 .of_match_table
= mv_cesa_of_match_table
,
541 module_platform_driver(marvell_cesa
);
543 MODULE_ALIAS("platform:mv_crypto");
544 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
545 MODULE_AUTHOR("Arnaud Ebalard <arno@natisbad.org>");
546 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
547 MODULE_LICENSE("GPL v2");