drivers/crypto/marvell/cesa.h

   1 #ifndef __MARVELL_CESA_H__
   2 #define __MARVELL_CESA_H__
   3
   4 #include <crypto/algapi.h>
   5 #include <crypto/hash.h>
   6 #include <crypto/internal/hash.h>
   7
   8 #include <linux/crypto.h>
   9 #include <linux/dmapool.h>
  10
  11 #define CESA_ENGINE_OFF(i)                      (((i) * 0x2000))
  12
  13 #define CESA_TDMA_BYTE_CNT                      0x800
  14 #define CESA_TDMA_SRC_ADDR                      0x810
  15 #define CESA_TDMA_DST_ADDR                      0x820
  16 #define CESA_TDMA_NEXT_ADDR                     0x830
  17
  18 #define CESA_TDMA_CONTROL                       0x840
  19 #define CESA_TDMA_DST_BURST                     GENMASK(2, 0)
  20 #define CESA_TDMA_DST_BURST_32B                 3
  21 #define CESA_TDMA_DST_BURST_128B                4
  22 #define CESA_TDMA_OUT_RD_EN                     BIT(4)
  23 #define CESA_TDMA_SRC_BURST                     GENMASK(8, 6)
  24 #define CESA_TDMA_SRC_BURST_32B                 (3 << 6)
  25 #define CESA_TDMA_SRC_BURST_128B                (4 << 6)
  26 #define CESA_TDMA_CHAIN                         BIT(9)
  27 #define CESA_TDMA_BYTE_SWAP                     BIT(11)
  28 #define CESA_TDMA_NO_BYTE_SWAP                  BIT(11)
  29 #define CESA_TDMA_EN                            BIT(12)
  30 #define CESA_TDMA_FETCH_ND                      BIT(13)
  31 #define CESA_TDMA_ACT                           BIT(14)
  32
  33 #define CESA_TDMA_CUR                           0x870
  34 #define CESA_TDMA_ERROR_CAUSE                   0x8c8
  35 #define CESA_TDMA_ERROR_MSK                     0x8cc
  36
  37 #define CESA_TDMA_WINDOW_BASE(x)                (((x) * 0x8) + 0xa00)
  38 #define CESA_TDMA_WINDOW_CTRL(x)                (((x) * 0x8) + 0xa04)
  39
  40 #define CESA_IVDIG(x)                           (0xdd00 + ((x) * 4) +   \
  41                                                  (((x) < 5) ? 0 : 0x14))
  42
  43 #define CESA_SA_CMD                             0xde00
  44 #define CESA_SA_CMD_EN_CESA_SA_ACCL0            BIT(0)
  45 #define CESA_SA_CMD_EN_CESA_SA_ACCL1            BIT(1)
  46 #define CESA_SA_CMD_DISABLE_SEC                 BIT(2)
  47
  48 #define CESA_SA_DESC_P0                         0xde04
  49
  50 #define CESA_SA_DESC_P1                         0xde14
  51
  52 #define CESA_SA_CFG                             0xde08
  53 #define CESA_SA_CFG_STOP_DIG_ERR                GENMASK(1, 0)
  54 #define CESA_SA_CFG_DIG_ERR_CONT                0
  55 #define CESA_SA_CFG_DIG_ERR_SKIP                1
  56 #define CESA_SA_CFG_DIG_ERR_STOP                3
  57 #define CESA_SA_CFG_CH0_W_IDMA                  BIT(7)
  58 #define CESA_SA_CFG_CH1_W_IDMA                  BIT(8)
  59 #define CESA_SA_CFG_ACT_CH0_IDMA                BIT(9)
  60 #define CESA_SA_CFG_ACT_CH1_IDMA                BIT(10)
  61 #define CESA_SA_CFG_MULTI_PKT                   BIT(11)
  62 #define CESA_SA_CFG_PARA_DIS                    BIT(13)
  63
  64 #define CESA_SA_ACCEL_STATUS                    0xde0c
  65 #define CESA_SA_ST_ACT_0                        BIT(0)
  66 #define CESA_SA_ST_ACT_1                        BIT(1)
  67
  68 /*
  69  * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
  70  * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
  71  * and someone forgot to remove  it while switching to the core and moving to
  72  * CESA_SA_INT_STATUS.
  73  */
  74 #define CESA_SA_FPGA_INT_STATUS                 0xdd68
  75 #define CESA_SA_INT_STATUS                      0xde20
  76 #define CESA_SA_INT_AUTH_DONE                   BIT(0)
  77 #define CESA_SA_INT_DES_E_DONE                  BIT(1)
  78 #define CESA_SA_INT_AES_E_DONE                  BIT(2)
  79 #define CESA_SA_INT_AES_D_DONE                  BIT(3)
  80 #define CESA_SA_INT_ENC_DONE                    BIT(4)
  81 #define CESA_SA_INT_ACCEL0_DONE                 BIT(5)
  82 #define CESA_SA_INT_ACCEL1_DONE                 BIT(6)
  83 #define CESA_SA_INT_ACC0_IDMA_DONE              BIT(7)
  84 #define CESA_SA_INT_ACC1_IDMA_DONE              BIT(8)
  85 #define CESA_SA_INT_IDMA_DONE                   BIT(9)
  86 #define CESA_SA_INT_IDMA_OWN_ERR                BIT(10)
  87
  88 #define CESA_SA_INT_MSK                         0xde24
  89
  90 #define CESA_SA_DESC_CFG_OP_MAC_ONLY            0
  91 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY          1
  92 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT           2
  93 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC           3
  94 #define CESA_SA_DESC_CFG_OP_MSK                 GENMASK(1, 0)
  95 #define CESA_SA_DESC_CFG_MACM_SHA256            (1 << 4)
  96 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256       (3 << 4)
  97 #define CESA_SA_DESC_CFG_MACM_MD5               (4 << 4)
  98 #define CESA_SA_DESC_CFG_MACM_SHA1              (5 << 4)
  99 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5          (6 << 4)
 100 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1         (7 << 4)
 101 #define CESA_SA_DESC_CFG_MACM_MSK               GENMASK(6, 4)
 102 #define CESA_SA_DESC_CFG_CRYPTM_DES             (1 << 8)
 103 #define CESA_SA_DESC_CFG_CRYPTM_3DES            (2 << 8)
 104 #define CESA_SA_DESC_CFG_CRYPTM_AES             (3 << 8)
 105 #define CESA_SA_DESC_CFG_CRYPTM_MSK             GENMASK(9, 8)
 106 #define CESA_SA_DESC_CFG_DIR_ENC                (0 << 12)
 107 #define CESA_SA_DESC_CFG_DIR_DEC                (1 << 12)
 108 #define CESA_SA_DESC_CFG_CRYPTCM_ECB            (0 << 16)
 109 #define CESA_SA_DESC_CFG_CRYPTCM_CBC            (1 << 16)
 110 #define CESA_SA_DESC_CFG_CRYPTCM_MSK            BIT(16)
 111 #define CESA_SA_DESC_CFG_3DES_EEE               (0 << 20)
 112 #define CESA_SA_DESC_CFG_3DES_EDE               (1 << 20)
 113 #define CESA_SA_DESC_CFG_AES_LEN_128            (0 << 24)
 114 #define CESA_SA_DESC_CFG_AES_LEN_192            (1 << 24)
 115 #define CESA_SA_DESC_CFG_AES_LEN_256            (2 << 24)
 116 #define CESA_SA_DESC_CFG_AES_LEN_MSK            GENMASK(25, 24)
 117 #define CESA_SA_DESC_CFG_NOT_FRAG               (0 << 30)
 118 #define CESA_SA_DESC_CFG_FIRST_FRAG             (1 << 30)
 119 #define CESA_SA_DESC_CFG_LAST_FRAG              (2 << 30)
 120 #define CESA_SA_DESC_CFG_MID_FRAG               (3 << 30)
 121 #define CESA_SA_DESC_CFG_FRAG_MSK               GENMASK(31, 30)
 122
 123 /*
 124  * /-----------\ 0
 125  * | ACCEL CFG |        4 * 8
 126  * |-----------| 0x20
 127  * | CRYPT KEY |        8 * 4
 128  * |-----------| 0x40
 129  * |  IV   IN  |        4 * 4
 130  * |-----------| 0x40 (inplace)
 131  * |  IV BUF   |        4 * 4
 132  * |-----------| 0x80
 133  * |  DATA IN  |        16 * x (max ->max_req_size)
 134  * |-----------| 0x80 (inplace operation)
 135  * |  DATA OUT |        16 * x (max ->max_req_size)
 136  * \-----------/ SRAM size
 137  */
 138
 139 /*
 140  * Hashing memory map:
 141  * /-----------\ 0
 142  * | ACCEL CFG |        4 * 8
 143  * |-----------| 0x20
 144  * | Inner IV  |        8 * 4
 145  * |-----------| 0x40
 146  * | Outer IV  |        8 * 4
 147  * |-----------| 0x60
 148  * | Output BUF|        8 * 4
 149  * |-----------| 0x80
 150  * |  DATA IN  |        64 * x (max ->max_req_size)
 151  * \-----------/ SRAM size
 152  */
 153
 154 #define CESA_SA_CFG_SRAM_OFFSET                 0x00
 155 #define CESA_SA_DATA_SRAM_OFFSET                0x80
 156
 157 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET           0x20
 158 #define CESA_SA_CRYPT_IV_SRAM_OFFSET            0x40
 159
 160 #define CESA_SA_MAC_IIV_SRAM_OFFSET             0x20
 161 #define CESA_SA_MAC_OIV_SRAM_OFFSET             0x40
 162 #define CESA_SA_MAC_DIG_SRAM_OFFSET             0x60
 163
 164 #define CESA_SA_DESC_CRYPT_DATA(offset)                                 \
 165         cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) |             \
 166                     ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
 167
 168 #define CESA_SA_DESC_CRYPT_IV(offset)                                   \
 169         cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
 170                     ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
 171
 172 #define CESA_SA_DESC_CRYPT_KEY(offset)                                  \
 173         cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
 174
 175 #define CESA_SA_DESC_MAC_DATA(offset)                                   \
 176         cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
 177 #define CESA_SA_DESC_MAC_DATA_MSK               GENMASK(15, 0)
 178
 179 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len)   cpu_to_le32((total_len) << 16)
 180 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK          GENMASK(31, 16)
 181
 182 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX      0xffff
 183
 184 #define CESA_SA_DESC_MAC_DIGEST(offset)                                 \
 185         cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
 186 #define CESA_SA_DESC_MAC_DIGEST_MSK             GENMASK(15, 0)
 187
 188 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len)     cpu_to_le32((frag_len) << 16)
 189 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK           GENMASK(31, 16)
 190
 191 #define CESA_SA_DESC_MAC_IV(offset)                                     \
 192         cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) |          \
 193                     ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
 194
 195 #define CESA_SA_SRAM_SIZE                       2048
 196 #define CESA_SA_SRAM_PAYLOAD_SIZE               (cesa_dev->sram_size - \
 197                                                  CESA_SA_DATA_SRAM_OFFSET)
 198
 199 #define CESA_SA_DEFAULT_SRAM_SIZE               2048
 200 #define CESA_SA_MIN_SRAM_SIZE                   1024
 201
 202 #define CESA_SA_SRAM_MSK                        (2048 - 1)
 203
 204 #define CESA_MAX_HASH_BLOCK_SIZE                64
 205 #define CESA_HASH_BLOCK_SIZE_MSK                (CESA_MAX_HASH_BLOCK_SIZE - 1)
 206
 207 /**
 208  * struct mv_cesa_sec_accel_desc - security accelerator descriptor
 209  * @config:     engine config
 210  * @enc_p:      input and output data pointers for a cipher operation
 211  * @enc_len:    cipher operation length
 212  * @enc_key_p:  cipher key pointer
 213  * @enc_iv:     cipher IV pointers
 214  * @mac_src_p:  input pointer and total hash length
 215  * @mac_digest: digest pointer and hash operation length
 216  * @mac_iv:     hmac IV pointers
 217  *
 218  * Structure passed to the CESA engine to describe the crypto operation
 219  * to be executed.
 220  */
 221 struct mv_cesa_sec_accel_desc {
 222         u32 config;
 223         u32 enc_p;
 224         u32 enc_len;
 225         u32 enc_key_p;
 226         u32 enc_iv;
 227         u32 mac_src_p;
 228         u32 mac_digest;
 229         u32 mac_iv;
 230 };
 231
 232 /**
 233  * struct mv_cesa_blkcipher_op_ctx - cipher operation context
 234  * @key:        cipher key
 235  * @iv:         cipher IV
 236  *
 237  * Context associated to a cipher operation.
 238  */
 239 struct mv_cesa_blkcipher_op_ctx {
 240         u32 key[8];
 241         u32 iv[4];
 242 };
 243
 244 /**
 245  * struct mv_cesa_hash_op_ctx - hash or hmac operation context
 246  * @key:        cipher key
 247  * @iv:         cipher IV
 248  *
 249  * Context associated to an hash or hmac operation.
 250  */
 251 struct mv_cesa_hash_op_ctx {
 252         u32 iv[16];
 253         u32 hash[8];
 254 };
 255
 256 /**
 257  * struct mv_cesa_op_ctx - crypto operation context
 258  * @desc:       CESA descriptor
 259  * @ctx:        context associated to the crypto operation
 260  *
 261  * Context associated to a crypto operation.
 262  */
 263 struct mv_cesa_op_ctx {
 264         struct mv_cesa_sec_accel_desc desc;
 265         union {
 266                 struct mv_cesa_blkcipher_op_ctx blkcipher;
 267                 struct mv_cesa_hash_op_ctx hash;
 268         } ctx;
 269 };
 270
 271 /* TDMA descriptor flags */
 272 #define CESA_TDMA_DST_IN_SRAM                   BIT(31)
 273 #define CESA_TDMA_SRC_IN_SRAM                   BIT(30)
 274 #define CESA_TDMA_TYPE_MSK                      GENMASK(29, 0)
 275 #define CESA_TDMA_DUMMY                         0
 276 #define CESA_TDMA_DATA                          1
 277 #define CESA_TDMA_OP                            2
 278
 279 /**
 280  * struct mv_cesa_tdma_desc - TDMA descriptor
 281  * @byte_cnt:   number of bytes to transfer
 282  * @src:        DMA address of the source
 283  * @dst:        DMA address of the destination
 284  * @next_dma:   DMA address of the next TDMA descriptor
 285  * @cur_dma:    DMA address of this TDMA descriptor
 286  * @next:       pointer to the next TDMA descriptor
 287  * @op:         CESA operation attached to this TDMA descriptor
 288  * @data:       raw data attached to this TDMA descriptor
 289  * @flags:      flags describing the TDMA transfer. See the
 290  *              "TDMA descriptor flags" section above
 291  *
 292  * TDMA descriptor used to create a transfer chain describing a crypto
 293  * operation.
 294  */
 295 struct mv_cesa_tdma_desc {
 296         u32 byte_cnt;
 297         u32 src;
 298         u32 dst;
 299         u32 next_dma;
 300         u32 cur_dma;
 301         struct mv_cesa_tdma_desc *next;
 302         union {
 303                 struct mv_cesa_op_ctx *op;
 304                 void *data;
 305         };
 306         u32 flags;
 307 };
 308
 309 /**
 310  * struct mv_cesa_sg_dma_iter - scatter-gather iterator
 311  * @dir:        transfer direction
 312  * @sg:         scatter list
 313  * @offset:     current position in the scatter list
 314  * @op_offset:  current position in the crypto operation
 315  *
 316  * Iterator used to iterate over a scatterlist while creating a TDMA chain for
 317  * a crypto operation.
 318  */
 319 struct mv_cesa_sg_dma_iter {
 320         enum dma_data_direction dir;
 321         struct scatterlist *sg;
 322         unsigned int offset;
 323         unsigned int op_offset;
 324 };
 325
 326 /**
 327  * struct mv_cesa_dma_iter - crypto operation iterator
 328  * @len:        the crypto operation length
 329  * @offset:     current position in the crypto operation
 330  * @op_len:     sub-operation length (the crypto engine can only act on 2kb
 331  *              chunks)
 332  *
 333  * Iterator used to create a TDMA chain for a given crypto operation.
 334  */
 335 struct mv_cesa_dma_iter {
 336         unsigned int len;
 337         unsigned int offset;
 338         unsigned int op_len;
 339 };
 340
 341 /**
 342  * struct mv_cesa_tdma_chain - TDMA chain
 343  * @first:      first entry in the TDMA chain
 344  * @last:       last entry in the TDMA chain
 345  *
 346  * Stores a TDMA chain for a specific crypto operation.
 347  */
 348 struct mv_cesa_tdma_chain {
 349         struct mv_cesa_tdma_desc *first;
 350         struct mv_cesa_tdma_desc *last;
 351 };
 352
 353 struct mv_cesa_engine;
 354
 355 /**
 356  * struct mv_cesa_caps - CESA device capabilities
 357  * @engines:            number of engines
 358  * @has_tdma:           whether this device has a TDMA block
 359  * @cipher_algs:        supported cipher algorithms
 360  * @ncipher_algs:       number of supported cipher algorithms
 361  * @ahash_algs:         supported hash algorithms
 362  * @nahash_algs:        number of supported hash algorithms
 363  *
 364  * Structure used to describe CESA device capabilities.
 365  */
 366 struct mv_cesa_caps {
 367         int nengines;
 368         bool has_tdma;
 369         struct crypto_alg **cipher_algs;
 370         int ncipher_algs;
 371         struct ahash_alg **ahash_algs;
 372         int nahash_algs;
 373 };
 374
 375 /**
 376  * struct mv_cesa_dev_dma - DMA pools
 377  * @tdma_desc_pool:     TDMA desc pool
 378  * @op_pool:            crypto operation pool
 379  * @cache_pool:         data cache pool (used by hash implementation when the
 380  *                      hash request is smaller than the hash block size)
 381  * @padding_pool:       padding pool (used by hash implementation when hardware
 382  *                      padding cannot be used)
 383  *
 384  * Structure containing the different DMA pools used by this driver.
 385  */
 386 struct mv_cesa_dev_dma {
 387         struct dma_pool *tdma_desc_pool;
 388         struct dma_pool *op_pool;
 389         struct dma_pool *cache_pool;
 390         struct dma_pool *padding_pool;
 391 };
 392
 393 /**
 394  * struct mv_cesa_dev - CESA device
 395  * @caps:       device capabilities
 396  * @regs:       device registers
 397  * @sram_size:  usable SRAM size
 398  * @lock:       device lock
 399  * @queue:      crypto request queue
 400  * @engines:    array of engines
 401  * @dma:        dma pools
 402  *
 403  * Structure storing CESA device information.
 404  */
 405 struct mv_cesa_dev {
 406         const struct mv_cesa_caps *caps;
 407         void __iomem *regs;
 408         struct device *dev;
 409         unsigned int sram_size;
 410         spinlock_t lock;
 411         struct crypto_queue queue;
 412         struct mv_cesa_engine *engines;
 413         struct mv_cesa_dev_dma *dma;
 414 };
 415
 416 /**
 417  * struct mv_cesa_engine - CESA engine
 418  * @id:                 engine id
 419  * @regs:               engine registers
 420  * @sram:               SRAM memory region
 421  * @sram_dma:           DMA address of the SRAM memory region
 422  * @lock:               engine lock
 423  * @req:                current crypto request
 424  * @clk:                engine clk
 425  * @zclk:               engine zclk
 426  * @max_req_len:        maximum chunk length (useful to create the TDMA chain)
 427  * @int_mask:           interrupt mask cache
 428  * @pool:               memory pool pointing to the memory region reserved in
 429  *                      SRAM
 430  *
 431  * Structure storing CESA engine information.
 432  */
 433 struct mv_cesa_engine {
 434         int id;
 435         void __iomem *regs;
 436         void __iomem *sram;
 437         dma_addr_t sram_dma;
 438         spinlock_t lock;
 439         struct crypto_async_request *req;
 440         struct clk *clk;
 441         struct clk *zclk;
 442         size_t max_req_len;
 443         u32 int_mask;
 444         struct gen_pool *pool;
 445 };
 446
 447 /**
 448  * struct mv_cesa_req_ops - CESA request operations
 449  * @prepare:    prepare a request to be executed on the specified engine
 450  * @process:    process a request chunk result (should return 0 if the
 451  *              operation, -EINPROGRESS if it needs more steps or an error
 452  *              code)
 453  * @step:       launch the crypto operation on the next chunk
 454  * @cleanup:    cleanup the crypto request (release associated data)
 455  */
 456 struct mv_cesa_req_ops {
 457         void (*prepare)(struct crypto_async_request *req,
 458                         struct mv_cesa_engine *engine);
 459         int (*process)(struct crypto_async_request *req, u32 status);
 460         void (*step)(struct crypto_async_request *req);
 461         void (*cleanup)(struct crypto_async_request *req);
 462 };
 463
 464 /**
 465  * struct mv_cesa_ctx - CESA operation context
 466  * @ops:        crypto operations
 467  *
 468  * Base context structure inherited by operation specific ones.
 469  */
 470 struct mv_cesa_ctx {
 471         const struct mv_cesa_req_ops *ops;
 472 };
 473
 474 /**
 475  * struct mv_cesa_hash_ctx - CESA hash operation context
 476  * @base:       base context structure
 477  *
 478  * Hash context structure.
 479  */
 480 struct mv_cesa_hash_ctx {
 481         struct mv_cesa_ctx base;
 482 };
 483
 484 /**
 485  * struct mv_cesa_hash_ctx - CESA hmac operation context
 486  * @base:       base context structure
 487  * @iv:         initialization vectors
 488  *
 489  * HMAC context structure.
 490  */
 491 struct mv_cesa_hmac_ctx {
 492         struct mv_cesa_ctx base;
 493         u32 iv[16];
 494 };
 495
 496 /**
 497  * enum mv_cesa_req_type - request type definitions
 498  * @CESA_STD_REQ:       standard request
 499  * @CESA_DMA_REQ:       DMA request
 500  */
 501 enum mv_cesa_req_type {
 502         CESA_STD_REQ,
 503         CESA_DMA_REQ,
 504 };
 505
 506 /**
 507  * struct mv_cesa_req - CESA request
 508  * @type:       request type
 509  * @engine:     engine associated with this request
 510  */
 511 struct mv_cesa_req {
 512         enum mv_cesa_req_type type;
 513         struct mv_cesa_engine *engine;
 514 };
 515
 516 /**
 517  * struct mv_cesa_tdma_req - CESA TDMA request
 518  * @base:       base information
 519  * @chain:      TDMA chain
 520  */
 521 struct mv_cesa_tdma_req {
 522         struct mv_cesa_req base;
 523         struct mv_cesa_tdma_chain chain;
 524 };
 525
 526 /**
 527  * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
 528  *                              requests
 529  * @iter:       sg mapping iterator
 530  * @offset:     current offset in the SG entry mapped in memory
 531  */
 532 struct mv_cesa_sg_std_iter {
 533         struct sg_mapping_iter iter;
 534         unsigned int offset;
 535 };
 536
 537 /**
 538  * struct mv_cesa_ablkcipher_std_req - cipher standard request
 539  * @base:       base information
 540  * @op:         operation context
 541  * @offset:     current operation offset
 542  * @size:       size of the crypto operation
 543  */
 544 struct mv_cesa_ablkcipher_std_req {
 545         struct mv_cesa_req base;
 546         struct mv_cesa_op_ctx op;
 547         unsigned int offset;
 548         unsigned int size;
 549         bool skip_ctx;
 550 };
 551
 552 /**
 553  * struct mv_cesa_ablkcipher_req - cipher request
 554  * @req:        type specific request information
 555  * @src_nents:  number of entries in the src sg list
 556  * @dst_nents:  number of entries in the dest sg list
 557  */
 558 struct mv_cesa_ablkcipher_req {
 559         union {
 560                 struct mv_cesa_req base;
 561                 struct mv_cesa_tdma_req dma;
 562                 struct mv_cesa_ablkcipher_std_req std;
 563         } req;
 564         int src_nents;
 565         int dst_nents;
 566 };
 567
 568 /**
 569  * struct mv_cesa_ahash_std_req - standard hash request
 570  * @base:       base information
 571  * @offset:     current operation offset
 572  */
 573 struct mv_cesa_ahash_std_req {
 574         struct mv_cesa_req base;
 575         unsigned int offset;
 576 };
 577
 578 /**
 579  * struct mv_cesa_ahash_dma_req - DMA hash request
 580  * @base:               base information
 581  * @padding:            padding buffer
 582  * @padding_dma:        DMA address of the padding buffer
 583  * @cache_dma:          DMA address of the cache buffer
 584  */
 585 struct mv_cesa_ahash_dma_req {
 586         struct mv_cesa_tdma_req base;
 587         u8 *padding;
 588         dma_addr_t padding_dma;
 589         dma_addr_t cache_dma;
 590 };
 591
 592 /**
 593  * struct mv_cesa_ahash_req - hash request
 594  * @req:                type specific request information
 595  * @cache:              cache buffer
 596  * @cache_ptr:          write pointer in the cache buffer
 597  * @len:                hash total length
 598  * @src_nents:          number of entries in the scatterlist
 599  * @last_req:           define whether the current operation is the last one
 600  *                      or not
 601  * @state:              hash state
 602  */
 603 struct mv_cesa_ahash_req {
 604         union {
 605                 struct mv_cesa_req base;
 606                 struct mv_cesa_ahash_dma_req dma;
 607                 struct mv_cesa_ahash_std_req std;
 608         } req;
 609         struct mv_cesa_op_ctx op_tmpl;
 610         u8 *cache;
 611         unsigned int cache_ptr;
 612         u64 len;
 613         int src_nents;
 614         bool last_req;
 615         __be32 state[8];
 616 };
 617
 618 /* CESA functions */
 619
 620 extern struct mv_cesa_dev *cesa_dev;
 621
 622 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
 623                                          u32 cfg, u32 mask)
 624 {
 625         op->desc.config &= cpu_to_le32(~mask);
 626         op->desc.config |= cpu_to_le32(cfg);
 627 }
 628
 629 static inline u32 mv_cesa_get_op_cfg(struct mv_cesa_op_ctx *op)
 630 {
 631         return le32_to_cpu(op->desc.config);
 632 }
 633
 634 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
 635 {
 636         op->desc.config = cpu_to_le32(cfg);
 637 }
 638
 639 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
 640                                      struct mv_cesa_op_ctx *op)
 641 {
 642         u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
 643
 644         op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
 645         op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
 646         op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
 647         op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
 648         op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
 649         op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
 650         op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
 651         op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
 652 }
 653
 654 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
 655 {
 656         op->desc.enc_len = cpu_to_le32(len);
 657 }
 658
 659 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
 660                                                 int len)
 661 {
 662         op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
 663         op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
 664 }
 665
 666 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
 667                                                int len)
 668 {
 669         op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
 670         op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
 671 }
 672
 673 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
 674                                         u32 int_mask)
 675 {
 676         if (int_mask == engine->int_mask)
 677                 return;
 678
 679         writel(int_mask, engine->regs + CESA_SA_INT_MSK);
 680         engine->int_mask = int_mask;
 681 }
 682
 683 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
 684 {
 685         return engine->int_mask;
 686 }
 687
 688 int mv_cesa_queue_req(struct crypto_async_request *req);
 689
 690 /* TDMA functions */
 691
 692 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
 693                                              unsigned int len)
 694 {
 695         iter->len = len;
 696         iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
 697         iter->offset = 0;
 698 }
 699
 700 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
 701                                             struct scatterlist *sg,
 702                                             enum dma_data_direction dir)
 703 {
 704         iter->op_offset = 0;
 705         iter->offset = 0;
 706         iter->sg = sg;
 707         iter->dir = dir;
 708 }
 709
 710 static inline unsigned int
 711 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
 712                                   struct mv_cesa_sg_dma_iter *sgiter)
 713 {
 714         return min(iter->op_len - sgiter->op_offset,
 715                    sg_dma_len(sgiter->sg) - sgiter->offset);
 716 }
 717
 718 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
 719                                         struct mv_cesa_sg_dma_iter *sgiter,
 720                                         unsigned int len);
 721
 722 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
 723 {
 724         iter->offset += iter->op_len;
 725         iter->op_len = min(iter->len - iter->offset,
 726                            CESA_SA_SRAM_PAYLOAD_SIZE);
 727
 728         return iter->op_len;
 729 }
 730
 731 void mv_cesa_dma_step(struct mv_cesa_tdma_req *dreq);
 732
 733 static inline int mv_cesa_dma_process(struct mv_cesa_tdma_req *dreq,
 734                                       u32 status)
 735 {
 736         if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
 737                 return -EINPROGRESS;
 738
 739         if (status & CESA_SA_INT_IDMA_OWN_ERR)
 740                 return -EINVAL;
 741
 742         return 0;
 743 }
 744
 745 void mv_cesa_dma_prepare(struct mv_cesa_tdma_req *dreq,
 746                          struct mv_cesa_engine *engine);
 747
 748 void mv_cesa_dma_cleanup(struct mv_cesa_tdma_req *dreq);
 749
 750 static inline void
 751 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
 752 {
 753         memset(chain, 0, sizeof(*chain));
 754 }
 755
 756 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
 757                                         const struct mv_cesa_op_ctx *op_templ,
 758                                         bool skip_ctx,
 759                                         gfp_t flags);
 760
 761 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
 762                                   dma_addr_t dst, dma_addr_t src, u32 size,
 763                                   u32 flags, gfp_t gfp_flags);
 764
 765 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain,
 766                                  u32 flags);
 767
 768 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, u32 flags);
 769
 770 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
 771                                  struct mv_cesa_dma_iter *dma_iter,
 772                                  struct mv_cesa_sg_dma_iter *sgiter,
 773                                  gfp_t gfp_flags);
 774
 775 /* Algorithm definitions */
 776
 777 extern struct ahash_alg mv_md5_alg;
 778 extern struct ahash_alg mv_sha1_alg;
 779 extern struct ahash_alg mv_sha256_alg;
 780 extern struct ahash_alg mv_ahmac_md5_alg;
 781 extern struct ahash_alg mv_ahmac_sha1_alg;
 782 extern struct ahash_alg mv_ahmac_sha256_alg;
 783
 784 extern struct crypto_alg mv_cesa_ecb_des_alg;
 785 extern struct crypto_alg mv_cesa_cbc_des_alg;
 786 extern struct crypto_alg mv_cesa_ecb_des3_ede_alg;
 787 extern struct crypto_alg mv_cesa_cbc_des3_ede_alg;
 788 extern struct crypto_alg mv_cesa_ecb_aes_alg;
 789 extern struct crypto_alg mv_cesa_cbc_aes_alg;
 790
 791 #endif /* __MARVELL_CESA_H__ */