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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/crypto/mv_cesa.h
1 #ifndef __MV_CRYPTO_H__
3 #define DIGEST_INITIAL_VAL_A 0xdd00
4 #define DES_CMD_REG 0xdd58
6 #define SEC_ACCEL_CMD 0xde00
7 #define SEC_CMD_EN_SEC_ACCL0 (1 << 0)
8 #define SEC_CMD_EN_SEC_ACCL1 (1 << 1)
9 #define SEC_CMD_DISABLE_SEC (1 << 2)
11 #define SEC_ACCEL_DESC_P0 0xde04
12 #define SEC_DESC_P0_PTR(x) (x)
14 #define SEC_ACCEL_DESC_P1 0xde14
15 #define SEC_DESC_P1_PTR(x) (x)
17 #define SEC_ACCEL_CFG 0xde08
18 #define SEC_CFG_STOP_DIG_ERR (1 << 0)
19 #define SEC_CFG_CH0_W_IDMA (1 << 7)
20 #define SEC_CFG_CH1_W_IDMA (1 << 8)
21 #define SEC_CFG_ACT_CH0_IDMA (1 << 9)
22 #define SEC_CFG_ACT_CH1_IDMA (1 << 10)
24 #define SEC_ACCEL_STATUS 0xde0c
25 #define SEC_ST_ACT_0 (1 << 0)
26 #define SEC_ST_ACT_1 (1 << 1)
29 * FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
30 * 4.12. It looks like that it was part of an IRQ-controller in FPGA and
31 * someone forgot to remove it while switching to the core and moving to
32 * SEC_ACCEL_INT_STATUS.
34 #define FPGA_INT_STATUS 0xdd68
35 #define SEC_ACCEL_INT_STATUS 0xde20
36 #define SEC_INT_AUTH_DONE (1 << 0)
37 #define SEC_INT_DES_E_DONE (1 << 1)
38 #define SEC_INT_AES_E_DONE (1 << 2)
39 #define SEC_INT_AES_D_DONE (1 << 3)
40 #define SEC_INT_ENC_DONE (1 << 4)
41 #define SEC_INT_ACCEL0_DONE (1 << 5)
42 #define SEC_INT_ACCEL1_DONE (1 << 6)
43 #define SEC_INT_ACC0_IDMA_DONE (1 << 7)
44 #define SEC_INT_ACC1_IDMA_DONE (1 << 8)
46 #define SEC_ACCEL_INT_MASK 0xde24
48 #define AES_KEY_LEN (8 * 4)
50 struct sec_accel_config
{
53 #define CFG_OP_MAC_ONLY 0
54 #define CFG_OP_CRYPT_ONLY 1
55 #define CFG_OP_MAC_CRYPT 2
56 #define CFG_OP_CRYPT_MAC 3
57 #define CFG_MACM_MD5 (4 << 4)
58 #define CFG_MACM_SHA1 (5 << 4)
59 #define CFG_MACM_HMAC_MD5 (6 << 4)
60 #define CFG_MACM_HMAC_SHA1 (7 << 4)
61 #define CFG_ENCM_DES (1 << 8)
62 #define CFG_ENCM_3DES (2 << 8)
63 #define CFG_ENCM_AES (3 << 8)
64 #define CFG_DIR_ENC (0 << 12)
65 #define CFG_DIR_DEC (1 << 12)
66 #define CFG_ENC_MODE_ECB (0 << 16)
67 #define CFG_ENC_MODE_CBC (1 << 16)
68 #define CFG_3DES_EEE (0 << 20)
69 #define CFG_3DES_EDE (1 << 20)
70 #define CFG_AES_LEN_128 (0 << 24)
71 #define CFG_AES_LEN_192 (1 << 24)
72 #define CFG_AES_LEN_256 (2 << 24)
75 #define ENC_P_SRC(x) (x)
76 #define ENC_P_DST(x) ((x) << 16)
79 #define ENC_LEN(x) (x)
82 #define ENC_KEY_P(x) (x)
85 #define ENC_IV_POINT(x) ((x) << 0)
86 #define ENC_IV_BUF_POINT(x) ((x) << 16)
89 #define MAC_SRC_DATA_P(x) (x)
90 #define MAC_SRC_TOTAL_LEN(x) ((x) << 16)
94 }__attribute__ ((packed
));
102 * |-----------| 0x40 (inplace)
105 * | DATA IN | 16 * x (max ->max_req_size)
106 * |-----------| 0x50 (inplace operation)
107 * | DATA OUT | 16 * x (max ->max_req_size)
108 * \-----------/ SRAM size
110 #define SRAM_CONFIG 0x00
111 #define SRAM_DATA_KEY_P 0x20
112 #define SRAM_DATA_IV 0x40
113 #define SRAM_DATA_IV_BUF 0x40
114 #define SRAM_DATA_IN_START 0x50
115 #define SRAM_DATA_OUT_START 0x50
117 #define SRAM_CFG_SPACE 0x50