drivers/crypto/nx/nx-sha256.c

   1 /**
   2  * SHA-256 routines supporting the Power 7+ Nest Accelerators driver
   3  *
   4  * Copyright (C) 2011-2012 International Business Machines Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 only.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Author: Kent Yoder <yoder1@us.ibm.com>
  20  */
  21
  22 #include <crypto/internal/hash.h>
  23 #include <crypto/sha.h>
  24 #include <linux/module.h>
  25 #include <asm/vio.h>
  26 #include <asm/byteorder.h>
  27
  28 #include "nx_csbcpb.h"
  29 #include "nx.h"
  30
  31
  32 static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
  33 {
  34         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
  35         int err;
  36
  37         err = nx_crypto_ctx_sha_init(tfm);
  38         if (err)
  39                 return err;
  40
  41         nx_ctx_init(nx_ctx, HCOP_FC_SHA);
  42
  43         nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];
  44
  45         NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);
  46
  47         return 0;
  48 }
  49
  50 static int nx_sha256_init(struct shash_desc *desc) {
  51         struct sha256_state *sctx = shash_desc_ctx(desc);
  52
  53         memset(sctx, 0, sizeof *sctx);
  54
  55         sctx->state[0] = __cpu_to_be32(SHA256_H0);
  56         sctx->state[1] = __cpu_to_be32(SHA256_H1);
  57         sctx->state[2] = __cpu_to_be32(SHA256_H2);
  58         sctx->state[3] = __cpu_to_be32(SHA256_H3);
  59         sctx->state[4] = __cpu_to_be32(SHA256_H4);
  60         sctx->state[5] = __cpu_to_be32(SHA256_H5);
  61         sctx->state[6] = __cpu_to_be32(SHA256_H6);
  62         sctx->state[7] = __cpu_to_be32(SHA256_H7);
  63         sctx->count = 0;
  64
  65         return 0;
  66 }
  67
  68 static int nx_sha256_update(struct shash_desc *desc, const u8 *data,
  69                             unsigned int len)
  70 {
  71         struct sha256_state *sctx = shash_desc_ctx(desc);
  72         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
  73         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
  74         struct nx_sg *in_sg;
  75         struct nx_sg *out_sg;
  76         u64 to_process = 0, leftover, total;
  77         unsigned long irq_flags;
  78         int rc = 0;
  79         int data_len;
  80         u32 max_sg_len;
  81         u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);
  82
  83         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
  84
  85         /* 2 cases for total data len:
  86          *  1: < SHA256_BLOCK_SIZE: copy into state, return 0
  87          *  2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
  88          */
  89         total = (sctx->count % SHA256_BLOCK_SIZE) + len;
  90         if (total < SHA256_BLOCK_SIZE) {
  91                 memcpy(sctx->buf + buf_len, data, len);
  92                 sctx->count += len;
  93                 goto out;
  94         }
  95
  96         memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
  97         NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
  98         NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
  99
 100         in_sg = nx_ctx->in_sg;
 101         max_sg_len = min_t(u64, nx_ctx->ap->sglen,
 102                         nx_driver.of.max_sg_len/sizeof(struct nx_sg));
 103         max_sg_len = min_t(u64, max_sg_len,
 104                         nx_ctx->ap->databytelen/NX_PAGE_SIZE);
 105
 106         data_len = SHA256_DIGEST_SIZE;
 107         out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
 108                                   &data_len, max_sg_len);
 109         nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
 110
 111         if (data_len != SHA256_DIGEST_SIZE) {
 112                 rc = -EINVAL;
 113                 goto out;
 114         }
 115
 116         do {
 117                 /*
 118                  * to_process: the SHA256_BLOCK_SIZE data chunk to process in
 119                  * this update. This value is also restricted by the sg list
 120                  * limits.
 121                  */
 122                 to_process = total - to_process;
 123                 to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);
 124
 125                 if (buf_len) {
 126                         data_len = buf_len;
 127                         in_sg = nx_build_sg_list(nx_ctx->in_sg,
 128                                                  (u8 *) sctx->buf,
 129                                                  &data_len,
 130                                                  max_sg_len);
 131
 132                         if (data_len != buf_len) {
 133                                 rc = -EINVAL;
 134                                 goto out;
 135                         }
 136                 }
 137
 138                 data_len = to_process - buf_len;
 139                 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
 140                                          &data_len, max_sg_len);
 141
 142                 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
 143
 144                 to_process = (data_len + buf_len);
 145                 leftover = total - to_process;
 146
 147                 /*
 148                  * we've hit the nx chip previously and we're updating
 149                  * again, so copy over the partial digest.
 150                  */
 151                 memcpy(csbcpb->cpb.sha256.input_partial_digest,
 152                                csbcpb->cpb.sha256.message_digest,
 153                                SHA256_DIGEST_SIZE);
 154
 155                 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
 156                         rc = -EINVAL;
 157                         goto out;
 158                 }
 159
 160                 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 161                                    desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 162                 if (rc)
 163                         goto out;
 164
 165                 atomic_inc(&(nx_ctx->stats->sha256_ops));
 166
 167                 total -= to_process;
 168                 data += to_process - buf_len;
 169                 buf_len = 0;
 170
 171         } while (leftover >= SHA256_BLOCK_SIZE);
 172
 173         /* copy the leftover back into the state struct */
 174         if (leftover)
 175                 memcpy(sctx->buf, data, leftover);
 176
 177         sctx->count += len;
 178         memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
 179 out:
 180         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 181         return rc;
 182 }
 183
 184 static int nx_sha256_final(struct shash_desc *desc, u8 *out)
 185 {
 186         struct sha256_state *sctx = shash_desc_ctx(desc);
 187         struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
 188         struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
 189         struct nx_sg *in_sg, *out_sg;
 190         unsigned long irq_flags;
 191         u32 max_sg_len;
 192         int rc = 0;
 193         int len;
 194
 195         spin_lock_irqsave(&nx_ctx->lock, irq_flags);
 196
 197         max_sg_len = min_t(u64, nx_ctx->ap->sglen,
 198                         nx_driver.of.max_sg_len/sizeof(struct nx_sg));
 199         max_sg_len = min_t(u64, max_sg_len,
 200                         nx_ctx->ap->databytelen/NX_PAGE_SIZE);
 201
 202         /* final is represented by continuing the operation and indicating that
 203          * this is not an intermediate operation */
 204         if (sctx->count >= SHA256_BLOCK_SIZE) {
 205                 /* we've hit the nx chip previously, now we're finalizing,
 206                  * so copy over the partial digest */
 207                 memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
 208                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 209                 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
 210         } else {
 211                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
 212                 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
 213         }
 214
 215         csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);
 216
 217         len = sctx->count & (SHA256_BLOCK_SIZE - 1);
 218         in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
 219                                  &len, max_sg_len);
 220
 221         if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
 222                 rc = -EINVAL;
 223                 goto out;
 224         }
 225
 226         len = SHA256_DIGEST_SIZE;
 227         out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);
 228
 229         if (len != SHA256_DIGEST_SIZE) {
 230                 rc = -EINVAL;
 231                 goto out;
 232         }
 233
 234         nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
 235         nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
 236         if (!nx_ctx->op.outlen) {
 237                 rc = -EINVAL;
 238                 goto out;
 239         }
 240
 241         rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
 242                            desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
 243         if (rc)
 244                 goto out;
 245
 246         atomic_inc(&(nx_ctx->stats->sha256_ops));
 247
 248         atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
 249         memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
 250 out:
 251         spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
 252         return rc;
 253 }
 254
 255 static int nx_sha256_export(struct shash_desc *desc, void *out)
 256 {
 257         struct sha256_state *sctx = shash_desc_ctx(desc);
 258
 259         memcpy(out, sctx, sizeof(*sctx));
 260
 261         return 0;
 262 }
 263
 264 static int nx_sha256_import(struct shash_desc *desc, const void *in)
 265 {
 266         struct sha256_state *sctx = shash_desc_ctx(desc);
 267
 268         memcpy(sctx, in, sizeof(*sctx));
 269
 270         return 0;
 271 }
 272
 273 struct shash_alg nx_shash_sha256_alg = {
 274         .digestsize = SHA256_DIGEST_SIZE,
 275         .init       = nx_sha256_init,
 276         .update     = nx_sha256_update,
 277         .final      = nx_sha256_final,
 278         .export     = nx_sha256_export,
 279         .import     = nx_sha256_import,
 280         .descsize   = sizeof(struct sha256_state),
 281         .statesize  = sizeof(struct sha256_state),
 282         .base       = {
 283                 .cra_name        = "sha256",
 284                 .cra_driver_name = "sha256-nx",
 285                 .cra_priority    = 300,
 286                 .cra_flags       = CRYPTO_ALG_TYPE_SHASH,
 287                 .cra_blocksize   = SHA256_BLOCK_SIZE,
 288                 .cra_module      = THIS_MODULE,
 289                 .cra_ctxsize     = sizeof(struct nx_crypto_ctx),
 290                 .cra_init        = nx_crypto_ctx_sha256_init,
 291                 .cra_exit        = nx_crypto_ctx_exit,
 292         }
 293 };