2 * Support for OMAP DES and Triple DES HW acceleration.
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
13 #define pr_fmt(fmt) "%s: " fmt, __func__
16 #define prn(num) printk(#num "=%d\n", num)
17 #define prx(num) printk(#num "=%x\n", num)
19 #define prn(num) do { } while (0)
20 #define prx(num) do { } while (0)
23 #include <linux/err.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/kernel.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
36 #include <linux/of_address.h>
38 #include <linux/crypto.h>
39 #include <linux/interrupt.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/des.h>
43 #define DST_MAXBURST 2
45 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
47 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
49 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
52 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
54 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55 #define DES_REG_CTRL_CBC BIT(4)
56 #define DES_REG_CTRL_TDES BIT(3)
57 #define DES_REG_CTRL_DIRECTION BIT(2)
58 #define DES_REG_CTRL_INPUT_READY BIT(1)
59 #define DES_REG_CTRL_OUTPUT_READY BIT(0)
61 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
63 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
65 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
67 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
69 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71 #define DES_REG_IRQ_DATA_IN BIT(1)
72 #define DES_REG_IRQ_DATA_OUT BIT(2)
74 #define FLAGS_MODE_MASK 0x000f
75 #define FLAGS_ENCRYPT BIT(0)
76 #define FLAGS_CBC BIT(1)
77 #define FLAGS_INIT BIT(4)
78 #define FLAGS_BUSY BIT(6)
81 struct omap_des_dev
*dd
;
84 u32 key
[(3 * DES_KEY_SIZE
) / sizeof(u32
)];
88 struct omap_des_reqctx
{
92 #define OMAP_DES_QUEUE_LENGTH 1
93 #define OMAP_DES_CACHE_SIZE 0
95 struct omap_des_algs_info
{
96 struct crypto_alg
*algs_list
;
98 unsigned int registered
;
101 struct omap_des_pdata
{
102 struct omap_des_algs_info
*algs_info
;
103 unsigned int algs_info_size
;
105 void (*trigger
)(struct omap_des_dev
*dd
, int length
);
126 struct omap_des_dev
{
127 struct list_head list
;
128 unsigned long phys_base
;
129 void __iomem
*io_base
;
130 struct omap_des_ctx
*ctx
;
135 /* spinlock used for queues */
137 struct crypto_queue queue
;
139 struct tasklet_struct done_task
;
140 struct tasklet_struct queue_task
;
142 struct ablkcipher_request
*req
;
144 * total is used by PIO mode for book keeping so introduce
145 * variable total_save as need it to calc page_order
150 struct scatterlist
*in_sg
;
151 struct scatterlist
*out_sg
;
153 /* Buffers for copying for unaligned cases */
154 struct scatterlist in_sgl
;
155 struct scatterlist out_sgl
;
156 struct scatterlist
*orig_out
;
159 struct scatter_walk in_walk
;
160 struct scatter_walk out_walk
;
162 struct dma_chan
*dma_lch_in
;
164 struct dma_chan
*dma_lch_out
;
168 const struct omap_des_pdata
*pdata
;
171 /* keep registered devices data here */
172 static LIST_HEAD(dev_list
);
173 static DEFINE_SPINLOCK(list_lock
);
176 #define omap_des_read(dd, offset) \
179 _read_ret = __raw_readl(dd->io_base + offset); \
180 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
181 offset, _read_ret); \
185 static inline u32
omap_des_read(struct omap_des_dev
*dd
, u32 offset
)
187 return __raw_readl(dd
->io_base
+ offset
);
192 #define omap_des_write(dd, offset, value) \
194 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
196 __raw_writel(value, dd->io_base + offset); \
199 static inline void omap_des_write(struct omap_des_dev
*dd
, u32 offset
,
202 __raw_writel(value
, dd
->io_base
+ offset
);
206 static inline void omap_des_write_mask(struct omap_des_dev
*dd
, u32 offset
,
211 val
= omap_des_read(dd
, offset
);
214 omap_des_write(dd
, offset
, val
);
217 static void omap_des_write_n(struct omap_des_dev
*dd
, u32 offset
,
218 u32
*value
, int count
)
220 for (; count
--; value
++, offset
+= 4)
221 omap_des_write(dd
, offset
, *value
);
224 static int omap_des_hw_init(struct omap_des_dev
*dd
)
227 * clocks are enabled when request starts and disabled when finished.
228 * It may be long delays between requests.
229 * Device might go to off mode to save power.
231 pm_runtime_get_sync(dd
->dev
);
233 if (!(dd
->flags
& FLAGS_INIT
)) {
234 dd
->flags
|= FLAGS_INIT
;
241 static int omap_des_write_ctrl(struct omap_des_dev
*dd
)
245 u32 val
= 0, mask
= 0;
247 err
= omap_des_hw_init(dd
);
251 key32
= dd
->ctx
->keylen
/ sizeof(u32
);
253 /* it seems a key should always be set even if it has not changed */
254 for (i
= 0; i
< key32
; i
++) {
255 omap_des_write(dd
, DES_REG_KEY(dd
, i
),
256 __le32_to_cpu(dd
->ctx
->key
[i
]));
259 if ((dd
->flags
& FLAGS_CBC
) && dd
->req
->info
)
260 omap_des_write_n(dd
, DES_REG_IV(dd
, 0), dd
->req
->info
, 2);
262 if (dd
->flags
& FLAGS_CBC
)
263 val
|= DES_REG_CTRL_CBC
;
264 if (dd
->flags
& FLAGS_ENCRYPT
)
265 val
|= DES_REG_CTRL_DIRECTION
;
267 val
|= DES_REG_CTRL_TDES
;
269 mask
|= DES_REG_CTRL_CBC
| DES_REG_CTRL_DIRECTION
| DES_REG_CTRL_TDES
;
271 omap_des_write_mask(dd
, DES_REG_CTRL(dd
), val
, mask
);
276 static void omap_des_dma_trigger_omap4(struct omap_des_dev
*dd
, int length
)
280 omap_des_write(dd
, DES_REG_LENGTH_N(0), length
);
282 val
= dd
->pdata
->dma_start
;
284 if (dd
->dma_lch_out
!= NULL
)
285 val
|= dd
->pdata
->dma_enable_out
;
286 if (dd
->dma_lch_in
!= NULL
)
287 val
|= dd
->pdata
->dma_enable_in
;
289 mask
= dd
->pdata
->dma_enable_out
| dd
->pdata
->dma_enable_in
|
290 dd
->pdata
->dma_start
;
292 omap_des_write_mask(dd
, DES_REG_MASK(dd
), val
, mask
);
295 static void omap_des_dma_stop(struct omap_des_dev
*dd
)
299 mask
= dd
->pdata
->dma_enable_out
| dd
->pdata
->dma_enable_in
|
300 dd
->pdata
->dma_start
;
302 omap_des_write_mask(dd
, DES_REG_MASK(dd
), 0, mask
);
305 static struct omap_des_dev
*omap_des_find_dev(struct omap_des_ctx
*ctx
)
307 struct omap_des_dev
*dd
= NULL
, *tmp
;
309 spin_lock_bh(&list_lock
);
311 list_for_each_entry(tmp
, &dev_list
, list
) {
312 /* FIXME: take fist available des core */
318 /* already found before */
321 spin_unlock_bh(&list_lock
);
326 static void omap_des_dma_out_callback(void *data
)
328 struct omap_des_dev
*dd
= data
;
330 /* dma_lch_out - completed */
331 tasklet_schedule(&dd
->done_task
);
334 static int omap_des_dma_init(struct omap_des_dev
*dd
)
339 dd
->dma_lch_out
= NULL
;
340 dd
->dma_lch_in
= NULL
;
343 dma_cap_set(DMA_SLAVE
, mask
);
345 dd
->dma_lch_in
= dma_request_slave_channel_compat(mask
,
349 if (!dd
->dma_lch_in
) {
350 dev_err(dd
->dev
, "Unable to request in DMA channel\n");
354 dd
->dma_lch_out
= dma_request_slave_channel_compat(mask
,
358 if (!dd
->dma_lch_out
) {
359 dev_err(dd
->dev
, "Unable to request out DMA channel\n");
366 dma_release_channel(dd
->dma_lch_in
);
369 pr_err("error: %d\n", err
);
373 static void omap_des_dma_cleanup(struct omap_des_dev
*dd
)
375 dma_release_channel(dd
->dma_lch_out
);
376 dma_release_channel(dd
->dma_lch_in
);
379 static void sg_copy_buf(void *buf
, struct scatterlist
*sg
,
380 unsigned int start
, unsigned int nbytes
, int out
)
382 struct scatter_walk walk
;
387 scatterwalk_start(&walk
, sg
);
388 scatterwalk_advance(&walk
, start
);
389 scatterwalk_copychunks(buf
, &walk
, nbytes
, out
);
390 scatterwalk_done(&walk
, out
, 0);
393 static int omap_des_crypt_dma(struct crypto_tfm
*tfm
,
394 struct scatterlist
*in_sg
, struct scatterlist
*out_sg
,
395 int in_sg_len
, int out_sg_len
)
397 struct omap_des_ctx
*ctx
= crypto_tfm_ctx(tfm
);
398 struct omap_des_dev
*dd
= ctx
->dd
;
399 struct dma_async_tx_descriptor
*tx_in
, *tx_out
;
400 struct dma_slave_config cfg
;
404 scatterwalk_start(&dd
->in_walk
, dd
->in_sg
);
405 scatterwalk_start(&dd
->out_walk
, dd
->out_sg
);
407 /* Enable DATAIN interrupt and let it take
409 omap_des_write(dd
, DES_REG_IRQ_ENABLE(dd
), 0x2);
413 dma_sync_sg_for_device(dd
->dev
, dd
->in_sg
, in_sg_len
, DMA_TO_DEVICE
);
415 memset(&cfg
, 0, sizeof(cfg
));
417 cfg
.src_addr
= dd
->phys_base
+ DES_REG_DATA_N(dd
, 0);
418 cfg
.dst_addr
= dd
->phys_base
+ DES_REG_DATA_N(dd
, 0);
419 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
420 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
421 cfg
.src_maxburst
= DST_MAXBURST
;
422 cfg
.dst_maxburst
= DST_MAXBURST
;
425 ret
= dmaengine_slave_config(dd
->dma_lch_in
, &cfg
);
427 dev_err(dd
->dev
, "can't configure IN dmaengine slave: %d\n",
432 tx_in
= dmaengine_prep_slave_sg(dd
->dma_lch_in
, in_sg
, in_sg_len
,
434 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
436 dev_err(dd
->dev
, "IN prep_slave_sg() failed\n");
440 /* No callback necessary */
441 tx_in
->callback_param
= dd
;
444 ret
= dmaengine_slave_config(dd
->dma_lch_out
, &cfg
);
446 dev_err(dd
->dev
, "can't configure OUT dmaengine slave: %d\n",
451 tx_out
= dmaengine_prep_slave_sg(dd
->dma_lch_out
, out_sg
, out_sg_len
,
453 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
455 dev_err(dd
->dev
, "OUT prep_slave_sg() failed\n");
459 tx_out
->callback
= omap_des_dma_out_callback
;
460 tx_out
->callback_param
= dd
;
462 dmaengine_submit(tx_in
);
463 dmaengine_submit(tx_out
);
465 dma_async_issue_pending(dd
->dma_lch_in
);
466 dma_async_issue_pending(dd
->dma_lch_out
);
469 dd
->pdata
->trigger(dd
, dd
->total
);
474 static int omap_des_crypt_dma_start(struct omap_des_dev
*dd
)
476 struct crypto_tfm
*tfm
= crypto_ablkcipher_tfm(
477 crypto_ablkcipher_reqtfm(dd
->req
));
480 pr_debug("total: %d\n", dd
->total
);
483 err
= dma_map_sg(dd
->dev
, dd
->in_sg
, dd
->in_sg_len
,
486 dev_err(dd
->dev
, "dma_map_sg() error\n");
490 err
= dma_map_sg(dd
->dev
, dd
->out_sg
, dd
->out_sg_len
,
493 dev_err(dd
->dev
, "dma_map_sg() error\n");
498 err
= omap_des_crypt_dma(tfm
, dd
->in_sg
, dd
->out_sg
, dd
->in_sg_len
,
500 if (err
&& !dd
->pio_only
) {
501 dma_unmap_sg(dd
->dev
, dd
->in_sg
, dd
->in_sg_len
, DMA_TO_DEVICE
);
502 dma_unmap_sg(dd
->dev
, dd
->out_sg
, dd
->out_sg_len
,
509 static void omap_des_finish_req(struct omap_des_dev
*dd
, int err
)
511 struct ablkcipher_request
*req
= dd
->req
;
513 pr_debug("err: %d\n", err
);
515 pm_runtime_put(dd
->dev
);
516 dd
->flags
&= ~FLAGS_BUSY
;
518 req
->base
.complete(&req
->base
, err
);
521 static int omap_des_crypt_dma_stop(struct omap_des_dev
*dd
)
525 pr_debug("total: %d\n", dd
->total
);
527 omap_des_dma_stop(dd
);
529 dmaengine_terminate_all(dd
->dma_lch_in
);
530 dmaengine_terminate_all(dd
->dma_lch_out
);
532 dma_unmap_sg(dd
->dev
, dd
->in_sg
, dd
->in_sg_len
, DMA_TO_DEVICE
);
533 dma_unmap_sg(dd
->dev
, dd
->out_sg
, dd
->out_sg_len
, DMA_FROM_DEVICE
);
538 static int omap_des_copy_needed(struct scatterlist
*sg
)
541 if (!IS_ALIGNED(sg
->offset
, 4))
543 if (!IS_ALIGNED(sg
->length
, DES_BLOCK_SIZE
))
550 static int omap_des_copy_sgs(struct omap_des_dev
*dd
)
552 void *buf_in
, *buf_out
;
555 pages
= dd
->total
>> PAGE_SHIFT
;
557 if (dd
->total
& (PAGE_SIZE
-1))
562 buf_in
= (void *)__get_free_pages(GFP_ATOMIC
, pages
);
563 buf_out
= (void *)__get_free_pages(GFP_ATOMIC
, pages
);
565 if (!buf_in
|| !buf_out
) {
566 pr_err("Couldn't allocated pages for unaligned cases.\n");
570 dd
->orig_out
= dd
->out_sg
;
572 sg_copy_buf(buf_in
, dd
->in_sg
, 0, dd
->total
, 0);
574 sg_init_table(&dd
->in_sgl
, 1);
575 sg_set_buf(&dd
->in_sgl
, buf_in
, dd
->total
);
576 dd
->in_sg
= &dd
->in_sgl
;
578 sg_init_table(&dd
->out_sgl
, 1);
579 sg_set_buf(&dd
->out_sgl
, buf_out
, dd
->total
);
580 dd
->out_sg
= &dd
->out_sgl
;
585 static int omap_des_handle_queue(struct omap_des_dev
*dd
,
586 struct ablkcipher_request
*req
)
588 struct crypto_async_request
*async_req
, *backlog
;
589 struct omap_des_ctx
*ctx
;
590 struct omap_des_reqctx
*rctx
;
594 spin_lock_irqsave(&dd
->lock
, flags
);
596 ret
= ablkcipher_enqueue_request(&dd
->queue
, req
);
597 if (dd
->flags
& FLAGS_BUSY
) {
598 spin_unlock_irqrestore(&dd
->lock
, flags
);
601 backlog
= crypto_get_backlog(&dd
->queue
);
602 async_req
= crypto_dequeue_request(&dd
->queue
);
604 dd
->flags
|= FLAGS_BUSY
;
605 spin_unlock_irqrestore(&dd
->lock
, flags
);
611 backlog
->complete(backlog
, -EINPROGRESS
);
613 req
= ablkcipher_request_cast(async_req
);
615 /* assign new request to device */
617 dd
->total
= req
->nbytes
;
618 dd
->total_save
= req
->nbytes
;
619 dd
->in_sg
= req
->src
;
620 dd
->out_sg
= req
->dst
;
622 if (omap_des_copy_needed(dd
->in_sg
) ||
623 omap_des_copy_needed(dd
->out_sg
)) {
624 if (omap_des_copy_sgs(dd
))
625 pr_err("Failed to copy SGs for unaligned cases\n");
631 dd
->in_sg_len
= scatterwalk_bytes_sglen(dd
->in_sg
, dd
->total
);
632 dd
->out_sg_len
= scatterwalk_bytes_sglen(dd
->out_sg
, dd
->total
);
633 BUG_ON(dd
->in_sg_len
< 0 || dd
->out_sg_len
< 0);
635 rctx
= ablkcipher_request_ctx(req
);
636 ctx
= crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req
));
637 rctx
->mode
&= FLAGS_MODE_MASK
;
638 dd
->flags
= (dd
->flags
& ~FLAGS_MODE_MASK
) | rctx
->mode
;
643 err
= omap_des_write_ctrl(dd
);
645 err
= omap_des_crypt_dma_start(dd
);
647 /* des_task will not finish it, so do it here */
648 omap_des_finish_req(dd
, err
);
649 tasklet_schedule(&dd
->queue_task
);
652 return ret
; /* return ret, which is enqueue return value */
655 static void omap_des_done_task(unsigned long data
)
657 struct omap_des_dev
*dd
= (struct omap_des_dev
*)data
;
658 void *buf_in
, *buf_out
;
661 pr_debug("enter done_task\n");
664 dma_sync_sg_for_device(dd
->dev
, dd
->out_sg
, dd
->out_sg_len
,
666 dma_unmap_sg(dd
->dev
, dd
->in_sg
, dd
->in_sg_len
, DMA_TO_DEVICE
);
667 dma_unmap_sg(dd
->dev
, dd
->out_sg
, dd
->out_sg_len
,
669 omap_des_crypt_dma_stop(dd
);
672 if (dd
->sgs_copied
) {
673 buf_in
= sg_virt(&dd
->in_sgl
);
674 buf_out
= sg_virt(&dd
->out_sgl
);
676 sg_copy_buf(buf_out
, dd
->orig_out
, 0, dd
->total_save
, 1);
678 pages
= get_order(dd
->total_save
);
679 free_pages((unsigned long)buf_in
, pages
);
680 free_pages((unsigned long)buf_out
, pages
);
683 omap_des_finish_req(dd
, 0);
684 omap_des_handle_queue(dd
, NULL
);
689 static void omap_des_queue_task(unsigned long data
)
691 struct omap_des_dev
*dd
= (struct omap_des_dev
*)data
;
693 omap_des_handle_queue(dd
, NULL
);
696 static int omap_des_crypt(struct ablkcipher_request
*req
, unsigned long mode
)
698 struct omap_des_ctx
*ctx
= crypto_ablkcipher_ctx(
699 crypto_ablkcipher_reqtfm(req
));
700 struct omap_des_reqctx
*rctx
= ablkcipher_request_ctx(req
);
701 struct omap_des_dev
*dd
;
703 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req
->nbytes
,
704 !!(mode
& FLAGS_ENCRYPT
),
705 !!(mode
& FLAGS_CBC
));
707 if (!IS_ALIGNED(req
->nbytes
, DES_BLOCK_SIZE
)) {
708 pr_err("request size is not exact amount of DES blocks\n");
712 dd
= omap_des_find_dev(ctx
);
718 return omap_des_handle_queue(dd
, req
);
721 /* ********************** ALG API ************************************ */
723 static int omap_des_setkey(struct crypto_ablkcipher
*tfm
, const u8
*key
,
726 struct omap_des_ctx
*ctx
= crypto_ablkcipher_ctx(tfm
);
728 if (keylen
!= DES_KEY_SIZE
&& keylen
!= (3*DES_KEY_SIZE
))
731 pr_debug("enter, keylen: %d\n", keylen
);
733 memcpy(ctx
->key
, key
, keylen
);
734 ctx
->keylen
= keylen
;
739 static int omap_des_ecb_encrypt(struct ablkcipher_request
*req
)
741 return omap_des_crypt(req
, FLAGS_ENCRYPT
);
744 static int omap_des_ecb_decrypt(struct ablkcipher_request
*req
)
746 return omap_des_crypt(req
, 0);
749 static int omap_des_cbc_encrypt(struct ablkcipher_request
*req
)
751 return omap_des_crypt(req
, FLAGS_ENCRYPT
| FLAGS_CBC
);
754 static int omap_des_cbc_decrypt(struct ablkcipher_request
*req
)
756 return omap_des_crypt(req
, FLAGS_CBC
);
759 static int omap_des_cra_init(struct crypto_tfm
*tfm
)
763 tfm
->crt_ablkcipher
.reqsize
= sizeof(struct omap_des_reqctx
);
768 static void omap_des_cra_exit(struct crypto_tfm
*tfm
)
773 /* ********************** ALGS ************************************ */
775 static struct crypto_alg algs_ecb_cbc
[] = {
777 .cra_name
= "ecb(des)",
778 .cra_driver_name
= "ecb-des-omap",
780 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
|
781 CRYPTO_ALG_KERN_DRIVER_ONLY
|
783 .cra_blocksize
= DES_BLOCK_SIZE
,
784 .cra_ctxsize
= sizeof(struct omap_des_ctx
),
786 .cra_type
= &crypto_ablkcipher_type
,
787 .cra_module
= THIS_MODULE
,
788 .cra_init
= omap_des_cra_init
,
789 .cra_exit
= omap_des_cra_exit
,
790 .cra_u
.ablkcipher
= {
791 .min_keysize
= DES_KEY_SIZE
,
792 .max_keysize
= DES_KEY_SIZE
,
793 .setkey
= omap_des_setkey
,
794 .encrypt
= omap_des_ecb_encrypt
,
795 .decrypt
= omap_des_ecb_decrypt
,
799 .cra_name
= "cbc(des)",
800 .cra_driver_name
= "cbc-des-omap",
802 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
|
803 CRYPTO_ALG_KERN_DRIVER_ONLY
|
805 .cra_blocksize
= DES_BLOCK_SIZE
,
806 .cra_ctxsize
= sizeof(struct omap_des_ctx
),
808 .cra_type
= &crypto_ablkcipher_type
,
809 .cra_module
= THIS_MODULE
,
810 .cra_init
= omap_des_cra_init
,
811 .cra_exit
= omap_des_cra_exit
,
812 .cra_u
.ablkcipher
= {
813 .min_keysize
= DES_KEY_SIZE
,
814 .max_keysize
= DES_KEY_SIZE
,
815 .ivsize
= DES_BLOCK_SIZE
,
816 .setkey
= omap_des_setkey
,
817 .encrypt
= omap_des_cbc_encrypt
,
818 .decrypt
= omap_des_cbc_decrypt
,
822 .cra_name
= "ecb(des3_ede)",
823 .cra_driver_name
= "ecb-des3-omap",
825 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
|
826 CRYPTO_ALG_KERN_DRIVER_ONLY
|
828 .cra_blocksize
= DES_BLOCK_SIZE
,
829 .cra_ctxsize
= sizeof(struct omap_des_ctx
),
831 .cra_type
= &crypto_ablkcipher_type
,
832 .cra_module
= THIS_MODULE
,
833 .cra_init
= omap_des_cra_init
,
834 .cra_exit
= omap_des_cra_exit
,
835 .cra_u
.ablkcipher
= {
836 .min_keysize
= 3*DES_KEY_SIZE
,
837 .max_keysize
= 3*DES_KEY_SIZE
,
838 .setkey
= omap_des_setkey
,
839 .encrypt
= omap_des_ecb_encrypt
,
840 .decrypt
= omap_des_ecb_decrypt
,
844 .cra_name
= "cbc(des3_ede)",
845 .cra_driver_name
= "cbc-des3-omap",
847 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
|
848 CRYPTO_ALG_KERN_DRIVER_ONLY
|
850 .cra_blocksize
= DES_BLOCK_SIZE
,
851 .cra_ctxsize
= sizeof(struct omap_des_ctx
),
853 .cra_type
= &crypto_ablkcipher_type
,
854 .cra_module
= THIS_MODULE
,
855 .cra_init
= omap_des_cra_init
,
856 .cra_exit
= omap_des_cra_exit
,
857 .cra_u
.ablkcipher
= {
858 .min_keysize
= 3*DES_KEY_SIZE
,
859 .max_keysize
= 3*DES_KEY_SIZE
,
860 .ivsize
= DES_BLOCK_SIZE
,
861 .setkey
= omap_des_setkey
,
862 .encrypt
= omap_des_cbc_encrypt
,
863 .decrypt
= omap_des_cbc_decrypt
,
868 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc
[] = {
870 .algs_list
= algs_ecb_cbc
,
871 .size
= ARRAY_SIZE(algs_ecb_cbc
),
876 static const struct omap_des_pdata omap_des_pdata_omap4
= {
877 .algs_info
= omap_des_algs_info_ecb_cbc
,
878 .algs_info_size
= ARRAY_SIZE(omap_des_algs_info_ecb_cbc
),
879 .trigger
= omap_des_dma_trigger_omap4
,
886 .irq_status_ofs
= 0x3c,
887 .irq_enable_ofs
= 0x40,
888 .dma_enable_in
= BIT(5),
889 .dma_enable_out
= BIT(6),
890 .major_mask
= 0x0700,
892 .minor_mask
= 0x003f,
896 static irqreturn_t
omap_des_irq(int irq
, void *dev_id
)
898 struct omap_des_dev
*dd
= dev_id
;
902 status
= omap_des_read(dd
, DES_REG_IRQ_STATUS(dd
));
903 if (status
& DES_REG_IRQ_DATA_IN
) {
904 omap_des_write(dd
, DES_REG_IRQ_ENABLE(dd
), 0x0);
908 BUG_ON(_calc_walked(in
) > dd
->in_sg
->length
);
910 src
= sg_virt(dd
->in_sg
) + _calc_walked(in
);
912 for (i
= 0; i
< DES_BLOCK_WORDS
; i
++) {
913 omap_des_write(dd
, DES_REG_DATA_N(dd
, i
), *src
);
915 scatterwalk_advance(&dd
->in_walk
, 4);
916 if (dd
->in_sg
->length
== _calc_walked(in
)) {
917 dd
->in_sg
= scatterwalk_sg_next(dd
->in_sg
);
919 scatterwalk_start(&dd
->in_walk
,
921 src
= sg_virt(dd
->in_sg
) +
929 /* Clear IRQ status */
930 status
&= ~DES_REG_IRQ_DATA_IN
;
931 omap_des_write(dd
, DES_REG_IRQ_STATUS(dd
), status
);
933 /* Enable DATA_OUT interrupt */
934 omap_des_write(dd
, DES_REG_IRQ_ENABLE(dd
), 0x4);
936 } else if (status
& DES_REG_IRQ_DATA_OUT
) {
937 omap_des_write(dd
, DES_REG_IRQ_ENABLE(dd
), 0x0);
941 BUG_ON(_calc_walked(out
) > dd
->out_sg
->length
);
943 dst
= sg_virt(dd
->out_sg
) + _calc_walked(out
);
945 for (i
= 0; i
< DES_BLOCK_WORDS
; i
++) {
946 *dst
= omap_des_read(dd
, DES_REG_DATA_N(dd
, i
));
947 scatterwalk_advance(&dd
->out_walk
, 4);
948 if (dd
->out_sg
->length
== _calc_walked(out
)) {
949 dd
->out_sg
= scatterwalk_sg_next(dd
->out_sg
);
951 scatterwalk_start(&dd
->out_walk
,
953 dst
= sg_virt(dd
->out_sg
) +
961 dd
->total
-= DES_BLOCK_SIZE
;
963 BUG_ON(dd
->total
< 0);
965 /* Clear IRQ status */
966 status
&= ~DES_REG_IRQ_DATA_OUT
;
967 omap_des_write(dd
, DES_REG_IRQ_STATUS(dd
), status
);
970 /* All bytes read! */
971 tasklet_schedule(&dd
->done_task
);
973 /* Enable DATA_IN interrupt for next block */
974 omap_des_write(dd
, DES_REG_IRQ_ENABLE(dd
), 0x2);
980 static const struct of_device_id omap_des_of_match
[] = {
982 .compatible
= "ti,omap4-des",
983 .data
= &omap_des_pdata_omap4
,
987 MODULE_DEVICE_TABLE(of
, omap_des_of_match
);
989 static int omap_des_get_of(struct omap_des_dev
*dd
,
990 struct platform_device
*pdev
)
992 const struct of_device_id
*match
;
994 match
= of_match_device(of_match_ptr(omap_des_of_match
), &pdev
->dev
);
996 dev_err(&pdev
->dev
, "no compatible OF match\n");
1000 dd
->dma_out
= -1; /* Dummy value that's unused */
1001 dd
->dma_in
= -1; /* Dummy value that's unused */
1002 dd
->pdata
= match
->data
;
1007 static int omap_des_get_of(struct omap_des_dev
*dd
,
1014 static int omap_des_get_pdev(struct omap_des_dev
*dd
,
1015 struct platform_device
*pdev
)
1017 struct device
*dev
= &pdev
->dev
;
1021 /* Get the DMA out channel */
1022 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1024 dev_err(dev
, "no DMA out resource info\n");
1028 dd
->dma_out
= r
->start
;
1030 /* Get the DMA in channel */
1031 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1033 dev_err(dev
, "no DMA in resource info\n");
1037 dd
->dma_in
= r
->start
;
1039 /* non-DT devices get pdata from pdev */
1040 dd
->pdata
= pdev
->dev
.platform_data
;
1046 static int omap_des_probe(struct platform_device
*pdev
)
1048 struct device
*dev
= &pdev
->dev
;
1049 struct omap_des_dev
*dd
;
1050 struct crypto_alg
*algp
;
1051 struct resource
*res
;
1052 int err
= -ENOMEM
, i
, j
, irq
= -1;
1055 dd
= devm_kzalloc(dev
, sizeof(struct omap_des_dev
), GFP_KERNEL
);
1057 dev_err(dev
, "unable to alloc data struct.\n");
1061 platform_set_drvdata(pdev
, dd
);
1063 spin_lock_init(&dd
->lock
);
1064 crypto_init_queue(&dd
->queue
, OMAP_DES_QUEUE_LENGTH
);
1066 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1068 dev_err(dev
, "no MEM resource info\n");
1072 err
= (dev
->of_node
) ? omap_des_get_of(dd
, pdev
) :
1073 omap_des_get_pdev(dd
, pdev
);
1077 dd
->io_base
= devm_request_and_ioremap(dev
, res
);
1079 dev_err(dev
, "can't ioremap\n");
1083 dd
->phys_base
= res
->start
;
1085 pm_runtime_enable(dev
);
1086 pm_runtime_get_sync(dev
);
1088 omap_des_dma_stop(dd
);
1090 reg
= omap_des_read(dd
, DES_REG_REV(dd
));
1092 pm_runtime_put_sync(dev
);
1094 dev_info(dev
, "OMAP DES hw accel rev: %u.%u\n",
1095 (reg
& dd
->pdata
->major_mask
) >> dd
->pdata
->major_shift
,
1096 (reg
& dd
->pdata
->minor_mask
) >> dd
->pdata
->minor_shift
);
1098 tasklet_init(&dd
->done_task
, omap_des_done_task
, (unsigned long)dd
);
1099 tasklet_init(&dd
->queue_task
, omap_des_queue_task
, (unsigned long)dd
);
1101 err
= omap_des_dma_init(dd
);
1102 if (err
&& DES_REG_IRQ_STATUS(dd
) && DES_REG_IRQ_ENABLE(dd
)) {
1105 irq
= platform_get_irq(pdev
, 0);
1107 dev_err(dev
, "can't get IRQ resource\n");
1111 err
= devm_request_irq(dev
, irq
, omap_des_irq
, 0,
1114 dev_err(dev
, "Unable to grab omap-des IRQ\n");
1120 INIT_LIST_HEAD(&dd
->list
);
1121 spin_lock(&list_lock
);
1122 list_add_tail(&dd
->list
, &dev_list
);
1123 spin_unlock(&list_lock
);
1125 for (i
= 0; i
< dd
->pdata
->algs_info_size
; i
++) {
1126 for (j
= 0; j
< dd
->pdata
->algs_info
[i
].size
; j
++) {
1127 algp
= &dd
->pdata
->algs_info
[i
].algs_list
[j
];
1129 pr_debug("reg alg: %s\n", algp
->cra_name
);
1130 INIT_LIST_HEAD(&algp
->cra_list
);
1132 err
= crypto_register_alg(algp
);
1136 dd
->pdata
->algs_info
[i
].registered
++;
1142 for (i
= dd
->pdata
->algs_info_size
- 1; i
>= 0; i
--)
1143 for (j
= dd
->pdata
->algs_info
[i
].registered
- 1; j
>= 0; j
--)
1144 crypto_unregister_alg(
1145 &dd
->pdata
->algs_info
[i
].algs_list
[j
]);
1147 omap_des_dma_cleanup(dd
);
1149 tasklet_kill(&dd
->done_task
);
1150 tasklet_kill(&dd
->queue_task
);
1151 pm_runtime_disable(dev
);
1155 dev_err(dev
, "initialization failed.\n");
1159 static int omap_des_remove(struct platform_device
*pdev
)
1161 struct omap_des_dev
*dd
= platform_get_drvdata(pdev
);
1167 spin_lock(&list_lock
);
1168 list_del(&dd
->list
);
1169 spin_unlock(&list_lock
);
1171 for (i
= dd
->pdata
->algs_info_size
- 1; i
>= 0; i
--)
1172 for (j
= dd
->pdata
->algs_info
[i
].registered
- 1; j
>= 0; j
--)
1173 crypto_unregister_alg(
1174 &dd
->pdata
->algs_info
[i
].algs_list
[j
]);
1176 tasklet_kill(&dd
->done_task
);
1177 tasklet_kill(&dd
->queue_task
);
1178 omap_des_dma_cleanup(dd
);
1179 pm_runtime_disable(dd
->dev
);
1185 #ifdef CONFIG_PM_SLEEP
1186 static int omap_des_suspend(struct device
*dev
)
1188 pm_runtime_put_sync(dev
);
1192 static int omap_des_resume(struct device
*dev
)
1194 pm_runtime_get_sync(dev
);
1199 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops
, omap_des_suspend
, omap_des_resume
);
1201 static struct platform_driver omap_des_driver
= {
1202 .probe
= omap_des_probe
,
1203 .remove
= omap_des_remove
,
1206 .owner
= THIS_MODULE
,
1207 .pm
= &omap_des_pm_ops
,
1208 .of_match_table
= of_match_ptr(omap_des_of_match
),
1212 module_platform_driver(omap_des_driver
);
1214 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1215 MODULE_LICENSE("GPL v2");
1216 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");