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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/crypto/sunxi-ss/sun4i-ss-hash.c
2 * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
6 * This file add support for MD5 and SHA1.
8 * You could find the datasheet in Documentation/arm/sunxi/README
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/scatterlist.h>
18 /* This is a totally arbitrary value */
19 #define SS_TIMEOUT 100
21 int sun4i_hash_crainit(struct crypto_tfm
*tfm
)
23 struct sun4i_tfm_ctx
*op
= crypto_tfm_ctx(tfm
);
24 struct ahash_alg
*alg
= __crypto_ahash_alg(tfm
->__crt_alg
);
25 struct sun4i_ss_alg_template
*algt
;
27 memset(op
, 0, sizeof(struct sun4i_tfm_ctx
));
29 algt
= container_of(alg
, struct sun4i_ss_alg_template
, alg
.hash
);
32 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm
),
33 sizeof(struct sun4i_req_ctx
));
37 /* sun4i_hash_init: initialize request context */
38 int sun4i_hash_init(struct ahash_request
*areq
)
40 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
41 struct crypto_ahash
*tfm
= crypto_ahash_reqtfm(areq
);
42 struct ahash_alg
*alg
= __crypto_ahash_alg(tfm
->base
.__crt_alg
);
43 struct sun4i_ss_alg_template
*algt
;
45 memset(op
, 0, sizeof(struct sun4i_req_ctx
));
47 algt
= container_of(alg
, struct sun4i_ss_alg_template
, alg
.hash
);
48 op
->mode
= algt
->mode
;
53 int sun4i_hash_export_md5(struct ahash_request
*areq
, void *out
)
55 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
56 struct md5_state
*octx
= out
;
59 octx
->byte_count
= op
->byte_count
+ op
->len
;
61 memcpy(octx
->block
, op
->buf
, op
->len
);
64 for (i
= 0; i
< 4; i
++)
65 octx
->hash
[i
] = op
->hash
[i
];
67 octx
->hash
[0] = SHA1_H0
;
68 octx
->hash
[1] = SHA1_H1
;
69 octx
->hash
[2] = SHA1_H2
;
70 octx
->hash
[3] = SHA1_H3
;
76 int sun4i_hash_import_md5(struct ahash_request
*areq
, const void *in
)
78 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
79 const struct md5_state
*ictx
= in
;
82 sun4i_hash_init(areq
);
84 op
->byte_count
= ictx
->byte_count
& ~0x3F;
85 op
->len
= ictx
->byte_count
& 0x3F;
87 memcpy(op
->buf
, ictx
->block
, op
->len
);
89 for (i
= 0; i
< 4; i
++)
90 op
->hash
[i
] = ictx
->hash
[i
];
95 int sun4i_hash_export_sha1(struct ahash_request
*areq
, void *out
)
97 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
98 struct sha1_state
*octx
= out
;
101 octx
->count
= op
->byte_count
+ op
->len
;
103 memcpy(octx
->buffer
, op
->buf
, op
->len
);
105 if (op
->byte_count
) {
106 for (i
= 0; i
< 5; i
++)
107 octx
->state
[i
] = op
->hash
[i
];
109 octx
->state
[0] = SHA1_H0
;
110 octx
->state
[1] = SHA1_H1
;
111 octx
->state
[2] = SHA1_H2
;
112 octx
->state
[3] = SHA1_H3
;
113 octx
->state
[4] = SHA1_H4
;
119 int sun4i_hash_import_sha1(struct ahash_request
*areq
, const void *in
)
121 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
122 const struct sha1_state
*ictx
= in
;
125 sun4i_hash_init(areq
);
127 op
->byte_count
= ictx
->count
& ~0x3F;
128 op
->len
= ictx
->count
& 0x3F;
130 memcpy(op
->buf
, ictx
->buffer
, op
->len
);
132 for (i
= 0; i
< 5; i
++)
133 op
->hash
[i
] = ictx
->state
[i
];
138 #define SS_HASH_UPDATE 1
139 #define SS_HASH_FINAL 2
142 * sun4i_hash_update: update hash engine
144 * Could be used for both SHA1 and MD5
145 * Write data by step of 32bits and put then in the SS.
147 * Since we cannot leave partial data and hash state in the engine,
148 * we need to get the hash state at the end of this function.
149 * We can get the hash state every 64 bytes
151 * So the first work is to get the number of bytes to write to SS modulo 64
152 * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
154 * So at the begin of update()
155 * if op->len + areq->nbytes < 64
156 * => all data will be written to wait buffer (op->buf) and end=0
157 * if not, write all data from op->buf to the device and position end to
158 * complete to 64bytes
161 * update1 60o => op->len=60
162 * update2 60o => need one more word to have 64 bytes
164 * so write all data from op->buf and one word of SGs
165 * write remaining data in op->buf
166 * final state op->len=56
168 static int sun4i_hash(struct ahash_request
*areq
)
171 * i is the total bytes read from SGs, to be compared to areq->nbytes
172 * i is important because we cannot rely on SG length since the sum of
173 * SG->length could be greater than areq->nbytes
175 * end is the position when we need to stop writing to the device,
176 * to be compared to i
178 * in_i: advancement in the current SG
180 unsigned int i
= 0, end
, fill
, min_fill
, nwait
, nbw
= 0, j
= 0, todo
;
181 unsigned int in_i
= 0;
182 u32 spaces
, rx_cnt
= SS_RX_DEFAULT
, bf
[32] = {0}, wb
= 0, v
, ivmode
= 0;
183 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
184 struct crypto_ahash
*tfm
= crypto_ahash_reqtfm(areq
);
185 struct sun4i_tfm_ctx
*tfmctx
= crypto_ahash_ctx(tfm
);
186 struct sun4i_ss_ctx
*ss
= tfmctx
->ss
;
187 struct scatterlist
*in_sg
= areq
->src
;
188 struct sg_mapping_iter mi
;
192 dev_dbg(ss
->dev
, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
193 __func__
, crypto_tfm_alg_name(areq
->base
.tfm
),
194 op
->byte_count
, areq
->nbytes
, op
->mode
,
195 op
->len
, op
->hash
[0]);
197 if (unlikely(!areq
->nbytes
) && !(op
->flags
& SS_HASH_FINAL
))
200 /* protect against overflow */
201 if (unlikely(areq
->nbytes
> UINT_MAX
- op
->len
)) {
202 dev_err(ss
->dev
, "Cannot process too large request\n");
206 if (op
->len
+ areq
->nbytes
< 64 && !(op
->flags
& SS_HASH_FINAL
)) {
207 /* linearize data to op->buf */
208 copied
= sg_pcopy_to_buffer(areq
->src
, sg_nents(areq
->src
),
209 op
->buf
+ op
->len
, areq
->nbytes
, 0);
214 spin_lock_bh(&ss
->slock
);
217 * if some data have been processed before,
218 * we need to restore the partial hash state
220 if (op
->byte_count
) {
221 ivmode
= SS_IV_ARBITRARY
;
222 for (i
= 0; i
< 5; i
++)
223 writel(op
->hash
[i
], ss
->base
+ SS_IV0
+ i
* 4);
225 /* Enable the device */
226 writel(op
->mode
| SS_ENABLED
| ivmode
, ss
->base
+ SS_CTL
);
228 if (!(op
->flags
& SS_HASH_UPDATE
))
231 /* start of handling data */
232 if (!(op
->flags
& SS_HASH_FINAL
)) {
233 end
= ((areq
->nbytes
+ op
->len
) / 64) * 64 - op
->len
;
235 if (end
> areq
->nbytes
|| areq
->nbytes
- end
> 63) {
236 dev_err(ss
->dev
, "ERROR: Bound error %u %u\n",
242 /* Since we have the flag final, we can go up to modulo 4 */
243 if (areq
->nbytes
< 4)
246 end
= ((areq
->nbytes
+ op
->len
) / 4) * 4 - op
->len
;
249 /* TODO if SGlen % 4 and !op->len then DMA */
251 while (in_sg
&& i
== 1) {
252 if (in_sg
->length
% 4)
254 in_sg
= sg_next(in_sg
);
256 if (i
== 1 && !op
->len
&& areq
->nbytes
)
257 dev_dbg(ss
->dev
, "We can DMA\n");
260 sg_miter_start(&mi
, areq
->src
, sg_nents(areq
->src
),
261 SG_MITER_FROM_SG
| SG_MITER_ATOMIC
);
267 * we need to linearize in two case:
268 * - the buffer is already used
269 * - the SG does not have enough byte remaining ( < 4)
271 if (op
->len
|| (mi
.length
- in_i
) < 4) {
273 * if we have entered here we have two reason to stop
274 * - the buffer is full
277 while (op
->len
< 64 && i
< end
) {
278 /* how many bytes we can read from current SG */
279 in_r
= min3(mi
.length
- in_i
, end
- i
,
281 memcpy(op
->buf
+ op
->len
, mi
.addr
+ in_i
, in_r
);
285 if (in_i
== mi
.length
) {
290 if (op
->len
> 3 && !(op
->len
% 4)) {
291 /* write buf to the device */
292 writesl(ss
->base
+ SS_RXFIFO
, op
->buf
,
294 op
->byte_count
+= op
->len
;
298 if (mi
.length
- in_i
> 3 && i
< end
) {
299 /* how many bytes we can read from current SG */
300 in_r
= min3(mi
.length
- in_i
, areq
->nbytes
- i
,
301 ((mi
.length
- in_i
) / 4) * 4);
302 /* how many bytes we can write in the device*/
303 todo
= min3((u32
)(end
- i
) / 4, rx_cnt
, (u32
)in_r
/ 4);
304 writesl(ss
->base
+ SS_RXFIFO
, mi
.addr
+ in_i
, todo
);
305 op
->byte_count
+= todo
* 4;
310 spaces
= readl(ss
->base
+ SS_FCSR
);
311 rx_cnt
= SS_RXFIFO_SPACES(spaces
);
313 if (in_i
== mi
.length
) {
321 * Now we have written to the device all that we can,
322 * store the remaining bytes in op->buf
324 if ((areq
->nbytes
- i
) < 64) {
325 while (i
< areq
->nbytes
&& in_i
< mi
.length
&& op
->len
< 64) {
326 /* how many bytes we can read from current SG */
327 in_r
= min3(mi
.length
- in_i
, areq
->nbytes
- i
,
329 memcpy(op
->buf
+ op
->len
, mi
.addr
+ in_i
, in_r
);
333 if (in_i
== mi
.length
) {
343 * End of data process
344 * Now if we have the flag final go to finalize part
345 * If not, store the partial hash
347 if (op
->flags
& SS_HASH_FINAL
)
350 writel(op
->mode
| SS_ENABLED
| SS_DATA_END
, ss
->base
+ SS_CTL
);
353 v
= readl(ss
->base
+ SS_CTL
);
355 } while (i
< SS_TIMEOUT
&& (v
& SS_DATA_END
));
356 if (unlikely(i
>= SS_TIMEOUT
)) {
357 dev_err_ratelimited(ss
->dev
,
358 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
359 i
, SS_TIMEOUT
, v
, areq
->nbytes
);
365 * The datasheet isn't very clear about when to retrieve the digest. The
366 * bit SS_DATA_END is cleared when the engine has processed the data and
367 * when the digest is computed *but* it doesn't mean the digest is
368 * available in the digest registers. Hence the delay to be sure we can
373 for (i
= 0; i
< crypto_ahash_digestsize(tfm
) / 4; i
++)
374 op
->hash
[i
] = readl(ss
->base
+ SS_MD0
+ i
* 4);
379 * hash_final: finalize hashing operation
381 * If we have some remaining bytes, we write them.
382 * Then ask the SS for finalizing the hashing operation
384 * I do not check RX FIFO size in this function since the size is 32
385 * after each enabling and this function neither write more than 32 words.
386 * If we come from the update part, we cannot have more than
387 * 3 remaining bytes to write and SS is fast enough to not care about it.
392 /* write the remaining words of the wait buffer */
396 writesl(ss
->base
+ SS_RXFIFO
, op
->buf
, nwait
);
397 op
->byte_count
+= 4 * nwait
;
400 nbw
= op
->len
- 4 * nwait
;
402 wb
= *(u32
*)(op
->buf
+ nwait
* 4);
403 wb
&= GENMASK((nbw
* 8) - 1, 0);
405 op
->byte_count
+= nbw
;
409 /* write the remaining bytes of the nbw buffer */
410 wb
|= ((1 << 7) << (nbw
* 8));
414 * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
415 * I take the operations from other MD5/SHA1 implementations
418 /* last block size */
419 fill
= 64 - (op
->byte_count
% 64);
420 min_fill
= 2 * sizeof(u32
) + (nbw
? 0 : sizeof(u32
));
422 /* if we can't fill all data, jump to the next 64 block */
426 j
+= (fill
- min_fill
) / sizeof(u32
);
428 /* write the length of data */
429 if (op
->mode
== SS_OP_SHA1
) {
430 __be64 bits
= cpu_to_be64(op
->byte_count
<< 3);
431 bf
[j
++] = lower_32_bits(bits
);
432 bf
[j
++] = upper_32_bits(bits
);
434 __le64 bits
= op
->byte_count
<< 3;
435 bf
[j
++] = lower_32_bits(bits
);
436 bf
[j
++] = upper_32_bits(bits
);
438 writesl(ss
->base
+ SS_RXFIFO
, bf
, j
);
440 /* Tell the SS to stop the hashing */
441 writel(op
->mode
| SS_ENABLED
| SS_DATA_END
, ss
->base
+ SS_CTL
);
444 * Wait for SS to finish the hash.
445 * The timeout could happen only in case of bad overclocking
450 v
= readl(ss
->base
+ SS_CTL
);
452 } while (i
< SS_TIMEOUT
&& (v
& SS_DATA_END
));
453 if (unlikely(i
>= SS_TIMEOUT
)) {
454 dev_err_ratelimited(ss
->dev
,
455 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
456 i
, SS_TIMEOUT
, v
, areq
->nbytes
);
462 * The datasheet isn't very clear about when to retrieve the digest. The
463 * bit SS_DATA_END is cleared when the engine has processed the data and
464 * when the digest is computed *but* it doesn't mean the digest is
465 * available in the digest registers. Hence the delay to be sure we can
470 /* Get the hash from the device */
471 if (op
->mode
== SS_OP_SHA1
) {
472 for (i
= 0; i
< 5; i
++) {
473 v
= cpu_to_be32(readl(ss
->base
+ SS_MD0
+ i
* 4));
474 memcpy(areq
->result
+ i
* 4, &v
, 4);
477 for (i
= 0; i
< 4; i
++) {
478 v
= readl(ss
->base
+ SS_MD0
+ i
* 4);
479 memcpy(areq
->result
+ i
* 4, &v
, 4);
484 writel(0, ss
->base
+ SS_CTL
);
485 spin_unlock_bh(&ss
->slock
);
489 int sun4i_hash_final(struct ahash_request
*areq
)
491 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
493 op
->flags
= SS_HASH_FINAL
;
494 return sun4i_hash(areq
);
497 int sun4i_hash_update(struct ahash_request
*areq
)
499 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
501 op
->flags
= SS_HASH_UPDATE
;
502 return sun4i_hash(areq
);
505 /* sun4i_hash_finup: finalize hashing operation after an update */
506 int sun4i_hash_finup(struct ahash_request
*areq
)
508 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
510 op
->flags
= SS_HASH_UPDATE
| SS_HASH_FINAL
;
511 return sun4i_hash(areq
);
514 /* combo of init/update/final functions */
515 int sun4i_hash_digest(struct ahash_request
*areq
)
518 struct sun4i_req_ctx
*op
= ahash_request_ctx(areq
);
520 err
= sun4i_hash_init(areq
);
524 op
->flags
= SS_HASH_UPDATE
| SS_HASH_FINAL
;
525 return sun4i_hash(areq
);