drivers/crypto/sunxi-ss/sun4i-ss-hash.c

   1 /*
   2  * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
   3  *
   4  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
   5  *
   6  * This file add support for MD5 and SHA1.
   7  *
   8  * You could find the datasheet in Documentation/arm/sunxi/README
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #include "sun4i-ss.h"
  16 #include <linux/scatterlist.h>
  17
  18 /* This is a totally arbitrary value */
  19 #define SS_TIMEOUT 100
  20
  21 int sun4i_hash_crainit(struct crypto_tfm *tfm)
  22 {
  23         struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
  24         struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
  25         struct sun4i_ss_alg_template *algt;
  26
  27         memset(op, 0, sizeof(struct sun4i_tfm_ctx));
  28
  29         algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
  30         op->ss = algt->ss;
  31
  32         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
  33                                  sizeof(struct sun4i_req_ctx));
  34         return 0;
  35 }
  36
  37 /* sun4i_hash_init: initialize request context */
  38 int sun4i_hash_init(struct ahash_request *areq)
  39 {
  40         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
  41         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  42         struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
  43         struct sun4i_ss_alg_template *algt;
  44
  45         memset(op, 0, sizeof(struct sun4i_req_ctx));
  46
  47         algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
  48         op->mode = algt->mode;
  49
  50         return 0;
  51 }
  52
  53 int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
  54 {
  55         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
  56         struct md5_state *octx = out;
  57         int i;
  58
  59         octx->byte_count = op->byte_count + op->len;
  60
  61         memcpy(octx->block, op->buf, op->len);
  62
  63         if (op->byte_count) {
  64                 for (i = 0; i < 4; i++)
  65                         octx->hash[i] = op->hash[i];
  66         } else {
  67                 octx->hash[0] = SHA1_H0;
  68                 octx->hash[1] = SHA1_H1;
  69                 octx->hash[2] = SHA1_H2;
  70                 octx->hash[3] = SHA1_H3;
  71         }
  72
  73         return 0;
  74 }
  75
  76 int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
  77 {
  78         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
  79         const struct md5_state *ictx = in;
  80         int i;
  81
  82         sun4i_hash_init(areq);
  83
  84         op->byte_count = ictx->byte_count & ~0x3F;
  85         op->len = ictx->byte_count & 0x3F;
  86
  87         memcpy(op->buf, ictx->block, op->len);
  88
  89         for (i = 0; i < 4; i++)
  90                 op->hash[i] = ictx->hash[i];
  91
  92         return 0;
  93 }
  94
  95 int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
  96 {
  97         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
  98         struct sha1_state *octx = out;
  99         int i;
 100
 101         octx->count = op->byte_count + op->len;
 102
 103         memcpy(octx->buffer, op->buf, op->len);
 104
 105         if (op->byte_count) {
 106                 for (i = 0; i < 5; i++)
 107                         octx->state[i] = op->hash[i];
 108         } else {
 109                 octx->state[0] = SHA1_H0;
 110                 octx->state[1] = SHA1_H1;
 111                 octx->state[2] = SHA1_H2;
 112                 octx->state[3] = SHA1_H3;
 113                 octx->state[4] = SHA1_H4;
 114         }
 115
 116         return 0;
 117 }
 118
 119 int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
 120 {
 121         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 122         const struct sha1_state *ictx = in;
 123         int i;
 124
 125         sun4i_hash_init(areq);
 126
 127         op->byte_count = ictx->count & ~0x3F;
 128         op->len = ictx->count & 0x3F;
 129
 130         memcpy(op->buf, ictx->buffer, op->len);
 131
 132         for (i = 0; i < 5; i++)
 133                 op->hash[i] = ictx->state[i];
 134
 135         return 0;
 136 }
 137
 138 #define SS_HASH_UPDATE 1
 139 #define SS_HASH_FINAL 2
 140
 141 /*
 142  * sun4i_hash_update: update hash engine
 143  *
 144  * Could be used for both SHA1 and MD5
 145  * Write data by step of 32bits and put then in the SS.
 146  *
 147  * Since we cannot leave partial data and hash state in the engine,
 148  * we need to get the hash state at the end of this function.
 149  * We can get the hash state every 64 bytes
 150  *
 151  * So the first work is to get the number of bytes to write to SS modulo 64
 152  * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
 153  *
 154  * So at the begin of update()
 155  * if op->len + areq->nbytes < 64
 156  * => all data will be written to wait buffer (op->buf) and end=0
 157  * if not, write all data from op->buf to the device and position end to
 158  * complete to 64bytes
 159  *
 160  * example 1:
 161  * update1 60o => op->len=60
 162  * update2 60o => need one more word to have 64 bytes
 163  * end=4
 164  * so write all data from op->buf and one word of SGs
 165  * write remaining data in op->buf
 166  * final state op->len=56
 167  */
 168 static int sun4i_hash(struct ahash_request *areq)
 169 {
 170         /*
 171          * i is the total bytes read from SGs, to be compared to areq->nbytes
 172          * i is important because we cannot rely on SG length since the sum of
 173          * SG->length could be greater than areq->nbytes
 174          *
 175          * end is the position when we need to stop writing to the device,
 176          * to be compared to i
 177          *
 178          * in_i: advancement in the current SG
 179          */
 180         unsigned int i = 0, end, fill, min_fill, nwait, nbw = 0, j = 0, todo;
 181         unsigned int in_i = 0;
 182         u32 spaces, rx_cnt = SS_RX_DEFAULT, bf[32] = {0}, wb = 0, v, ivmode = 0;
 183         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 184         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
 185         struct sun4i_tfm_ctx *tfmctx = crypto_ahash_ctx(tfm);
 186         struct sun4i_ss_ctx *ss = tfmctx->ss;
 187         struct scatterlist *in_sg = areq->src;
 188         struct sg_mapping_iter mi;
 189         int in_r, err = 0;
 190         size_t copied = 0;
 191
 192         dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
 193                 __func__, crypto_tfm_alg_name(areq->base.tfm),
 194                 op->byte_count, areq->nbytes, op->mode,
 195                 op->len, op->hash[0]);
 196
 197         if (unlikely(!areq->nbytes) && !(op->flags & SS_HASH_FINAL))
 198                 return 0;
 199
 200         /* protect against overflow */
 201         if (unlikely(areq->nbytes > UINT_MAX - op->len)) {
 202                 dev_err(ss->dev, "Cannot process too large request\n");
 203                 return -EINVAL;
 204         }
 205
 206         if (op->len + areq->nbytes < 64 && !(op->flags & SS_HASH_FINAL)) {
 207                 /* linearize data to op->buf */
 208                 copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
 209                                             op->buf + op->len, areq->nbytes, 0);
 210                 op->len += copied;
 211                 return 0;
 212         }
 213
 214         spin_lock_bh(&ss->slock);
 215
 216         /*
 217          * if some data have been processed before,
 218          * we need to restore the partial hash state
 219          */
 220         if (op->byte_count) {
 221                 ivmode = SS_IV_ARBITRARY;
 222                 for (i = 0; i < 5; i++)
 223                         writel(op->hash[i], ss->base + SS_IV0 + i * 4);
 224         }
 225         /* Enable the device */
 226         writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
 227
 228         if (!(op->flags & SS_HASH_UPDATE))
 229                 goto hash_final;
 230
 231         /* start of handling data */
 232         if (!(op->flags & SS_HASH_FINAL)) {
 233                 end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
 234
 235                 if (end > areq->nbytes || areq->nbytes - end > 63) {
 236                         dev_err(ss->dev, "ERROR: Bound error %u %u\n",
 237                                 end, areq->nbytes);
 238                         err = -EINVAL;
 239                         goto release_ss;
 240                 }
 241         } else {
 242                 /* Since we have the flag final, we can go up to modulo 4 */
 243                 if (areq->nbytes < 4)
 244                         end = 0;
 245                 else
 246                         end = ((areq->nbytes + op->len) / 4) * 4 - op->len;
 247         }
 248
 249         /* TODO if SGlen % 4 and !op->len then DMA */
 250         i = 1;
 251         while (in_sg && i == 1) {
 252                 if (in_sg->length % 4)
 253                         i = 0;
 254                 in_sg = sg_next(in_sg);
 255         }
 256         if (i == 1 && !op->len && areq->nbytes)
 257                 dev_dbg(ss->dev, "We can DMA\n");
 258
 259         i = 0;
 260         sg_miter_start(&mi, areq->src, sg_nents(areq->src),
 261                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 262         sg_miter_next(&mi);
 263         in_i = 0;
 264
 265         do {
 266                 /*
 267                  * we need to linearize in two case:
 268                  * - the buffer is already used
 269                  * - the SG does not have enough byte remaining ( < 4)
 270                  */
 271                 if (op->len || (mi.length - in_i) < 4) {
 272                         /*
 273                          * if we have entered here we have two reason to stop
 274                          * - the buffer is full
 275                          * - reach the end
 276                          */
 277                         while (op->len < 64 && i < end) {
 278                                 /* how many bytes we can read from current SG */
 279                                 in_r = min3(mi.length - in_i, end - i,
 280                                             64 - op->len);
 281                                 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
 282                                 op->len += in_r;
 283                                 i += in_r;
 284                                 in_i += in_r;
 285                                 if (in_i == mi.length) {
 286                                         sg_miter_next(&mi);
 287                                         in_i = 0;
 288                                 }
 289                         }
 290                         if (op->len > 3 && !(op->len % 4)) {
 291                                 /* write buf to the device */
 292                                 writesl(ss->base + SS_RXFIFO, op->buf,
 293                                         op->len / 4);
 294                                 op->byte_count += op->len;
 295                                 op->len = 0;
 296                         }
 297                 }
 298                 if (mi.length - in_i > 3 && i < end) {
 299                         /* how many bytes we can read from current SG */
 300                         in_r = min3(mi.length - in_i, areq->nbytes - i,
 301                                     ((mi.length - in_i) / 4) * 4);
 302                         /* how many bytes we can write in the device*/
 303                         todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
 304                         writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
 305                         op->byte_count += todo * 4;
 306                         i += todo * 4;
 307                         in_i += todo * 4;
 308                         rx_cnt -= todo;
 309                         if (!rx_cnt) {
 310                                 spaces = readl(ss->base + SS_FCSR);
 311                                 rx_cnt = SS_RXFIFO_SPACES(spaces);
 312                         }
 313                         if (in_i == mi.length) {
 314                                 sg_miter_next(&mi);
 315                                 in_i = 0;
 316                         }
 317                 }
 318         } while (i < end);
 319
 320         /*
 321          * Now we have written to the device all that we can,
 322          * store the remaining bytes in op->buf
 323          */
 324         if ((areq->nbytes - i) < 64) {
 325                 while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
 326                         /* how many bytes we can read from current SG */
 327                         in_r = min3(mi.length - in_i, areq->nbytes - i,
 328                                     64 - op->len);
 329                         memcpy(op->buf + op->len, mi.addr + in_i, in_r);
 330                         op->len += in_r;
 331                         i += in_r;
 332                         in_i += in_r;
 333                         if (in_i == mi.length) {
 334                                 sg_miter_next(&mi);
 335                                 in_i = 0;
 336                         }
 337                 }
 338         }
 339
 340         sg_miter_stop(&mi);
 341
 342         /*
 343          * End of data process
 344          * Now if we have the flag final go to finalize part
 345          * If not, store the partial hash
 346          */
 347         if (op->flags & SS_HASH_FINAL)
 348                 goto hash_final;
 349
 350         writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
 351         i = 0;
 352         do {
 353                 v = readl(ss->base + SS_CTL);
 354                 i++;
 355         } while (i < SS_TIMEOUT && (v & SS_DATA_END));
 356         if (unlikely(i >= SS_TIMEOUT)) {
 357                 dev_err_ratelimited(ss->dev,
 358                                     "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
 359                                     i, SS_TIMEOUT, v, areq->nbytes);
 360                 err = -EIO;
 361                 goto release_ss;
 362         }
 363
 364         /*
 365          * The datasheet isn't very clear about when to retrieve the digest. The
 366          * bit SS_DATA_END is cleared when the engine has processed the data and
 367          * when the digest is computed *but* it doesn't mean the digest is
 368          * available in the digest registers. Hence the delay to be sure we can
 369          * read it.
 370          */
 371         ndelay(1);
 372
 373         for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
 374                 op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
 375
 376         goto release_ss;
 377
 378 /*
 379  * hash_final: finalize hashing operation
 380  *
 381  * If we have some remaining bytes, we write them.
 382  * Then ask the SS for finalizing the hashing operation
 383  *
 384  * I do not check RX FIFO size in this function since the size is 32
 385  * after each enabling and this function neither write more than 32 words.
 386  * If we come from the update part, we cannot have more than
 387  * 3 remaining bytes to write and SS is fast enough to not care about it.
 388  */
 389
 390 hash_final:
 391
 392         /* write the remaining words of the wait buffer */
 393         if (op->len) {
 394                 nwait = op->len / 4;
 395                 if (nwait) {
 396                         writesl(ss->base + SS_RXFIFO, op->buf, nwait);
 397                         op->byte_count += 4 * nwait;
 398                 }
 399
 400                 nbw = op->len - 4 * nwait;
 401                 if (nbw) {
 402                         wb = *(u32 *)(op->buf + nwait * 4);
 403                         wb &= GENMASK((nbw * 8) - 1, 0);
 404
 405                         op->byte_count += nbw;
 406                 }
 407         }
 408
 409         /* write the remaining bytes of the nbw buffer */
 410         wb |= ((1 << 7) << (nbw * 8));
 411         bf[j++] = wb;
 412
 413         /*
 414          * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
 415          * I take the operations from other MD5/SHA1 implementations
 416          */
 417
 418         /* last block size */
 419         fill = 64 - (op->byte_count % 64);
 420         min_fill = 2 * sizeof(u32) + (nbw ? 0 : sizeof(u32));
 421
 422         /* if we can't fill all data, jump to the next 64 block */
 423         if (fill < min_fill)
 424                 fill += 64;
 425
 426         j += (fill - min_fill) / sizeof(u32);
 427
 428         /* write the length of data */
 429         if (op->mode == SS_OP_SHA1) {
 430                 __be64 bits = cpu_to_be64(op->byte_count << 3);
 431                 bf[j++] = lower_32_bits(bits);
 432                 bf[j++] = upper_32_bits(bits);
 433         } else {
 434                 __le64 bits = op->byte_count << 3;
 435                 bf[j++] = lower_32_bits(bits);
 436                 bf[j++] = upper_32_bits(bits);
 437         }
 438         writesl(ss->base + SS_RXFIFO, bf, j);
 439
 440         /* Tell the SS to stop the hashing */
 441         writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
 442
 443         /*
 444          * Wait for SS to finish the hash.
 445          * The timeout could happen only in case of bad overclocking
 446          * or driver bug.
 447          */
 448         i = 0;
 449         do {
 450                 v = readl(ss->base + SS_CTL);
 451                 i++;
 452         } while (i < SS_TIMEOUT && (v & SS_DATA_END));
 453         if (unlikely(i >= SS_TIMEOUT)) {
 454                 dev_err_ratelimited(ss->dev,
 455                                     "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
 456                                     i, SS_TIMEOUT, v, areq->nbytes);
 457                 err = -EIO;
 458                 goto release_ss;
 459         }
 460
 461         /*
 462          * The datasheet isn't very clear about when to retrieve the digest. The
 463          * bit SS_DATA_END is cleared when the engine has processed the data and
 464          * when the digest is computed *but* it doesn't mean the digest is
 465          * available in the digest registers. Hence the delay to be sure we can
 466          * read it.
 467          */
 468         ndelay(1);
 469
 470         /* Get the hash from the device */
 471         if (op->mode == SS_OP_SHA1) {
 472                 for (i = 0; i < 5; i++) {
 473                         v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
 474                         memcpy(areq->result + i * 4, &v, 4);
 475                 }
 476         } else {
 477                 for (i = 0; i < 4; i++) {
 478                         v = readl(ss->base + SS_MD0 + i * 4);
 479                         memcpy(areq->result + i * 4, &v, 4);
 480                 }
 481         }
 482
 483 release_ss:
 484         writel(0, ss->base + SS_CTL);
 485         spin_unlock_bh(&ss->slock);
 486         return err;
 487 }
 488
 489 int sun4i_hash_final(struct ahash_request *areq)
 490 {
 491         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 492
 493         op->flags = SS_HASH_FINAL;
 494         return sun4i_hash(areq);
 495 }
 496
 497 int sun4i_hash_update(struct ahash_request *areq)
 498 {
 499         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 500
 501         op->flags = SS_HASH_UPDATE;
 502         return sun4i_hash(areq);
 503 }
 504
 505 /* sun4i_hash_finup: finalize hashing operation after an update */
 506 int sun4i_hash_finup(struct ahash_request *areq)
 507 {
 508         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 509
 510         op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
 511         return sun4i_hash(areq);
 512 }
 513
 514 /* combo of init/update/final functions */
 515 int sun4i_hash_digest(struct ahash_request *areq)
 516 {
 517         int err;
 518         struct sun4i_req_ctx *op = ahash_request_ctx(areq);
 519
 520         err = sun4i_hash_init(areq);
 521         if (err)
 522                 return err;
 523
 524         op->flags = SS_HASH_UPDATE | SS_HASH_FINAL;
 525         return sun4i_hash(areq);
 526 }