drivers/cxl/mem.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright(c) 2020-2021 Intel Corporation. */
   3 #ifndef __CXL_MEM_H__
   4 #define __CXL_MEM_H__
   5 #include <linux/cdev.h>
   6 #include "cxl.h"
   7
   8 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
   9 #define CXLMDEV_STATUS_OFFSET 0x0
  10 #define   CXLMDEV_DEV_FATAL BIT(0)
  11 #define   CXLMDEV_FW_HALT BIT(1)
  12 #define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
  13 #define     CXLMDEV_MS_NOT_READY 0
  14 #define     CXLMDEV_MS_READY 1
  15 #define     CXLMDEV_MS_ERROR 2
  16 #define     CXLMDEV_MS_DISABLED 3
  17 #define CXLMDEV_READY(status)                                                  \
  18         (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \
  19          CXLMDEV_MS_READY)
  20 #define   CXLMDEV_MBOX_IF_READY BIT(4)
  21 #define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
  22 #define     CXLMDEV_RESET_NEEDED_NOT 0
  23 #define     CXLMDEV_RESET_NEEDED_COLD 1
  24 #define     CXLMDEV_RESET_NEEDED_WARM 2
  25 #define     CXLMDEV_RESET_NEEDED_HOT 3
  26 #define     CXLMDEV_RESET_NEEDED_CXL 4
  27 #define CXLMDEV_RESET_NEEDED(status)                                           \
  28         (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \
  29          CXLMDEV_RESET_NEEDED_NOT)
  30
  31 /*
  32  * An entire PCI topology full of devices should be enough for any
  33  * config
  34  */
  35 #define CXL_MEM_MAX_DEVS 65536
  36
  37 /**
  38  * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
  39  * @dev: driver core device object
  40  * @cdev: char dev core object for ioctl operations
  41  * @cxlm: pointer to the parent device driver data
  42  * @id: id number of this memdev instance.
  43  */
  44 struct cxl_memdev {
  45         struct device dev;
  46         struct cdev cdev;
  47         struct cxl_mem *cxlm;
  48         int id;
  49 };
  50
  51 /**
  52  * struct cxl_mem - A CXL memory device
  53  * @pdev: The PCI device associated with this CXL device.
  54  * @cxlmd: Logical memory device chardev / interface
  55  * @regs: Parsed register blocks
  56  * @payload_size: Size of space for payload
  57  *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
  58  * @lsa_size: Size of Label Storage Area
  59  *                (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
  60  * @mbox_mutex: Mutex to synchronize mailbox access.
  61  * @firmware_version: Firmware version for the memory device.
  62  * @enabled_cmds: Hardware commands found enabled in CEL.
  63  * @pmem_range: Persistent memory capacity information.
  64  * @ram_range: Volatile memory capacity information.
  65  */
  66 struct cxl_mem {
  67         struct pci_dev *pdev;
  68         struct cxl_memdev *cxlmd;
  69
  70         struct cxl_regs regs;
  71
  72         size_t payload_size;
  73         size_t lsa_size;
  74         struct mutex mbox_mutex; /* Protects device mailbox and firmware */
  75         char firmware_version[0x10];
  76         unsigned long *enabled_cmds;
  77
  78         struct range pmem_range;
  79         struct range ram_range;
  80 };
  81 #endif /* __CXL_MEM_H__ */