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Merge branch 'pm-qos'
[mirror_ubuntu-artful-kernel.git] / drivers / devfreq / exynos4_bus.c
1 /* drivers/devfreq/exynos4210_memorybus.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 * MyungJoo Ham <myungjoo.ham@samsung.com>
6 *
7 * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
8 * This version supports EXYNOS4210 only. This changes bus frequencies
9 * and vddint voltages. Exynos4412/4212 should be able to be supported
10 * with minor modifications.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/io.h>
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/suspend.h>
22 #include <linux/opp.h>
23 #include <linux/devfreq.h>
24 #include <linux/platform_device.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/module.h>
27
28 /* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
29 #ifdef CONFIG_EXYNOS_ASV
30 extern unsigned int exynos_result_of_asv;
31 #endif
32
33 #include <mach/regs-clock.h>
34
35 #include <plat/map-s5p.h>
36
37 #define MAX_SAFEVOLT 1200000 /* 1.2V */
38
39 enum exynos4_busf_type {
40 TYPE_BUSF_EXYNOS4210,
41 TYPE_BUSF_EXYNOS4x12,
42 };
43
44 /* Assume that the bus is saturated if the utilization is 40% */
45 #define BUS_SATURATION_RATIO 40
46
47 enum ppmu_counter {
48 PPMU_PMNCNT0 = 0,
49 PPMU_PMCCNT1,
50 PPMU_PMNCNT2,
51 PPMU_PMNCNT3,
52 PPMU_PMNCNT_MAX,
53 };
54 struct exynos4_ppmu {
55 void __iomem *hw_base;
56 unsigned int ccnt;
57 unsigned int event;
58 unsigned int count[PPMU_PMNCNT_MAX];
59 bool ccnt_overflow;
60 bool count_overflow[PPMU_PMNCNT_MAX];
61 };
62
63 enum busclk_level_idx {
64 LV_0 = 0,
65 LV_1,
66 LV_2,
67 LV_3,
68 LV_4,
69 _LV_END
70 };
71 #define EX4210_LV_MAX LV_2
72 #define EX4x12_LV_MAX LV_4
73 #define EX4210_LV_NUM (LV_2 + 1)
74 #define EX4x12_LV_NUM (LV_4 + 1)
75
76 struct busfreq_data {
77 enum exynos4_busf_type type;
78 struct device *dev;
79 struct devfreq *devfreq;
80 bool disabled;
81 struct regulator *vdd_int;
82 struct regulator *vdd_mif; /* Exynos4412/4212 only */
83 struct opp *curr_opp;
84 struct exynos4_ppmu dmc[2];
85
86 struct notifier_block pm_notifier;
87 struct mutex lock;
88
89 /* Dividers calculated at boot/probe-time */
90 unsigned int dmc_divtable[_LV_END]; /* DMC0 */
91 unsigned int top_divtable[_LV_END];
92 };
93
94 struct bus_opp_table {
95 unsigned int idx;
96 unsigned long clk;
97 unsigned long volt;
98 };
99
100 /* 4210 controls clock of mif and voltage of int */
101 static struct bus_opp_table exynos4210_busclk_table[] = {
102 {LV_0, 400000, 1150000},
103 {LV_1, 267000, 1050000},
104 {LV_2, 133000, 1025000},
105 {0, 0, 0},
106 };
107
108 /*
109 * MIF is the main control knob clock for exynox4x12 MIF/INT
110 * clock and voltage of both mif/int are controlled.
111 */
112 static struct bus_opp_table exynos4x12_mifclk_table[] = {
113 {LV_0, 400000, 1100000},
114 {LV_1, 267000, 1000000},
115 {LV_2, 160000, 950000},
116 {LV_3, 133000, 950000},
117 {LV_4, 100000, 950000},
118 {0, 0, 0},
119 };
120
121 /*
122 * INT is not the control knob of 4x12. LV_x is not meant to represent
123 * the current performance. (MIF does)
124 */
125 static struct bus_opp_table exynos4x12_intclk_table[] = {
126 {LV_0, 200000, 1000000},
127 {LV_1, 160000, 950000},
128 {LV_2, 133000, 925000},
129 {LV_3, 100000, 900000},
130 {0, 0, 0},
131 };
132
133 /* TODO: asv volt definitions are "__initdata"? */
134 /* Some chips have different operating voltages */
135 static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
136 {1150000, 1050000, 1050000},
137 {1125000, 1025000, 1025000},
138 {1100000, 1000000, 1000000},
139 {1075000, 975000, 975000},
140 {1050000, 950000, 950000},
141 };
142
143 static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
144 /* 400 267 160 133 100 */
145 {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
146 {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
147 {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
148 {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
149 {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
150 {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
151 {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
152 {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
153 {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
154 };
155
156 static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
157 /* 200 160 133 100 */
158 {1000000, 950000, 925000, 900000}, /* ASV0 */
159 {975000, 925000, 925000, 900000}, /* ASV1 */
160 {950000, 925000, 900000, 875000}, /* ASV2 */
161 {950000, 900000, 900000, 875000}, /* ASV3 */
162 {925000, 875000, 875000, 875000}, /* ASV4 */
163 {900000, 850000, 850000, 850000}, /* ASV5 */
164 {900000, 850000, 850000, 850000}, /* ASV6 */
165 {900000, 850000, 850000, 850000}, /* ASV7 */
166 {900000, 850000, 850000, 850000}, /* ASV8 */
167 };
168
169 /*** Clock Divider Data for Exynos4210 ***/
170 static unsigned int exynos4210_clkdiv_dmc0[][8] = {
171 /*
172 * Clock divider value for following
173 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
174 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
175 */
176
177 /* DMC L0: 400MHz */
178 { 3, 1, 1, 1, 1, 1, 3, 1 },
179 /* DMC L1: 266.7MHz */
180 { 4, 1, 1, 2, 1, 1, 3, 1 },
181 /* DMC L2: 133MHz */
182 { 5, 1, 1, 5, 1, 1, 3, 1 },
183 };
184 static unsigned int exynos4210_clkdiv_top[][5] = {
185 /*
186 * Clock divider value for following
187 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
188 */
189 /* ACLK200 L0: 200MHz */
190 { 3, 7, 4, 5, 1 },
191 /* ACLK200 L1: 160MHz */
192 { 4, 7, 5, 6, 1 },
193 /* ACLK200 L2: 133MHz */
194 { 5, 7, 7, 7, 1 },
195 };
196 static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
197 /*
198 * Clock divider value for following
199 * { DIVGDL/R, DIVGPL/R }
200 */
201 /* ACLK_GDL/R L1: 200MHz */
202 { 3, 1 },
203 /* ACLK_GDL/R L2: 160MHz */
204 { 4, 1 },
205 /* ACLK_GDL/R L3: 133MHz */
206 { 5, 1 },
207 };
208
209 /*** Clock Divider Data for Exynos4212/4412 ***/
210 static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
211 /*
212 * Clock divider value for following
213 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
214 * DIVDMCP}
215 */
216
217 /* DMC L0: 400MHz */
218 {3, 1, 1, 1, 1, 1},
219 /* DMC L1: 266.7MHz */
220 {4, 1, 1, 2, 1, 1},
221 /* DMC L2: 160MHz */
222 {5, 1, 1, 4, 1, 1},
223 /* DMC L3: 133MHz */
224 {5, 1, 1, 5, 1, 1},
225 /* DMC L4: 100MHz */
226 {7, 1, 1, 7, 1, 1},
227 };
228 static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
229 /*
230 * Clock divider value for following
231 * { G2DACP, DIVC2C, DIVC2C_ACLK }
232 */
233
234 /* DMC L0: 400MHz */
235 {3, 1, 1},
236 /* DMC L1: 266.7MHz */
237 {4, 2, 1},
238 /* DMC L2: 160MHz */
239 {5, 4, 1},
240 /* DMC L3: 133MHz */
241 {5, 5, 1},
242 /* DMC L4: 100MHz */
243 {7, 7, 1},
244 };
245 static unsigned int exynos4x12_clkdiv_top[][5] = {
246 /*
247 * Clock divider value for following
248 * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
249 DIVACLK133, DIVONENAND }
250 */
251
252 /* ACLK_GDL/R L0: 200MHz */
253 {2, 7, 4, 5, 1},
254 /* ACLK_GDL/R L1: 200MHz */
255 {2, 7, 4, 5, 1},
256 /* ACLK_GDL/R L2: 160MHz */
257 {4, 7, 5, 7, 1},
258 /* ACLK_GDL/R L3: 133MHz */
259 {4, 7, 5, 7, 1},
260 /* ACLK_GDL/R L4: 100MHz */
261 {7, 7, 7, 7, 1},
262 };
263 static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
264 /*
265 * Clock divider value for following
266 * { DIVGDL/R, DIVGPL/R }
267 */
268
269 /* ACLK_GDL/R L0: 200MHz */
270 {3, 1},
271 /* ACLK_GDL/R L1: 200MHz */
272 {3, 1},
273 /* ACLK_GDL/R L2: 160MHz */
274 {4, 1},
275 /* ACLK_GDL/R L3: 133MHz */
276 {5, 1},
277 /* ACLK_GDL/R L4: 100MHz */
278 {7, 1},
279 };
280 static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
281 /*
282 * Clock divider value for following
283 * { DIVMFC, DIVJPEG, DIVFIMC0~3}
284 */
285
286 /* SCLK_MFC: 200MHz */
287 {3, 3, 4},
288 /* SCLK_MFC: 200MHz */
289 {3, 3, 4},
290 /* SCLK_MFC: 160MHz */
291 {4, 4, 5},
292 /* SCLK_MFC: 133MHz */
293 {5, 5, 5},
294 /* SCLK_MFC: 100MHz */
295 {7, 7, 7},
296 };
297
298
299 static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
300 {
301 unsigned int index;
302 unsigned int tmp;
303
304 for (index = LV_0; index < EX4210_LV_NUM; index++)
305 if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk)
306 break;
307
308 if (index == EX4210_LV_NUM)
309 return -EINVAL;
310
311 /* Change Divider - DMC0 */
312 tmp = data->dmc_divtable[index];
313
314 __raw_writel(tmp, S5P_CLKDIV_DMC0);
315
316 do {
317 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
318 } while (tmp & 0x11111111);
319
320 /* Change Divider - TOP */
321 tmp = data->top_divtable[index];
322
323 __raw_writel(tmp, S5P_CLKDIV_TOP);
324
325 do {
326 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
327 } while (tmp & 0x11111);
328
329 /* Change Divider - LEFTBUS */
330 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
331
332 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
333
334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
335 S5P_CLKDIV_BUS_GDLR_SHIFT) |
336 (exynos4210_clkdiv_lr_bus[index][1] <<
337 S5P_CLKDIV_BUS_GPLR_SHIFT));
338
339 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
340
341 do {
342 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
343 } while (tmp & 0x11);
344
345 /* Change Divider - RIGHTBUS */
346 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
347
348 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
349
350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
351 S5P_CLKDIV_BUS_GDLR_SHIFT) |
352 (exynos4210_clkdiv_lr_bus[index][1] <<
353 S5P_CLKDIV_BUS_GPLR_SHIFT));
354
355 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
356
357 do {
358 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
359 } while (tmp & 0x11);
360
361 return 0;
362 }
363
364 static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
365 {
366 unsigned int index;
367 unsigned int tmp;
368
369 for (index = LV_0; index < EX4x12_LV_NUM; index++)
370 if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk)
371 break;
372
373 if (index == EX4x12_LV_NUM)
374 return -EINVAL;
375
376 /* Change Divider - DMC0 */
377 tmp = data->dmc_divtable[index];
378
379 __raw_writel(tmp, S5P_CLKDIV_DMC0);
380
381 do {
382 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
383 } while (tmp & 0x11111111);
384
385 /* Change Divider - DMC1 */
386 tmp = __raw_readl(S5P_CLKDIV_DMC1);
387
388 tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK |
389 S5P_CLKDIV_DMC1_C2C_MASK |
390 S5P_CLKDIV_DMC1_C2CACLK_MASK);
391
392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
393 S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) |
394 (exynos4x12_clkdiv_dmc1[index][1] <<
395 S5P_CLKDIV_DMC1_C2C_SHIFT) |
396 (exynos4x12_clkdiv_dmc1[index][2] <<
397 S5P_CLKDIV_DMC1_C2CACLK_SHIFT));
398
399 __raw_writel(tmp, S5P_CLKDIV_DMC1);
400
401 do {
402 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1);
403 } while (tmp & 0x111111);
404
405 /* Change Divider - TOP */
406 tmp = __raw_readl(S5P_CLKDIV_TOP);
407
408 tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK |
409 S5P_CLKDIV_TOP_ACLK100_MASK |
410 S5P_CLKDIV_TOP_ACLK160_MASK |
411 S5P_CLKDIV_TOP_ACLK133_MASK |
412 S5P_CLKDIV_TOP_ONENAND_MASK);
413
414 tmp |= ((exynos4x12_clkdiv_top[index][0] <<
415 S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
416 (exynos4x12_clkdiv_top[index][1] <<
417 S5P_CLKDIV_TOP_ACLK100_SHIFT) |
418 (exynos4x12_clkdiv_top[index][2] <<
419 S5P_CLKDIV_TOP_ACLK160_SHIFT) |
420 (exynos4x12_clkdiv_top[index][3] <<
421 S5P_CLKDIV_TOP_ACLK133_SHIFT) |
422 (exynos4x12_clkdiv_top[index][4] <<
423 S5P_CLKDIV_TOP_ONENAND_SHIFT));
424
425 __raw_writel(tmp, S5P_CLKDIV_TOP);
426
427 do {
428 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
429 } while (tmp & 0x11111);
430
431 /* Change Divider - LEFTBUS */
432 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
433
434 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
435
436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
437 S5P_CLKDIV_BUS_GDLR_SHIFT) |
438 (exynos4x12_clkdiv_lr_bus[index][1] <<
439 S5P_CLKDIV_BUS_GPLR_SHIFT));
440
441 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
442
443 do {
444 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
445 } while (tmp & 0x11);
446
447 /* Change Divider - RIGHTBUS */
448 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
449
450 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
451
452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
453 S5P_CLKDIV_BUS_GDLR_SHIFT) |
454 (exynos4x12_clkdiv_lr_bus[index][1] <<
455 S5P_CLKDIV_BUS_GPLR_SHIFT));
456
457 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
458
459 do {
460 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
461 } while (tmp & 0x11);
462
463 /* Change Divider - MFC */
464 tmp = __raw_readl(S5P_CLKDIV_MFC);
465
466 tmp &= ~(S5P_CLKDIV_MFC_MASK);
467
468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
469 S5P_CLKDIV_MFC_SHIFT));
470
471 __raw_writel(tmp, S5P_CLKDIV_MFC);
472
473 do {
474 tmp = __raw_readl(S5P_CLKDIV_STAT_MFC);
475 } while (tmp & 0x1);
476
477 /* Change Divider - JPEG */
478 tmp = __raw_readl(S5P_CLKDIV_CAM1);
479
480 tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK);
481
482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
483 S5P_CLKDIV_CAM1_JPEG_SHIFT));
484
485 __raw_writel(tmp, S5P_CLKDIV_CAM1);
486
487 do {
488 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
489 } while (tmp & 0x1);
490
491 /* Change Divider - FIMC0~3 */
492 tmp = __raw_readl(S5P_CLKDIV_CAM);
493
494 tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK |
495 S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK);
496
497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
498 S5P_CLKDIV_CAM_FIMC0_SHIFT) |
499 (exynos4x12_clkdiv_sclkip[index][2] <<
500 S5P_CLKDIV_CAM_FIMC1_SHIFT) |
501 (exynos4x12_clkdiv_sclkip[index][2] <<
502 S5P_CLKDIV_CAM_FIMC2_SHIFT) |
503 (exynos4x12_clkdiv_sclkip[index][2] <<
504 S5P_CLKDIV_CAM_FIMC3_SHIFT));
505
506 __raw_writel(tmp, S5P_CLKDIV_CAM);
507
508 do {
509 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
510 } while (tmp & 0x1111);
511
512 return 0;
513 }
514
515
516 static void busfreq_mon_reset(struct busfreq_data *data)
517 {
518 unsigned int i;
519
520 for (i = 0; i < 2; i++) {
521 void __iomem *ppmu_base = data->dmc[i].hw_base;
522
523 /* Reset PPMU */
524 __raw_writel(0x8000000f, ppmu_base + 0xf010);
525 __raw_writel(0x8000000f, ppmu_base + 0xf050);
526 __raw_writel(0x6, ppmu_base + 0xf000);
527 __raw_writel(0x0, ppmu_base + 0xf100);
528
529 /* Set PPMU Event */
530 data->dmc[i].event = 0x6;
531 __raw_writel(((data->dmc[i].event << 12) | 0x1),
532 ppmu_base + 0xfc);
533
534 /* Start PPMU */
535 __raw_writel(0x1, ppmu_base + 0xf000);
536 }
537 }
538
539 static void exynos4_read_ppmu(struct busfreq_data *data)
540 {
541 int i, j;
542
543 for (i = 0; i < 2; i++) {
544 void __iomem *ppmu_base = data->dmc[i].hw_base;
545 u32 overflow;
546
547 /* Stop PPMU */
548 __raw_writel(0x0, ppmu_base + 0xf000);
549
550 /* Update local data from PPMU */
551 overflow = __raw_readl(ppmu_base + 0xf050);
552
553 data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100);
554 data->dmc[i].ccnt_overflow = overflow & (1 << 31);
555
556 for (j = 0; j < PPMU_PMNCNT_MAX; j++) {
557 data->dmc[i].count[j] = __raw_readl(
558 ppmu_base + (0xf110 + (0x10 * j)));
559 data->dmc[i].count_overflow[j] = overflow & (1 << j);
560 }
561 }
562
563 busfreq_mon_reset(data);
564 }
565
566 static int exynos4x12_get_intspec(unsigned long mifclk)
567 {
568 int i = 0;
569
570 while (exynos4x12_intclk_table[i].clk) {
571 if (exynos4x12_intclk_table[i].clk <= mifclk)
572 return i;
573 i++;
574 }
575
576 return -EINVAL;
577 }
578
579 static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
580 struct opp *oldopp)
581 {
582 int err = 0, tmp;
583 unsigned long volt = opp_get_voltage(opp);
584
585 switch (data->type) {
586 case TYPE_BUSF_EXYNOS4210:
587 /* OPP represents DMC clock + INT voltage */
588 err = regulator_set_voltage(data->vdd_int, volt,
589 MAX_SAFEVOLT);
590 break;
591 case TYPE_BUSF_EXYNOS4x12:
592 /* OPP represents MIF clock + MIF voltage */
593 err = regulator_set_voltage(data->vdd_mif, volt,
594 MAX_SAFEVOLT);
595 if (err)
596 break;
597
598 tmp = exynos4x12_get_intspec(opp_get_freq(opp));
599 if (tmp < 0) {
600 err = tmp;
601 regulator_set_voltage(data->vdd_mif,
602 opp_get_voltage(oldopp),
603 MAX_SAFEVOLT);
604 break;
605 }
606 err = regulator_set_voltage(data->vdd_int,
607 exynos4x12_intclk_table[tmp].volt,
608 MAX_SAFEVOLT);
609 /* Try to recover */
610 if (err)
611 regulator_set_voltage(data->vdd_mif,
612 opp_get_voltage(oldopp),
613 MAX_SAFEVOLT);
614 break;
615 default:
616 err = -EINVAL;
617 }
618
619 return err;
620 }
621
622 static int exynos4_bus_target(struct device *dev, unsigned long *_freq)
623 {
624 int err = 0;
625 struct busfreq_data *data = dev_get_drvdata(dev);
626 struct opp *opp = devfreq_recommended_opp(dev, _freq);
627 unsigned long old_freq = opp_get_freq(data->curr_opp);
628 unsigned long freq = opp_get_freq(opp);
629
630 if (old_freq == freq)
631 return 0;
632
633 dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp));
634
635 mutex_lock(&data->lock);
636
637 if (data->disabled)
638 goto out;
639
640 if (old_freq < freq)
641 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
642 if (err)
643 goto out;
644
645 if (old_freq != freq) {
646 switch (data->type) {
647 case TYPE_BUSF_EXYNOS4210:
648 err = exynos4210_set_busclk(data, opp);
649 break;
650 case TYPE_BUSF_EXYNOS4x12:
651 err = exynos4x12_set_busclk(data, opp);
652 break;
653 default:
654 err = -EINVAL;
655 }
656 }
657 if (err)
658 goto out;
659
660 if (old_freq > freq)
661 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
662 if (err)
663 goto out;
664
665 data->curr_opp = opp;
666 out:
667 mutex_unlock(&data->lock);
668 return err;
669 }
670
671 static int exynos4_get_busier_dmc(struct busfreq_data *data)
672 {
673 u64 p0 = data->dmc[0].count[0];
674 u64 p1 = data->dmc[1].count[0];
675
676 p0 *= data->dmc[1].ccnt;
677 p1 *= data->dmc[0].ccnt;
678
679 if (data->dmc[1].ccnt == 0)
680 return 0;
681
682 if (p0 > p1)
683 return 0;
684 return 1;
685 }
686
687 static int exynos4_bus_get_dev_status(struct device *dev,
688 struct devfreq_dev_status *stat)
689 {
690 struct busfreq_data *data = dev_get_drvdata(dev);
691 int busier_dmc;
692 int cycles_x2 = 2; /* 2 x cycles */
693 void __iomem *addr;
694 u32 timing;
695 u32 memctrl;
696
697 exynos4_read_ppmu(data);
698 busier_dmc = exynos4_get_busier_dmc(data);
699 stat->current_frequency = opp_get_freq(data->curr_opp);
700
701 if (busier_dmc)
702 addr = S5P_VA_DMC1;
703 else
704 addr = S5P_VA_DMC0;
705
706 memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */
707 timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */
708
709 switch ((memctrl >> 8) & 0xf) {
710 case 0x4: /* DDR2 */
711 cycles_x2 = ((timing >> 16) & 0xf) * 2;
712 break;
713 case 0x5: /* LPDDR2 */
714 case 0x6: /* DDR3 */
715 cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf);
716 break;
717 default:
718 pr_err("%s: Unknown Memory Type(%d).\n", __func__,
719 (memctrl >> 8) & 0xf);
720 return -EINVAL;
721 }
722
723 /* Number of cycles spent on memory access */
724 stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2);
725 stat->busy_time *= 100 / BUS_SATURATION_RATIO;
726 stat->total_time = data->dmc[busier_dmc].ccnt;
727
728 /* If the counters have overflown, retry */
729 if (data->dmc[busier_dmc].ccnt_overflow ||
730 data->dmc[busier_dmc].count_overflow[0])
731 return -EAGAIN;
732
733 return 0;
734 }
735
736 static void exynos4_bus_exit(struct device *dev)
737 {
738 struct busfreq_data *data = dev_get_drvdata(dev);
739
740 devfreq_unregister_opp_notifier(dev, data->devfreq);
741 }
742
743 static struct devfreq_dev_profile exynos4_devfreq_profile = {
744 .initial_freq = 400000,
745 .polling_ms = 50,
746 .target = exynos4_bus_target,
747 .get_dev_status = exynos4_bus_get_dev_status,
748 .exit = exynos4_bus_exit,
749 };
750
751 static int exynos4210_init_tables(struct busfreq_data *data)
752 {
753 u32 tmp;
754 int mgrp;
755 int i, err = 0;
756
757 tmp = __raw_readl(S5P_CLKDIV_DMC0);
758 for (i = LV_0; i < EX4210_LV_NUM; i++) {
759 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
760 S5P_CLKDIV_DMC0_ACPPCLK_MASK |
761 S5P_CLKDIV_DMC0_DPHY_MASK |
762 S5P_CLKDIV_DMC0_DMC_MASK |
763 S5P_CLKDIV_DMC0_DMCD_MASK |
764 S5P_CLKDIV_DMC0_DMCP_MASK |
765 S5P_CLKDIV_DMC0_COPY2_MASK |
766 S5P_CLKDIV_DMC0_CORETI_MASK);
767
768 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
769 S5P_CLKDIV_DMC0_ACP_SHIFT) |
770 (exynos4210_clkdiv_dmc0[i][1] <<
771 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
772 (exynos4210_clkdiv_dmc0[i][2] <<
773 S5P_CLKDIV_DMC0_DPHY_SHIFT) |
774 (exynos4210_clkdiv_dmc0[i][3] <<
775 S5P_CLKDIV_DMC0_DMC_SHIFT) |
776 (exynos4210_clkdiv_dmc0[i][4] <<
777 S5P_CLKDIV_DMC0_DMCD_SHIFT) |
778 (exynos4210_clkdiv_dmc0[i][5] <<
779 S5P_CLKDIV_DMC0_DMCP_SHIFT) |
780 (exynos4210_clkdiv_dmc0[i][6] <<
781 S5P_CLKDIV_DMC0_COPY2_SHIFT) |
782 (exynos4210_clkdiv_dmc0[i][7] <<
783 S5P_CLKDIV_DMC0_CORETI_SHIFT));
784
785 data->dmc_divtable[i] = tmp;
786 }
787
788 tmp = __raw_readl(S5P_CLKDIV_TOP);
789 for (i = LV_0; i < EX4210_LV_NUM; i++) {
790 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK |
791 S5P_CLKDIV_TOP_ACLK100_MASK |
792 S5P_CLKDIV_TOP_ACLK160_MASK |
793 S5P_CLKDIV_TOP_ACLK133_MASK |
794 S5P_CLKDIV_TOP_ONENAND_MASK);
795
796 tmp |= ((exynos4210_clkdiv_top[i][0] <<
797 S5P_CLKDIV_TOP_ACLK200_SHIFT) |
798 (exynos4210_clkdiv_top[i][1] <<
799 S5P_CLKDIV_TOP_ACLK100_SHIFT) |
800 (exynos4210_clkdiv_top[i][2] <<
801 S5P_CLKDIV_TOP_ACLK160_SHIFT) |
802 (exynos4210_clkdiv_top[i][3] <<
803 S5P_CLKDIV_TOP_ACLK133_SHIFT) |
804 (exynos4210_clkdiv_top[i][4] <<
805 S5P_CLKDIV_TOP_ONENAND_SHIFT));
806
807 data->top_divtable[i] = tmp;
808 }
809
810 #ifdef CONFIG_EXYNOS_ASV
811 tmp = exynos4_result_of_asv;
812 #else
813 tmp = 0; /* Max voltages for the reliability of the unknown */
814 #endif
815
816 pr_debug("ASV Group of Exynos4 is %d\n", tmp);
817 /* Use merged grouping for voltage */
818 switch (tmp) {
819 case 0:
820 mgrp = 0;
821 break;
822 case 1:
823 case 2:
824 mgrp = 1;
825 break;
826 case 3:
827 case 4:
828 mgrp = 2;
829 break;
830 case 5:
831 case 6:
832 mgrp = 3;
833 break;
834 case 7:
835 mgrp = 4;
836 break;
837 default:
838 pr_warn("Unknown ASV Group. Use max voltage.\n");
839 mgrp = 0;
840 }
841
842 for (i = LV_0; i < EX4210_LV_NUM; i++)
843 exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
844
845 for (i = LV_0; i < EX4210_LV_NUM; i++) {
846 err = opp_add(data->dev, exynos4210_busclk_table[i].clk,
847 exynos4210_busclk_table[i].volt);
848 if (err) {
849 dev_err(data->dev, "Cannot add opp entries.\n");
850 return err;
851 }
852 }
853
854
855 return 0;
856 }
857
858 static int exynos4x12_init_tables(struct busfreq_data *data)
859 {
860 unsigned int i;
861 unsigned int tmp;
862 int ret;
863
864 /* Enable pause function for DREX2 DVFS */
865 tmp = __raw_readl(S5P_DMC_PAUSE_CTRL);
866 tmp |= DMC_PAUSE_ENABLE;
867 __raw_writel(tmp, S5P_DMC_PAUSE_CTRL);
868
869 tmp = __raw_readl(S5P_CLKDIV_DMC0);
870
871 for (i = 0; i < EX4x12_LV_NUM; i++) {
872 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
873 S5P_CLKDIV_DMC0_ACPPCLK_MASK |
874 S5P_CLKDIV_DMC0_DPHY_MASK |
875 S5P_CLKDIV_DMC0_DMC_MASK |
876 S5P_CLKDIV_DMC0_DMCD_MASK |
877 S5P_CLKDIV_DMC0_DMCP_MASK);
878
879 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
880 S5P_CLKDIV_DMC0_ACP_SHIFT) |
881 (exynos4x12_clkdiv_dmc0[i][1] <<
882 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
883 (exynos4x12_clkdiv_dmc0[i][2] <<
884 S5P_CLKDIV_DMC0_DPHY_SHIFT) |
885 (exynos4x12_clkdiv_dmc0[i][3] <<
886 S5P_CLKDIV_DMC0_DMC_SHIFT) |
887 (exynos4x12_clkdiv_dmc0[i][4] <<
888 S5P_CLKDIV_DMC0_DMCD_SHIFT) |
889 (exynos4x12_clkdiv_dmc0[i][5] <<
890 S5P_CLKDIV_DMC0_DMCP_SHIFT));
891
892 data->dmc_divtable[i] = tmp;
893 }
894
895 #ifdef CONFIG_EXYNOS_ASV
896 tmp = exynos4_result_of_asv;
897 #else
898 tmp = 0; /* Max voltages for the reliability of the unknown */
899 #endif
900
901 if (tmp > 8)
902 tmp = 0;
903 pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
904
905 for (i = 0; i < EX4x12_LV_NUM; i++) {
906 exynos4x12_mifclk_table[i].volt =
907 exynos4x12_mif_step_50[tmp][i];
908 exynos4x12_intclk_table[i].volt =
909 exynos4x12_int_volt[tmp][i];
910 }
911
912 for (i = 0; i < EX4x12_LV_NUM; i++) {
913 ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
914 exynos4x12_mifclk_table[i].volt);
915 if (ret) {
916 dev_err(data->dev, "Fail to add opp entries.\n");
917 return ret;
918 }
919 }
920
921 return 0;
922 }
923
924 static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
925 unsigned long event, void *ptr)
926 {
927 struct busfreq_data *data = container_of(this, struct busfreq_data,
928 pm_notifier);
929 struct opp *opp;
930 unsigned long maxfreq = ULONG_MAX;
931 int err = 0;
932
933 switch (event) {
934 case PM_SUSPEND_PREPARE:
935 /* Set Fastest and Deactivate DVFS */
936 mutex_lock(&data->lock);
937
938 data->disabled = true;
939
940 opp = opp_find_freq_floor(data->dev, &maxfreq);
941
942 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
943 if (err)
944 goto unlock;
945
946 switch (data->type) {
947 case TYPE_BUSF_EXYNOS4210:
948 err = exynos4210_set_busclk(data, opp);
949 break;
950 case TYPE_BUSF_EXYNOS4x12:
951 err = exynos4x12_set_busclk(data, opp);
952 break;
953 default:
954 err = -EINVAL;
955 }
956 if (err)
957 goto unlock;
958
959 data->curr_opp = opp;
960 unlock:
961 mutex_unlock(&data->lock);
962 if (err)
963 return err;
964 return NOTIFY_OK;
965 case PM_POST_RESTORE:
966 case PM_POST_SUSPEND:
967 /* Reactivate */
968 mutex_lock(&data->lock);
969 data->disabled = false;
970 mutex_unlock(&data->lock);
971 return NOTIFY_OK;
972 }
973
974 return NOTIFY_DONE;
975 }
976
977 static __devinit int exynos4_busfreq_probe(struct platform_device *pdev)
978 {
979 struct busfreq_data *data;
980 struct opp *opp;
981 struct device *dev = &pdev->dev;
982 int err = 0;
983
984 data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL);
985 if (data == NULL) {
986 dev_err(dev, "Cannot allocate memory.\n");
987 return -ENOMEM;
988 }
989
990 data->type = pdev->id_entry->driver_data;
991 data->dmc[0].hw_base = S5P_VA_DMC0;
992 data->dmc[1].hw_base = S5P_VA_DMC1;
993 data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
994 data->dev = dev;
995 mutex_init(&data->lock);
996
997 switch (data->type) {
998 case TYPE_BUSF_EXYNOS4210:
999 err = exynos4210_init_tables(data);
1000 break;
1001 case TYPE_BUSF_EXYNOS4x12:
1002 err = exynos4x12_init_tables(data);
1003 break;
1004 default:
1005 dev_err(dev, "Cannot determine the device id %d\n", data->type);
1006 err = -EINVAL;
1007 }
1008 if (err)
1009 goto err_regulator;
1010
1011 data->vdd_int = regulator_get(dev, "vdd_int");
1012 if (IS_ERR(data->vdd_int)) {
1013 dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
1014 err = PTR_ERR(data->vdd_int);
1015 goto err_regulator;
1016 }
1017 if (data->type == TYPE_BUSF_EXYNOS4x12) {
1018 data->vdd_mif = regulator_get(dev, "vdd_mif");
1019 if (IS_ERR(data->vdd_mif)) {
1020 dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
1021 err = PTR_ERR(data->vdd_mif);
1022 regulator_put(data->vdd_int);
1023 goto err_regulator;
1024
1025 }
1026 }
1027
1028 opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq);
1029 if (IS_ERR(opp)) {
1030 dev_err(dev, "Invalid initial frequency %lu kHz.\n",
1031 exynos4_devfreq_profile.initial_freq);
1032 err = PTR_ERR(opp);
1033 goto err_opp_add;
1034 }
1035 data->curr_opp = opp;
1036
1037 platform_set_drvdata(pdev, data);
1038
1039 busfreq_mon_reset(data);
1040
1041 data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile,
1042 &devfreq_simple_ondemand, NULL);
1043 if (IS_ERR(data->devfreq)) {
1044 err = PTR_ERR(data->devfreq);
1045 goto err_opp_add;
1046 }
1047
1048 devfreq_register_opp_notifier(dev, data->devfreq);
1049
1050 err = register_pm_notifier(&data->pm_notifier);
1051 if (err) {
1052 dev_err(dev, "Failed to setup pm notifier\n");
1053 goto err_devfreq_add;
1054 }
1055
1056 return 0;
1057 err_devfreq_add:
1058 devfreq_remove_device(data->devfreq);
1059 err_opp_add:
1060 if (data->vdd_mif)
1061 regulator_put(data->vdd_mif);
1062 regulator_put(data->vdd_int);
1063 err_regulator:
1064 kfree(data);
1065 return err;
1066 }
1067
1068 static __devexit int exynos4_busfreq_remove(struct platform_device *pdev)
1069 {
1070 struct busfreq_data *data = platform_get_drvdata(pdev);
1071
1072 unregister_pm_notifier(&data->pm_notifier);
1073 devfreq_remove_device(data->devfreq);
1074 regulator_put(data->vdd_int);
1075 if (data->vdd_mif)
1076 regulator_put(data->vdd_mif);
1077 kfree(data);
1078
1079 return 0;
1080 }
1081
1082 static int exynos4_busfreq_resume(struct device *dev)
1083 {
1084 struct busfreq_data *data = dev_get_drvdata(dev);
1085
1086 busfreq_mon_reset(data);
1087 return 0;
1088 }
1089
1090 static const struct dev_pm_ops exynos4_busfreq_pm = {
1091 .resume = exynos4_busfreq_resume,
1092 };
1093
1094 static const struct platform_device_id exynos4_busfreq_id[] = {
1095 { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
1096 { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
1097 { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
1098 { },
1099 };
1100
1101 static struct platform_driver exynos4_busfreq_driver = {
1102 .probe = exynos4_busfreq_probe,
1103 .remove = __devexit_p(exynos4_busfreq_remove),
1104 .id_table = exynos4_busfreq_id,
1105 .driver = {
1106 .name = "exynos4-busfreq",
1107 .owner = THIS_MODULE,
1108 .pm = &exynos4_busfreq_pm,
1109 },
1110 };
1111
1112 static int __init exynos4_busfreq_init(void)
1113 {
1114 return platform_driver_register(&exynos4_busfreq_driver);
1115 }
1116 late_initcall(exynos4_busfreq_init);
1117
1118 static void __exit exynos4_busfreq_exit(void)
1119 {
1120 platform_driver_unregister(&exynos4_busfreq_driver);
1121 }
1122 module_exit(exynos4_busfreq_exit);
1123
1124 MODULE_LICENSE("GPL");
1125 MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
1126 MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");
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