2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <linux/amba/pl080.h>
88 #include "dmaengine.h"
91 #define DRIVER_NAME "pl08xdmac"
93 static struct amba_driver pl08x_amba_driver
;
94 struct pl08x_driver_data
;
97 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
98 * @channels: the number of channels available in this variant
99 * @dualmaster: whether this version supports dual AHB masters or not.
100 * @nomadik: whether the channels have Nomadik security extension bits
101 * that need to be checked for permission before use and some registers are
111 * PL08X private data structures
112 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
113 * start & end do not - their bus bit info is in cctl. Also note that these
114 * are fixed 32-bit quantities.
124 * struct pl08x_bus_data - information of source or destination
125 * busses for a transfer
126 * @addr: current address
127 * @maxwidth: the maximum width of a transfer on this bus
128 * @buswidth: the width of this bus in bytes: 1, 2 or 4
130 struct pl08x_bus_data
{
136 #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
139 * struct pl08x_phy_chan - holder for the physical channels
140 * @id: physical index to this channel
141 * @lock: a lock to use when altering an instance of this struct
142 * @serving: the virtual channel currently being served by this physical
144 * @locked: channel unavailable for the system, e.g. dedicated to secure
147 struct pl08x_phy_chan
{
151 struct pl08x_dma_chan
*serving
;
156 * struct pl08x_sg - structure containing data per sg
157 * @src_addr: src address of sg
158 * @dst_addr: dst address of sg
159 * @len: transfer len in bytes
160 * @node: node for txd's dsg_list
166 struct list_head node
;
170 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
171 * @vd: virtual DMA descriptor
172 * @dsg_list: list of children sg's
173 * @llis_bus: DMA memory address (physical) start for the LLIs
174 * @llis_va: virtual memory address start for the LLIs
175 * @cctl: control reg values for current txd
176 * @ccfg: config reg values for current txd
177 * @done: this marks completed descriptors, which should not have their
181 struct virt_dma_desc vd
;
182 struct list_head dsg_list
;
184 struct pl08x_lli
*llis_va
;
185 /* Default cctl value for LLIs */
188 * Settings to be put into the physical channel when we
189 * trigger this txd. Other registers are in llis_va[0].
196 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
198 * @PL08X_CHAN_IDLE: the channel is idle
199 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
200 * channel and is running a transfer on it
201 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
202 * channel, but the transfer is currently paused
203 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
204 * channel to become available (only pertains to memcpy channels)
206 enum pl08x_dma_chan_state
{
214 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
215 * @vc: wrappped virtual channel
216 * @phychan: the physical channel utilized by this channel, if there is one
217 * @name: name of channel
218 * @cd: channel platform data
219 * @runtime_addr: address for RX/TX according to the runtime config
220 * @at: active transaction on this channel
221 * @lock: a lock for this channel data
222 * @host: a pointer to the host (internal use)
223 * @state: whether the channel is idle, paused, running etc
224 * @slave: whether this channel is a device (slave) or for memcpy
225 * @signal: the physical DMA request signal which this channel is using
226 * @mux_use: count of descriptors using this DMA request signal setting
228 struct pl08x_dma_chan
{
229 struct virt_dma_chan vc
;
230 struct pl08x_phy_chan
*phychan
;
232 const struct pl08x_channel_data
*cd
;
233 struct dma_slave_config cfg
;
234 struct pl08x_txd
*at
;
235 struct pl08x_driver_data
*host
;
236 enum pl08x_dma_chan_state state
;
243 * struct pl08x_driver_data - the local state holder for the PL08x
244 * @slave: slave engine for this instance
245 * @memcpy: memcpy engine for this instance
246 * @base: virtual memory base (remapped) for the PL08x
247 * @adev: the corresponding AMBA (PrimeCell) bus entry
248 * @vd: vendor data for this PL08x variant
249 * @pd: platform data passed in from the platform/machine
250 * @phy_chans: array of data for the physical channels
251 * @pool: a pool for the LLI descriptors
252 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
254 * @mem_buses: set to indicate memory transfers on AHB2.
255 * @lock: a spinlock for this struct
257 struct pl08x_driver_data
{
258 struct dma_device slave
;
259 struct dma_device memcpy
;
261 struct amba_device
*adev
;
262 const struct vendor_data
*vd
;
263 struct pl08x_platform_data
*pd
;
264 struct pl08x_phy_chan
*phy_chans
;
265 struct dma_pool
*pool
;
271 * PL08X specific defines
274 /* Size (bytes) of each LLI buffer allocated for one transfer */
275 # define PL08X_LLI_TSFR_SIZE 0x2000
277 /* Maximum times we call dma_pool_alloc on this pool without freeing */
278 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
279 #define PL08X_ALIGN 8
281 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
283 return container_of(chan
, struct pl08x_dma_chan
, vc
.chan
);
286 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
288 return container_of(tx
, struct pl08x_txd
, vd
.tx
);
294 * This gives us the DMA request input to the PL08x primecell which the
295 * peripheral described by the channel data will be routed to, possibly
296 * via a board/SoC specific external MUX. One important point to note
297 * here is that this does not depend on the physical channel.
299 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
301 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
304 if (plchan
->mux_use
++ == 0 && pd
->get_xfer_signal
) {
305 ret
= pd
->get_xfer_signal(plchan
->cd
);
311 plchan
->signal
= ret
;
316 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
318 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
320 if (plchan
->signal
>= 0) {
321 WARN_ON(plchan
->mux_use
== 0);
323 if (--plchan
->mux_use
== 0 && pd
->put_xfer_signal
) {
324 pd
->put_xfer_signal(plchan
->cd
, plchan
->signal
);
331 * Physical channel handling
334 /* Whether a certain channel is busy or not */
335 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
339 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
340 return val
& PL080_CONFIG_ACTIVE
;
344 * Set the initial DMA register values i.e. those for the first LLI
345 * The next LLI pointer and the configuration interrupt bit have
346 * been set when the LLIs were constructed. Poke them into the hardware
347 * and start the transfer.
349 static void pl08x_start_next_txd(struct pl08x_dma_chan
*plchan
)
351 struct pl08x_driver_data
*pl08x
= plchan
->host
;
352 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
353 struct virt_dma_desc
*vd
= vchan_next_desc(&plchan
->vc
);
354 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
355 struct pl08x_lli
*lli
;
358 list_del(&txd
->vd
.node
);
362 /* Wait for channel inactive */
363 while (pl08x_phy_channel_busy(phychan
))
366 lli
= &txd
->llis_va
[0];
368 dev_vdbg(&pl08x
->adev
->dev
,
369 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
370 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
371 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
374 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
375 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
376 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
377 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
378 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
380 /* Enable the DMA channel */
381 /* Do not access config register until channel shows as disabled */
382 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
385 /* Do not access config register until channel shows as inactive */
386 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
387 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
388 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
390 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
394 * Pause the channel by setting the HALT bit.
396 * For M->P transfers, pause the DMAC first and then stop the peripheral -
397 * the FIFO can only drain if the peripheral is still requesting data.
398 * (note: this can still timeout if the DMAC FIFO never drains of data.)
400 * For P->M transfers, disable the peripheral first to stop it filling
401 * the DMAC FIFO, and then pause the DMAC.
403 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
408 /* Set the HALT bit and wait for the FIFO to drain */
409 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
410 val
|= PL080_CONFIG_HALT
;
411 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
413 /* Wait for channel inactive */
414 for (timeout
= 1000; timeout
; timeout
--) {
415 if (!pl08x_phy_channel_busy(ch
))
419 if (pl08x_phy_channel_busy(ch
))
420 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
423 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
427 /* Clear the HALT bit */
428 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
429 val
&= ~PL080_CONFIG_HALT
;
430 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
434 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
435 * clears any pending interrupt status. This should not be used for
436 * an on-going transfer, but as a method of shutting down a channel
437 * (eg, when it's no longer used) or terminating a transfer.
439 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
440 struct pl08x_phy_chan
*ch
)
442 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
444 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
445 PL080_CONFIG_TC_IRQ_MASK
);
447 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
449 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
450 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
453 static inline u32
get_bytes_in_cctl(u32 cctl
)
455 /* The source width defines the number of bytes */
456 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
458 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
459 case PL080_WIDTH_8BIT
:
461 case PL080_WIDTH_16BIT
:
464 case PL080_WIDTH_32BIT
:
471 /* The channel should be paused when calling this */
472 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
474 struct pl08x_phy_chan
*ch
;
475 struct pl08x_txd
*txd
;
478 ch
= plchan
->phychan
;
482 * Follow the LLIs to get the number of remaining
483 * bytes in the currently active transaction.
486 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
488 /* First get the remaining bytes in the active transfer */
489 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
492 struct pl08x_lli
*llis_va
= txd
->llis_va
;
493 dma_addr_t llis_bus
= txd
->llis_bus
;
496 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
497 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
500 * Locate the next LLI - as this is an array,
501 * it's simple maths to find.
503 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
505 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
506 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
509 * A LLI pointer of 0 terminates the LLI list
511 if (!llis_va
[index
].lli
)
521 * Allocate a physical channel for a virtual channel
523 * Try to locate a physical channel to be used for this transfer. If all
524 * are taken return NULL and the requester will have to cope by using
525 * some fallback PIO mode or retrying later.
527 static struct pl08x_phy_chan
*
528 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
529 struct pl08x_dma_chan
*virt_chan
)
531 struct pl08x_phy_chan
*ch
= NULL
;
535 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
536 ch
= &pl08x
->phy_chans
[i
];
538 spin_lock_irqsave(&ch
->lock
, flags
);
540 if (!ch
->locked
&& !ch
->serving
) {
541 ch
->serving
= virt_chan
;
542 spin_unlock_irqrestore(&ch
->lock
, flags
);
546 spin_unlock_irqrestore(&ch
->lock
, flags
);
549 if (i
== pl08x
->vd
->channels
) {
550 /* No physical channel available, cope with it */
557 /* Mark the physical channel as free. Note, this write is atomic. */
558 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
559 struct pl08x_phy_chan
*ch
)
565 * Try to allocate a physical channel. When successful, assign it to
566 * this virtual channel, and initiate the next descriptor. The
567 * virtual channel lock must be held at this point.
569 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan
*plchan
)
571 struct pl08x_driver_data
*pl08x
= plchan
->host
;
572 struct pl08x_phy_chan
*ch
;
574 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
576 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
577 plchan
->state
= PL08X_CHAN_WAITING
;
581 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
582 ch
->id
, plchan
->name
);
584 plchan
->phychan
= ch
;
585 plchan
->state
= PL08X_CHAN_RUNNING
;
586 pl08x_start_next_txd(plchan
);
589 static void pl08x_phy_reassign_start(struct pl08x_phy_chan
*ch
,
590 struct pl08x_dma_chan
*plchan
)
592 struct pl08x_driver_data
*pl08x
= plchan
->host
;
594 dev_dbg(&pl08x
->adev
->dev
, "reassigned physical channel %d for xfer on %s\n",
595 ch
->id
, plchan
->name
);
598 * We do this without taking the lock; we're really only concerned
599 * about whether this pointer is NULL or not, and we're guaranteed
600 * that this will only be called when it _already_ is non-NULL.
602 ch
->serving
= plchan
;
603 plchan
->phychan
= ch
;
604 plchan
->state
= PL08X_CHAN_RUNNING
;
605 pl08x_start_next_txd(plchan
);
609 * Free a physical DMA channel, potentially reallocating it to another
610 * virtual channel if we have any pending.
612 static void pl08x_phy_free(struct pl08x_dma_chan
*plchan
)
614 struct pl08x_driver_data
*pl08x
= plchan
->host
;
615 struct pl08x_dma_chan
*p
, *next
;
620 /* Find a waiting virtual channel for the next transfer. */
621 list_for_each_entry(p
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
)
622 if (p
->state
== PL08X_CHAN_WAITING
) {
628 list_for_each_entry(p
, &pl08x
->slave
.channels
, vc
.chan
.device_node
)
629 if (p
->state
== PL08X_CHAN_WAITING
) {
635 /* Ensure that the physical channel is stopped */
636 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
642 * Eww. We know this isn't going to deadlock
643 * but lockdep probably doesn't.
645 spin_lock(&next
->vc
.lock
);
646 /* Re-check the state now that we have the lock */
647 success
= next
->state
== PL08X_CHAN_WAITING
;
649 pl08x_phy_reassign_start(plchan
->phychan
, next
);
650 spin_unlock(&next
->vc
.lock
);
652 /* If the state changed, try to find another channel */
656 /* No more jobs, so free up the physical channel */
657 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
660 plchan
->phychan
= NULL
;
661 plchan
->state
= PL08X_CHAN_IDLE
;
668 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
671 case PL080_WIDTH_8BIT
:
673 case PL080_WIDTH_16BIT
:
675 case PL080_WIDTH_32BIT
:
684 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
689 /* Remove all src, dst and transfer size bits */
690 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
691 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
692 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
694 /* Then set the bits according to the parameters */
697 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
700 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
703 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
712 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
715 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
718 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
725 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
729 struct pl08x_lli_build_data
{
730 struct pl08x_txd
*txd
;
731 struct pl08x_bus_data srcbus
;
732 struct pl08x_bus_data dstbus
;
738 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
739 * victim in case src & dest are not similarly aligned. i.e. If after aligning
740 * masters address with width requirements of transfer (by sending few byte by
741 * byte data), slave is still not aligned, then its width will be reduced to
743 * - prefers the destination bus if both available
744 * - prefers bus with fixed address (i.e. peripheral)
746 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
747 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
749 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
752 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
756 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
767 * Fills in one LLI for a certain transfer descriptor and advance the counter
769 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
770 int num_llis
, int len
, u32 cctl
)
772 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
773 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
775 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
777 llis_va
[num_llis
].cctl
= cctl
;
778 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
779 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
780 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
781 sizeof(struct pl08x_lli
);
782 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
784 if (cctl
& PL080_CONTROL_SRC_INCR
)
785 bd
->srcbus
.addr
+= len
;
786 if (cctl
& PL080_CONTROL_DST_INCR
)
787 bd
->dstbus
.addr
+= len
;
789 BUG_ON(bd
->remainder
< len
);
791 bd
->remainder
-= len
;
794 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
795 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
797 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
798 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
799 (*total_bytes
) += len
;
803 * This fills in the table of LLIs for the transfer descriptor
804 * Note that we assume we never have to change the burst sizes
807 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
808 struct pl08x_txd
*txd
)
810 struct pl08x_bus_data
*mbus
, *sbus
;
811 struct pl08x_lli_build_data bd
;
813 u32 cctl
, early_bytes
= 0;
814 size_t max_bytes_per_lli
, total_bytes
;
815 struct pl08x_lli
*llis_va
;
816 struct pl08x_sg
*dsg
;
818 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
820 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
825 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
828 /* Find maximum width of the source bus */
830 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
831 PL080_CONTROL_SWIDTH_SHIFT
);
833 /* Find maximum width of the destination bus */
835 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
836 PL080_CONTROL_DWIDTH_SHIFT
);
838 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
842 bd
.srcbus
.addr
= dsg
->src_addr
;
843 bd
.dstbus
.addr
= dsg
->dst_addr
;
844 bd
.remainder
= dsg
->len
;
845 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
846 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
848 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
850 dev_vdbg(&pl08x
->adev
->dev
,
851 "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
853 cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
856 cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
859 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
860 mbus
== &bd
.srcbus
? "src" : "dst",
861 sbus
== &bd
.srcbus
? "src" : "dst");
864 * Zero length is only allowed if all these requirements are
866 * - flow controller is peripheral.
867 * - src.addr is aligned to src.width
868 * - dst.addr is aligned to dst.width
870 * sg_len == 1 should be true, as there can be two cases here:
872 * - Memory addresses are contiguous and are not scattered.
873 * Here, Only one sg will be passed by user driver, with
874 * memory address and zero length. We pass this to controller
875 * and after the transfer it will receive the last burst
876 * request from peripheral and so transfer finishes.
878 * - Memory addresses are scattered and are not contiguous.
879 * Here, Obviously as DMA controller doesn't know when a lli's
880 * transfer gets over, it can't load next lli. So in this
881 * case, there has to be an assumption that only one lli is
882 * supported. Thus, we can't have scattered addresses.
885 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
886 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
887 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
888 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
889 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
894 if (!IS_BUS_ALIGNED(&bd
.srcbus
) ||
895 !IS_BUS_ALIGNED(&bd
.dstbus
)) {
896 dev_err(&pl08x
->adev
->dev
,
897 "%s src & dst address must be aligned to src"
898 " & dst width if peripheral is flow controller",
903 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
904 bd
.dstbus
.buswidth
, 0);
905 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
910 * Send byte by byte for following cases
911 * - Less than a bus width available
912 * - until master bus is aligned
914 if (bd
.remainder
< mbus
->buswidth
)
915 early_bytes
= bd
.remainder
;
916 else if (!IS_BUS_ALIGNED(mbus
)) {
917 early_bytes
= mbus
->buswidth
-
918 (mbus
->addr
& (mbus
->buswidth
- 1));
919 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
920 early_bytes
= bd
.remainder
;
924 dev_vdbg(&pl08x
->adev
->dev
,
925 "%s byte width LLIs (remain 0x%08x)\n",
926 __func__
, bd
.remainder
);
927 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
934 * - if slave is not then we must set its width down
936 if (!IS_BUS_ALIGNED(sbus
)) {
937 dev_dbg(&pl08x
->adev
->dev
,
938 "%s set down bus width to one byte\n",
945 * Bytes transferred = tsize * src width, not
948 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
949 PL080_CONTROL_TRANSFER_SIZE_MASK
;
950 dev_vdbg(&pl08x
->adev
->dev
,
951 "%s max bytes per lli = %zu\n",
952 __func__
, max_bytes_per_lli
);
955 * Make largest possible LLIs until less than one bus
958 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
959 size_t lli_len
, tsize
, width
;
962 * If enough left try to send max possible,
963 * otherwise try to send the remainder
965 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
968 * Check against maximum bus alignment:
969 * Calculate actual transfer size in relation to
970 * bus width an get a maximum remainder of the
971 * highest bus width - 1
973 width
= max(mbus
->buswidth
, sbus
->buswidth
);
974 lli_len
= (lli_len
/ width
) * width
;
975 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
977 dev_vdbg(&pl08x
->adev
->dev
,
978 "%s fill lli with single lli chunk of "
979 "size 0x%08zx (remainder 0x%08zx)\n",
980 __func__
, lli_len
, bd
.remainder
);
982 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
983 bd
.dstbus
.buswidth
, tsize
);
984 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
986 total_bytes
+= lli_len
;
993 dev_vdbg(&pl08x
->adev
->dev
,
994 "%s align with boundary, send odd bytes (remain %zu)\n",
995 __func__
, bd
.remainder
);
996 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
997 num_llis
++, &total_bytes
);
1001 if (total_bytes
!= dsg
->len
) {
1002 dev_err(&pl08x
->adev
->dev
,
1003 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1004 __func__
, total_bytes
, dsg
->len
);
1008 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
1009 dev_err(&pl08x
->adev
->dev
,
1010 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1011 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
1016 llis_va
= txd
->llis_va
;
1017 /* The final LLI terminates the LLI. */
1018 llis_va
[num_llis
- 1].lli
= 0;
1019 /* The final LLI element shall also fire an interrupt. */
1020 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
1022 #ifdef VERBOSE_DEBUG
1026 dev_vdbg(&pl08x
->adev
->dev
,
1027 "%-3s %-9s %-10s %-10s %-10s %s\n",
1028 "lli", "", "csrc", "cdst", "clli", "cctl");
1029 for (i
= 0; i
< num_llis
; i
++) {
1030 dev_vdbg(&pl08x
->adev
->dev
,
1031 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1032 i
, &llis_va
[i
], llis_va
[i
].src
,
1033 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
1042 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
1043 struct pl08x_txd
*txd
)
1045 struct pl08x_sg
*dsg
, *_dsg
;
1048 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
1050 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
1051 list_del(&dsg
->node
);
1058 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1060 struct device
*dev
= txd
->vd
.tx
.chan
->device
->dev
;
1061 struct pl08x_sg
*dsg
;
1063 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1064 if (txd
->vd
.tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1065 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1066 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1069 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1070 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1074 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1075 if (txd
->vd
.tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1076 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1077 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1080 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1081 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1086 static void pl08x_desc_free(struct virt_dma_desc
*vd
)
1088 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
1089 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(vd
->tx
.chan
);
1092 pl08x_unmap_buffers(txd
);
1095 pl08x_release_mux(plchan
);
1097 pl08x_free_txd(plchan
->host
, txd
);
1100 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
1101 struct pl08x_dma_chan
*plchan
)
1105 vchan_get_all_descriptors(&plchan
->vc
, &head
);
1106 vchan_dma_desc_free_list(&plchan
->vc
, &head
);
1110 * The DMA ENGINE API
1112 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1117 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1119 /* Ensure all queued descriptors are freed */
1120 vchan_free_chan_resources(to_virt_chan(chan
));
1123 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1124 struct dma_chan
*chan
, unsigned long flags
)
1126 struct dma_async_tx_descriptor
*retval
= NULL
;
1132 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1133 * If slaves are relying on interrupts to signal completion this function
1134 * must not be called with interrupts disabled.
1136 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1137 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1139 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1140 struct virt_dma_desc
*vd
;
1141 unsigned long flags
;
1142 enum dma_status ret
;
1145 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1146 if (ret
== DMA_SUCCESS
)
1150 * There's no point calculating the residue if there's
1151 * no txstate to store the value.
1154 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1159 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1160 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1161 if (ret
!= DMA_SUCCESS
) {
1162 vd
= vchan_find_desc(&plchan
->vc
, cookie
);
1164 /* On the issued list, so hasn't been processed yet */
1165 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
1166 struct pl08x_sg
*dsg
;
1168 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1171 bytes
= pl08x_getbytes_chan(plchan
);
1174 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1177 * This cookie not complete yet
1178 * Get number of bytes left in the active transactions and queue
1180 dma_set_residue(txstate
, bytes
);
1182 if (plchan
->state
== PL08X_CHAN_PAUSED
&& ret
== DMA_IN_PROGRESS
)
1185 /* Whether waiting or running, we're in progress */
1189 /* PrimeCell DMA extension */
1190 struct burst_table
{
1195 static const struct burst_table burst_sizes
[] = {
1198 .reg
= PL080_BSIZE_256
,
1202 .reg
= PL080_BSIZE_128
,
1206 .reg
= PL080_BSIZE_64
,
1210 .reg
= PL080_BSIZE_32
,
1214 .reg
= PL080_BSIZE_16
,
1218 .reg
= PL080_BSIZE_8
,
1222 .reg
= PL080_BSIZE_4
,
1226 .reg
= PL080_BSIZE_1
,
1231 * Given the source and destination available bus masks, select which
1232 * will be routed to each port. We try to have source and destination
1233 * on separate ports, but always respect the allowable settings.
1235 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1239 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1240 cctl
|= PL080_CONTROL_DST_AHB2
;
1241 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1242 cctl
|= PL080_CONTROL_SRC_AHB2
;
1247 static u32
pl08x_cctl(u32 cctl
)
1249 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1250 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1251 PL080_CONTROL_PROT_MASK
);
1253 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1254 return cctl
| PL080_CONTROL_PROT_SYS
;
1257 static u32
pl08x_width(enum dma_slave_buswidth width
)
1260 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1261 return PL080_WIDTH_8BIT
;
1262 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1263 return PL080_WIDTH_16BIT
;
1264 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1265 return PL080_WIDTH_32BIT
;
1271 static u32
pl08x_burst(u32 maxburst
)
1275 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1276 if (burst_sizes
[i
].burstwords
<= maxburst
)
1279 return burst_sizes
[i
].reg
;
1282 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1283 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1285 u32 width
, burst
, cctl
= 0;
1287 width
= pl08x_width(addr_width
);
1291 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1292 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1295 * If this channel will only request single transfers, set this
1296 * down to ONE element. Also select one element if no maxburst
1299 if (plchan
->cd
->single
)
1302 burst
= pl08x_burst(maxburst
);
1303 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1304 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1306 return pl08x_cctl(cctl
);
1309 static int dma_set_runtime_config(struct dma_chan
*chan
,
1310 struct dma_slave_config
*config
)
1312 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1317 /* Reject definitely invalid configurations */
1318 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1319 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1322 plchan
->cfg
= *config
;
1328 * Slave transactions callback to the slave device to allow
1329 * synchronization of slave DMA signals with the DMAC enable
1331 static void pl08x_issue_pending(struct dma_chan
*chan
)
1333 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1334 unsigned long flags
;
1336 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1337 if (vchan_issue_pending(&plchan
->vc
)) {
1338 if (!plchan
->phychan
&& plchan
->state
!= PL08X_CHAN_WAITING
)
1339 pl08x_phy_alloc_and_start(plchan
);
1341 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1344 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
)
1346 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1349 INIT_LIST_HEAD(&txd
->dsg_list
);
1351 /* Always enable error and terminal interrupts */
1352 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1353 PL080_CONFIG_TC_IRQ_MASK
;
1359 * Initialize a descriptor to be used by memcpy submit
1361 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1362 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1363 size_t len
, unsigned long flags
)
1365 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1366 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1367 struct pl08x_txd
*txd
;
1368 struct pl08x_sg
*dsg
;
1371 txd
= pl08x_get_txd(plchan
);
1373 dev_err(&pl08x
->adev
->dev
,
1374 "%s no memory for descriptor\n", __func__
);
1378 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1380 pl08x_free_txd(pl08x
, txd
);
1381 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1385 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1387 dsg
->src_addr
= src
;
1388 dsg
->dst_addr
= dest
;
1391 /* Set platform data for m2m */
1392 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1393 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1394 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1396 /* Both to be incremented or the code will break */
1397 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1399 if (pl08x
->vd
->dualmaster
)
1400 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1403 ret
= pl08x_fill_llis_for_desc(plchan
->host
, txd
);
1405 pl08x_free_txd(pl08x
, txd
);
1409 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1412 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1413 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1414 unsigned int sg_len
, enum dma_transfer_direction direction
,
1415 unsigned long flags
, void *context
)
1417 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1418 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1419 struct pl08x_txd
*txd
;
1420 struct pl08x_sg
*dsg
;
1421 struct scatterlist
*sg
;
1422 enum dma_slave_buswidth addr_width
;
1423 dma_addr_t slave_addr
;
1425 u8 src_buses
, dst_buses
;
1428 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1429 __func__
, sg_dma_len(sgl
), plchan
->name
);
1431 txd
= pl08x_get_txd(plchan
);
1433 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1438 * Set up addresses, the PrimeCell configured address
1439 * will take precedence since this may configure the
1440 * channel target address dynamically at runtime.
1442 if (direction
== DMA_MEM_TO_DEV
) {
1443 cctl
= PL080_CONTROL_SRC_INCR
;
1444 slave_addr
= plchan
->cfg
.dst_addr
;
1445 addr_width
= plchan
->cfg
.dst_addr_width
;
1446 maxburst
= plchan
->cfg
.dst_maxburst
;
1447 src_buses
= pl08x
->mem_buses
;
1448 dst_buses
= plchan
->cd
->periph_buses
;
1449 } else if (direction
== DMA_DEV_TO_MEM
) {
1450 cctl
= PL080_CONTROL_DST_INCR
;
1451 slave_addr
= plchan
->cfg
.src_addr
;
1452 addr_width
= plchan
->cfg
.src_addr_width
;
1453 maxburst
= plchan
->cfg
.src_maxburst
;
1454 src_buses
= plchan
->cd
->periph_buses
;
1455 dst_buses
= pl08x
->mem_buses
;
1457 pl08x_free_txd(pl08x
, txd
);
1458 dev_err(&pl08x
->adev
->dev
,
1459 "%s direction unsupported\n", __func__
);
1463 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1465 pl08x_free_txd(pl08x
, txd
);
1466 dev_err(&pl08x
->adev
->dev
,
1467 "DMA slave configuration botched?\n");
1471 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1473 if (plchan
->cfg
.device_fc
)
1474 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1475 PL080_FLOW_PER2MEM_PER
;
1477 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1480 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1482 ret
= pl08x_request_mux(plchan
);
1484 pl08x_free_txd(pl08x
, txd
);
1485 dev_dbg(&pl08x
->adev
->dev
,
1486 "unable to mux for transfer on %s due to platform restrictions\n",
1491 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1492 plchan
->signal
, plchan
->name
);
1494 /* Assign the flow control signal to this channel */
1495 if (direction
== DMA_MEM_TO_DEV
)
1496 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1498 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1500 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1501 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1503 pl08x_release_mux(plchan
);
1504 pl08x_free_txd(pl08x
, txd
);
1505 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1509 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1511 dsg
->len
= sg_dma_len(sg
);
1512 if (direction
== DMA_MEM_TO_DEV
) {
1513 dsg
->src_addr
= sg_dma_address(sg
);
1514 dsg
->dst_addr
= slave_addr
;
1516 dsg
->src_addr
= slave_addr
;
1517 dsg
->dst_addr
= sg_dma_address(sg
);
1521 ret
= pl08x_fill_llis_for_desc(plchan
->host
, txd
);
1523 pl08x_release_mux(plchan
);
1524 pl08x_free_txd(pl08x
, txd
);
1528 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1531 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1534 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1535 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1536 unsigned long flags
;
1539 /* Controls applicable to inactive channels */
1540 if (cmd
== DMA_SLAVE_CONFIG
) {
1541 return dma_set_runtime_config(chan
,
1542 (struct dma_slave_config
*)arg
);
1546 * Anything succeeds on channels with no physical allocation and
1547 * no queued transfers.
1549 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1550 if (!plchan
->phychan
&& !plchan
->at
) {
1551 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1556 case DMA_TERMINATE_ALL
:
1557 plchan
->state
= PL08X_CHAN_IDLE
;
1559 if (plchan
->phychan
) {
1561 * Mark physical channel as free and free any slave
1564 pl08x_phy_free(plchan
);
1566 /* Dequeue jobs and free LLIs */
1568 pl08x_desc_free(&plchan
->at
->vd
);
1571 /* Dequeue jobs not yet fired as well */
1572 pl08x_free_txd_list(pl08x
, plchan
);
1575 pl08x_pause_phy_chan(plchan
->phychan
);
1576 plchan
->state
= PL08X_CHAN_PAUSED
;
1579 pl08x_resume_phy_chan(plchan
->phychan
);
1580 plchan
->state
= PL08X_CHAN_RUNNING
;
1583 /* Unknown command */
1588 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1593 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1595 struct pl08x_dma_chan
*plchan
;
1596 char *name
= chan_id
;
1598 /* Reject channels for devices not bound to this driver */
1599 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1602 plchan
= to_pl08x_chan(chan
);
1604 /* Check that the channel is not taken! */
1605 if (!strcmp(plchan
->name
, name
))
1612 * Just check that the device is there and active
1613 * TODO: turn this bit on/off depending on the number of physical channels
1614 * actually used, if it is zero... well shut it off. That will save some
1615 * power. Cut the clock at the same time.
1617 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1619 /* The Nomadik variant does not have the config register */
1620 if (pl08x
->vd
->nomadik
)
1622 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1625 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1627 struct pl08x_driver_data
*pl08x
= dev
;
1628 u32 mask
= 0, err
, tc
, i
;
1630 /* check & clear - ERR & TC interrupts */
1631 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1633 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1635 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1637 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1639 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1644 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1645 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1646 /* Locate physical channel */
1647 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1648 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1649 struct pl08x_txd
*tx
;
1652 dev_err(&pl08x
->adev
->dev
,
1653 "%s Error TC interrupt on unused channel: 0x%08x\n",
1658 spin_lock(&plchan
->vc
.lock
);
1663 * This descriptor is done, release its mux
1666 pl08x_release_mux(plchan
);
1668 vchan_cookie_complete(&tx
->vd
);
1671 * And start the next descriptor (if any),
1672 * otherwise free this channel.
1674 if (vchan_next_desc(&plchan
->vc
))
1675 pl08x_start_next_txd(plchan
);
1677 pl08x_phy_free(plchan
);
1679 spin_unlock(&plchan
->vc
.lock
);
1685 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1688 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1691 chan
->name
= chan
->cd
->bus_id
;
1692 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1693 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1697 * Initialise the DMAC memcpy/slave channels.
1698 * Make a local wrapper to hold required data
1700 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1701 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1703 struct pl08x_dma_chan
*chan
;
1706 INIT_LIST_HEAD(&dmadev
->channels
);
1709 * Register as many many memcpy as we have physical channels,
1710 * we won't always be able to use all but the code will have
1711 * to cope with that situation.
1713 for (i
= 0; i
< channels
; i
++) {
1714 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1716 dev_err(&pl08x
->adev
->dev
,
1717 "%s no memory for channel\n", __func__
);
1722 chan
->state
= PL08X_CHAN_IDLE
;
1726 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1727 pl08x_dma_slave_init(chan
);
1729 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1730 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1736 dev_dbg(&pl08x
->adev
->dev
,
1737 "initialize virtual channel \"%s\"\n",
1740 chan
->vc
.desc_free
= pl08x_desc_free
;
1741 vchan_init(&chan
->vc
, dmadev
);
1743 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1744 i
, slave
? "slave" : "memcpy");
1748 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1750 struct pl08x_dma_chan
*chan
= NULL
;
1751 struct pl08x_dma_chan
*next
;
1753 list_for_each_entry_safe(chan
,
1754 next
, &dmadev
->channels
, vc
.chan
.device_node
) {
1755 list_del(&chan
->vc
.chan
.device_node
);
1760 #ifdef CONFIG_DEBUG_FS
1761 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1764 case PL08X_CHAN_IDLE
:
1766 case PL08X_CHAN_RUNNING
:
1768 case PL08X_CHAN_PAUSED
:
1770 case PL08X_CHAN_WAITING
:
1775 return "UNKNOWN STATE";
1778 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1780 struct pl08x_driver_data
*pl08x
= s
->private;
1781 struct pl08x_dma_chan
*chan
;
1782 struct pl08x_phy_chan
*ch
;
1783 unsigned long flags
;
1786 seq_printf(s
, "PL08x physical channels:\n");
1787 seq_printf(s
, "CHANNEL:\tUSER:\n");
1788 seq_printf(s
, "--------\t-----\n");
1789 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1790 struct pl08x_dma_chan
*virt_chan
;
1792 ch
= &pl08x
->phy_chans
[i
];
1794 spin_lock_irqsave(&ch
->lock
, flags
);
1795 virt_chan
= ch
->serving
;
1797 seq_printf(s
, "%d\t\t%s%s\n",
1799 virt_chan
? virt_chan
->name
: "(none)",
1800 ch
->locked
? " LOCKED" : "");
1802 spin_unlock_irqrestore(&ch
->lock
, flags
);
1805 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1806 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1807 seq_printf(s
, "--------\t------\n");
1808 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
) {
1809 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1810 pl08x_state_str(chan
->state
));
1813 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1814 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1815 seq_printf(s
, "--------\t------\n");
1816 list_for_each_entry(chan
, &pl08x
->slave
.channels
, vc
.chan
.device_node
) {
1817 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1818 pl08x_state_str(chan
->state
));
1824 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1826 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1829 static const struct file_operations pl08x_debugfs_operations
= {
1830 .open
= pl08x_debugfs_open
,
1832 .llseek
= seq_lseek
,
1833 .release
= single_release
,
1836 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1838 /* Expose a simple debugfs interface to view all clocks */
1839 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1840 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1841 &pl08x_debugfs_operations
);
1845 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1850 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1852 struct pl08x_driver_data
*pl08x
;
1853 const struct vendor_data
*vd
= id
->data
;
1857 ret
= amba_request_regions(adev
, NULL
);
1861 /* Create the driver state holder */
1862 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1868 /* Initialize memcpy engine */
1869 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1870 pl08x
->memcpy
.dev
= &adev
->dev
;
1871 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1872 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1873 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1874 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1875 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1876 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1877 pl08x
->memcpy
.device_control
= pl08x_control
;
1879 /* Initialize slave engine */
1880 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1881 pl08x
->slave
.dev
= &adev
->dev
;
1882 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1883 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1884 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1885 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1886 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1887 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1888 pl08x
->slave
.device_control
= pl08x_control
;
1890 /* Get the platform data */
1891 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1893 dev_err(&adev
->dev
, "no platform data supplied\n");
1895 goto out_no_platdata
;
1898 /* Assign useful pointers to the driver state */
1902 /* By default, AHB1 only. If dualmaster, from platform */
1903 pl08x
->lli_buses
= PL08X_AHB1
;
1904 pl08x
->mem_buses
= PL08X_AHB1
;
1905 if (pl08x
->vd
->dualmaster
) {
1906 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
1907 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
1910 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1911 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1912 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1915 goto out_no_lli_pool
;
1918 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
1921 goto out_no_ioremap
;
1924 /* Turn on the PL08x */
1925 pl08x_ensure_on(pl08x
);
1927 /* Attach the interrupt handler */
1928 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1929 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
1931 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
1932 DRIVER_NAME
, pl08x
);
1934 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
1935 __func__
, adev
->irq
[0]);
1939 /* Initialize physical channels */
1940 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
1942 if (!pl08x
->phy_chans
) {
1943 dev_err(&adev
->dev
, "%s failed to allocate "
1944 "physical channel holders\n",
1947 goto out_no_phychans
;
1950 for (i
= 0; i
< vd
->channels
; i
++) {
1951 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
1954 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
1955 spin_lock_init(&ch
->lock
);
1958 * Nomadik variants can have channels that are locked
1959 * down for the secure world only. Lock up these channels
1960 * by perpetually serving a dummy virtual channel.
1965 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
1966 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
1967 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
1972 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
1973 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
1976 /* Register as many memcpy channels as there are physical channels */
1977 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
1978 pl08x
->vd
->channels
, false);
1980 dev_warn(&pl08x
->adev
->dev
,
1981 "%s failed to enumerate memcpy channels - %d\n",
1985 pl08x
->memcpy
.chancnt
= ret
;
1987 /* Register slave channels */
1988 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
1989 pl08x
->pd
->num_slave_channels
, true);
1991 dev_warn(&pl08x
->adev
->dev
,
1992 "%s failed to enumerate slave channels - %d\n",
1996 pl08x
->slave
.chancnt
= ret
;
1998 ret
= dma_async_device_register(&pl08x
->memcpy
);
2000 dev_warn(&pl08x
->adev
->dev
,
2001 "%s failed to register memcpy as an async device - %d\n",
2003 goto out_no_memcpy_reg
;
2006 ret
= dma_async_device_register(&pl08x
->slave
);
2008 dev_warn(&pl08x
->adev
->dev
,
2009 "%s failed to register slave as an async device - %d\n",
2011 goto out_no_slave_reg
;
2014 amba_set_drvdata(adev
, pl08x
);
2015 init_pl08x_debugfs(pl08x
);
2016 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2017 amba_part(adev
), amba_rev(adev
),
2018 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2023 dma_async_device_unregister(&pl08x
->memcpy
);
2025 pl08x_free_virtual_channels(&pl08x
->slave
);
2027 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2029 kfree(pl08x
->phy_chans
);
2031 free_irq(adev
->irq
[0], pl08x
);
2033 iounmap(pl08x
->base
);
2035 dma_pool_destroy(pl08x
->pool
);
2040 amba_release_regions(adev
);
2044 /* PL080 has 8 channels and the PL080 have just 2 */
2045 static struct vendor_data vendor_pl080
= {
2050 static struct vendor_data vendor_nomadik
= {
2056 static struct vendor_data vendor_pl081
= {
2058 .dualmaster
= false,
2061 static struct amba_id pl08x_ids
[] = {
2066 .data
= &vendor_pl080
,
2072 .data
= &vendor_pl081
,
2074 /* Nomadik 8815 PL080 variant */
2078 .data
= &vendor_nomadik
,
2083 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2085 static struct amba_driver pl08x_amba_driver
= {
2086 .drv
.name
= DRIVER_NAME
,
2087 .id_table
= pl08x_ids
,
2088 .probe
= pl08x_probe
,
2091 static int __init
pl08x_init(void)
2094 retval
= amba_driver_register(&pl08x_amba_driver
);
2096 printk(KERN_WARNING DRIVER_NAME
2097 "failed to register as an AMBA device (%d)\n",
2101 subsys_initcall(pl08x_init
);