2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
17 #include <linux/clk.h>
18 #include <linux/dmaengine.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmapool.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
26 #include <linux/of_device.h>
27 #include <linux/of_dma.h>
29 #include "at_hdmac_regs.h"
30 #include "dmaengine.h"
36 * at_hdmac : Name of the ATmel AHB DMA Controller
37 * at_dma_ / atdma : ATmel DMA controller entity related
38 * atc_ / atchan : ATmel DMA Channel entity related
41 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
42 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
43 |ATC_DIF(AT_DMA_MEM_IF))
46 * Initial number of descriptors to allocate for each channel. This could
47 * be increased during dma usage.
49 static unsigned int init_nr_desc_per_channel
= 64;
50 module_param(init_nr_desc_per_channel
, uint
, 0644);
51 MODULE_PARM_DESC(init_nr_desc_per_channel
,
52 "initial descriptors per channel (default: 64)");
56 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
);
59 /*----------------------------------------------------------------------*/
61 static struct at_desc
*atc_first_active(struct at_dma_chan
*atchan
)
63 return list_first_entry(&atchan
->active_list
,
64 struct at_desc
, desc_node
);
67 static struct at_desc
*atc_first_queued(struct at_dma_chan
*atchan
)
69 return list_first_entry(&atchan
->queue
,
70 struct at_desc
, desc_node
);
74 * atc_alloc_descriptor - allocate and return an initialized descriptor
75 * @chan: the channel to allocate descriptors for
76 * @gfp_flags: GFP allocation flags
78 * Note: The ack-bit is positioned in the descriptor flag at creation time
79 * to make initial allocation more convenient. This bit will be cleared
80 * and control will be given to client at usage time (during
81 * preparation functions).
83 static struct at_desc
*atc_alloc_descriptor(struct dma_chan
*chan
,
86 struct at_desc
*desc
= NULL
;
87 struct at_dma
*atdma
= to_at_dma(chan
->device
);
90 desc
= dma_pool_alloc(atdma
->dma_desc_pool
, gfp_flags
, &phys
);
92 memset(desc
, 0, sizeof(struct at_desc
));
93 INIT_LIST_HEAD(&desc
->tx_list
);
94 dma_async_tx_descriptor_init(&desc
->txd
, chan
);
95 /* txd.flags will be overwritten in prep functions */
96 desc
->txd
.flags
= DMA_CTRL_ACK
;
97 desc
->txd
.tx_submit
= atc_tx_submit
;
98 desc
->txd
.phys
= phys
;
105 * atc_desc_get - get an unused descriptor from free_list
106 * @atchan: channel we want a new descriptor for
108 static struct at_desc
*atc_desc_get(struct at_dma_chan
*atchan
)
110 struct at_desc
*desc
, *_desc
;
111 struct at_desc
*ret
= NULL
;
116 spin_lock_irqsave(&atchan
->lock
, flags
);
117 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
119 if (async_tx_test_ack(&desc
->txd
)) {
120 list_del(&desc
->desc_node
);
124 dev_dbg(chan2dev(&atchan
->chan_common
),
125 "desc %p not ACKed\n", desc
);
127 spin_unlock_irqrestore(&atchan
->lock
, flags
);
128 dev_vdbg(chan2dev(&atchan
->chan_common
),
129 "scanned %u descriptors on freelist\n", i
);
131 /* no more descriptor available in initial pool: create one more */
133 ret
= atc_alloc_descriptor(&atchan
->chan_common
, GFP_ATOMIC
);
135 spin_lock_irqsave(&atchan
->lock
, flags
);
136 atchan
->descs_allocated
++;
137 spin_unlock_irqrestore(&atchan
->lock
, flags
);
139 dev_err(chan2dev(&atchan
->chan_common
),
140 "not enough descriptors available\n");
148 * atc_desc_put - move a descriptor, including any children, to the free list
149 * @atchan: channel we work on
150 * @desc: descriptor, at the head of a chain, to move to free list
152 static void atc_desc_put(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
155 struct at_desc
*child
;
158 spin_lock_irqsave(&atchan
->lock
, flags
);
159 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
160 dev_vdbg(chan2dev(&atchan
->chan_common
),
161 "moving child desc %p to freelist\n",
163 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
164 dev_vdbg(chan2dev(&atchan
->chan_common
),
165 "moving desc %p to freelist\n", desc
);
166 list_add(&desc
->desc_node
, &atchan
->free_list
);
167 spin_unlock_irqrestore(&atchan
->lock
, flags
);
172 * atc_desc_chain - build chain adding a descriptor
173 * @first: address of first descriptor of the chain
174 * @prev: address of previous descriptor of the chain
175 * @desc: descriptor to queue
177 * Called from prep_* functions
179 static void atc_desc_chain(struct at_desc
**first
, struct at_desc
**prev
,
180 struct at_desc
*desc
)
185 /* inform the HW lli about chaining */
186 (*prev
)->lli
.dscr
= desc
->txd
.phys
;
187 /* insert the link descriptor to the LD ring */
188 list_add_tail(&desc
->desc_node
,
195 * atc_dostart - starts the DMA engine for real
196 * @atchan: the channel we want to start
197 * @first: first descriptor in the list we want to begin with
199 * Called with atchan->lock held and bh disabled
201 static void atc_dostart(struct at_dma_chan
*atchan
, struct at_desc
*first
)
203 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
205 /* ASSERT: channel is idle */
206 if (atc_chan_is_enabled(atchan
)) {
207 dev_err(chan2dev(&atchan
->chan_common
),
208 "BUG: Attempted to start non-idle channel\n");
209 dev_err(chan2dev(&atchan
->chan_common
),
210 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
211 channel_readl(atchan
, SADDR
),
212 channel_readl(atchan
, DADDR
),
213 channel_readl(atchan
, CTRLA
),
214 channel_readl(atchan
, CTRLB
),
215 channel_readl(atchan
, DSCR
));
217 /* The tasklet will hopefully advance the queue... */
221 vdbg_dump_regs(atchan
);
223 channel_writel(atchan
, SADDR
, 0);
224 channel_writel(atchan
, DADDR
, 0);
225 channel_writel(atchan
, CTRLA
, 0);
226 channel_writel(atchan
, CTRLB
, 0);
227 channel_writel(atchan
, DSCR
, first
->txd
.phys
);
228 dma_writel(atdma
, CHER
, atchan
->mask
);
230 vdbg_dump_regs(atchan
);
234 * atc_chain_complete - finish work for one transaction chain
235 * @atchan: channel we work on
236 * @desc: descriptor at the head of the chain we want do complete
238 * Called with atchan->lock held and bh disabled */
240 atc_chain_complete(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
242 struct dma_async_tx_descriptor
*txd
= &desc
->txd
;
244 dev_vdbg(chan2dev(&atchan
->chan_common
),
245 "descriptor %u complete\n", txd
->cookie
);
247 /* mark the descriptor as complete for non cyclic cases only */
248 if (!atc_chan_is_cyclic(atchan
))
249 dma_cookie_complete(txd
);
251 /* move children to free_list */
252 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
253 /* move myself to free_list */
254 list_move(&desc
->desc_node
, &atchan
->free_list
);
256 /* unmap dma addresses (not on slave channels) */
257 if (!atchan
->chan_common
.private) {
258 struct device
*parent
= chan2parent(&atchan
->chan_common
);
259 if (!(txd
->flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
260 if (txd
->flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
261 dma_unmap_single(parent
,
263 desc
->len
, DMA_FROM_DEVICE
);
265 dma_unmap_page(parent
,
267 desc
->len
, DMA_FROM_DEVICE
);
269 if (!(txd
->flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
270 if (txd
->flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
271 dma_unmap_single(parent
,
273 desc
->len
, DMA_TO_DEVICE
);
275 dma_unmap_page(parent
,
277 desc
->len
, DMA_TO_DEVICE
);
281 /* for cyclic transfers,
282 * no need to replay callback function while stopping */
283 if (!atc_chan_is_cyclic(atchan
)) {
284 dma_async_tx_callback callback
= txd
->callback
;
285 void *param
= txd
->callback_param
;
288 * The API requires that no submissions are done from a
289 * callback, so we don't need to drop the lock here
295 dma_run_dependencies(txd
);
299 * atc_complete_all - finish work for all transactions
300 * @atchan: channel to complete transactions for
302 * Eventually submit queued descriptors if any
304 * Assume channel is idle while calling this function
305 * Called with atchan->lock held and bh disabled
307 static void atc_complete_all(struct at_dma_chan
*atchan
)
309 struct at_desc
*desc
, *_desc
;
312 dev_vdbg(chan2dev(&atchan
->chan_common
), "complete all\n");
315 * Submit queued descriptors ASAP, i.e. before we go through
316 * the completed ones.
318 if (!list_empty(&atchan
->queue
))
319 atc_dostart(atchan
, atc_first_queued(atchan
));
320 /* empty active_list now it is completed */
321 list_splice_init(&atchan
->active_list
, &list
);
322 /* empty queue list by moving descriptors (if any) to active_list */
323 list_splice_init(&atchan
->queue
, &atchan
->active_list
);
325 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
326 atc_chain_complete(atchan
, desc
);
330 * atc_cleanup_descriptors - cleanup up finished descriptors in active_list
331 * @atchan: channel to be cleaned up
333 * Called with atchan->lock held and bh disabled
335 static void atc_cleanup_descriptors(struct at_dma_chan
*atchan
)
337 struct at_desc
*desc
, *_desc
;
338 struct at_desc
*child
;
340 dev_vdbg(chan2dev(&atchan
->chan_common
), "cleanup descriptors\n");
342 list_for_each_entry_safe(desc
, _desc
, &atchan
->active_list
, desc_node
) {
343 if (!(desc
->lli
.ctrla
& ATC_DONE
))
344 /* This one is currently in progress */
347 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
348 if (!(child
->lli
.ctrla
& ATC_DONE
))
349 /* Currently in progress */
353 * No descriptors so far seem to be in progress, i.e.
354 * this chain must be done.
356 atc_chain_complete(atchan
, desc
);
361 * atc_advance_work - at the end of a transaction, move forward
362 * @atchan: channel where the transaction ended
364 * Called with atchan->lock held and bh disabled
366 static void atc_advance_work(struct at_dma_chan
*atchan
)
368 dev_vdbg(chan2dev(&atchan
->chan_common
), "advance_work\n");
370 if (atc_chan_is_enabled(atchan
))
373 if (list_empty(&atchan
->active_list
) ||
374 list_is_singular(&atchan
->active_list
)) {
375 atc_complete_all(atchan
);
377 atc_chain_complete(atchan
, atc_first_active(atchan
));
379 atc_dostart(atchan
, atc_first_active(atchan
));
385 * atc_handle_error - handle errors reported by DMA controller
386 * @atchan: channel where error occurs
388 * Called with atchan->lock held and bh disabled
390 static void atc_handle_error(struct at_dma_chan
*atchan
)
392 struct at_desc
*bad_desc
;
393 struct at_desc
*child
;
396 * The descriptor currently at the head of the active list is
397 * broked. Since we don't have any way to report errors, we'll
398 * just have to scream loudly and try to carry on.
400 bad_desc
= atc_first_active(atchan
);
401 list_del_init(&bad_desc
->desc_node
);
403 /* As we are stopped, take advantage to push queued descriptors
405 list_splice_init(&atchan
->queue
, atchan
->active_list
.prev
);
407 /* Try to restart the controller */
408 if (!list_empty(&atchan
->active_list
))
409 atc_dostart(atchan
, atc_first_active(atchan
));
412 * KERN_CRITICAL may seem harsh, but since this only happens
413 * when someone submits a bad physical address in a
414 * descriptor, we should consider ourselves lucky that the
415 * controller flagged an error instead of scribbling over
416 * random memory locations.
418 dev_crit(chan2dev(&atchan
->chan_common
),
419 "Bad descriptor submitted for DMA!\n");
420 dev_crit(chan2dev(&atchan
->chan_common
),
421 " cookie: %d\n", bad_desc
->txd
.cookie
);
422 atc_dump_lli(atchan
, &bad_desc
->lli
);
423 list_for_each_entry(child
, &bad_desc
->tx_list
, desc_node
)
424 atc_dump_lli(atchan
, &child
->lli
);
426 /* Pretend the descriptor completed successfully */
427 atc_chain_complete(atchan
, bad_desc
);
431 * atc_handle_cyclic - at the end of a period, run callback function
432 * @atchan: channel used for cyclic operations
434 * Called with atchan->lock held and bh disabled
436 static void atc_handle_cyclic(struct at_dma_chan
*atchan
)
438 struct at_desc
*first
= atc_first_active(atchan
);
439 struct dma_async_tx_descriptor
*txd
= &first
->txd
;
440 dma_async_tx_callback callback
= txd
->callback
;
441 void *param
= txd
->callback_param
;
443 dev_vdbg(chan2dev(&atchan
->chan_common
),
444 "new cyclic period llp 0x%08x\n",
445 channel_readl(atchan
, DSCR
));
451 /*-- IRQ & Tasklet ---------------------------------------------------*/
453 static void atc_tasklet(unsigned long data
)
455 struct at_dma_chan
*atchan
= (struct at_dma_chan
*)data
;
458 spin_lock_irqsave(&atchan
->lock
, flags
);
459 if (test_and_clear_bit(ATC_IS_ERROR
, &atchan
->status
))
460 atc_handle_error(atchan
);
461 else if (atc_chan_is_cyclic(atchan
))
462 atc_handle_cyclic(atchan
);
464 atc_advance_work(atchan
);
466 spin_unlock_irqrestore(&atchan
->lock
, flags
);
469 static irqreturn_t
at_dma_interrupt(int irq
, void *dev_id
)
471 struct at_dma
*atdma
= (struct at_dma
*)dev_id
;
472 struct at_dma_chan
*atchan
;
474 u32 status
, pending
, imr
;
478 imr
= dma_readl(atdma
, EBCIMR
);
479 status
= dma_readl(atdma
, EBCISR
);
480 pending
= status
& imr
;
485 dev_vdbg(atdma
->dma_common
.dev
,
486 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
487 status
, imr
, pending
);
489 for (i
= 0; i
< atdma
->dma_common
.chancnt
; i
++) {
490 atchan
= &atdma
->chan
[i
];
491 if (pending
& (AT_DMA_BTC(i
) | AT_DMA_ERR(i
))) {
492 if (pending
& AT_DMA_ERR(i
)) {
493 /* Disable channel on AHB error */
494 dma_writel(atdma
, CHDR
,
495 AT_DMA_RES(i
) | atchan
->mask
);
496 /* Give information to tasklet */
497 set_bit(ATC_IS_ERROR
, &atchan
->status
);
499 tasklet_schedule(&atchan
->tasklet
);
510 /*-- DMA Engine API --------------------------------------------------*/
513 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
514 * @desc: descriptor at the head of the transaction chain
516 * Queue chain if DMA engine is working already
518 * Cookie increment and adding to active_list or queue must be atomic
520 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
)
522 struct at_desc
*desc
= txd_to_at_desc(tx
);
523 struct at_dma_chan
*atchan
= to_at_dma_chan(tx
->chan
);
527 spin_lock_irqsave(&atchan
->lock
, flags
);
528 cookie
= dma_cookie_assign(tx
);
530 if (list_empty(&atchan
->active_list
)) {
531 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: started %u\n",
533 atc_dostart(atchan
, desc
);
534 list_add_tail(&desc
->desc_node
, &atchan
->active_list
);
536 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: queued %u\n",
538 list_add_tail(&desc
->desc_node
, &atchan
->queue
);
541 spin_unlock_irqrestore(&atchan
->lock
, flags
);
547 * atc_prep_dma_memcpy - prepare a memcpy operation
548 * @chan: the channel to prepare operation on
549 * @dest: operation virtual destination address
550 * @src: operation virtual source address
551 * @len: operation length
552 * @flags: tx descriptor status flags
554 static struct dma_async_tx_descriptor
*
555 atc_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
556 size_t len
, unsigned long flags
)
558 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
559 struct at_desc
*desc
= NULL
;
560 struct at_desc
*first
= NULL
;
561 struct at_desc
*prev
= NULL
;
564 unsigned int src_width
;
565 unsigned int dst_width
;
569 dev_vdbg(chan2dev(chan
), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
570 dest
, src
, len
, flags
);
572 if (unlikely(!len
)) {
573 dev_dbg(chan2dev(chan
), "prep_dma_memcpy: length is zero!\n");
577 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
578 | ATC_SRC_ADDR_MODE_INCR
579 | ATC_DST_ADDR_MODE_INCR
583 * We can be a lot more clever here, but this should take care
584 * of the most common optimization.
586 if (!((src
| dest
| len
) & 3)) {
587 ctrla
= ATC_SRC_WIDTH_WORD
| ATC_DST_WIDTH_WORD
;
588 src_width
= dst_width
= 2;
589 } else if (!((src
| dest
| len
) & 1)) {
590 ctrla
= ATC_SRC_WIDTH_HALFWORD
| ATC_DST_WIDTH_HALFWORD
;
591 src_width
= dst_width
= 1;
593 ctrla
= ATC_SRC_WIDTH_BYTE
| ATC_DST_WIDTH_BYTE
;
594 src_width
= dst_width
= 0;
597 for (offset
= 0; offset
< len
; offset
+= xfer_count
<< src_width
) {
598 xfer_count
= min_t(size_t, (len
- offset
) >> src_width
,
601 desc
= atc_desc_get(atchan
);
605 desc
->lli
.saddr
= src
+ offset
;
606 desc
->lli
.daddr
= dest
+ offset
;
607 desc
->lli
.ctrla
= ctrla
| xfer_count
;
608 desc
->lli
.ctrlb
= ctrlb
;
610 desc
->txd
.cookie
= 0;
612 atc_desc_chain(&first
, &prev
, desc
);
615 /* First descriptor of the chain embedds additional information */
616 first
->txd
.cookie
= -EBUSY
;
618 first
->tx_width
= src_width
;
620 /* set end-of-link to the last link descriptor of list*/
623 first
->txd
.flags
= flags
; /* client is in control of this ack */
628 atc_desc_put(atchan
, first
);
634 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
636 * @sgl: scatterlist to transfer to/from
637 * @sg_len: number of entries in @scatterlist
638 * @direction: DMA direction
639 * @flags: tx descriptor status flags
640 * @context: transaction context (ignored)
642 static struct dma_async_tx_descriptor
*
643 atc_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
644 unsigned int sg_len
, enum dma_transfer_direction direction
,
645 unsigned long flags
, void *context
)
647 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
648 struct at_dma_slave
*atslave
= chan
->private;
649 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
650 struct at_desc
*first
= NULL
;
651 struct at_desc
*prev
= NULL
;
655 unsigned int reg_width
;
656 unsigned int mem_width
;
658 struct scatterlist
*sg
;
659 size_t total_len
= 0;
661 dev_vdbg(chan2dev(chan
), "prep_slave_sg (%d): %s f0x%lx\n",
663 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
666 if (unlikely(!atslave
|| !sg_len
)) {
667 dev_dbg(chan2dev(chan
), "prep_slave_sg: sg length is zero!\n");
671 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
672 | ATC_DCSIZE(sconfig
->dst_maxburst
);
677 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
678 ctrla
|= ATC_DST_WIDTH(reg_width
);
679 ctrlb
|= ATC_DST_ADDR_MODE_FIXED
680 | ATC_SRC_ADDR_MODE_INCR
682 | ATC_SIF(atchan
->mem_if
) | ATC_DIF(atchan
->per_if
);
683 reg
= sconfig
->dst_addr
;
684 for_each_sg(sgl
, sg
, sg_len
, i
) {
685 struct at_desc
*desc
;
689 desc
= atc_desc_get(atchan
);
693 mem
= sg_dma_address(sg
);
694 len
= sg_dma_len(sg
);
695 if (unlikely(!len
)) {
696 dev_dbg(chan2dev(chan
),
697 "prep_slave_sg: sg(%d) data length is zero\n", i
);
701 if (unlikely(mem
& 3 || len
& 3))
704 desc
->lli
.saddr
= mem
;
705 desc
->lli
.daddr
= reg
;
706 desc
->lli
.ctrla
= ctrla
707 | ATC_SRC_WIDTH(mem_width
)
709 desc
->lli
.ctrlb
= ctrlb
;
711 atc_desc_chain(&first
, &prev
, desc
);
716 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
717 ctrla
|= ATC_SRC_WIDTH(reg_width
);
718 ctrlb
|= ATC_DST_ADDR_MODE_INCR
719 | ATC_SRC_ADDR_MODE_FIXED
721 | ATC_SIF(atchan
->per_if
) | ATC_DIF(atchan
->mem_if
);
723 reg
= sconfig
->src_addr
;
724 for_each_sg(sgl
, sg
, sg_len
, i
) {
725 struct at_desc
*desc
;
729 desc
= atc_desc_get(atchan
);
733 mem
= sg_dma_address(sg
);
734 len
= sg_dma_len(sg
);
735 if (unlikely(!len
)) {
736 dev_dbg(chan2dev(chan
),
737 "prep_slave_sg: sg(%d) data length is zero\n", i
);
741 if (unlikely(mem
& 3 || len
& 3))
744 desc
->lli
.saddr
= reg
;
745 desc
->lli
.daddr
= mem
;
746 desc
->lli
.ctrla
= ctrla
747 | ATC_DST_WIDTH(mem_width
)
749 desc
->lli
.ctrlb
= ctrlb
;
751 atc_desc_chain(&first
, &prev
, desc
);
759 /* set end-of-link to the last link descriptor of list*/
762 /* First descriptor of the chain embedds additional information */
763 first
->txd
.cookie
= -EBUSY
;
764 first
->len
= total_len
;
765 first
->tx_width
= reg_width
;
767 /* first link descriptor of list is responsible of flags */
768 first
->txd
.flags
= flags
; /* client is in control of this ack */
773 dev_err(chan2dev(chan
), "not enough descriptors available\n");
775 atc_desc_put(atchan
, first
);
780 * atc_dma_cyclic_check_values
781 * Check for too big/unaligned periods and unaligned DMA buffer
784 atc_dma_cyclic_check_values(unsigned int reg_width
, dma_addr_t buf_addr
,
787 if (period_len
> (ATC_BTSIZE_MAX
<< reg_width
))
789 if (unlikely(period_len
& ((1 << reg_width
) - 1)))
791 if (unlikely(buf_addr
& ((1 << reg_width
) - 1)))
801 * atc_dma_cyclic_fill_desc - Fill one period descriptor
804 atc_dma_cyclic_fill_desc(struct dma_chan
*chan
, struct at_desc
*desc
,
805 unsigned int period_index
, dma_addr_t buf_addr
,
806 unsigned int reg_width
, size_t period_len
,
807 enum dma_transfer_direction direction
)
809 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
810 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
813 /* prepare common CRTLA value */
814 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
815 | ATC_DCSIZE(sconfig
->dst_maxburst
)
816 | ATC_DST_WIDTH(reg_width
)
817 | ATC_SRC_WIDTH(reg_width
)
818 | period_len
>> reg_width
;
822 desc
->lli
.saddr
= buf_addr
+ (period_len
* period_index
);
823 desc
->lli
.daddr
= sconfig
->dst_addr
;
824 desc
->lli
.ctrla
= ctrla
;
825 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_FIXED
826 | ATC_SRC_ADDR_MODE_INCR
828 | ATC_SIF(atchan
->mem_if
)
829 | ATC_DIF(atchan
->per_if
);
833 desc
->lli
.saddr
= sconfig
->src_addr
;
834 desc
->lli
.daddr
= buf_addr
+ (period_len
* period_index
);
835 desc
->lli
.ctrla
= ctrla
;
836 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_INCR
837 | ATC_SRC_ADDR_MODE_FIXED
839 | ATC_SIF(atchan
->per_if
)
840 | ATC_DIF(atchan
->mem_if
);
851 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
852 * @chan: the DMA channel to prepare
853 * @buf_addr: physical DMA address where the buffer starts
854 * @buf_len: total number of bytes for the entire buffer
855 * @period_len: number of bytes for each period
856 * @direction: transfer direction, to or from device
857 * @flags: tx descriptor status flags
858 * @context: transfer context (ignored)
860 static struct dma_async_tx_descriptor
*
861 atc_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
862 size_t period_len
, enum dma_transfer_direction direction
,
863 unsigned long flags
, void *context
)
865 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
866 struct at_dma_slave
*atslave
= chan
->private;
867 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
868 struct at_desc
*first
= NULL
;
869 struct at_desc
*prev
= NULL
;
870 unsigned long was_cyclic
;
871 unsigned int reg_width
;
872 unsigned int periods
= buf_len
/ period_len
;
875 dev_vdbg(chan2dev(chan
), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
876 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
878 periods
, buf_len
, period_len
);
880 if (unlikely(!atslave
|| !buf_len
|| !period_len
)) {
881 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: length is zero!\n");
885 was_cyclic
= test_and_set_bit(ATC_IS_CYCLIC
, &atchan
->status
);
887 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: channel in use!\n");
891 if (unlikely(!is_slave_direction(direction
)))
894 if (sconfig
->direction
== DMA_MEM_TO_DEV
)
895 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
897 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
899 /* Check for too big/unaligned periods and unaligned DMA buffer */
900 if (atc_dma_cyclic_check_values(reg_width
, buf_addr
, period_len
))
903 /* build cyclic linked list */
904 for (i
= 0; i
< periods
; i
++) {
905 struct at_desc
*desc
;
907 desc
= atc_desc_get(atchan
);
911 if (atc_dma_cyclic_fill_desc(chan
, desc
, i
, buf_addr
,
912 reg_width
, period_len
, direction
))
915 atc_desc_chain(&first
, &prev
, desc
);
918 /* lets make a cyclic list */
919 prev
->lli
.dscr
= first
->txd
.phys
;
921 /* First descriptor of the chain embedds additional information */
922 first
->txd
.cookie
= -EBUSY
;
923 first
->len
= buf_len
;
924 first
->tx_width
= reg_width
;
929 dev_err(chan2dev(chan
), "not enough descriptors available\n");
930 atc_desc_put(atchan
, first
);
932 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
936 static int set_runtime_config(struct dma_chan
*chan
,
937 struct dma_slave_config
*sconfig
)
939 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
941 /* Check if it is chan is configured for slave transfers */
945 memcpy(&atchan
->dma_sconfig
, sconfig
, sizeof(*sconfig
));
947 convert_burst(&atchan
->dma_sconfig
.src_maxburst
);
948 convert_burst(&atchan
->dma_sconfig
.dst_maxburst
);
954 static int atc_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
957 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
958 struct at_dma
*atdma
= to_at_dma(chan
->device
);
959 int chan_id
= atchan
->chan_common
.chan_id
;
964 dev_vdbg(chan2dev(chan
), "atc_control (%d)\n", cmd
);
966 if (cmd
== DMA_PAUSE
) {
967 spin_lock_irqsave(&atchan
->lock
, flags
);
969 dma_writel(atdma
, CHER
, AT_DMA_SUSP(chan_id
));
970 set_bit(ATC_IS_PAUSED
, &atchan
->status
);
972 spin_unlock_irqrestore(&atchan
->lock
, flags
);
973 } else if (cmd
== DMA_RESUME
) {
974 if (!atc_chan_is_paused(atchan
))
977 spin_lock_irqsave(&atchan
->lock
, flags
);
979 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
));
980 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
982 spin_unlock_irqrestore(&atchan
->lock
, flags
);
983 } else if (cmd
== DMA_TERMINATE_ALL
) {
984 struct at_desc
*desc
, *_desc
;
986 * This is only called when something went wrong elsewhere, so
987 * we don't really care about the data. Just disable the
988 * channel. We still have to poll the channel enable bit due
989 * to AHB/HSB limitations.
991 spin_lock_irqsave(&atchan
->lock
, flags
);
993 /* disabling channel: must also remove suspend state */
994 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
) | atchan
->mask
);
996 /* confirm that this channel is disabled */
997 while (dma_readl(atdma
, CHSR
) & atchan
->mask
)
1000 /* active_list entries will end up before queued entries */
1001 list_splice_init(&atchan
->queue
, &list
);
1002 list_splice_init(&atchan
->active_list
, &list
);
1004 /* Flush all pending and queued descriptors */
1005 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
1006 atc_chain_complete(atchan
, desc
);
1008 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1009 /* if channel dedicated to cyclic operations, free it */
1010 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1012 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1013 } else if (cmd
== DMA_SLAVE_CONFIG
) {
1014 return set_runtime_config(chan
, (struct dma_slave_config
*)arg
);
1023 * atc_tx_status - poll for transaction completion
1024 * @chan: DMA channel
1025 * @cookie: transaction identifier to check status of
1026 * @txstate: if not %NULL updated with transaction state
1028 * If @txstate is passed in, upon return it reflect the driver
1029 * internal state and can be used with dma_async_is_complete() to check
1030 * the status of multiple cookies without re-checking hardware state.
1032 static enum dma_status
1033 atc_tx_status(struct dma_chan
*chan
,
1034 dma_cookie_t cookie
,
1035 struct dma_tx_state
*txstate
)
1037 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1038 dma_cookie_t last_used
;
1039 dma_cookie_t last_complete
;
1040 unsigned long flags
;
1041 enum dma_status ret
;
1043 spin_lock_irqsave(&atchan
->lock
, flags
);
1045 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1046 if (ret
!= DMA_SUCCESS
) {
1047 atc_cleanup_descriptors(atchan
);
1049 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1052 last_complete
= chan
->completed_cookie
;
1053 last_used
= chan
->cookie
;
1055 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1057 if (ret
!= DMA_SUCCESS
)
1058 dma_set_residue(txstate
, atc_first_active(atchan
)->len
);
1060 if (atc_chan_is_paused(atchan
))
1063 dev_vdbg(chan2dev(chan
), "tx_status %d: cookie = %d (d%d, u%d)\n",
1064 ret
, cookie
, last_complete
? last_complete
: 0,
1065 last_used
? last_used
: 0);
1071 * atc_issue_pending - try to finish work
1072 * @chan: target DMA channel
1074 static void atc_issue_pending(struct dma_chan
*chan
)
1076 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1077 unsigned long flags
;
1079 dev_vdbg(chan2dev(chan
), "issue_pending\n");
1081 /* Not needed for cyclic transfers */
1082 if (atc_chan_is_cyclic(atchan
))
1085 spin_lock_irqsave(&atchan
->lock
, flags
);
1086 atc_advance_work(atchan
);
1087 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1091 * atc_alloc_chan_resources - allocate resources for DMA channel
1092 * @chan: allocate descriptor resources for this channel
1093 * @client: current client requesting the channel be ready for requests
1095 * return - the number of allocated descriptors
1097 static int atc_alloc_chan_resources(struct dma_chan
*chan
)
1099 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1100 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1101 struct at_desc
*desc
;
1102 struct at_dma_slave
*atslave
;
1103 unsigned long flags
;
1106 LIST_HEAD(tmp_list
);
1108 dev_vdbg(chan2dev(chan
), "alloc_chan_resources\n");
1110 /* ASSERT: channel is idle */
1111 if (atc_chan_is_enabled(atchan
)) {
1112 dev_dbg(chan2dev(chan
), "DMA channel not idle ?\n");
1116 cfg
= ATC_DEFAULT_CFG
;
1118 atslave
= chan
->private;
1121 * We need controller-specific data to set up slave
1124 BUG_ON(!atslave
->dma_dev
|| atslave
->dma_dev
!= atdma
->dma_common
.dev
);
1126 /* if cfg configuration specified take it instead of default */
1131 /* have we already been set up?
1132 * reconfigure channel but no need to reallocate descriptors */
1133 if (!list_empty(&atchan
->free_list
))
1134 return atchan
->descs_allocated
;
1136 /* Allocate initial pool of descriptors */
1137 for (i
= 0; i
< init_nr_desc_per_channel
; i
++) {
1138 desc
= atc_alloc_descriptor(chan
, GFP_KERNEL
);
1140 dev_err(atdma
->dma_common
.dev
,
1141 "Only %d initial descriptors\n", i
);
1144 list_add_tail(&desc
->desc_node
, &tmp_list
);
1147 spin_lock_irqsave(&atchan
->lock
, flags
);
1148 atchan
->descs_allocated
= i
;
1149 list_splice(&tmp_list
, &atchan
->free_list
);
1150 dma_cookie_init(chan
);
1151 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1153 /* channel parameters */
1154 channel_writel(atchan
, CFG
, cfg
);
1156 dev_dbg(chan2dev(chan
),
1157 "alloc_chan_resources: allocated %d descriptors\n",
1158 atchan
->descs_allocated
);
1160 return atchan
->descs_allocated
;
1164 * atc_free_chan_resources - free all channel resources
1165 * @chan: DMA channel
1167 static void atc_free_chan_resources(struct dma_chan
*chan
)
1169 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1170 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1171 struct at_desc
*desc
, *_desc
;
1174 dev_dbg(chan2dev(chan
), "free_chan_resources: (descs allocated=%u)\n",
1175 atchan
->descs_allocated
);
1177 /* ASSERT: channel is idle */
1178 BUG_ON(!list_empty(&atchan
->active_list
));
1179 BUG_ON(!list_empty(&atchan
->queue
));
1180 BUG_ON(atc_chan_is_enabled(atchan
));
1182 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
1183 dev_vdbg(chan2dev(chan
), " freeing descriptor %p\n", desc
);
1184 list_del(&desc
->desc_node
);
1185 /* free link descriptor */
1186 dma_pool_free(atdma
->dma_desc_pool
, desc
, desc
->txd
.phys
);
1188 list_splice_init(&atchan
->free_list
, &list
);
1189 atchan
->descs_allocated
= 0;
1192 dev_vdbg(chan2dev(chan
), "free_chan_resources: done\n");
1196 static bool at_dma_filter(struct dma_chan
*chan
, void *slave
)
1198 struct at_dma_slave
*atslave
= slave
;
1200 if (atslave
->dma_dev
== chan
->device
->dev
) {
1201 chan
->private = atslave
;
1208 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1209 struct of_dma
*of_dma
)
1211 struct dma_chan
*chan
;
1212 struct at_dma_chan
*atchan
;
1213 struct at_dma_slave
*atslave
;
1214 dma_cap_mask_t mask
;
1215 unsigned int per_id
;
1216 struct platform_device
*dmac_pdev
;
1218 if (dma_spec
->args_count
!= 2)
1221 dmac_pdev
= of_find_device_by_node(dma_spec
->np
);
1224 dma_cap_set(DMA_SLAVE
, mask
);
1226 atslave
= devm_kzalloc(&dmac_pdev
->dev
, sizeof(*atslave
), GFP_KERNEL
);
1230 * We can fill both SRC_PER and DST_PER, one of these fields will be
1231 * ignored depending on DMA transfer direction.
1233 per_id
= dma_spec
->args
[1];
1234 atslave
->cfg
= ATC_FIFOCFG_HALFFIFO
1235 | ATC_DST_H2SEL_HW
| ATC_SRC_H2SEL_HW
1236 | ATC_DST_PER_MSB(per_id
) | ATC_DST_PER(per_id
)
1237 | ATC_SRC_PER_MSB(per_id
) | ATC_SRC_PER(per_id
);
1238 atslave
->dma_dev
= &dmac_pdev
->dev
;
1240 chan
= dma_request_channel(mask
, at_dma_filter
, atslave
);
1244 atchan
= to_at_dma_chan(chan
);
1245 atchan
->per_if
= dma_spec
->args
[0] & 0xff;
1246 atchan
->mem_if
= (dma_spec
->args
[0] >> 16) & 0xff;
1251 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1252 struct of_dma
*of_dma
)
1258 /*-- Module Management -----------------------------------------------*/
1260 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1261 static struct at_dma_platform_data at91sam9rl_config
= {
1264 static struct at_dma_platform_data at91sam9g45_config
= {
1268 #if defined(CONFIG_OF)
1269 static const struct of_device_id atmel_dma_dt_ids
[] = {
1271 .compatible
= "atmel,at91sam9rl-dma",
1272 .data
= &at91sam9rl_config
,
1274 .compatible
= "atmel,at91sam9g45-dma",
1275 .data
= &at91sam9g45_config
,
1281 MODULE_DEVICE_TABLE(of
, atmel_dma_dt_ids
);
1284 static const struct platform_device_id atdma_devtypes
[] = {
1286 .name
= "at91sam9rl_dma",
1287 .driver_data
= (unsigned long) &at91sam9rl_config
,
1289 .name
= "at91sam9g45_dma",
1290 .driver_data
= (unsigned long) &at91sam9g45_config
,
1296 static inline const struct at_dma_platform_data
* __init
at_dma_get_driver_data(
1297 struct platform_device
*pdev
)
1299 if (pdev
->dev
.of_node
) {
1300 const struct of_device_id
*match
;
1301 match
= of_match_node(atmel_dma_dt_ids
, pdev
->dev
.of_node
);
1306 return (struct at_dma_platform_data
*)
1307 platform_get_device_id(pdev
)->driver_data
;
1311 * at_dma_off - disable DMA controller
1312 * @atdma: the Atmel HDAMC device
1314 static void at_dma_off(struct at_dma
*atdma
)
1316 dma_writel(atdma
, EN
, 0);
1318 /* disable all interrupts */
1319 dma_writel(atdma
, EBCIDR
, -1L);
1321 /* confirm that all channels are disabled */
1322 while (dma_readl(atdma
, CHSR
) & atdma
->all_chan_mask
)
1326 static int __init
at_dma_probe(struct platform_device
*pdev
)
1328 struct resource
*io
;
1329 struct at_dma
*atdma
;
1334 const struct at_dma_platform_data
*plat_dat
;
1336 /* setup platform data for each SoC */
1337 dma_cap_set(DMA_MEMCPY
, at91sam9rl_config
.cap_mask
);
1338 dma_cap_set(DMA_MEMCPY
, at91sam9g45_config
.cap_mask
);
1339 dma_cap_set(DMA_SLAVE
, at91sam9g45_config
.cap_mask
);
1341 /* get DMA parameters from controller type */
1342 plat_dat
= at_dma_get_driver_data(pdev
);
1346 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1350 irq
= platform_get_irq(pdev
, 0);
1354 size
= sizeof(struct at_dma
);
1355 size
+= plat_dat
->nr_channels
* sizeof(struct at_dma_chan
);
1356 atdma
= kzalloc(size
, GFP_KERNEL
);
1360 /* discover transaction capabilities */
1361 atdma
->dma_common
.cap_mask
= plat_dat
->cap_mask
;
1362 atdma
->all_chan_mask
= (1 << plat_dat
->nr_channels
) - 1;
1364 size
= resource_size(io
);
1365 if (!request_mem_region(io
->start
, size
, pdev
->dev
.driver
->name
)) {
1370 atdma
->regs
= ioremap(io
->start
, size
);
1376 atdma
->clk
= clk_get(&pdev
->dev
, "dma_clk");
1377 if (IS_ERR(atdma
->clk
)) {
1378 err
= PTR_ERR(atdma
->clk
);
1381 clk_enable(atdma
->clk
);
1383 /* force dma off, just in case */
1386 err
= request_irq(irq
, at_dma_interrupt
, 0, "at_hdmac", atdma
);
1390 platform_set_drvdata(pdev
, atdma
);
1392 /* create a pool of consistent memory blocks for hardware descriptors */
1393 atdma
->dma_desc_pool
= dma_pool_create("at_hdmac_desc_pool",
1394 &pdev
->dev
, sizeof(struct at_desc
),
1395 4 /* word alignment */, 0);
1396 if (!atdma
->dma_desc_pool
) {
1397 dev_err(&pdev
->dev
, "No memory for descriptors dma pool\n");
1399 goto err_pool_create
;
1402 /* clear any pending interrupt */
1403 while (dma_readl(atdma
, EBCISR
))
1406 /* initialize channels related values */
1407 INIT_LIST_HEAD(&atdma
->dma_common
.channels
);
1408 for (i
= 0; i
< plat_dat
->nr_channels
; i
++) {
1409 struct at_dma_chan
*atchan
= &atdma
->chan
[i
];
1411 atchan
->mem_if
= AT_DMA_MEM_IF
;
1412 atchan
->per_if
= AT_DMA_PER_IF
;
1413 atchan
->chan_common
.device
= &atdma
->dma_common
;
1414 dma_cookie_init(&atchan
->chan_common
);
1415 list_add_tail(&atchan
->chan_common
.device_node
,
1416 &atdma
->dma_common
.channels
);
1418 atchan
->ch_regs
= atdma
->regs
+ ch_regs(i
);
1419 spin_lock_init(&atchan
->lock
);
1420 atchan
->mask
= 1 << i
;
1422 INIT_LIST_HEAD(&atchan
->active_list
);
1423 INIT_LIST_HEAD(&atchan
->queue
);
1424 INIT_LIST_HEAD(&atchan
->free_list
);
1426 tasklet_init(&atchan
->tasklet
, atc_tasklet
,
1427 (unsigned long)atchan
);
1428 atc_enable_chan_irq(atdma
, i
);
1431 /* set base routines */
1432 atdma
->dma_common
.device_alloc_chan_resources
= atc_alloc_chan_resources
;
1433 atdma
->dma_common
.device_free_chan_resources
= atc_free_chan_resources
;
1434 atdma
->dma_common
.device_tx_status
= atc_tx_status
;
1435 atdma
->dma_common
.device_issue_pending
= atc_issue_pending
;
1436 atdma
->dma_common
.dev
= &pdev
->dev
;
1438 /* set prep routines based on capability */
1439 if (dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
))
1440 atdma
->dma_common
.device_prep_dma_memcpy
= atc_prep_dma_memcpy
;
1442 if (dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
)) {
1443 atdma
->dma_common
.device_prep_slave_sg
= atc_prep_slave_sg
;
1444 /* controller can do slave DMA: can trigger cyclic transfers */
1445 dma_cap_set(DMA_CYCLIC
, atdma
->dma_common
.cap_mask
);
1446 atdma
->dma_common
.device_prep_dma_cyclic
= atc_prep_dma_cyclic
;
1447 atdma
->dma_common
.device_control
= atc_control
;
1450 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1452 dev_info(&pdev
->dev
, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1453 dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
) ? "cpy " : "",
1454 dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
) ? "slave " : "",
1455 plat_dat
->nr_channels
);
1457 dma_async_device_register(&atdma
->dma_common
);
1460 * Do not return an error if the dmac node is not present in order to
1461 * not break the existing way of requesting channel with
1462 * dma_request_channel().
1464 if (pdev
->dev
.of_node
) {
1465 err
= of_dma_controller_register(pdev
->dev
.of_node
,
1466 at_dma_xlate
, atdma
);
1468 dev_err(&pdev
->dev
, "could not register of_dma_controller\n");
1469 goto err_of_dma_controller_register
;
1475 err_of_dma_controller_register
:
1476 dma_async_device_unregister(&atdma
->dma_common
);
1477 dma_pool_destroy(atdma
->dma_desc_pool
);
1479 platform_set_drvdata(pdev
, NULL
);
1480 free_irq(platform_get_irq(pdev
, 0), atdma
);
1482 clk_disable(atdma
->clk
);
1483 clk_put(atdma
->clk
);
1485 iounmap(atdma
->regs
);
1488 release_mem_region(io
->start
, size
);
1494 static int at_dma_remove(struct platform_device
*pdev
)
1496 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1497 struct dma_chan
*chan
, *_chan
;
1498 struct resource
*io
;
1501 dma_async_device_unregister(&atdma
->dma_common
);
1503 dma_pool_destroy(atdma
->dma_desc_pool
);
1504 platform_set_drvdata(pdev
, NULL
);
1505 free_irq(platform_get_irq(pdev
, 0), atdma
);
1507 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1509 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1511 /* Disable interrupts */
1512 atc_disable_chan_irq(atdma
, chan
->chan_id
);
1513 tasklet_disable(&atchan
->tasklet
);
1515 tasklet_kill(&atchan
->tasklet
);
1516 list_del(&chan
->device_node
);
1519 clk_disable(atdma
->clk
);
1520 clk_put(atdma
->clk
);
1522 iounmap(atdma
->regs
);
1525 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1526 release_mem_region(io
->start
, resource_size(io
));
1533 static void at_dma_shutdown(struct platform_device
*pdev
)
1535 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1537 at_dma_off(platform_get_drvdata(pdev
));
1538 clk_disable(atdma
->clk
);
1541 static int at_dma_prepare(struct device
*dev
)
1543 struct platform_device
*pdev
= to_platform_device(dev
);
1544 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1545 struct dma_chan
*chan
, *_chan
;
1547 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1549 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1550 /* wait for transaction completion (except in cyclic case) */
1551 if (atc_chan_is_enabled(atchan
) && !atc_chan_is_cyclic(atchan
))
1557 static void atc_suspend_cyclic(struct at_dma_chan
*atchan
)
1559 struct dma_chan
*chan
= &atchan
->chan_common
;
1561 /* Channel should be paused by user
1562 * do it anyway even if it is not done already */
1563 if (!atc_chan_is_paused(atchan
)) {
1564 dev_warn(chan2dev(chan
),
1565 "cyclic channel not paused, should be done by channel user\n");
1566 atc_control(chan
, DMA_PAUSE
, 0);
1569 /* now preserve additional data for cyclic operations */
1570 /* next descriptor address in the cyclic list */
1571 atchan
->save_dscr
= channel_readl(atchan
, DSCR
);
1573 vdbg_dump_regs(atchan
);
1576 static int at_dma_suspend_noirq(struct device
*dev
)
1578 struct platform_device
*pdev
= to_platform_device(dev
);
1579 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1580 struct dma_chan
*chan
, *_chan
;
1583 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1585 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1587 if (atc_chan_is_cyclic(atchan
))
1588 atc_suspend_cyclic(atchan
);
1589 atchan
->save_cfg
= channel_readl(atchan
, CFG
);
1591 atdma
->save_imr
= dma_readl(atdma
, EBCIMR
);
1593 /* disable DMA controller */
1595 clk_disable(atdma
->clk
);
1599 static void atc_resume_cyclic(struct at_dma_chan
*atchan
)
1601 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
1603 /* restore channel status for cyclic descriptors list:
1604 * next descriptor in the cyclic list at the time of suspend */
1605 channel_writel(atchan
, SADDR
, 0);
1606 channel_writel(atchan
, DADDR
, 0);
1607 channel_writel(atchan
, CTRLA
, 0);
1608 channel_writel(atchan
, CTRLB
, 0);
1609 channel_writel(atchan
, DSCR
, atchan
->save_dscr
);
1610 dma_writel(atdma
, CHER
, atchan
->mask
);
1612 /* channel pause status should be removed by channel user
1613 * We cannot take the initiative to do it here */
1615 vdbg_dump_regs(atchan
);
1618 static int at_dma_resume_noirq(struct device
*dev
)
1620 struct platform_device
*pdev
= to_platform_device(dev
);
1621 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1622 struct dma_chan
*chan
, *_chan
;
1624 /* bring back DMA controller */
1625 clk_enable(atdma
->clk
);
1626 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1628 /* clear any pending interrupt */
1629 while (dma_readl(atdma
, EBCISR
))
1632 /* restore saved data */
1633 dma_writel(atdma
, EBCIER
, atdma
->save_imr
);
1634 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1636 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1638 channel_writel(atchan
, CFG
, atchan
->save_cfg
);
1639 if (atc_chan_is_cyclic(atchan
))
1640 atc_resume_cyclic(atchan
);
1645 static const struct dev_pm_ops at_dma_dev_pm_ops
= {
1646 .prepare
= at_dma_prepare
,
1647 .suspend_noirq
= at_dma_suspend_noirq
,
1648 .resume_noirq
= at_dma_resume_noirq
,
1651 static struct platform_driver at_dma_driver
= {
1652 .remove
= at_dma_remove
,
1653 .shutdown
= at_dma_shutdown
,
1654 .id_table
= atdma_devtypes
,
1657 .pm
= &at_dma_dev_pm_ops
,
1658 .of_match_table
= of_match_ptr(atmel_dma_dt_ids
),
1662 static int __init
at_dma_init(void)
1664 return platform_driver_probe(&at_dma_driver
, at_dma_probe
);
1666 subsys_initcall(at_dma_init
);
1668 static void __exit
at_dma_exit(void)
1670 platform_driver_unregister(&at_dma_driver
);
1672 module_exit(at_dma_exit
);
1674 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1675 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1676 MODULE_LICENSE("GPL");
1677 MODULE_ALIAS("platform:at_hdmac");