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dmaengine: xdmac: Handle descriptor's view 3 registers
[mirror_ubuntu-zesty-kernel.git] / drivers / dma / at_xdmac.c
1 /*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35
36 #include "dmaengine.h"
37
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176 #define AT_XDMAC_MAX_CHAN 0x20
177
178 #define AT_XDMAC_DMA_BUSWIDTHS\
179 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
180 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
181 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
182 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
183 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
184
185 enum atc_status {
186 AT_XDMAC_CHAN_IS_CYCLIC = 0,
187 AT_XDMAC_CHAN_IS_PAUSED,
188 };
189
190 /* ----- Channels ----- */
191 struct at_xdmac_chan {
192 struct dma_chan chan;
193 void __iomem *ch_regs;
194 u32 mask; /* Channel Mask */
195 u32 cfg[2]; /* Channel Configuration Register */
196 #define AT_XDMAC_DEV_TO_MEM_CFG 0 /* Predifined dev to mem channel conf */
197 #define AT_XDMAC_MEM_TO_DEV_CFG 1 /* Predifined mem to dev channel conf */
198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
201 u32 per_src_addr;
202 u32 per_dst_addr;
203 u32 save_cc;
204 u32 save_cim;
205 u32 save_cnda;
206 u32 save_cndc;
207 unsigned long status;
208 struct tasklet_struct tasklet;
209
210 spinlock_t lock;
211
212 struct list_head xfers_list;
213 struct list_head free_descs_list;
214 };
215
216
217 /* ----- Controller ----- */
218 struct at_xdmac {
219 struct dma_device dma;
220 void __iomem *regs;
221 int irq;
222 struct clk *clk;
223 u32 save_gim;
224 u32 save_gs;
225 struct dma_pool *at_xdmac_desc_pool;
226 struct at_xdmac_chan chan[0];
227 };
228
229
230 /* ----- Descriptors ----- */
231
232 /* Linked List Descriptor */
233 struct at_xdmac_lld {
234 dma_addr_t mbr_nda; /* Next Descriptor Member */
235 u32 mbr_ubc; /* Microblock Control Member */
236 dma_addr_t mbr_sa; /* Source Address Member */
237 dma_addr_t mbr_da; /* Destination Address Member */
238 u32 mbr_cfg; /* Configuration Register */
239 u32 mbr_bc; /* Block Control Register */
240 u32 mbr_ds; /* Data Stride Register */
241 u32 mbr_sus; /* Source Microblock Stride Register */
242 u32 mbr_dus; /* Destination Microblock Stride Register */
243 };
244
245
246 struct at_xdmac_desc {
247 struct at_xdmac_lld lld;
248 enum dma_transfer_direction direction;
249 struct dma_async_tx_descriptor tx_dma_desc;
250 struct list_head desc_node;
251 /* Following members are only used by the first descriptor */
252 bool active_xfer;
253 unsigned int xfer_size;
254 struct list_head descs_list;
255 struct list_head xfer_node;
256 };
257
258 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
259 {
260 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
261 }
262
263 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
264 #define at_xdmac_write(atxdmac, reg, value) \
265 writel_relaxed((value), (atxdmac)->regs + (reg))
266
267 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
268 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
269
270 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
271 {
272 return container_of(dchan, struct at_xdmac_chan, chan);
273 }
274
275 static struct device *chan2dev(struct dma_chan *chan)
276 {
277 return &chan->dev->device;
278 }
279
280 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
281 {
282 return container_of(ddev, struct at_xdmac, dma);
283 }
284
285 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
286 {
287 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
288 }
289
290 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
291 {
292 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
293 }
294
295 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
296 {
297 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
298 }
299
300 static inline int at_xdmac_csize(u32 maxburst)
301 {
302 int csize;
303
304 csize = ffs(maxburst) - 1;
305 if (csize > 4)
306 csize = -EINVAL;
307
308 return csize;
309 };
310
311 static inline u8 at_xdmac_get_dwidth(u32 cfg)
312 {
313 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
314 };
315
316 static unsigned int init_nr_desc_per_channel = 64;
317 module_param(init_nr_desc_per_channel, uint, 0644);
318 MODULE_PARM_DESC(init_nr_desc_per_channel,
319 "initial descriptors per channel (default: 64)");
320
321
322 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
323 {
324 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
325 }
326
327 static void at_xdmac_off(struct at_xdmac *atxdmac)
328 {
329 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
330
331 /* Wait that all chans are disabled. */
332 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
333 cpu_relax();
334
335 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
336 }
337
338 /* Call with lock hold. */
339 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
340 struct at_xdmac_desc *first)
341 {
342 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
343 u32 reg;
344
345 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
346
347 if (at_xdmac_chan_is_enabled(atchan))
348 return;
349
350 /* Set transfer as active to not try to start it again. */
351 first->active_xfer = true;
352
353 /* Tell xdmac where to get the first descriptor. */
354 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
355 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
356 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
357
358 /*
359 * When doing non cyclic transfer we need to use the next
360 * descriptor view 2 since some fields of the configuration register
361 * depend on transfer size and src/dest addresses.
362 */
363 if (at_xdmac_chan_is_cyclic(atchan)) {
364 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
365 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
366 } else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) {
367 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
368 } else {
369 /*
370 * No need to write AT_XDMAC_CC reg, it will be done when the
371 * descriptor is fecthed.
372 */
373 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
374 }
375
376 reg |= AT_XDMAC_CNDC_NDDUP
377 | AT_XDMAC_CNDC_NDSUP
378 | AT_XDMAC_CNDC_NDE;
379 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
380
381 dev_vdbg(chan2dev(&atchan->chan),
382 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
383 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
384 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
388 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
389
390 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
391 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
392 /*
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
395 */
396 if (at_xdmac_chan_is_cyclic(atchan))
397 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
398 reg | AT_XDMAC_CIE_BIE);
399 else
400 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
401 reg | AT_XDMAC_CIE_LIE);
402 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
403 dev_vdbg(chan2dev(&atchan->chan),
404 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
405 wmb();
406 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
407
408 dev_vdbg(chan2dev(&atchan->chan),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
416
417 }
418
419 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
420 {
421 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
422 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
423 dma_cookie_t cookie;
424
425 spin_lock_bh(&atchan->lock);
426 cookie = dma_cookie_assign(tx);
427
428 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
429 __func__, atchan, desc);
430 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
431 if (list_is_singular(&atchan->xfers_list))
432 at_xdmac_start_xfer(atchan, desc);
433
434 spin_unlock_bh(&atchan->lock);
435 return cookie;
436 }
437
438 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
439 gfp_t gfp_flags)
440 {
441 struct at_xdmac_desc *desc;
442 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
443 dma_addr_t phys;
444
445 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
446 if (desc) {
447 memset(desc, 0, sizeof(*desc));
448 INIT_LIST_HEAD(&desc->descs_list);
449 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
450 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
451 desc->tx_dma_desc.phys = phys;
452 }
453
454 return desc;
455 }
456
457 /* Call must be protected by lock. */
458 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
459 {
460 struct at_xdmac_desc *desc;
461
462 if (list_empty(&atchan->free_descs_list)) {
463 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
464 } else {
465 desc = list_first_entry(&atchan->free_descs_list,
466 struct at_xdmac_desc, desc_node);
467 list_del(&desc->desc_node);
468 desc->active_xfer = false;
469 }
470
471 return desc;
472 }
473
474 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
475 struct of_dma *of_dma)
476 {
477 struct at_xdmac *atxdmac = of_dma->of_dma_data;
478 struct at_xdmac_chan *atchan;
479 struct dma_chan *chan;
480 struct device *dev = atxdmac->dma.dev;
481
482 if (dma_spec->args_count != 1) {
483 dev_err(dev, "dma phandler args: bad number of args\n");
484 return NULL;
485 }
486
487 chan = dma_get_any_slave_channel(&atxdmac->dma);
488 if (!chan) {
489 dev_err(dev, "can't get a dma channel\n");
490 return NULL;
491 }
492
493 atchan = to_at_xdmac_chan(chan);
494 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
495 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
496 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
497 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
498 atchan->memif, atchan->perif, atchan->perid);
499
500 return chan;
501 }
502
503 static int at_xdmac_set_slave_config(struct dma_chan *chan,
504 struct dma_slave_config *sconfig)
505 {
506 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
507 u8 dwidth;
508 int csize;
509
510 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] =
511 AT91_XDMAC_DT_PERID(atchan->perid)
512 | AT_XDMAC_CC_DAM_INCREMENTED_AM
513 | AT_XDMAC_CC_SAM_FIXED_AM
514 | AT_XDMAC_CC_DIF(atchan->memif)
515 | AT_XDMAC_CC_SIF(atchan->perif)
516 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
517 | AT_XDMAC_CC_DSYNC_PER2MEM
518 | AT_XDMAC_CC_MBSIZE_SIXTEEN
519 | AT_XDMAC_CC_TYPE_PER_TRAN;
520 csize = at_xdmac_csize(sconfig->src_maxburst);
521 if (csize < 0) {
522 dev_err(chan2dev(chan), "invalid src maxburst value\n");
523 return -EINVAL;
524 }
525 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_CSIZE(csize);
526 dwidth = ffs(sconfig->src_addr_width) - 1;
527 atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
528
529
530 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] =
531 AT91_XDMAC_DT_PERID(atchan->perid)
532 | AT_XDMAC_CC_DAM_FIXED_AM
533 | AT_XDMAC_CC_SAM_INCREMENTED_AM
534 | AT_XDMAC_CC_DIF(atchan->perif)
535 | AT_XDMAC_CC_SIF(atchan->memif)
536 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
537 | AT_XDMAC_CC_DSYNC_MEM2PER
538 | AT_XDMAC_CC_MBSIZE_SIXTEEN
539 | AT_XDMAC_CC_TYPE_PER_TRAN;
540 csize = at_xdmac_csize(sconfig->dst_maxburst);
541 if (csize < 0) {
542 dev_err(chan2dev(chan), "invalid src maxburst value\n");
543 return -EINVAL;
544 }
545 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_CSIZE(csize);
546 dwidth = ffs(sconfig->dst_addr_width) - 1;
547 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth);
548
549 /* Src and dst addr are needed to configure the link list descriptor. */
550 atchan->per_src_addr = sconfig->src_addr;
551 atchan->per_dst_addr = sconfig->dst_addr;
552
553 dev_dbg(chan2dev(chan),
554 "%s: cfg[dev2mem]=0x%08x, cfg[mem2dev]=0x%08x, per_src_addr=0x%08x, per_dst_addr=0x%08x\n",
555 __func__, atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG],
556 atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG],
557 atchan->per_src_addr, atchan->per_dst_addr);
558
559 return 0;
560 }
561
562 static struct dma_async_tx_descriptor *
563 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
564 unsigned int sg_len, enum dma_transfer_direction direction,
565 unsigned long flags, void *context)
566 {
567 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
568 struct at_xdmac_desc *first = NULL, *prev = NULL;
569 struct scatterlist *sg;
570 int i;
571 unsigned int xfer_size = 0;
572
573 if (!sgl)
574 return NULL;
575
576 if (!is_slave_direction(direction)) {
577 dev_err(chan2dev(chan), "invalid DMA direction\n");
578 return NULL;
579 }
580
581 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
582 __func__, sg_len,
583 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
584 flags);
585
586 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
587 spin_lock_bh(&atchan->lock);
588
589 /* Prepare descriptors. */
590 for_each_sg(sgl, sg, sg_len, i) {
591 struct at_xdmac_desc *desc = NULL;
592 u32 len, mem, dwidth, fixed_dwidth;
593
594 len = sg_dma_len(sg);
595 mem = sg_dma_address(sg);
596 if (unlikely(!len)) {
597 dev_err(chan2dev(chan), "sg data length is zero\n");
598 spin_unlock_bh(&atchan->lock);
599 return NULL;
600 }
601 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
602 __func__, i, len, mem);
603
604 desc = at_xdmac_get_desc(atchan);
605 if (!desc) {
606 dev_err(chan2dev(chan), "can't get descriptor\n");
607 if (first)
608 list_splice_init(&first->descs_list, &atchan->free_descs_list);
609 spin_unlock_bh(&atchan->lock);
610 return NULL;
611 }
612
613 /* Linked list descriptor setup. */
614 if (direction == DMA_DEV_TO_MEM) {
615 desc->lld.mbr_sa = atchan->per_src_addr;
616 desc->lld.mbr_da = mem;
617 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
618 } else {
619 desc->lld.mbr_sa = mem;
620 desc->lld.mbr_da = atchan->per_dst_addr;
621 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
622 }
623 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
624 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
625 ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
626 : AT_XDMAC_CC_DWIDTH_BYTE;
627 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
628 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
629 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
630 | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
631 | (len >> fixed_dwidth); /* microblock length */
632 dev_dbg(chan2dev(chan),
633 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
634 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
635
636 /* Chain lld. */
637 if (prev) {
638 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
639 dev_dbg(chan2dev(chan),
640 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
641 __func__, prev, &prev->lld.mbr_nda);
642 }
643
644 prev = desc;
645 if (!first)
646 first = desc;
647
648 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
649 __func__, desc, first);
650 list_add_tail(&desc->desc_node, &first->descs_list);
651 xfer_size += len;
652 }
653
654 spin_unlock_bh(&atchan->lock);
655
656 first->tx_dma_desc.flags = flags;
657 first->xfer_size = xfer_size;
658 first->direction = direction;
659
660 return &first->tx_dma_desc;
661 }
662
663 static struct dma_async_tx_descriptor *
664 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
665 size_t buf_len, size_t period_len,
666 enum dma_transfer_direction direction,
667 unsigned long flags)
668 {
669 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
670 struct at_xdmac_desc *first = NULL, *prev = NULL;
671 unsigned int periods = buf_len / period_len;
672 int i;
673
674 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
675 __func__, &buf_addr, buf_len, period_len,
676 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
677
678 if (!is_slave_direction(direction)) {
679 dev_err(chan2dev(chan), "invalid DMA direction\n");
680 return NULL;
681 }
682
683 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
684 dev_err(chan2dev(chan), "channel currently used\n");
685 return NULL;
686 }
687
688 for (i = 0; i < periods; i++) {
689 struct at_xdmac_desc *desc = NULL;
690
691 spin_lock_bh(&atchan->lock);
692 desc = at_xdmac_get_desc(atchan);
693 if (!desc) {
694 dev_err(chan2dev(chan), "can't get descriptor\n");
695 if (first)
696 list_splice_init(&first->descs_list, &atchan->free_descs_list);
697 spin_unlock_bh(&atchan->lock);
698 return NULL;
699 }
700 spin_unlock_bh(&atchan->lock);
701 dev_dbg(chan2dev(chan),
702 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
703 __func__, desc, &desc->tx_dma_desc.phys);
704
705 if (direction == DMA_DEV_TO_MEM) {
706 desc->lld.mbr_sa = atchan->per_src_addr;
707 desc->lld.mbr_da = buf_addr + i * period_len;
708 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG];
709 } else {
710 desc->lld.mbr_sa = buf_addr + i * period_len;
711 desc->lld.mbr_da = atchan->per_dst_addr;
712 desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG];
713 }
714 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
715 | AT_XDMAC_MBR_UBC_NDEN
716 | AT_XDMAC_MBR_UBC_NSEN
717 | AT_XDMAC_MBR_UBC_NDE
718 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
719
720 dev_dbg(chan2dev(chan),
721 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
722 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
723
724 /* Chain lld. */
725 if (prev) {
726 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
727 dev_dbg(chan2dev(chan),
728 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
729 __func__, prev, &prev->lld.mbr_nda);
730 }
731
732 prev = desc;
733 if (!first)
734 first = desc;
735
736 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
737 __func__, desc, first);
738 list_add_tail(&desc->desc_node, &first->descs_list);
739 }
740
741 prev->lld.mbr_nda = first->tx_dma_desc.phys;
742 dev_dbg(chan2dev(chan),
743 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
744 __func__, prev, &prev->lld.mbr_nda);
745 first->tx_dma_desc.flags = flags;
746 first->xfer_size = buf_len;
747 first->direction = direction;
748
749 return &first->tx_dma_desc;
750 }
751
752 static struct dma_async_tx_descriptor *
753 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
754 size_t len, unsigned long flags)
755 {
756 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
757 struct at_xdmac_desc *first = NULL, *prev = NULL;
758 size_t remaining_size = len, xfer_size = 0, ublen;
759 dma_addr_t src_addr = src, dst_addr = dest;
760 u32 dwidth;
761 /*
762 * WARNING: We don't know the direction, it involves we can't
763 * dynamically set the source and dest interface so we have to use the
764 * same one. Only interface 0 allows EBI access. Hopefully we can
765 * access DDR through both ports (at least on SAMA5D4x), so we can use
766 * the same interface for source and dest, that solves the fact we
767 * don't know the direction.
768 */
769 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
770 | AT_XDMAC_CC_SAM_INCREMENTED_AM
771 | AT_XDMAC_CC_DIF(0)
772 | AT_XDMAC_CC_SIF(0)
773 | AT_XDMAC_CC_MBSIZE_SIXTEEN
774 | AT_XDMAC_CC_TYPE_MEM_TRAN;
775
776 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
777 __func__, &src, &dest, len, flags);
778
779 if (unlikely(!len))
780 return NULL;
781
782 /*
783 * Check address alignment to select the greater data width we can use.
784 * Some XDMAC implementations don't provide dword transfer, in this
785 * case selecting dword has the same behavior as selecting word transfers.
786 */
787 if (!((src_addr | dst_addr) & 7)) {
788 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
789 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
790 } else if (!((src_addr | dst_addr) & 3)) {
791 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
792 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
793 } else if (!((src_addr | dst_addr) & 1)) {
794 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
795 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
796 } else {
797 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
798 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
799 }
800
801 /* Prepare descriptors. */
802 while (remaining_size) {
803 struct at_xdmac_desc *desc = NULL;
804
805 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
806
807 spin_lock_bh(&atchan->lock);
808 desc = at_xdmac_get_desc(atchan);
809 spin_unlock_bh(&atchan->lock);
810 if (!desc) {
811 dev_err(chan2dev(chan), "can't get descriptor\n");
812 if (first)
813 list_splice_init(&first->descs_list, &atchan->free_descs_list);
814 return NULL;
815 }
816
817 /* Update src and dest addresses. */
818 src_addr += xfer_size;
819 dst_addr += xfer_size;
820
821 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
822 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
823 else
824 xfer_size = remaining_size;
825
826 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
827
828 /* Check remaining length and change data width if needed. */
829 if (!((src_addr | dst_addr | xfer_size) & 7)) {
830 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
831 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
832 } else if (!((src_addr | dst_addr | xfer_size) & 3)) {
833 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
834 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
835 } else if (!((src_addr | dst_addr | xfer_size) & 1)) {
836 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
837 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
838 } else if ((src_addr | dst_addr | xfer_size) & 1) {
839 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
840 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
841 }
842 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
843
844 ublen = xfer_size >> dwidth;
845 remaining_size -= xfer_size;
846
847 desc->lld.mbr_sa = src_addr;
848 desc->lld.mbr_da = dst_addr;
849 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
850 | AT_XDMAC_MBR_UBC_NDEN
851 | AT_XDMAC_MBR_UBC_NSEN
852 | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0)
853 | ublen;
854 desc->lld.mbr_cfg = chan_cc;
855
856 dev_dbg(chan2dev(chan),
857 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
858 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
859
860 /* Chain lld. */
861 if (prev) {
862 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
863 dev_dbg(chan2dev(chan),
864 "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
865 __func__, prev, prev->lld.mbr_nda);
866 }
867
868 prev = desc;
869 if (!first)
870 first = desc;
871
872 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
873 __func__, desc, first);
874 list_add_tail(&desc->desc_node, &first->descs_list);
875 }
876
877 first->tx_dma_desc.flags = flags;
878 first->xfer_size = len;
879
880 return &first->tx_dma_desc;
881 }
882
883 static enum dma_status
884 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
885 struct dma_tx_state *txstate)
886 {
887 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
888 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
889 struct at_xdmac_desc *desc, *_desc;
890 struct list_head *descs_list;
891 enum dma_status ret;
892 int residue;
893 u32 cur_nda, mask, value;
894 u8 dwidth = 0;
895
896 ret = dma_cookie_status(chan, cookie, txstate);
897 if (ret == DMA_COMPLETE)
898 return ret;
899
900 if (!txstate)
901 return ret;
902
903 spin_lock_bh(&atchan->lock);
904
905 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
906
907 /*
908 * If the transfer has not been started yet, don't need to compute the
909 * residue, it's the transfer length.
910 */
911 if (!desc->active_xfer) {
912 dma_set_residue(txstate, desc->xfer_size);
913 spin_unlock_bh(&atchan->lock);
914 return ret;
915 }
916
917 residue = desc->xfer_size;
918 /*
919 * Flush FIFO: only relevant when the transfer is source peripheral
920 * synchronized.
921 */
922 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
923 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
924 if ((desc->lld.mbr_cfg & mask) == value) {
925 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
926 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
927 cpu_relax();
928 }
929
930 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
931 /*
932 * Remove size of all microblocks already transferred and the current
933 * one. Then add the remaining size to transfer of the current
934 * microblock.
935 */
936 descs_list = &desc->descs_list;
937 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
938 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
939 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
940 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
941 break;
942 }
943 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
944
945 spin_unlock_bh(&atchan->lock);
946
947 dma_set_residue(txstate, residue);
948
949 dev_dbg(chan2dev(chan),
950 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
951 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
952
953 return ret;
954 }
955
956 /* Call must be protected by lock. */
957 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
958 struct at_xdmac_desc *desc)
959 {
960 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
961
962 /*
963 * Remove the transfer from the transfer list then move the transfer
964 * descriptors into the free descriptors list.
965 */
966 list_del(&desc->xfer_node);
967 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
968 }
969
970 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
971 {
972 struct at_xdmac_desc *desc;
973
974 spin_lock_bh(&atchan->lock);
975
976 /*
977 * If channel is enabled, do nothing, advance_work will be triggered
978 * after the interruption.
979 */
980 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
981 desc = list_first_entry(&atchan->xfers_list,
982 struct at_xdmac_desc,
983 xfer_node);
984 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
985 if (!desc->active_xfer)
986 at_xdmac_start_xfer(atchan, desc);
987 }
988
989 spin_unlock_bh(&atchan->lock);
990 }
991
992 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
993 {
994 struct at_xdmac_desc *desc;
995 struct dma_async_tx_descriptor *txd;
996
997 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
998 txd = &desc->tx_dma_desc;
999
1000 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1001 txd->callback(txd->callback_param);
1002 }
1003
1004 static void at_xdmac_tasklet(unsigned long data)
1005 {
1006 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1007 struct at_xdmac_desc *desc;
1008 u32 error_mask;
1009
1010 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1011 __func__, atchan->status);
1012
1013 error_mask = AT_XDMAC_CIS_RBEIS
1014 | AT_XDMAC_CIS_WBEIS
1015 | AT_XDMAC_CIS_ROIS;
1016
1017 if (at_xdmac_chan_is_cyclic(atchan)) {
1018 at_xdmac_handle_cyclic(atchan);
1019 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1020 || (atchan->status & error_mask)) {
1021 struct dma_async_tx_descriptor *txd;
1022
1023 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1024 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1025 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1026 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1027 if (atchan->status & AT_XDMAC_CIS_ROIS)
1028 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1029
1030 spin_lock_bh(&atchan->lock);
1031 desc = list_first_entry(&atchan->xfers_list,
1032 struct at_xdmac_desc,
1033 xfer_node);
1034 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1035 BUG_ON(!desc->active_xfer);
1036
1037 txd = &desc->tx_dma_desc;
1038
1039 at_xdmac_remove_xfer(atchan, desc);
1040 spin_unlock_bh(&atchan->lock);
1041
1042 if (!at_xdmac_chan_is_cyclic(atchan)) {
1043 dma_cookie_complete(txd);
1044 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1045 txd->callback(txd->callback_param);
1046 }
1047
1048 dma_run_dependencies(txd);
1049
1050 at_xdmac_advance_work(atchan);
1051 }
1052 }
1053
1054 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1055 {
1056 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1057 struct at_xdmac_chan *atchan;
1058 u32 imr, status, pending;
1059 u32 chan_imr, chan_status;
1060 int i, ret = IRQ_NONE;
1061
1062 do {
1063 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1064 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1065 pending = status & imr;
1066
1067 dev_vdbg(atxdmac->dma.dev,
1068 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1069 __func__, status, imr, pending);
1070
1071 if (!pending)
1072 break;
1073
1074 /* We have to find which channel has generated the interrupt. */
1075 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1076 if (!((1 << i) & pending))
1077 continue;
1078
1079 atchan = &atxdmac->chan[i];
1080 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1081 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1082 atchan->status = chan_status & chan_imr;
1083 dev_vdbg(atxdmac->dma.dev,
1084 "%s: chan%d: imr=0x%x, status=0x%x\n",
1085 __func__, i, chan_imr, chan_status);
1086 dev_vdbg(chan2dev(&atchan->chan),
1087 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1088 __func__,
1089 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1090 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1091 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1092 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1093 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1094 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1095
1096 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1097 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1098
1099 tasklet_schedule(&atchan->tasklet);
1100 ret = IRQ_HANDLED;
1101 }
1102
1103 } while (pending);
1104
1105 return ret;
1106 }
1107
1108 static void at_xdmac_issue_pending(struct dma_chan *chan)
1109 {
1110 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1111
1112 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1113
1114 if (!at_xdmac_chan_is_cyclic(atchan))
1115 at_xdmac_advance_work(atchan);
1116
1117 return;
1118 }
1119
1120 static int at_xdmac_device_config(struct dma_chan *chan,
1121 struct dma_slave_config *config)
1122 {
1123 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1124 int ret;
1125
1126 dev_dbg(chan2dev(chan), "%s\n", __func__);
1127
1128 spin_lock_bh(&atchan->lock);
1129 ret = at_xdmac_set_slave_config(chan, config);
1130 spin_unlock_bh(&atchan->lock);
1131
1132 return ret;
1133 }
1134
1135 static int at_xdmac_device_pause(struct dma_chan *chan)
1136 {
1137 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1138 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1139
1140 dev_dbg(chan2dev(chan), "%s\n", __func__);
1141
1142 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1143 return 0;
1144
1145 spin_lock_bh(&atchan->lock);
1146 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1147 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1148 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1149 cpu_relax();
1150 spin_unlock_bh(&atchan->lock);
1151
1152 return 0;
1153 }
1154
1155 static int at_xdmac_device_resume(struct dma_chan *chan)
1156 {
1157 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1158 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1159
1160 dev_dbg(chan2dev(chan), "%s\n", __func__);
1161
1162 spin_lock_bh(&atchan->lock);
1163 if (!at_xdmac_chan_is_paused(atchan)) {
1164 spin_unlock_bh(&atchan->lock);
1165 return 0;
1166 }
1167
1168 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1169 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1170 spin_unlock_bh(&atchan->lock);
1171
1172 return 0;
1173 }
1174
1175 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1176 {
1177 struct at_xdmac_desc *desc, *_desc;
1178 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1179 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1180
1181 dev_dbg(chan2dev(chan), "%s\n", __func__);
1182
1183 spin_lock_bh(&atchan->lock);
1184 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1185 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1186 cpu_relax();
1187
1188 /* Cancel all pending transfers. */
1189 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1190 at_xdmac_remove_xfer(atchan, desc);
1191
1192 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1193 spin_unlock_bh(&atchan->lock);
1194
1195 return 0;
1196 }
1197
1198 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1199 {
1200 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1201 struct at_xdmac_desc *desc;
1202 int i;
1203
1204 spin_lock_bh(&atchan->lock);
1205
1206 if (at_xdmac_chan_is_enabled(atchan)) {
1207 dev_err(chan2dev(chan),
1208 "can't allocate channel resources (channel enabled)\n");
1209 i = -EIO;
1210 goto spin_unlock;
1211 }
1212
1213 if (!list_empty(&atchan->free_descs_list)) {
1214 dev_err(chan2dev(chan),
1215 "can't allocate channel resources (channel not free from a previous use)\n");
1216 i = -EIO;
1217 goto spin_unlock;
1218 }
1219
1220 for (i = 0; i < init_nr_desc_per_channel; i++) {
1221 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1222 if (!desc) {
1223 dev_warn(chan2dev(chan),
1224 "only %d descriptors have been allocated\n", i);
1225 break;
1226 }
1227 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1228 }
1229
1230 dma_cookie_init(chan);
1231
1232 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1233
1234 spin_unlock:
1235 spin_unlock_bh(&atchan->lock);
1236 return i;
1237 }
1238
1239 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1240 {
1241 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1242 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1243 struct at_xdmac_desc *desc, *_desc;
1244
1245 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1246 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1247 list_del(&desc->desc_node);
1248 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1249 }
1250
1251 return;
1252 }
1253
1254 #ifdef CONFIG_PM
1255 static int atmel_xdmac_prepare(struct device *dev)
1256 {
1257 struct platform_device *pdev = to_platform_device(dev);
1258 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1259 struct dma_chan *chan, *_chan;
1260
1261 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1262 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1263
1264 /* Wait for transfer completion, except in cyclic case. */
1265 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1266 return -EAGAIN;
1267 }
1268 return 0;
1269 }
1270 #else
1271 # define atmel_xdmac_prepare NULL
1272 #endif
1273
1274 #ifdef CONFIG_PM_SLEEP
1275 static int atmel_xdmac_suspend(struct device *dev)
1276 {
1277 struct platform_device *pdev = to_platform_device(dev);
1278 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1279 struct dma_chan *chan, *_chan;
1280
1281 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1282 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1283
1284 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1285 if (at_xdmac_chan_is_cyclic(atchan)) {
1286 if (!at_xdmac_chan_is_paused(atchan))
1287 at_xdmac_device_pause(chan);
1288 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1289 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1290 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1291 }
1292 }
1293 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1294
1295 at_xdmac_off(atxdmac);
1296 clk_disable_unprepare(atxdmac->clk);
1297 return 0;
1298 }
1299
1300 static int atmel_xdmac_resume(struct device *dev)
1301 {
1302 struct platform_device *pdev = to_platform_device(dev);
1303 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1304 struct at_xdmac_chan *atchan;
1305 struct dma_chan *chan, *_chan;
1306 int i;
1307
1308 clk_prepare_enable(atxdmac->clk);
1309
1310 /* Clear pending interrupts. */
1311 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1312 atchan = &atxdmac->chan[i];
1313 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1314 cpu_relax();
1315 }
1316
1317 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1318 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1319 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1320 atchan = to_at_xdmac_chan(chan);
1321 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1322 if (at_xdmac_chan_is_cyclic(atchan)) {
1323 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1324 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1325 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1326 wmb();
1327 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1328 }
1329 }
1330 return 0;
1331 }
1332 #endif /* CONFIG_PM_SLEEP */
1333
1334 static int at_xdmac_probe(struct platform_device *pdev)
1335 {
1336 struct resource *res;
1337 struct at_xdmac *atxdmac;
1338 int irq, size, nr_channels, i, ret;
1339 void __iomem *base;
1340 u32 reg;
1341
1342 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343 if (!res)
1344 return -EINVAL;
1345
1346 irq = platform_get_irq(pdev, 0);
1347 if (irq < 0)
1348 return irq;
1349
1350 base = devm_ioremap_resource(&pdev->dev, res);
1351 if (IS_ERR(base))
1352 return PTR_ERR(base);
1353
1354 /*
1355 * Read number of xdmac channels, read helper function can't be used
1356 * since atxdmac is not yet allocated and we need to know the number
1357 * of channels to do the allocation.
1358 */
1359 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1360 nr_channels = AT_XDMAC_NB_CH(reg);
1361 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1362 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1363 nr_channels);
1364 return -EINVAL;
1365 }
1366
1367 size = sizeof(*atxdmac);
1368 size += nr_channels * sizeof(struct at_xdmac_chan);
1369 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1370 if (!atxdmac) {
1371 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1372 return -ENOMEM;
1373 }
1374
1375 atxdmac->regs = base;
1376 atxdmac->irq = irq;
1377
1378 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1379 if (IS_ERR(atxdmac->clk)) {
1380 dev_err(&pdev->dev, "can't get dma_clk\n");
1381 return PTR_ERR(atxdmac->clk);
1382 }
1383
1384 /* Do not use dev res to prevent races with tasklet */
1385 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1386 if (ret) {
1387 dev_err(&pdev->dev, "can't request irq\n");
1388 return ret;
1389 }
1390
1391 ret = clk_prepare_enable(atxdmac->clk);
1392 if (ret) {
1393 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1394 goto err_free_irq;
1395 }
1396
1397 atxdmac->at_xdmac_desc_pool =
1398 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1399 sizeof(struct at_xdmac_desc), 4, 0);
1400 if (!atxdmac->at_xdmac_desc_pool) {
1401 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1402 ret = -ENOMEM;
1403 goto err_clk_disable;
1404 }
1405
1406 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1407 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1408 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1409 /*
1410 * Without DMA_PRIVATE the driver is not able to allocate more than
1411 * one channel, second allocation fails in private_candidate.
1412 */
1413 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1414 atxdmac->dma.dev = &pdev->dev;
1415 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1416 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1417 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1418 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1419 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1420 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1421 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1422 atxdmac->dma.device_config = at_xdmac_device_config;
1423 atxdmac->dma.device_pause = at_xdmac_device_pause;
1424 atxdmac->dma.device_resume = at_xdmac_device_resume;
1425 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
1426 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1427 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1428 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1429 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1430
1431 /* Disable all chans and interrupts. */
1432 at_xdmac_off(atxdmac);
1433
1434 /* Init channels. */
1435 INIT_LIST_HEAD(&atxdmac->dma.channels);
1436 for (i = 0; i < nr_channels; i++) {
1437 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1438
1439 atchan->chan.device = &atxdmac->dma;
1440 list_add_tail(&atchan->chan.device_node,
1441 &atxdmac->dma.channels);
1442
1443 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1444 atchan->mask = 1 << i;
1445
1446 spin_lock_init(&atchan->lock);
1447 INIT_LIST_HEAD(&atchan->xfers_list);
1448 INIT_LIST_HEAD(&atchan->free_descs_list);
1449 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1450 (unsigned long)atchan);
1451
1452 /* Clear pending interrupts. */
1453 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1454 cpu_relax();
1455 }
1456 platform_set_drvdata(pdev, atxdmac);
1457
1458 ret = dma_async_device_register(&atxdmac->dma);
1459 if (ret) {
1460 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1461 goto err_clk_disable;
1462 }
1463
1464 ret = of_dma_controller_register(pdev->dev.of_node,
1465 at_xdmac_xlate, atxdmac);
1466 if (ret) {
1467 dev_err(&pdev->dev, "could not register of dma controller\n");
1468 goto err_dma_unregister;
1469 }
1470
1471 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1472 nr_channels, atxdmac->regs);
1473
1474 return 0;
1475
1476 err_dma_unregister:
1477 dma_async_device_unregister(&atxdmac->dma);
1478 err_clk_disable:
1479 clk_disable_unprepare(atxdmac->clk);
1480 err_free_irq:
1481 free_irq(atxdmac->irq, atxdmac->dma.dev);
1482 return ret;
1483 }
1484
1485 static int at_xdmac_remove(struct platform_device *pdev)
1486 {
1487 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1488 int i;
1489
1490 at_xdmac_off(atxdmac);
1491 of_dma_controller_free(pdev->dev.of_node);
1492 dma_async_device_unregister(&atxdmac->dma);
1493 clk_disable_unprepare(atxdmac->clk);
1494
1495 synchronize_irq(atxdmac->irq);
1496
1497 free_irq(atxdmac->irq, atxdmac->dma.dev);
1498
1499 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1500 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1501
1502 tasklet_kill(&atchan->tasklet);
1503 at_xdmac_free_chan_resources(&atchan->chan);
1504 }
1505
1506 return 0;
1507 }
1508
1509 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1510 .prepare = atmel_xdmac_prepare,
1511 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1512 };
1513
1514 static const struct of_device_id atmel_xdmac_dt_ids[] = {
1515 {
1516 .compatible = "atmel,sama5d4-dma",
1517 }, {
1518 /* sentinel */
1519 }
1520 };
1521 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1522
1523 static struct platform_driver at_xdmac_driver = {
1524 .probe = at_xdmac_probe,
1525 .remove = at_xdmac_remove,
1526 .driver = {
1527 .name = "at_xdmac",
1528 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1529 .pm = &atmel_xdmac_dev_pm_ops,
1530 }
1531 };
1532
1533 static int __init at_xdmac_init(void)
1534 {
1535 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1536 }
1537 subsys_initcall(at_xdmac_init);
1538
1539 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1540 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1541 MODULE_LICENSE("GPL");
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