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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / at_xdmac.c
1 /*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35
36 #include "dmaengine.h"
37
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176 #define AT_XDMAC_MAX_CHAN 0x20
177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
179
180 #define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
186
187 enum atc_status {
188 AT_XDMAC_CHAN_IS_CYCLIC = 0,
189 AT_XDMAC_CHAN_IS_PAUSED,
190 };
191
192 /* ----- Channels ----- */
193 struct at_xdmac_chan {
194 struct dma_chan chan;
195 void __iomem *ch_regs;
196 u32 mask; /* Channel Mask */
197 u32 cfg; /* Channel Configuration Register */
198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
201 u32 save_cc;
202 u32 save_cim;
203 u32 save_cnda;
204 u32 save_cndc;
205 unsigned long status;
206 struct tasklet_struct tasklet;
207 struct dma_slave_config sconfig;
208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213 };
214
215
216 /* ----- Controller ----- */
217 struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226 };
227
228
229 /* ----- Descriptors ----- */
230
231 /* Linked List Descriptor */
232 struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
238 };
239
240
241 struct at_xdmac_desc {
242 struct at_xdmac_lld lld;
243 enum dma_transfer_direction direction;
244 struct dma_async_tx_descriptor tx_dma_desc;
245 struct list_head desc_node;
246 /* Following members are only used by the first descriptor */
247 bool active_xfer;
248 unsigned int xfer_size;
249 struct list_head descs_list;
250 struct list_head xfer_node;
251 };
252
253 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
254 {
255 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
256 }
257
258 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
259 #define at_xdmac_write(atxdmac, reg, value) \
260 writel_relaxed((value), (atxdmac)->regs + (reg))
261
262 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
263 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
264
265 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
266 {
267 return container_of(dchan, struct at_xdmac_chan, chan);
268 }
269
270 static struct device *chan2dev(struct dma_chan *chan)
271 {
272 return &chan->dev->device;
273 }
274
275 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
276 {
277 return container_of(ddev, struct at_xdmac, dma);
278 }
279
280 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
281 {
282 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
283 }
284
285 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
286 {
287 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
288 }
289
290 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
291 {
292 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
293 }
294
295 static inline int at_xdmac_csize(u32 maxburst)
296 {
297 int csize;
298
299 csize = ffs(maxburst) - 1;
300 if (csize > 4)
301 csize = -EINVAL;
302
303 return csize;
304 };
305
306 static inline u8 at_xdmac_get_dwidth(u32 cfg)
307 {
308 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
309 };
310
311 static unsigned int init_nr_desc_per_channel = 64;
312 module_param(init_nr_desc_per_channel, uint, 0644);
313 MODULE_PARM_DESC(init_nr_desc_per_channel,
314 "initial descriptors per channel (default: 64)");
315
316
317 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
318 {
319 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
320 }
321
322 static void at_xdmac_off(struct at_xdmac *atxdmac)
323 {
324 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
325
326 /* Wait that all chans are disabled. */
327 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
328 cpu_relax();
329
330 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
331 }
332
333 /* Call with lock hold. */
334 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
335 struct at_xdmac_desc *first)
336 {
337 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
338 u32 reg;
339
340 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
341
342 if (at_xdmac_chan_is_enabled(atchan))
343 return;
344
345 /* Set transfer as active to not try to start it again. */
346 first->active_xfer = true;
347
348 /* Tell xdmac where to get the first descriptor. */
349 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
350 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
351 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
352
353 /*
354 * When doing non cyclic transfer we need to use the next
355 * descriptor view 2 since some fields of the configuration register
356 * depend on transfer size and src/dest addresses.
357 */
358 if (at_xdmac_chan_is_cyclic(atchan)) {
359 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
360 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
361 } else {
362 /*
363 * No need to write AT_XDMAC_CC reg, it will be done when the
364 * descriptor is fecthed.
365 */
366 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
367 }
368
369 reg |= AT_XDMAC_CNDC_NDDUP
370 | AT_XDMAC_CNDC_NDSUP
371 | AT_XDMAC_CNDC_NDE;
372 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
373
374 dev_vdbg(chan2dev(&atchan->chan),
375 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
376 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
377 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
378 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
379 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
380 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
381 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
382
383 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
384 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
385 /*
386 * There is no end of list when doing cyclic dma, we need to get
387 * an interrupt after each periods.
388 */
389 if (at_xdmac_chan_is_cyclic(atchan))
390 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
391 reg | AT_XDMAC_CIE_BIE);
392 else
393 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
394 reg | AT_XDMAC_CIE_LIE);
395 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
396 dev_vdbg(chan2dev(&atchan->chan),
397 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
398 wmb();
399 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
400
401 dev_vdbg(chan2dev(&atchan->chan),
402 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
403 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
404 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
405 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
406 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
407 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
408 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
409
410 }
411
412 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
413 {
414 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
415 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
416 dma_cookie_t cookie;
417 unsigned long irqflags;
418
419 spin_lock_irqsave(&atchan->lock, irqflags);
420 cookie = dma_cookie_assign(tx);
421
422 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
423 __func__, atchan, desc);
424 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
425 if (list_is_singular(&atchan->xfers_list))
426 at_xdmac_start_xfer(atchan, desc);
427
428 spin_unlock_irqrestore(&atchan->lock, irqflags);
429 return cookie;
430 }
431
432 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
433 gfp_t gfp_flags)
434 {
435 struct at_xdmac_desc *desc;
436 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
437 dma_addr_t phys;
438
439 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
440 if (desc) {
441 memset(desc, 0, sizeof(*desc));
442 INIT_LIST_HEAD(&desc->descs_list);
443 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
444 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
445 desc->tx_dma_desc.phys = phys;
446 }
447
448 return desc;
449 }
450
451 /* Call must be protected by lock. */
452 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
453 {
454 struct at_xdmac_desc *desc;
455
456 if (list_empty(&atchan->free_descs_list)) {
457 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
458 } else {
459 desc = list_first_entry(&atchan->free_descs_list,
460 struct at_xdmac_desc, desc_node);
461 list_del(&desc->desc_node);
462 desc->active_xfer = false;
463 }
464
465 return desc;
466 }
467
468 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
469 struct of_dma *of_dma)
470 {
471 struct at_xdmac *atxdmac = of_dma->of_dma_data;
472 struct at_xdmac_chan *atchan;
473 struct dma_chan *chan;
474 struct device *dev = atxdmac->dma.dev;
475
476 if (dma_spec->args_count != 1) {
477 dev_err(dev, "dma phandler args: bad number of args\n");
478 return NULL;
479 }
480
481 chan = dma_get_any_slave_channel(&atxdmac->dma);
482 if (!chan) {
483 dev_err(dev, "can't get a dma channel\n");
484 return NULL;
485 }
486
487 atchan = to_at_xdmac_chan(chan);
488 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
489 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
490 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
491 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
492 atchan->memif, atchan->perif, atchan->perid);
493
494 return chan;
495 }
496
497 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
498 enum dma_transfer_direction direction)
499 {
500 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
501 int csize, dwidth;
502
503 if (direction == DMA_DEV_TO_MEM) {
504 atchan->cfg =
505 AT91_XDMAC_DT_PERID(atchan->perid)
506 | AT_XDMAC_CC_DAM_INCREMENTED_AM
507 | AT_XDMAC_CC_SAM_FIXED_AM
508 | AT_XDMAC_CC_DIF(atchan->memif)
509 | AT_XDMAC_CC_SIF(atchan->perif)
510 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
511 | AT_XDMAC_CC_DSYNC_PER2MEM
512 | AT_XDMAC_CC_MBSIZE_SIXTEEN
513 | AT_XDMAC_CC_TYPE_PER_TRAN;
514 csize = ffs(atchan->sconfig.src_maxburst) - 1;
515 if (csize < 0) {
516 dev_err(chan2dev(chan), "invalid src maxburst value\n");
517 return -EINVAL;
518 }
519 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
520 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
521 if (dwidth < 0) {
522 dev_err(chan2dev(chan), "invalid src addr width value\n");
523 return -EINVAL;
524 }
525 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
526 } else if (direction == DMA_MEM_TO_DEV) {
527 atchan->cfg =
528 AT91_XDMAC_DT_PERID(atchan->perid)
529 | AT_XDMAC_CC_DAM_FIXED_AM
530 | AT_XDMAC_CC_SAM_INCREMENTED_AM
531 | AT_XDMAC_CC_DIF(atchan->perif)
532 | AT_XDMAC_CC_SIF(atchan->memif)
533 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
534 | AT_XDMAC_CC_DSYNC_MEM2PER
535 | AT_XDMAC_CC_MBSIZE_SIXTEEN
536 | AT_XDMAC_CC_TYPE_PER_TRAN;
537 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
538 if (csize < 0) {
539 dev_err(chan2dev(chan), "invalid src maxburst value\n");
540 return -EINVAL;
541 }
542 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
543 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
544 if (dwidth < 0) {
545 dev_err(chan2dev(chan), "invalid dst addr width value\n");
546 return -EINVAL;
547 }
548 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
549 }
550
551 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
552
553 return 0;
554 }
555
556 /*
557 * Only check that maxburst and addr width values are supported by the
558 * the controller but not that the configuration is good to perform the
559 * transfer since we don't know the direction at this stage.
560 */
561 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
562 {
563 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
564 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
565 return -EINVAL;
566
567 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
568 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
569 return -EINVAL;
570
571 return 0;
572 }
573
574 static int at_xdmac_set_slave_config(struct dma_chan *chan,
575 struct dma_slave_config *sconfig)
576 {
577 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
578
579 if (at_xdmac_check_slave_config(sconfig)) {
580 dev_err(chan2dev(chan), "invalid slave configuration\n");
581 return -EINVAL;
582 }
583
584 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
585
586 return 0;
587 }
588
589 static struct dma_async_tx_descriptor *
590 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
591 unsigned int sg_len, enum dma_transfer_direction direction,
592 unsigned long flags, void *context)
593 {
594 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
595 struct at_xdmac_desc *first = NULL, *prev = NULL;
596 struct scatterlist *sg;
597 int i;
598 unsigned int xfer_size = 0;
599 unsigned long irqflags;
600 struct dma_async_tx_descriptor *ret = NULL;
601
602 if (!sgl)
603 return NULL;
604
605 if (!is_slave_direction(direction)) {
606 dev_err(chan2dev(chan), "invalid DMA direction\n");
607 return NULL;
608 }
609
610 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
611 __func__, sg_len,
612 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
613 flags);
614
615 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
616 spin_lock_irqsave(&atchan->lock, irqflags);
617
618 if (at_xdmac_compute_chan_conf(chan, direction))
619 goto spin_unlock;
620
621 /* Prepare descriptors. */
622 for_each_sg(sgl, sg, sg_len, i) {
623 struct at_xdmac_desc *desc = NULL;
624 u32 len, mem, dwidth, fixed_dwidth;
625
626 len = sg_dma_len(sg);
627 mem = sg_dma_address(sg);
628 if (unlikely(!len)) {
629 dev_err(chan2dev(chan), "sg data length is zero\n");
630 goto spin_unlock;
631 }
632 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
633 __func__, i, len, mem);
634
635 desc = at_xdmac_get_desc(atchan);
636 if (!desc) {
637 dev_err(chan2dev(chan), "can't get descriptor\n");
638 if (first)
639 list_splice_init(&first->descs_list, &atchan->free_descs_list);
640 goto spin_unlock;
641 }
642
643 /* Linked list descriptor setup. */
644 if (direction == DMA_DEV_TO_MEM) {
645 desc->lld.mbr_sa = atchan->sconfig.src_addr;
646 desc->lld.mbr_da = mem;
647 } else {
648 desc->lld.mbr_sa = mem;
649 desc->lld.mbr_da = atchan->sconfig.dst_addr;
650 }
651 desc->lld.mbr_cfg = atchan->cfg;
652 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
653 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
654 ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
655 : AT_XDMAC_CC_DWIDTH_BYTE;
656 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
657 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
658 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
659 | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */
660 | (len >> fixed_dwidth); /* microblock length */
661 dev_dbg(chan2dev(chan),
662 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
663 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
664
665 /* Chain lld. */
666 if (prev) {
667 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
668 dev_dbg(chan2dev(chan),
669 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
670 __func__, prev, &prev->lld.mbr_nda);
671 }
672
673 prev = desc;
674 if (!first)
675 first = desc;
676
677 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
678 __func__, desc, first);
679 list_add_tail(&desc->desc_node, &first->descs_list);
680 xfer_size += len;
681 }
682
683
684 first->tx_dma_desc.flags = flags;
685 first->xfer_size = xfer_size;
686 first->direction = direction;
687 ret = &first->tx_dma_desc;
688
689 spin_unlock:
690 spin_unlock_irqrestore(&atchan->lock, irqflags);
691 return ret;
692 }
693
694 static struct dma_async_tx_descriptor *
695 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
696 size_t buf_len, size_t period_len,
697 enum dma_transfer_direction direction,
698 unsigned long flags)
699 {
700 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
701 struct at_xdmac_desc *first = NULL, *prev = NULL;
702 unsigned int periods = buf_len / period_len;
703 int i;
704 unsigned long irqflags;
705
706 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
707 __func__, &buf_addr, buf_len, period_len,
708 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
709
710 if (!is_slave_direction(direction)) {
711 dev_err(chan2dev(chan), "invalid DMA direction\n");
712 return NULL;
713 }
714
715 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
716 dev_err(chan2dev(chan), "channel currently used\n");
717 return NULL;
718 }
719
720 if (at_xdmac_compute_chan_conf(chan, direction))
721 return NULL;
722
723 for (i = 0; i < periods; i++) {
724 struct at_xdmac_desc *desc = NULL;
725
726 spin_lock_irqsave(&atchan->lock, irqflags);
727 desc = at_xdmac_get_desc(atchan);
728 if (!desc) {
729 dev_err(chan2dev(chan), "can't get descriptor\n");
730 if (first)
731 list_splice_init(&first->descs_list, &atchan->free_descs_list);
732 spin_unlock_irqrestore(&atchan->lock, irqflags);
733 return NULL;
734 }
735 spin_unlock_irqrestore(&atchan->lock, irqflags);
736 dev_dbg(chan2dev(chan),
737 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
738 __func__, desc, &desc->tx_dma_desc.phys);
739
740 if (direction == DMA_DEV_TO_MEM) {
741 desc->lld.mbr_sa = atchan->sconfig.src_addr;
742 desc->lld.mbr_da = buf_addr + i * period_len;
743 } else {
744 desc->lld.mbr_sa = buf_addr + i * period_len;
745 desc->lld.mbr_da = atchan->sconfig.dst_addr;
746 }
747 desc->lld.mbr_cfg = atchan->cfg;
748 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
749 | AT_XDMAC_MBR_UBC_NDEN
750 | AT_XDMAC_MBR_UBC_NSEN
751 | AT_XDMAC_MBR_UBC_NDE
752 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
753
754 dev_dbg(chan2dev(chan),
755 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
756 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
757
758 /* Chain lld. */
759 if (prev) {
760 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
761 dev_dbg(chan2dev(chan),
762 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
763 __func__, prev, &prev->lld.mbr_nda);
764 }
765
766 prev = desc;
767 if (!first)
768 first = desc;
769
770 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
771 __func__, desc, first);
772 list_add_tail(&desc->desc_node, &first->descs_list);
773 }
774
775 prev->lld.mbr_nda = first->tx_dma_desc.phys;
776 dev_dbg(chan2dev(chan),
777 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
778 __func__, prev, &prev->lld.mbr_nda);
779 first->tx_dma_desc.flags = flags;
780 first->xfer_size = buf_len;
781 first->direction = direction;
782
783 return &first->tx_dma_desc;
784 }
785
786 static struct dma_async_tx_descriptor *
787 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
788 size_t len, unsigned long flags)
789 {
790 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
791 struct at_xdmac_desc *first = NULL, *prev = NULL;
792 size_t remaining_size = len, xfer_size = 0, ublen;
793 dma_addr_t src_addr = src, dst_addr = dest;
794 u32 dwidth;
795 /*
796 * WARNING: We don't know the direction, it involves we can't
797 * dynamically set the source and dest interface so we have to use the
798 * same one. Only interface 0 allows EBI access. Hopefully we can
799 * access DDR through both ports (at least on SAMA5D4x), so we can use
800 * the same interface for source and dest, that solves the fact we
801 * don't know the direction.
802 */
803 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
804 | AT_XDMAC_CC_SAM_INCREMENTED_AM
805 | AT_XDMAC_CC_DIF(0)
806 | AT_XDMAC_CC_SIF(0)
807 | AT_XDMAC_CC_MBSIZE_SIXTEEN
808 | AT_XDMAC_CC_TYPE_MEM_TRAN;
809 unsigned long irqflags;
810
811 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
812 __func__, &src, &dest, len, flags);
813
814 if (unlikely(!len))
815 return NULL;
816
817 /*
818 * Check address alignment to select the greater data width we can use.
819 * Some XDMAC implementations don't provide dword transfer, in this
820 * case selecting dword has the same behavior as selecting word transfers.
821 */
822 if (!((src_addr | dst_addr) & 7)) {
823 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
824 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
825 } else if (!((src_addr | dst_addr) & 3)) {
826 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
827 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
828 } else if (!((src_addr | dst_addr) & 1)) {
829 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
830 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
831 } else {
832 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
833 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
834 }
835
836 /* Prepare descriptors. */
837 while (remaining_size) {
838 struct at_xdmac_desc *desc = NULL;
839
840 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
841
842 spin_lock_irqsave(&atchan->lock, irqflags);
843 desc = at_xdmac_get_desc(atchan);
844 spin_unlock_irqrestore(&atchan->lock, irqflags);
845 if (!desc) {
846 dev_err(chan2dev(chan), "can't get descriptor\n");
847 if (first)
848 list_splice_init(&first->descs_list, &atchan->free_descs_list);
849 return NULL;
850 }
851
852 /* Update src and dest addresses. */
853 src_addr += xfer_size;
854 dst_addr += xfer_size;
855
856 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
857 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
858 else
859 xfer_size = remaining_size;
860
861 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
862
863 /* Check remaining length and change data width if needed. */
864 if (!((src_addr | dst_addr | xfer_size) & 7)) {
865 dwidth = AT_XDMAC_CC_DWIDTH_DWORD;
866 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
867 } else if (!((src_addr | dst_addr | xfer_size) & 3)) {
868 dwidth = AT_XDMAC_CC_DWIDTH_WORD;
869 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
870 } else if (!((src_addr | dst_addr | xfer_size) & 1)) {
871 dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD;
872 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
873 } else if ((src_addr | dst_addr | xfer_size) & 1) {
874 dwidth = AT_XDMAC_CC_DWIDTH_BYTE;
875 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
876 }
877 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
878
879 ublen = xfer_size >> dwidth;
880 remaining_size -= xfer_size;
881
882 desc->lld.mbr_sa = src_addr;
883 desc->lld.mbr_da = dst_addr;
884 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
885 | AT_XDMAC_MBR_UBC_NDEN
886 | AT_XDMAC_MBR_UBC_NSEN
887 | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0)
888 | ublen;
889 desc->lld.mbr_cfg = chan_cc;
890
891 dev_dbg(chan2dev(chan),
892 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
893 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
894
895 /* Chain lld. */
896 if (prev) {
897 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
898 dev_dbg(chan2dev(chan),
899 "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n",
900 __func__, prev, prev->lld.mbr_nda);
901 }
902
903 prev = desc;
904 if (!first)
905 first = desc;
906
907 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
908 __func__, desc, first);
909 list_add_tail(&desc->desc_node, &first->descs_list);
910 }
911
912 first->tx_dma_desc.flags = flags;
913 first->xfer_size = len;
914
915 return &first->tx_dma_desc;
916 }
917
918 static enum dma_status
919 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
920 struct dma_tx_state *txstate)
921 {
922 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
923 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
924 struct at_xdmac_desc *desc, *_desc;
925 struct list_head *descs_list;
926 enum dma_status ret;
927 int residue;
928 u32 cur_nda, mask, value;
929 u8 dwidth = 0;
930 unsigned long flags;
931
932 ret = dma_cookie_status(chan, cookie, txstate);
933 if (ret == DMA_COMPLETE)
934 return ret;
935
936 if (!txstate)
937 return ret;
938
939 spin_lock_irqsave(&atchan->lock, flags);
940
941 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
942
943 /*
944 * If the transfer has not been started yet, don't need to compute the
945 * residue, it's the transfer length.
946 */
947 if (!desc->active_xfer) {
948 dma_set_residue(txstate, desc->xfer_size);
949 goto spin_unlock;
950 }
951
952 residue = desc->xfer_size;
953 /*
954 * Flush FIFO: only relevant when the transfer is source peripheral
955 * synchronized.
956 */
957 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
958 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
959 if ((desc->lld.mbr_cfg & mask) == value) {
960 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
961 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
962 cpu_relax();
963 }
964
965 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
966 /*
967 * Remove size of all microblocks already transferred and the current
968 * one. Then add the remaining size to transfer of the current
969 * microblock.
970 */
971 descs_list = &desc->descs_list;
972 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
973 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
974 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
975 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
976 break;
977 }
978 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
979
980 dma_set_residue(txstate, residue);
981
982 dev_dbg(chan2dev(chan),
983 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
984 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
985
986 spin_unlock:
987 spin_unlock_irqrestore(&atchan->lock, flags);
988 return ret;
989 }
990
991 /* Call must be protected by lock. */
992 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
993 struct at_xdmac_desc *desc)
994 {
995 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
996
997 /*
998 * Remove the transfer from the transfer list then move the transfer
999 * descriptors into the free descriptors list.
1000 */
1001 list_del(&desc->xfer_node);
1002 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1003 }
1004
1005 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1006 {
1007 struct at_xdmac_desc *desc;
1008 unsigned long flags;
1009
1010 spin_lock_irqsave(&atchan->lock, flags);
1011
1012 /*
1013 * If channel is enabled, do nothing, advance_work will be triggered
1014 * after the interruption.
1015 */
1016 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1017 desc = list_first_entry(&atchan->xfers_list,
1018 struct at_xdmac_desc,
1019 xfer_node);
1020 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1021 if (!desc->active_xfer)
1022 at_xdmac_start_xfer(atchan, desc);
1023 }
1024
1025 spin_unlock_irqrestore(&atchan->lock, flags);
1026 }
1027
1028 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1029 {
1030 struct at_xdmac_desc *desc;
1031 struct dma_async_tx_descriptor *txd;
1032
1033 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1034 txd = &desc->tx_dma_desc;
1035
1036 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1037 txd->callback(txd->callback_param);
1038 }
1039
1040 static void at_xdmac_tasklet(unsigned long data)
1041 {
1042 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1043 struct at_xdmac_desc *desc;
1044 u32 error_mask;
1045
1046 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1047 __func__, atchan->status);
1048
1049 error_mask = AT_XDMAC_CIS_RBEIS
1050 | AT_XDMAC_CIS_WBEIS
1051 | AT_XDMAC_CIS_ROIS;
1052
1053 if (at_xdmac_chan_is_cyclic(atchan)) {
1054 at_xdmac_handle_cyclic(atchan);
1055 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1056 || (atchan->status & error_mask)) {
1057 struct dma_async_tx_descriptor *txd;
1058
1059 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1060 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1061 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1062 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1063 if (atchan->status & AT_XDMAC_CIS_ROIS)
1064 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1065
1066 spin_lock_bh(&atchan->lock);
1067 desc = list_first_entry(&atchan->xfers_list,
1068 struct at_xdmac_desc,
1069 xfer_node);
1070 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1071 BUG_ON(!desc->active_xfer);
1072
1073 txd = &desc->tx_dma_desc;
1074
1075 at_xdmac_remove_xfer(atchan, desc);
1076 spin_unlock_bh(&atchan->lock);
1077
1078 if (!at_xdmac_chan_is_cyclic(atchan)) {
1079 dma_cookie_complete(txd);
1080 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1081 txd->callback(txd->callback_param);
1082 }
1083
1084 dma_run_dependencies(txd);
1085
1086 at_xdmac_advance_work(atchan);
1087 }
1088 }
1089
1090 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1091 {
1092 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1093 struct at_xdmac_chan *atchan;
1094 u32 imr, status, pending;
1095 u32 chan_imr, chan_status;
1096 int i, ret = IRQ_NONE;
1097
1098 do {
1099 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1100 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1101 pending = status & imr;
1102
1103 dev_vdbg(atxdmac->dma.dev,
1104 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1105 __func__, status, imr, pending);
1106
1107 if (!pending)
1108 break;
1109
1110 /* We have to find which channel has generated the interrupt. */
1111 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1112 if (!((1 << i) & pending))
1113 continue;
1114
1115 atchan = &atxdmac->chan[i];
1116 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1117 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1118 atchan->status = chan_status & chan_imr;
1119 dev_vdbg(atxdmac->dma.dev,
1120 "%s: chan%d: imr=0x%x, status=0x%x\n",
1121 __func__, i, chan_imr, chan_status);
1122 dev_vdbg(chan2dev(&atchan->chan),
1123 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1124 __func__,
1125 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1126 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1127 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1128 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1129 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1130 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1131
1132 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1133 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1134
1135 tasklet_schedule(&atchan->tasklet);
1136 ret = IRQ_HANDLED;
1137 }
1138
1139 } while (pending);
1140
1141 return ret;
1142 }
1143
1144 static void at_xdmac_issue_pending(struct dma_chan *chan)
1145 {
1146 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1147
1148 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1149
1150 if (!at_xdmac_chan_is_cyclic(atchan))
1151 at_xdmac_advance_work(atchan);
1152
1153 return;
1154 }
1155
1156 static int at_xdmac_device_config(struct dma_chan *chan,
1157 struct dma_slave_config *config)
1158 {
1159 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1160 int ret;
1161 unsigned long flags;
1162
1163 dev_dbg(chan2dev(chan), "%s\n", __func__);
1164
1165 spin_lock_irqsave(&atchan->lock, flags);
1166 ret = at_xdmac_set_slave_config(chan, config);
1167 spin_unlock_irqrestore(&atchan->lock, flags);
1168
1169 return ret;
1170 }
1171
1172 static int at_xdmac_device_pause(struct dma_chan *chan)
1173 {
1174 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1175 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1176 unsigned long flags;
1177
1178 dev_dbg(chan2dev(chan), "%s\n", __func__);
1179
1180 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1181 return 0;
1182
1183 spin_lock_irqsave(&atchan->lock, flags);
1184 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1185 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1186 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1187 cpu_relax();
1188 spin_unlock_irqrestore(&atchan->lock, flags);
1189
1190 return 0;
1191 }
1192
1193 static int at_xdmac_device_resume(struct dma_chan *chan)
1194 {
1195 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1196 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1197 unsigned long flags;
1198
1199 dev_dbg(chan2dev(chan), "%s\n", __func__);
1200
1201 spin_lock_irqsave(&atchan->lock, flags);
1202 if (!at_xdmac_chan_is_paused(atchan)) {
1203 spin_unlock_irqrestore(&atchan->lock, flags);
1204 return 0;
1205 }
1206
1207 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1208 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1209 spin_unlock_irqrestore(&atchan->lock, flags);
1210
1211 return 0;
1212 }
1213
1214 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1215 {
1216 struct at_xdmac_desc *desc, *_desc;
1217 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1218 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1219 unsigned long flags;
1220
1221 dev_dbg(chan2dev(chan), "%s\n", __func__);
1222
1223 spin_lock_irqsave(&atchan->lock, flags);
1224 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1225 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1226 cpu_relax();
1227
1228 /* Cancel all pending transfers. */
1229 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1230 at_xdmac_remove_xfer(atchan, desc);
1231
1232 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1233 spin_unlock_irqrestore(&atchan->lock, flags);
1234
1235 return 0;
1236 }
1237
1238 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1239 {
1240 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1241 struct at_xdmac_desc *desc;
1242 int i;
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&atchan->lock, flags);
1246
1247 if (at_xdmac_chan_is_enabled(atchan)) {
1248 dev_err(chan2dev(chan),
1249 "can't allocate channel resources (channel enabled)\n");
1250 i = -EIO;
1251 goto spin_unlock;
1252 }
1253
1254 if (!list_empty(&atchan->free_descs_list)) {
1255 dev_err(chan2dev(chan),
1256 "can't allocate channel resources (channel not free from a previous use)\n");
1257 i = -EIO;
1258 goto spin_unlock;
1259 }
1260
1261 for (i = 0; i < init_nr_desc_per_channel; i++) {
1262 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1263 if (!desc) {
1264 dev_warn(chan2dev(chan),
1265 "only %d descriptors have been allocated\n", i);
1266 break;
1267 }
1268 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1269 }
1270
1271 dma_cookie_init(chan);
1272
1273 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1274
1275 spin_unlock:
1276 spin_unlock_irqrestore(&atchan->lock, flags);
1277 return i;
1278 }
1279
1280 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1281 {
1282 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1283 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1284 struct at_xdmac_desc *desc, *_desc;
1285
1286 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1287 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1288 list_del(&desc->desc_node);
1289 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1290 }
1291
1292 return;
1293 }
1294
1295 #ifdef CONFIG_PM
1296 static int atmel_xdmac_prepare(struct device *dev)
1297 {
1298 struct platform_device *pdev = to_platform_device(dev);
1299 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1300 struct dma_chan *chan, *_chan;
1301
1302 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1303 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1304
1305 /* Wait for transfer completion, except in cyclic case. */
1306 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1307 return -EAGAIN;
1308 }
1309 return 0;
1310 }
1311 #else
1312 # define atmel_xdmac_prepare NULL
1313 #endif
1314
1315 #ifdef CONFIG_PM_SLEEP
1316 static int atmel_xdmac_suspend(struct device *dev)
1317 {
1318 struct platform_device *pdev = to_platform_device(dev);
1319 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1320 struct dma_chan *chan, *_chan;
1321
1322 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1323 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1324
1325 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1326 if (at_xdmac_chan_is_cyclic(atchan)) {
1327 if (!at_xdmac_chan_is_paused(atchan))
1328 at_xdmac_device_pause(chan);
1329 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1330 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1331 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1332 }
1333 }
1334 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1335
1336 at_xdmac_off(atxdmac);
1337 clk_disable_unprepare(atxdmac->clk);
1338 return 0;
1339 }
1340
1341 static int atmel_xdmac_resume(struct device *dev)
1342 {
1343 struct platform_device *pdev = to_platform_device(dev);
1344 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1345 struct at_xdmac_chan *atchan;
1346 struct dma_chan *chan, *_chan;
1347 int i;
1348
1349 clk_prepare_enable(atxdmac->clk);
1350
1351 /* Clear pending interrupts. */
1352 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1353 atchan = &atxdmac->chan[i];
1354 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1355 cpu_relax();
1356 }
1357
1358 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1359 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1360 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1361 atchan = to_at_xdmac_chan(chan);
1362 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1363 if (at_xdmac_chan_is_cyclic(atchan)) {
1364 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1365 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1366 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1367 wmb();
1368 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1369 }
1370 }
1371 return 0;
1372 }
1373 #endif /* CONFIG_PM_SLEEP */
1374
1375 static int at_xdmac_probe(struct platform_device *pdev)
1376 {
1377 struct resource *res;
1378 struct at_xdmac *atxdmac;
1379 int irq, size, nr_channels, i, ret;
1380 void __iomem *base;
1381 u32 reg;
1382
1383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1384 if (!res)
1385 return -EINVAL;
1386
1387 irq = platform_get_irq(pdev, 0);
1388 if (irq < 0)
1389 return irq;
1390
1391 base = devm_ioremap_resource(&pdev->dev, res);
1392 if (IS_ERR(base))
1393 return PTR_ERR(base);
1394
1395 /*
1396 * Read number of xdmac channels, read helper function can't be used
1397 * since atxdmac is not yet allocated and we need to know the number
1398 * of channels to do the allocation.
1399 */
1400 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1401 nr_channels = AT_XDMAC_NB_CH(reg);
1402 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1403 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1404 nr_channels);
1405 return -EINVAL;
1406 }
1407
1408 size = sizeof(*atxdmac);
1409 size += nr_channels * sizeof(struct at_xdmac_chan);
1410 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1411 if (!atxdmac) {
1412 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1413 return -ENOMEM;
1414 }
1415
1416 atxdmac->regs = base;
1417 atxdmac->irq = irq;
1418
1419 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1420 if (IS_ERR(atxdmac->clk)) {
1421 dev_err(&pdev->dev, "can't get dma_clk\n");
1422 return PTR_ERR(atxdmac->clk);
1423 }
1424
1425 /* Do not use dev res to prevent races with tasklet */
1426 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1427 if (ret) {
1428 dev_err(&pdev->dev, "can't request irq\n");
1429 return ret;
1430 }
1431
1432 ret = clk_prepare_enable(atxdmac->clk);
1433 if (ret) {
1434 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1435 goto err_free_irq;
1436 }
1437
1438 atxdmac->at_xdmac_desc_pool =
1439 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1440 sizeof(struct at_xdmac_desc), 4, 0);
1441 if (!atxdmac->at_xdmac_desc_pool) {
1442 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1443 ret = -ENOMEM;
1444 goto err_clk_disable;
1445 }
1446
1447 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1448 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1449 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1450 /*
1451 * Without DMA_PRIVATE the driver is not able to allocate more than
1452 * one channel, second allocation fails in private_candidate.
1453 */
1454 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1455 atxdmac->dma.dev = &pdev->dev;
1456 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1457 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1458 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1459 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1460 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1461 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1462 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1463 atxdmac->dma.device_config = at_xdmac_device_config;
1464 atxdmac->dma.device_pause = at_xdmac_device_pause;
1465 atxdmac->dma.device_resume = at_xdmac_device_resume;
1466 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
1467 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1468 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1469 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1470 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1471
1472 /* Disable all chans and interrupts. */
1473 at_xdmac_off(atxdmac);
1474
1475 /* Init channels. */
1476 INIT_LIST_HEAD(&atxdmac->dma.channels);
1477 for (i = 0; i < nr_channels; i++) {
1478 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1479
1480 atchan->chan.device = &atxdmac->dma;
1481 list_add_tail(&atchan->chan.device_node,
1482 &atxdmac->dma.channels);
1483
1484 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1485 atchan->mask = 1 << i;
1486
1487 spin_lock_init(&atchan->lock);
1488 INIT_LIST_HEAD(&atchan->xfers_list);
1489 INIT_LIST_HEAD(&atchan->free_descs_list);
1490 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1491 (unsigned long)atchan);
1492
1493 /* Clear pending interrupts. */
1494 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1495 cpu_relax();
1496 }
1497 platform_set_drvdata(pdev, atxdmac);
1498
1499 ret = dma_async_device_register(&atxdmac->dma);
1500 if (ret) {
1501 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1502 goto err_clk_disable;
1503 }
1504
1505 ret = of_dma_controller_register(pdev->dev.of_node,
1506 at_xdmac_xlate, atxdmac);
1507 if (ret) {
1508 dev_err(&pdev->dev, "could not register of dma controller\n");
1509 goto err_dma_unregister;
1510 }
1511
1512 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1513 nr_channels, atxdmac->regs);
1514
1515 return 0;
1516
1517 err_dma_unregister:
1518 dma_async_device_unregister(&atxdmac->dma);
1519 err_clk_disable:
1520 clk_disable_unprepare(atxdmac->clk);
1521 err_free_irq:
1522 free_irq(atxdmac->irq, atxdmac->dma.dev);
1523 return ret;
1524 }
1525
1526 static int at_xdmac_remove(struct platform_device *pdev)
1527 {
1528 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1529 int i;
1530
1531 at_xdmac_off(atxdmac);
1532 of_dma_controller_free(pdev->dev.of_node);
1533 dma_async_device_unregister(&atxdmac->dma);
1534 clk_disable_unprepare(atxdmac->clk);
1535
1536 synchronize_irq(atxdmac->irq);
1537
1538 free_irq(atxdmac->irq, atxdmac->dma.dev);
1539
1540 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1541 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1542
1543 tasklet_kill(&atchan->tasklet);
1544 at_xdmac_free_chan_resources(&atchan->chan);
1545 }
1546
1547 return 0;
1548 }
1549
1550 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1551 .prepare = atmel_xdmac_prepare,
1552 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1553 };
1554
1555 static const struct of_device_id atmel_xdmac_dt_ids[] = {
1556 {
1557 .compatible = "atmel,sama5d4-dma",
1558 }, {
1559 /* sentinel */
1560 }
1561 };
1562 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1563
1564 static struct platform_driver at_xdmac_driver = {
1565 .probe = at_xdmac_probe,
1566 .remove = at_xdmac_remove,
1567 .driver = {
1568 .name = "at_xdmac",
1569 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1570 .pm = &atmel_xdmac_dev_pm_ops,
1571 }
1572 };
1573
1574 static int __init at_xdmac_init(void)
1575 {
1576 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1577 }
1578 subsys_initcall(at_xdmac_init);
1579
1580 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1581 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1582 MODULE_LICENSE("GPL");
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