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Merge tag 'oxnas-arm-soc-dt-fixes-for-5.6' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-jammy-kernel.git] / drivers / dma / coh901318.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * driver/dma/coh901318.c
4 *
5 * Copyright (C) 2007-2009 ST-Ericsson
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/scatterlist.h>
15 #include <linux/slab.h> /* kmalloc() */
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/irqreturn.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/uaccess.h>
23 #include <linux/debugfs.h>
24 #include <linux/platform_data/dma-coh901318.h>
25 #include <linux/of_dma.h>
26
27 #include "coh901318.h"
28 #include "dmaengine.h"
29
30 #define COH901318_MOD32_MASK (0x1F)
31 #define COH901318_WORD_MASK (0xFFFFFFFF)
32 /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
33 #define COH901318_INT_STATUS1 (0x0000)
34 #define COH901318_INT_STATUS2 (0x0004)
35 /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
36 #define COH901318_TC_INT_STATUS1 (0x0008)
37 #define COH901318_TC_INT_STATUS2 (0x000C)
38 /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
39 #define COH901318_TC_INT_CLEAR1 (0x0010)
40 #define COH901318_TC_INT_CLEAR2 (0x0014)
41 /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
42 #define COH901318_RAW_TC_INT_STATUS1 (0x0018)
43 #define COH901318_RAW_TC_INT_STATUS2 (0x001C)
44 /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
45 #define COH901318_BE_INT_STATUS1 (0x0020)
46 #define COH901318_BE_INT_STATUS2 (0x0024)
47 /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
48 #define COH901318_BE_INT_CLEAR1 (0x0028)
49 #define COH901318_BE_INT_CLEAR2 (0x002C)
50 /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
51 #define COH901318_RAW_BE_INT_STATUS1 (0x0030)
52 #define COH901318_RAW_BE_INT_STATUS2 (0x0034)
53
54 /*
55 * CX_CFG - Channel Configuration Registers 32bit (R/W)
56 */
57 #define COH901318_CX_CFG (0x0100)
58 #define COH901318_CX_CFG_SPACING (0x04)
59 /* Channel enable activates tha dma job */
60 #define COH901318_CX_CFG_CH_ENABLE (0x00000001)
61 #define COH901318_CX_CFG_CH_DISABLE (0x00000000)
62 /* Request Mode */
63 #define COH901318_CX_CFG_RM_MASK (0x00000006)
64 #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
65 #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
66 #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
67 #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
68 #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
69 /* Linked channel request field. RM must == 11 */
70 #define COH901318_CX_CFG_LCRF_SHIFT 3
71 #define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
72 #define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
73 /* Terminal Counter Interrupt Request Mask */
74 #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
75 #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
76 /* Bus Error interrupt Mask */
77 #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
78 #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
79
80 /*
81 * CX_STAT - Channel Status Registers 32bit (R/-)
82 */
83 #define COH901318_CX_STAT (0x0200)
84 #define COH901318_CX_STAT_SPACING (0x04)
85 #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
86 #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
87 #define COH901318_CX_STAT_ACTIVE (0x00000002)
88 #define COH901318_CX_STAT_ENABLED (0x00000001)
89
90 /*
91 * CX_CTRL - Channel Control Registers 32bit (R/W)
92 */
93 #define COH901318_CX_CTRL (0x0400)
94 #define COH901318_CX_CTRL_SPACING (0x10)
95 /* Transfer Count Enable */
96 #define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
97 #define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
98 /* Transfer Count Value 0 - 4095 */
99 #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
100 /* Burst count */
101 #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
102 #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
103 #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
104 #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
105 #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
106 #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
107 #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
108 #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
109 #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
110 /* Source bus size */
111 #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
112 #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
113 #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
114 #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
115 /* Source address increment */
116 #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
117 #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
118 /* Destination Bus Size */
119 #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
120 #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
121 #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
122 #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
123 /* Destination address increment */
124 #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
125 #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
126 /* Master Mode (Master2 is only connected to MSL) */
127 #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
128 #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
129 #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
130 #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
131 #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
132 /* Terminal Count flag to PER enable */
133 #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
134 #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
135 /* Terminal Count flags to CPU enable */
136 #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
137 #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
138 /* Hand shake to peripheral */
139 #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
140 #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
141 #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
142 #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
143 /* DMA mode */
144 #define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
145 #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
146 #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
147 #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
148 /* Primary Request Data Destination */
149 #define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
150 #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
151 #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
152
153 /*
154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
155 */
156 #define COH901318_CX_SRC_ADDR (0x0404)
157 #define COH901318_CX_SRC_ADDR_SPACING (0x10)
158
159 /*
160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
161 */
162 #define COH901318_CX_DST_ADDR (0x0408)
163 #define COH901318_CX_DST_ADDR_SPACING (0x10)
164
165 /*
166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
167 */
168 #define COH901318_CX_LNK_ADDR (0x040C)
169 #define COH901318_CX_LNK_ADDR_SPACING (0x10)
170 #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
171
172 /**
173 * struct coh901318_params - parameters for DMAC configuration
174 * @config: DMA config register
175 * @ctrl_lli_last: DMA control register for the last lli in the list
176 * @ctrl_lli: DMA control register for an lli
177 * @ctrl_lli_chained: DMA control register for a chained lli
178 */
179 struct coh901318_params {
180 u32 config;
181 u32 ctrl_lli_last;
182 u32 ctrl_lli;
183 u32 ctrl_lli_chained;
184 };
185
186 /**
187 * struct coh_dma_channel - dma channel base
188 * @name: ascii name of dma channel
189 * @number: channel id number
190 * @desc_nbr_max: number of preallocated descriptors
191 * @priority_high: prio of channel, 0 low otherwise high.
192 * @param: configuration parameters
193 */
194 struct coh_dma_channel {
195 const char name[32];
196 const int number;
197 const int desc_nbr_max;
198 const int priority_high;
199 const struct coh901318_params param;
200 };
201
202 /**
203 * struct powersave - DMA power save structure
204 * @lock: lock protecting data in this struct
205 * @started_channels: bit mask indicating active dma channels
206 */
207 struct powersave {
208 spinlock_t lock;
209 u64 started_channels;
210 };
211
212 /* points out all dma slave channels.
213 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
214 * Select all channels from A to B, end of list is marked with -1,-1
215 */
216 static int dma_slave_channels[] = {
217 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
218 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
219
220 /* points out all dma memcpy channels. */
221 static int dma_memcpy_channels[] = {
222 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
223
224 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
225 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
226 COH901318_CX_CFG_LCR_DISABLE | \
227 COH901318_CX_CFG_TC_IRQ_ENABLE | \
228 COH901318_CX_CFG_BE_IRQ_ENABLE)
229 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
230 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
231 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
232 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
233 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
234 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
235 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
236 COH901318_CX_CTRL_TCP_DISABLE | \
237 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
238 COH901318_CX_CTRL_HSP_DISABLE | \
239 COH901318_CX_CTRL_HSS_DISABLE | \
240 COH901318_CX_CTRL_DDMA_LEGACY | \
241 COH901318_CX_CTRL_PRDD_SOURCE)
242 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
243 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
244 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
245 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
246 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
247 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
248 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
249 COH901318_CX_CTRL_TCP_DISABLE | \
250 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
251 COH901318_CX_CTRL_HSP_DISABLE | \
252 COH901318_CX_CTRL_HSS_DISABLE | \
253 COH901318_CX_CTRL_DDMA_LEGACY | \
254 COH901318_CX_CTRL_PRDD_SOURCE)
255 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
256 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
257 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
258 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
259 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
260 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
261 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
262 COH901318_CX_CTRL_TCP_DISABLE | \
263 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
264 COH901318_CX_CTRL_HSP_DISABLE | \
265 COH901318_CX_CTRL_HSS_DISABLE | \
266 COH901318_CX_CTRL_DDMA_LEGACY | \
267 COH901318_CX_CTRL_PRDD_SOURCE)
268
269 static const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
270 {
271 .number = U300_DMA_MSL_TX_0,
272 .name = "MSL TX 0",
273 .priority_high = 0,
274 },
275 {
276 .number = U300_DMA_MSL_TX_1,
277 .name = "MSL TX 1",
278 .priority_high = 0,
279 .param.config = COH901318_CX_CFG_CH_DISABLE |
280 COH901318_CX_CFG_LCR_DISABLE |
281 COH901318_CX_CFG_TC_IRQ_ENABLE |
282 COH901318_CX_CFG_BE_IRQ_ENABLE,
283 .param.ctrl_lli_chained = 0 |
284 COH901318_CX_CTRL_TC_ENABLE |
285 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
286 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
287 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
288 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
289 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
290 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
291 COH901318_CX_CTRL_TCP_DISABLE |
292 COH901318_CX_CTRL_TC_IRQ_DISABLE |
293 COH901318_CX_CTRL_HSP_ENABLE |
294 COH901318_CX_CTRL_HSS_DISABLE |
295 COH901318_CX_CTRL_DDMA_LEGACY |
296 COH901318_CX_CTRL_PRDD_SOURCE,
297 .param.ctrl_lli = 0 |
298 COH901318_CX_CTRL_TC_ENABLE |
299 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
300 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
301 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
302 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
303 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
304 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
305 COH901318_CX_CTRL_TCP_ENABLE |
306 COH901318_CX_CTRL_TC_IRQ_DISABLE |
307 COH901318_CX_CTRL_HSP_ENABLE |
308 COH901318_CX_CTRL_HSS_DISABLE |
309 COH901318_CX_CTRL_DDMA_LEGACY |
310 COH901318_CX_CTRL_PRDD_SOURCE,
311 .param.ctrl_lli_last = 0 |
312 COH901318_CX_CTRL_TC_ENABLE |
313 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
314 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
315 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
316 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
317 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
318 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
319 COH901318_CX_CTRL_TCP_ENABLE |
320 COH901318_CX_CTRL_TC_IRQ_ENABLE |
321 COH901318_CX_CTRL_HSP_ENABLE |
322 COH901318_CX_CTRL_HSS_DISABLE |
323 COH901318_CX_CTRL_DDMA_LEGACY |
324 COH901318_CX_CTRL_PRDD_SOURCE,
325 },
326 {
327 .number = U300_DMA_MSL_TX_2,
328 .name = "MSL TX 2",
329 .priority_high = 0,
330 .param.config = COH901318_CX_CFG_CH_DISABLE |
331 COH901318_CX_CFG_LCR_DISABLE |
332 COH901318_CX_CFG_TC_IRQ_ENABLE |
333 COH901318_CX_CFG_BE_IRQ_ENABLE,
334 .param.ctrl_lli_chained = 0 |
335 COH901318_CX_CTRL_TC_ENABLE |
336 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
337 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
338 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
339 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
340 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
341 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
342 COH901318_CX_CTRL_TCP_DISABLE |
343 COH901318_CX_CTRL_TC_IRQ_DISABLE |
344 COH901318_CX_CTRL_HSP_ENABLE |
345 COH901318_CX_CTRL_HSS_DISABLE |
346 COH901318_CX_CTRL_DDMA_LEGACY |
347 COH901318_CX_CTRL_PRDD_SOURCE,
348 .param.ctrl_lli = 0 |
349 COH901318_CX_CTRL_TC_ENABLE |
350 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
351 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
352 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
353 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
354 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
355 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
356 COH901318_CX_CTRL_TCP_ENABLE |
357 COH901318_CX_CTRL_TC_IRQ_DISABLE |
358 COH901318_CX_CTRL_HSP_ENABLE |
359 COH901318_CX_CTRL_HSS_DISABLE |
360 COH901318_CX_CTRL_DDMA_LEGACY |
361 COH901318_CX_CTRL_PRDD_SOURCE,
362 .param.ctrl_lli_last = 0 |
363 COH901318_CX_CTRL_TC_ENABLE |
364 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
365 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
366 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
367 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
368 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
369 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
370 COH901318_CX_CTRL_TCP_ENABLE |
371 COH901318_CX_CTRL_TC_IRQ_ENABLE |
372 COH901318_CX_CTRL_HSP_ENABLE |
373 COH901318_CX_CTRL_HSS_DISABLE |
374 COH901318_CX_CTRL_DDMA_LEGACY |
375 COH901318_CX_CTRL_PRDD_SOURCE,
376 .desc_nbr_max = 10,
377 },
378 {
379 .number = U300_DMA_MSL_TX_3,
380 .name = "MSL TX 3",
381 .priority_high = 0,
382 .param.config = COH901318_CX_CFG_CH_DISABLE |
383 COH901318_CX_CFG_LCR_DISABLE |
384 COH901318_CX_CFG_TC_IRQ_ENABLE |
385 COH901318_CX_CFG_BE_IRQ_ENABLE,
386 .param.ctrl_lli_chained = 0 |
387 COH901318_CX_CTRL_TC_ENABLE |
388 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
389 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
390 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
391 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
392 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
393 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
394 COH901318_CX_CTRL_TCP_DISABLE |
395 COH901318_CX_CTRL_TC_IRQ_DISABLE |
396 COH901318_CX_CTRL_HSP_ENABLE |
397 COH901318_CX_CTRL_HSS_DISABLE |
398 COH901318_CX_CTRL_DDMA_LEGACY |
399 COH901318_CX_CTRL_PRDD_SOURCE,
400 .param.ctrl_lli = 0 |
401 COH901318_CX_CTRL_TC_ENABLE |
402 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
403 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
404 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
405 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
406 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
407 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
408 COH901318_CX_CTRL_TCP_ENABLE |
409 COH901318_CX_CTRL_TC_IRQ_DISABLE |
410 COH901318_CX_CTRL_HSP_ENABLE |
411 COH901318_CX_CTRL_HSS_DISABLE |
412 COH901318_CX_CTRL_DDMA_LEGACY |
413 COH901318_CX_CTRL_PRDD_SOURCE,
414 .param.ctrl_lli_last = 0 |
415 COH901318_CX_CTRL_TC_ENABLE |
416 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
417 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
418 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
419 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
420 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
421 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
422 COH901318_CX_CTRL_TCP_ENABLE |
423 COH901318_CX_CTRL_TC_IRQ_ENABLE |
424 COH901318_CX_CTRL_HSP_ENABLE |
425 COH901318_CX_CTRL_HSS_DISABLE |
426 COH901318_CX_CTRL_DDMA_LEGACY |
427 COH901318_CX_CTRL_PRDD_SOURCE,
428 },
429 {
430 .number = U300_DMA_MSL_TX_4,
431 .name = "MSL TX 4",
432 .priority_high = 0,
433 .param.config = COH901318_CX_CFG_CH_DISABLE |
434 COH901318_CX_CFG_LCR_DISABLE |
435 COH901318_CX_CFG_TC_IRQ_ENABLE |
436 COH901318_CX_CFG_BE_IRQ_ENABLE,
437 .param.ctrl_lli_chained = 0 |
438 COH901318_CX_CTRL_TC_ENABLE |
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
443 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
444 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
445 COH901318_CX_CTRL_TCP_DISABLE |
446 COH901318_CX_CTRL_TC_IRQ_DISABLE |
447 COH901318_CX_CTRL_HSP_ENABLE |
448 COH901318_CX_CTRL_HSS_DISABLE |
449 COH901318_CX_CTRL_DDMA_LEGACY |
450 COH901318_CX_CTRL_PRDD_SOURCE,
451 .param.ctrl_lli = 0 |
452 COH901318_CX_CTRL_TC_ENABLE |
453 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
454 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
455 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
456 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
457 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
458 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
459 COH901318_CX_CTRL_TCP_ENABLE |
460 COH901318_CX_CTRL_TC_IRQ_DISABLE |
461 COH901318_CX_CTRL_HSP_ENABLE |
462 COH901318_CX_CTRL_HSS_DISABLE |
463 COH901318_CX_CTRL_DDMA_LEGACY |
464 COH901318_CX_CTRL_PRDD_SOURCE,
465 .param.ctrl_lli_last = 0 |
466 COH901318_CX_CTRL_TC_ENABLE |
467 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
468 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
469 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
470 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
471 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
472 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
473 COH901318_CX_CTRL_TCP_ENABLE |
474 COH901318_CX_CTRL_TC_IRQ_ENABLE |
475 COH901318_CX_CTRL_HSP_ENABLE |
476 COH901318_CX_CTRL_HSS_DISABLE |
477 COH901318_CX_CTRL_DDMA_LEGACY |
478 COH901318_CX_CTRL_PRDD_SOURCE,
479 },
480 {
481 .number = U300_DMA_MSL_TX_5,
482 .name = "MSL TX 5",
483 .priority_high = 0,
484 },
485 {
486 .number = U300_DMA_MSL_TX_6,
487 .name = "MSL TX 6",
488 .priority_high = 0,
489 },
490 {
491 .number = U300_DMA_MSL_RX_0,
492 .name = "MSL RX 0",
493 .priority_high = 0,
494 },
495 {
496 .number = U300_DMA_MSL_RX_1,
497 .name = "MSL RX 1",
498 .priority_high = 0,
499 .param.config = COH901318_CX_CFG_CH_DISABLE |
500 COH901318_CX_CFG_LCR_DISABLE |
501 COH901318_CX_CFG_TC_IRQ_ENABLE |
502 COH901318_CX_CFG_BE_IRQ_ENABLE,
503 .param.ctrl_lli_chained = 0 |
504 COH901318_CX_CTRL_TC_ENABLE |
505 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
506 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
507 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
508 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
509 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
510 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
511 COH901318_CX_CTRL_TCP_DISABLE |
512 COH901318_CX_CTRL_TC_IRQ_DISABLE |
513 COH901318_CX_CTRL_HSP_ENABLE |
514 COH901318_CX_CTRL_HSS_DISABLE |
515 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
516 COH901318_CX_CTRL_PRDD_DEST,
517 .param.ctrl_lli = 0,
518 .param.ctrl_lli_last = 0 |
519 COH901318_CX_CTRL_TC_ENABLE |
520 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
521 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
522 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
523 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
524 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
525 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
526 COH901318_CX_CTRL_TCP_DISABLE |
527 COH901318_CX_CTRL_TC_IRQ_ENABLE |
528 COH901318_CX_CTRL_HSP_ENABLE |
529 COH901318_CX_CTRL_HSS_DISABLE |
530 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
531 COH901318_CX_CTRL_PRDD_DEST,
532 },
533 {
534 .number = U300_DMA_MSL_RX_2,
535 .name = "MSL RX 2",
536 .priority_high = 0,
537 .param.config = COH901318_CX_CFG_CH_DISABLE |
538 COH901318_CX_CFG_LCR_DISABLE |
539 COH901318_CX_CFG_TC_IRQ_ENABLE |
540 COH901318_CX_CFG_BE_IRQ_ENABLE,
541 .param.ctrl_lli_chained = 0 |
542 COH901318_CX_CTRL_TC_ENABLE |
543 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
544 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
545 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
546 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
547 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
548 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
549 COH901318_CX_CTRL_TCP_DISABLE |
550 COH901318_CX_CTRL_TC_IRQ_DISABLE |
551 COH901318_CX_CTRL_HSP_ENABLE |
552 COH901318_CX_CTRL_HSS_DISABLE |
553 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
554 COH901318_CX_CTRL_PRDD_DEST,
555 .param.ctrl_lli = 0 |
556 COH901318_CX_CTRL_TC_ENABLE |
557 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
558 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
559 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
560 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
561 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
562 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
563 COH901318_CX_CTRL_TCP_DISABLE |
564 COH901318_CX_CTRL_TC_IRQ_ENABLE |
565 COH901318_CX_CTRL_HSP_ENABLE |
566 COH901318_CX_CTRL_HSS_DISABLE |
567 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
568 COH901318_CX_CTRL_PRDD_DEST,
569 .param.ctrl_lli_last = 0 |
570 COH901318_CX_CTRL_TC_ENABLE |
571 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
572 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
573 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
574 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
575 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
576 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
577 COH901318_CX_CTRL_TCP_DISABLE |
578 COH901318_CX_CTRL_TC_IRQ_ENABLE |
579 COH901318_CX_CTRL_HSP_ENABLE |
580 COH901318_CX_CTRL_HSS_DISABLE |
581 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
582 COH901318_CX_CTRL_PRDD_DEST,
583 },
584 {
585 .number = U300_DMA_MSL_RX_3,
586 .name = "MSL RX 3",
587 .priority_high = 0,
588 .param.config = COH901318_CX_CFG_CH_DISABLE |
589 COH901318_CX_CFG_LCR_DISABLE |
590 COH901318_CX_CFG_TC_IRQ_ENABLE |
591 COH901318_CX_CFG_BE_IRQ_ENABLE,
592 .param.ctrl_lli_chained = 0 |
593 COH901318_CX_CTRL_TC_ENABLE |
594 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
595 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
596 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
597 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
598 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
599 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
600 COH901318_CX_CTRL_TCP_DISABLE |
601 COH901318_CX_CTRL_TC_IRQ_DISABLE |
602 COH901318_CX_CTRL_HSP_ENABLE |
603 COH901318_CX_CTRL_HSS_DISABLE |
604 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
605 COH901318_CX_CTRL_PRDD_DEST,
606 .param.ctrl_lli = 0 |
607 COH901318_CX_CTRL_TC_ENABLE |
608 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
609 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
610 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
611 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
612 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
613 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
614 COH901318_CX_CTRL_TCP_DISABLE |
615 COH901318_CX_CTRL_TC_IRQ_ENABLE |
616 COH901318_CX_CTRL_HSP_ENABLE |
617 COH901318_CX_CTRL_HSS_DISABLE |
618 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
619 COH901318_CX_CTRL_PRDD_DEST,
620 .param.ctrl_lli_last = 0 |
621 COH901318_CX_CTRL_TC_ENABLE |
622 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
623 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
624 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
625 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
626 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
627 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
628 COH901318_CX_CTRL_TCP_DISABLE |
629 COH901318_CX_CTRL_TC_IRQ_ENABLE |
630 COH901318_CX_CTRL_HSP_ENABLE |
631 COH901318_CX_CTRL_HSS_DISABLE |
632 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
633 COH901318_CX_CTRL_PRDD_DEST,
634 },
635 {
636 .number = U300_DMA_MSL_RX_4,
637 .name = "MSL RX 4",
638 .priority_high = 0,
639 .param.config = COH901318_CX_CFG_CH_DISABLE |
640 COH901318_CX_CFG_LCR_DISABLE |
641 COH901318_CX_CFG_TC_IRQ_ENABLE |
642 COH901318_CX_CFG_BE_IRQ_ENABLE,
643 .param.ctrl_lli_chained = 0 |
644 COH901318_CX_CTRL_TC_ENABLE |
645 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
646 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
647 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
648 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
649 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
650 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
651 COH901318_CX_CTRL_TCP_DISABLE |
652 COH901318_CX_CTRL_TC_IRQ_DISABLE |
653 COH901318_CX_CTRL_HSP_ENABLE |
654 COH901318_CX_CTRL_HSS_DISABLE |
655 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
656 COH901318_CX_CTRL_PRDD_DEST,
657 .param.ctrl_lli = 0 |
658 COH901318_CX_CTRL_TC_ENABLE |
659 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
660 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
661 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
662 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
663 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
664 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
665 COH901318_CX_CTRL_TCP_DISABLE |
666 COH901318_CX_CTRL_TC_IRQ_ENABLE |
667 COH901318_CX_CTRL_HSP_ENABLE |
668 COH901318_CX_CTRL_HSS_DISABLE |
669 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
670 COH901318_CX_CTRL_PRDD_DEST,
671 .param.ctrl_lli_last = 0 |
672 COH901318_CX_CTRL_TC_ENABLE |
673 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
674 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
675 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
676 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
677 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
678 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
679 COH901318_CX_CTRL_TCP_DISABLE |
680 COH901318_CX_CTRL_TC_IRQ_ENABLE |
681 COH901318_CX_CTRL_HSP_ENABLE |
682 COH901318_CX_CTRL_HSS_DISABLE |
683 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
684 COH901318_CX_CTRL_PRDD_DEST,
685 },
686 {
687 .number = U300_DMA_MSL_RX_5,
688 .name = "MSL RX 5",
689 .priority_high = 0,
690 .param.config = COH901318_CX_CFG_CH_DISABLE |
691 COH901318_CX_CFG_LCR_DISABLE |
692 COH901318_CX_CFG_TC_IRQ_ENABLE |
693 COH901318_CX_CFG_BE_IRQ_ENABLE,
694 .param.ctrl_lli_chained = 0 |
695 COH901318_CX_CTRL_TC_ENABLE |
696 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
697 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
698 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
699 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
700 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
701 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
702 COH901318_CX_CTRL_TCP_DISABLE |
703 COH901318_CX_CTRL_TC_IRQ_DISABLE |
704 COH901318_CX_CTRL_HSP_ENABLE |
705 COH901318_CX_CTRL_HSS_DISABLE |
706 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
707 COH901318_CX_CTRL_PRDD_DEST,
708 .param.ctrl_lli = 0 |
709 COH901318_CX_CTRL_TC_ENABLE |
710 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
711 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
713 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
714 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
715 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
716 COH901318_CX_CTRL_TCP_DISABLE |
717 COH901318_CX_CTRL_TC_IRQ_ENABLE |
718 COH901318_CX_CTRL_HSP_ENABLE |
719 COH901318_CX_CTRL_HSS_DISABLE |
720 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
721 COH901318_CX_CTRL_PRDD_DEST,
722 .param.ctrl_lli_last = 0 |
723 COH901318_CX_CTRL_TC_ENABLE |
724 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
725 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
726 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
727 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
728 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
729 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
730 COH901318_CX_CTRL_TCP_DISABLE |
731 COH901318_CX_CTRL_TC_IRQ_ENABLE |
732 COH901318_CX_CTRL_HSP_ENABLE |
733 COH901318_CX_CTRL_HSS_DISABLE |
734 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
735 COH901318_CX_CTRL_PRDD_DEST,
736 },
737 {
738 .number = U300_DMA_MSL_RX_6,
739 .name = "MSL RX 6",
740 .priority_high = 0,
741 },
742 /*
743 * Don't set up device address, burst count or size of src
744 * or dst bus for this peripheral - handled by PrimeCell
745 * DMA extension.
746 */
747 {
748 .number = U300_DMA_MMCSD_RX_TX,
749 .name = "MMCSD RX TX",
750 .priority_high = 0,
751 .param.config = COH901318_CX_CFG_CH_DISABLE |
752 COH901318_CX_CFG_LCR_DISABLE |
753 COH901318_CX_CFG_TC_IRQ_ENABLE |
754 COH901318_CX_CFG_BE_IRQ_ENABLE,
755 .param.ctrl_lli_chained = 0 |
756 COH901318_CX_CTRL_TC_ENABLE |
757 COH901318_CX_CTRL_MASTER_MODE_M1RW |
758 COH901318_CX_CTRL_TCP_ENABLE |
759 COH901318_CX_CTRL_TC_IRQ_DISABLE |
760 COH901318_CX_CTRL_HSP_ENABLE |
761 COH901318_CX_CTRL_HSS_DISABLE |
762 COH901318_CX_CTRL_DDMA_LEGACY,
763 .param.ctrl_lli = 0 |
764 COH901318_CX_CTRL_TC_ENABLE |
765 COH901318_CX_CTRL_MASTER_MODE_M1RW |
766 COH901318_CX_CTRL_TCP_ENABLE |
767 COH901318_CX_CTRL_TC_IRQ_DISABLE |
768 COH901318_CX_CTRL_HSP_ENABLE |
769 COH901318_CX_CTRL_HSS_DISABLE |
770 COH901318_CX_CTRL_DDMA_LEGACY,
771 .param.ctrl_lli_last = 0 |
772 COH901318_CX_CTRL_TC_ENABLE |
773 COH901318_CX_CTRL_MASTER_MODE_M1RW |
774 COH901318_CX_CTRL_TCP_DISABLE |
775 COH901318_CX_CTRL_TC_IRQ_ENABLE |
776 COH901318_CX_CTRL_HSP_ENABLE |
777 COH901318_CX_CTRL_HSS_DISABLE |
778 COH901318_CX_CTRL_DDMA_LEGACY,
779
780 },
781 {
782 .number = U300_DMA_MSPRO_TX,
783 .name = "MSPRO TX",
784 .priority_high = 0,
785 },
786 {
787 .number = U300_DMA_MSPRO_RX,
788 .name = "MSPRO RX",
789 .priority_high = 0,
790 },
791 /*
792 * Don't set up device address, burst count or size of src
793 * or dst bus for this peripheral - handled by PrimeCell
794 * DMA extension.
795 */
796 {
797 .number = U300_DMA_UART0_TX,
798 .name = "UART0 TX",
799 .priority_high = 0,
800 .param.config = COH901318_CX_CFG_CH_DISABLE |
801 COH901318_CX_CFG_LCR_DISABLE |
802 COH901318_CX_CFG_TC_IRQ_ENABLE |
803 COH901318_CX_CFG_BE_IRQ_ENABLE,
804 .param.ctrl_lli_chained = 0 |
805 COH901318_CX_CTRL_TC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M1RW |
807 COH901318_CX_CTRL_TCP_ENABLE |
808 COH901318_CX_CTRL_TC_IRQ_DISABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_LEGACY,
812 .param.ctrl_lli = 0 |
813 COH901318_CX_CTRL_TC_ENABLE |
814 COH901318_CX_CTRL_MASTER_MODE_M1RW |
815 COH901318_CX_CTRL_TCP_ENABLE |
816 COH901318_CX_CTRL_TC_IRQ_ENABLE |
817 COH901318_CX_CTRL_HSP_ENABLE |
818 COH901318_CX_CTRL_HSS_DISABLE |
819 COH901318_CX_CTRL_DDMA_LEGACY,
820 .param.ctrl_lli_last = 0 |
821 COH901318_CX_CTRL_TC_ENABLE |
822 COH901318_CX_CTRL_MASTER_MODE_M1RW |
823 COH901318_CX_CTRL_TCP_ENABLE |
824 COH901318_CX_CTRL_TC_IRQ_ENABLE |
825 COH901318_CX_CTRL_HSP_ENABLE |
826 COH901318_CX_CTRL_HSS_DISABLE |
827 COH901318_CX_CTRL_DDMA_LEGACY,
828 },
829 {
830 .number = U300_DMA_UART0_RX,
831 .name = "UART0 RX",
832 .priority_high = 0,
833 .param.config = COH901318_CX_CFG_CH_DISABLE |
834 COH901318_CX_CFG_LCR_DISABLE |
835 COH901318_CX_CFG_TC_IRQ_ENABLE |
836 COH901318_CX_CFG_BE_IRQ_ENABLE,
837 .param.ctrl_lli_chained = 0 |
838 COH901318_CX_CTRL_TC_ENABLE |
839 COH901318_CX_CTRL_MASTER_MODE_M1RW |
840 COH901318_CX_CTRL_TCP_ENABLE |
841 COH901318_CX_CTRL_TC_IRQ_DISABLE |
842 COH901318_CX_CTRL_HSP_ENABLE |
843 COH901318_CX_CTRL_HSS_DISABLE |
844 COH901318_CX_CTRL_DDMA_LEGACY,
845 .param.ctrl_lli = 0 |
846 COH901318_CX_CTRL_TC_ENABLE |
847 COH901318_CX_CTRL_MASTER_MODE_M1RW |
848 COH901318_CX_CTRL_TCP_ENABLE |
849 COH901318_CX_CTRL_TC_IRQ_ENABLE |
850 COH901318_CX_CTRL_HSP_ENABLE |
851 COH901318_CX_CTRL_HSS_DISABLE |
852 COH901318_CX_CTRL_DDMA_LEGACY,
853 .param.ctrl_lli_last = 0 |
854 COH901318_CX_CTRL_TC_ENABLE |
855 COH901318_CX_CTRL_MASTER_MODE_M1RW |
856 COH901318_CX_CTRL_TCP_ENABLE |
857 COH901318_CX_CTRL_TC_IRQ_ENABLE |
858 COH901318_CX_CTRL_HSP_ENABLE |
859 COH901318_CX_CTRL_HSS_DISABLE |
860 COH901318_CX_CTRL_DDMA_LEGACY,
861 },
862 {
863 .number = U300_DMA_APEX_TX,
864 .name = "APEX TX",
865 .priority_high = 0,
866 },
867 {
868 .number = U300_DMA_APEX_RX,
869 .name = "APEX RX",
870 .priority_high = 0,
871 },
872 {
873 .number = U300_DMA_PCM_I2S0_TX,
874 .name = "PCM I2S0 TX",
875 .priority_high = 1,
876 .param.config = COH901318_CX_CFG_CH_DISABLE |
877 COH901318_CX_CFG_LCR_DISABLE |
878 COH901318_CX_CFG_TC_IRQ_ENABLE |
879 COH901318_CX_CFG_BE_IRQ_ENABLE,
880 .param.ctrl_lli_chained = 0 |
881 COH901318_CX_CTRL_TC_ENABLE |
882 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
883 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
884 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
885 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
886 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
887 COH901318_CX_CTRL_MASTER_MODE_M1RW |
888 COH901318_CX_CTRL_TCP_DISABLE |
889 COH901318_CX_CTRL_TC_IRQ_DISABLE |
890 COH901318_CX_CTRL_HSP_ENABLE |
891 COH901318_CX_CTRL_HSS_DISABLE |
892 COH901318_CX_CTRL_DDMA_LEGACY |
893 COH901318_CX_CTRL_PRDD_SOURCE,
894 .param.ctrl_lli = 0 |
895 COH901318_CX_CTRL_TC_ENABLE |
896 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
897 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
898 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
899 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
900 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
901 COH901318_CX_CTRL_MASTER_MODE_M1RW |
902 COH901318_CX_CTRL_TCP_ENABLE |
903 COH901318_CX_CTRL_TC_IRQ_DISABLE |
904 COH901318_CX_CTRL_HSP_ENABLE |
905 COH901318_CX_CTRL_HSS_DISABLE |
906 COH901318_CX_CTRL_DDMA_LEGACY |
907 COH901318_CX_CTRL_PRDD_SOURCE,
908 .param.ctrl_lli_last = 0 |
909 COH901318_CX_CTRL_TC_ENABLE |
910 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
911 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
912 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
913 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
914 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
915 COH901318_CX_CTRL_MASTER_MODE_M1RW |
916 COH901318_CX_CTRL_TCP_ENABLE |
917 COH901318_CX_CTRL_TC_IRQ_DISABLE |
918 COH901318_CX_CTRL_HSP_ENABLE |
919 COH901318_CX_CTRL_HSS_DISABLE |
920 COH901318_CX_CTRL_DDMA_LEGACY |
921 COH901318_CX_CTRL_PRDD_SOURCE,
922 },
923 {
924 .number = U300_DMA_PCM_I2S0_RX,
925 .name = "PCM I2S0 RX",
926 .priority_high = 1,
927 .param.config = COH901318_CX_CFG_CH_DISABLE |
928 COH901318_CX_CFG_LCR_DISABLE |
929 COH901318_CX_CFG_TC_IRQ_ENABLE |
930 COH901318_CX_CFG_BE_IRQ_ENABLE,
931 .param.ctrl_lli_chained = 0 |
932 COH901318_CX_CTRL_TC_ENABLE |
933 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
934 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
935 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
936 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
937 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
938 COH901318_CX_CTRL_MASTER_MODE_M1RW |
939 COH901318_CX_CTRL_TCP_DISABLE |
940 COH901318_CX_CTRL_TC_IRQ_DISABLE |
941 COH901318_CX_CTRL_HSP_ENABLE |
942 COH901318_CX_CTRL_HSS_DISABLE |
943 COH901318_CX_CTRL_DDMA_LEGACY |
944 COH901318_CX_CTRL_PRDD_DEST,
945 .param.ctrl_lli = 0 |
946 COH901318_CX_CTRL_TC_ENABLE |
947 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
948 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
949 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
950 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
951 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
952 COH901318_CX_CTRL_MASTER_MODE_M1RW |
953 COH901318_CX_CTRL_TCP_ENABLE |
954 COH901318_CX_CTRL_TC_IRQ_DISABLE |
955 COH901318_CX_CTRL_HSP_ENABLE |
956 COH901318_CX_CTRL_HSS_DISABLE |
957 COH901318_CX_CTRL_DDMA_LEGACY |
958 COH901318_CX_CTRL_PRDD_DEST,
959 .param.ctrl_lli_last = 0 |
960 COH901318_CX_CTRL_TC_ENABLE |
961 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
962 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
963 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
964 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
965 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
966 COH901318_CX_CTRL_MASTER_MODE_M1RW |
967 COH901318_CX_CTRL_TCP_ENABLE |
968 COH901318_CX_CTRL_TC_IRQ_ENABLE |
969 COH901318_CX_CTRL_HSP_ENABLE |
970 COH901318_CX_CTRL_HSS_DISABLE |
971 COH901318_CX_CTRL_DDMA_LEGACY |
972 COH901318_CX_CTRL_PRDD_DEST,
973 },
974 {
975 .number = U300_DMA_PCM_I2S1_TX,
976 .name = "PCM I2S1 TX",
977 .priority_high = 1,
978 .param.config = COH901318_CX_CFG_CH_DISABLE |
979 COH901318_CX_CFG_LCR_DISABLE |
980 COH901318_CX_CFG_TC_IRQ_ENABLE |
981 COH901318_CX_CFG_BE_IRQ_ENABLE,
982 .param.ctrl_lli_chained = 0 |
983 COH901318_CX_CTRL_TC_ENABLE |
984 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
985 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
986 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
989 COH901318_CX_CTRL_MASTER_MODE_M1RW |
990 COH901318_CX_CTRL_TCP_DISABLE |
991 COH901318_CX_CTRL_TC_IRQ_DISABLE |
992 COH901318_CX_CTRL_HSP_ENABLE |
993 COH901318_CX_CTRL_HSS_DISABLE |
994 COH901318_CX_CTRL_DDMA_LEGACY |
995 COH901318_CX_CTRL_PRDD_SOURCE,
996 .param.ctrl_lli = 0 |
997 COH901318_CX_CTRL_TC_ENABLE |
998 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
999 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1000 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1001 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1002 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1003 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1004 COH901318_CX_CTRL_TCP_ENABLE |
1005 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1006 COH901318_CX_CTRL_HSP_ENABLE |
1007 COH901318_CX_CTRL_HSS_DISABLE |
1008 COH901318_CX_CTRL_DDMA_LEGACY |
1009 COH901318_CX_CTRL_PRDD_SOURCE,
1010 .param.ctrl_lli_last = 0 |
1011 COH901318_CX_CTRL_TC_ENABLE |
1012 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1013 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1014 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1015 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1016 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1017 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1018 COH901318_CX_CTRL_TCP_ENABLE |
1019 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1020 COH901318_CX_CTRL_HSP_ENABLE |
1021 COH901318_CX_CTRL_HSS_DISABLE |
1022 COH901318_CX_CTRL_DDMA_LEGACY |
1023 COH901318_CX_CTRL_PRDD_SOURCE,
1024 },
1025 {
1026 .number = U300_DMA_PCM_I2S1_RX,
1027 .name = "PCM I2S1 RX",
1028 .priority_high = 1,
1029 .param.config = COH901318_CX_CFG_CH_DISABLE |
1030 COH901318_CX_CFG_LCR_DISABLE |
1031 COH901318_CX_CFG_TC_IRQ_ENABLE |
1032 COH901318_CX_CFG_BE_IRQ_ENABLE,
1033 .param.ctrl_lli_chained = 0 |
1034 COH901318_CX_CTRL_TC_ENABLE |
1035 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1036 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1037 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1038 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1039 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1040 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1041 COH901318_CX_CTRL_TCP_DISABLE |
1042 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1043 COH901318_CX_CTRL_HSP_ENABLE |
1044 COH901318_CX_CTRL_HSS_DISABLE |
1045 COH901318_CX_CTRL_DDMA_LEGACY |
1046 COH901318_CX_CTRL_PRDD_DEST,
1047 .param.ctrl_lli = 0 |
1048 COH901318_CX_CTRL_TC_ENABLE |
1049 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1050 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1051 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1052 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1053 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1054 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1055 COH901318_CX_CTRL_TCP_ENABLE |
1056 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1057 COH901318_CX_CTRL_HSP_ENABLE |
1058 COH901318_CX_CTRL_HSS_DISABLE |
1059 COH901318_CX_CTRL_DDMA_LEGACY |
1060 COH901318_CX_CTRL_PRDD_DEST,
1061 .param.ctrl_lli_last = 0 |
1062 COH901318_CX_CTRL_TC_ENABLE |
1063 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1064 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1065 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1066 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1067 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1068 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1069 COH901318_CX_CTRL_TCP_ENABLE |
1070 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1071 COH901318_CX_CTRL_HSP_ENABLE |
1072 COH901318_CX_CTRL_HSS_DISABLE |
1073 COH901318_CX_CTRL_DDMA_LEGACY |
1074 COH901318_CX_CTRL_PRDD_DEST,
1075 },
1076 {
1077 .number = U300_DMA_XGAM_CDI,
1078 .name = "XGAM CDI",
1079 .priority_high = 0,
1080 },
1081 {
1082 .number = U300_DMA_XGAM_PDI,
1083 .name = "XGAM PDI",
1084 .priority_high = 0,
1085 },
1086 /*
1087 * Don't set up device address, burst count or size of src
1088 * or dst bus for this peripheral - handled by PrimeCell
1089 * DMA extension.
1090 */
1091 {
1092 .number = U300_DMA_SPI_TX,
1093 .name = "SPI TX",
1094 .priority_high = 0,
1095 .param.config = COH901318_CX_CFG_CH_DISABLE |
1096 COH901318_CX_CFG_LCR_DISABLE |
1097 COH901318_CX_CFG_TC_IRQ_ENABLE |
1098 COH901318_CX_CFG_BE_IRQ_ENABLE,
1099 .param.ctrl_lli_chained = 0 |
1100 COH901318_CX_CTRL_TC_ENABLE |
1101 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1102 COH901318_CX_CTRL_TCP_DISABLE |
1103 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1104 COH901318_CX_CTRL_HSP_ENABLE |
1105 COH901318_CX_CTRL_HSS_DISABLE |
1106 COH901318_CX_CTRL_DDMA_LEGACY,
1107 .param.ctrl_lli = 0 |
1108 COH901318_CX_CTRL_TC_ENABLE |
1109 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110 COH901318_CX_CTRL_TCP_DISABLE |
1111 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112 COH901318_CX_CTRL_HSP_ENABLE |
1113 COH901318_CX_CTRL_HSS_DISABLE |
1114 COH901318_CX_CTRL_DDMA_LEGACY,
1115 .param.ctrl_lli_last = 0 |
1116 COH901318_CX_CTRL_TC_ENABLE |
1117 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1118 COH901318_CX_CTRL_TCP_DISABLE |
1119 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1120 COH901318_CX_CTRL_HSP_ENABLE |
1121 COH901318_CX_CTRL_HSS_DISABLE |
1122 COH901318_CX_CTRL_DDMA_LEGACY,
1123 },
1124 {
1125 .number = U300_DMA_SPI_RX,
1126 .name = "SPI RX",
1127 .priority_high = 0,
1128 .param.config = COH901318_CX_CFG_CH_DISABLE |
1129 COH901318_CX_CFG_LCR_DISABLE |
1130 COH901318_CX_CFG_TC_IRQ_ENABLE |
1131 COH901318_CX_CFG_BE_IRQ_ENABLE,
1132 .param.ctrl_lli_chained = 0 |
1133 COH901318_CX_CTRL_TC_ENABLE |
1134 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135 COH901318_CX_CTRL_TCP_DISABLE |
1136 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1137 COH901318_CX_CTRL_HSP_ENABLE |
1138 COH901318_CX_CTRL_HSS_DISABLE |
1139 COH901318_CX_CTRL_DDMA_LEGACY,
1140 .param.ctrl_lli = 0 |
1141 COH901318_CX_CTRL_TC_ENABLE |
1142 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1143 COH901318_CX_CTRL_TCP_DISABLE |
1144 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1145 COH901318_CX_CTRL_HSP_ENABLE |
1146 COH901318_CX_CTRL_HSS_DISABLE |
1147 COH901318_CX_CTRL_DDMA_LEGACY,
1148 .param.ctrl_lli_last = 0 |
1149 COH901318_CX_CTRL_TC_ENABLE |
1150 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151 COH901318_CX_CTRL_TCP_DISABLE |
1152 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1153 COH901318_CX_CTRL_HSP_ENABLE |
1154 COH901318_CX_CTRL_HSS_DISABLE |
1155 COH901318_CX_CTRL_DDMA_LEGACY,
1156
1157 },
1158 {
1159 .number = U300_DMA_GENERAL_PURPOSE_0,
1160 .name = "GENERAL 00",
1161 .priority_high = 0,
1162
1163 .param.config = flags_memcpy_config,
1164 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1165 .param.ctrl_lli = flags_memcpy_lli,
1166 .param.ctrl_lli_last = flags_memcpy_lli_last,
1167 },
1168 {
1169 .number = U300_DMA_GENERAL_PURPOSE_1,
1170 .name = "GENERAL 01",
1171 .priority_high = 0,
1172
1173 .param.config = flags_memcpy_config,
1174 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1175 .param.ctrl_lli = flags_memcpy_lli,
1176 .param.ctrl_lli_last = flags_memcpy_lli_last,
1177 },
1178 {
1179 .number = U300_DMA_GENERAL_PURPOSE_2,
1180 .name = "GENERAL 02",
1181 .priority_high = 0,
1182
1183 .param.config = flags_memcpy_config,
1184 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1185 .param.ctrl_lli = flags_memcpy_lli,
1186 .param.ctrl_lli_last = flags_memcpy_lli_last,
1187 },
1188 {
1189 .number = U300_DMA_GENERAL_PURPOSE_3,
1190 .name = "GENERAL 03",
1191 .priority_high = 0,
1192
1193 .param.config = flags_memcpy_config,
1194 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1195 .param.ctrl_lli = flags_memcpy_lli,
1196 .param.ctrl_lli_last = flags_memcpy_lli_last,
1197 },
1198 {
1199 .number = U300_DMA_GENERAL_PURPOSE_4,
1200 .name = "GENERAL 04",
1201 .priority_high = 0,
1202
1203 .param.config = flags_memcpy_config,
1204 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1205 .param.ctrl_lli = flags_memcpy_lli,
1206 .param.ctrl_lli_last = flags_memcpy_lli_last,
1207 },
1208 {
1209 .number = U300_DMA_GENERAL_PURPOSE_5,
1210 .name = "GENERAL 05",
1211 .priority_high = 0,
1212
1213 .param.config = flags_memcpy_config,
1214 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1215 .param.ctrl_lli = flags_memcpy_lli,
1216 .param.ctrl_lli_last = flags_memcpy_lli_last,
1217 },
1218 {
1219 .number = U300_DMA_GENERAL_PURPOSE_6,
1220 .name = "GENERAL 06",
1221 .priority_high = 0,
1222
1223 .param.config = flags_memcpy_config,
1224 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1225 .param.ctrl_lli = flags_memcpy_lli,
1226 .param.ctrl_lli_last = flags_memcpy_lli_last,
1227 },
1228 {
1229 .number = U300_DMA_GENERAL_PURPOSE_7,
1230 .name = "GENERAL 07",
1231 .priority_high = 0,
1232
1233 .param.config = flags_memcpy_config,
1234 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1235 .param.ctrl_lli = flags_memcpy_lli,
1236 .param.ctrl_lli_last = flags_memcpy_lli_last,
1237 },
1238 {
1239 .number = U300_DMA_GENERAL_PURPOSE_8,
1240 .name = "GENERAL 08",
1241 .priority_high = 0,
1242
1243 .param.config = flags_memcpy_config,
1244 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1245 .param.ctrl_lli = flags_memcpy_lli,
1246 .param.ctrl_lli_last = flags_memcpy_lli_last,
1247 },
1248 {
1249 .number = U300_DMA_UART1_TX,
1250 .name = "UART1 TX",
1251 .priority_high = 0,
1252 },
1253 {
1254 .number = U300_DMA_UART1_RX,
1255 .name = "UART1 RX",
1256 .priority_high = 0,
1257 }
1258 };
1259
1260 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1261
1262 #ifdef VERBOSE_DEBUG
1263 #define COH_DBG(x) ({ if (1) x; 0; })
1264 #else
1265 #define COH_DBG(x) ({ if (0) x; 0; })
1266 #endif
1267
1268 struct coh901318_desc {
1269 struct dma_async_tx_descriptor desc;
1270 struct list_head node;
1271 struct scatterlist *sg;
1272 unsigned int sg_len;
1273 struct coh901318_lli *lli;
1274 enum dma_transfer_direction dir;
1275 unsigned long flags;
1276 u32 head_config;
1277 u32 head_ctrl;
1278 };
1279
1280 struct coh901318_base {
1281 struct device *dev;
1282 void __iomem *virtbase;
1283 unsigned int irq;
1284 struct coh901318_pool pool;
1285 struct powersave pm;
1286 struct dma_device dma_slave;
1287 struct dma_device dma_memcpy;
1288 struct coh901318_chan *chans;
1289 };
1290
1291 struct coh901318_chan {
1292 spinlock_t lock;
1293 int allocated;
1294 int id;
1295 int stopped;
1296
1297 struct work_struct free_work;
1298 struct dma_chan chan;
1299
1300 struct tasklet_struct tasklet;
1301
1302 struct list_head active;
1303 struct list_head queue;
1304 struct list_head free;
1305
1306 unsigned long nbr_active_done;
1307 unsigned long busy;
1308
1309 struct dma_slave_config config;
1310 u32 addr;
1311 u32 ctrl;
1312
1313 struct coh901318_base *base;
1314 };
1315
1316 static void coh901318_list_print(struct coh901318_chan *cohc,
1317 struct coh901318_lli *lli)
1318 {
1319 struct coh901318_lli *l = lli;
1320 int i = 0;
1321
1322 while (l) {
1323 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src %pad"
1324 ", dst %pad, link %pad virt_link_addr 0x%p\n",
1325 i, l, l->control, &l->src_addr, &l->dst_addr,
1326 &l->link_addr, l->virt_link_addr);
1327 i++;
1328 l = l->virt_link_addr;
1329 }
1330 }
1331
1332 #ifdef CONFIG_DEBUG_FS
1333
1334 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1335
1336 static struct coh901318_base *debugfs_dma_base;
1337 static struct dentry *dma_dentry;
1338
1339 static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf,
1340 size_t count, loff_t *f_pos)
1341 {
1342 u64 started_channels = debugfs_dma_base->pm.started_channels;
1343 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1344 char *dev_buf;
1345 char *tmp;
1346 int ret;
1347 int i;
1348
1349 dev_buf = kmalloc(4*1024, GFP_KERNEL);
1350 if (dev_buf == NULL)
1351 return -ENOMEM;
1352 tmp = dev_buf;
1353
1354 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
1355
1356 for (i = 0; i < U300_DMA_CHANNELS; i++) {
1357 if (started_channels & (1ULL << i))
1358 tmp += sprintf(tmp, "channel %d\n", i);
1359 }
1360
1361 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1362
1363 ret = simple_read_from_buffer(buf, count, f_pos, dev_buf,
1364 tmp - dev_buf);
1365 kfree(dev_buf);
1366 return ret;
1367 }
1368
1369 static const struct file_operations coh901318_debugfs_status_operations = {
1370 .open = simple_open,
1371 .read = coh901318_debugfs_read,
1372 .llseek = default_llseek,
1373 };
1374
1375
1376 static int __init init_coh901318_debugfs(void)
1377 {
1378
1379 dma_dentry = debugfs_create_dir("dma", NULL);
1380
1381 debugfs_create_file("status", S_IFREG | S_IRUGO, dma_dentry, NULL,
1382 &coh901318_debugfs_status_operations);
1383 return 0;
1384 }
1385
1386 static void __exit exit_coh901318_debugfs(void)
1387 {
1388 debugfs_remove_recursive(dma_dentry);
1389 }
1390
1391 module_init(init_coh901318_debugfs);
1392 module_exit(exit_coh901318_debugfs);
1393 #else
1394
1395 #define COH901318_DEBUGFS_ASSIGN(x, y)
1396
1397 #endif /* CONFIG_DEBUG_FS */
1398
1399 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1400 {
1401 return container_of(chan, struct coh901318_chan, chan);
1402 }
1403
1404 static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1405 struct dma_slave_config *config,
1406 enum dma_transfer_direction direction);
1407
1408 static inline const struct coh901318_params *
1409 cohc_chan_param(struct coh901318_chan *cohc)
1410 {
1411 return &chan_config[cohc->id].param;
1412 }
1413
1414 static inline const struct coh_dma_channel *
1415 cohc_chan_conf(struct coh901318_chan *cohc)
1416 {
1417 return &chan_config[cohc->id];
1418 }
1419
1420 static void enable_powersave(struct coh901318_chan *cohc)
1421 {
1422 unsigned long flags;
1423 struct powersave *pm = &cohc->base->pm;
1424
1425 spin_lock_irqsave(&pm->lock, flags);
1426
1427 pm->started_channels &= ~(1ULL << cohc->id);
1428
1429 spin_unlock_irqrestore(&pm->lock, flags);
1430 }
1431 static void disable_powersave(struct coh901318_chan *cohc)
1432 {
1433 unsigned long flags;
1434 struct powersave *pm = &cohc->base->pm;
1435
1436 spin_lock_irqsave(&pm->lock, flags);
1437
1438 pm->started_channels |= (1ULL << cohc->id);
1439
1440 spin_unlock_irqrestore(&pm->lock, flags);
1441 }
1442
1443 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1444 {
1445 int channel = cohc->id;
1446 void __iomem *virtbase = cohc->base->virtbase;
1447
1448 writel(control,
1449 virtbase + COH901318_CX_CTRL +
1450 COH901318_CX_CTRL_SPACING * channel);
1451 return 0;
1452 }
1453
1454 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1455 {
1456 int channel = cohc->id;
1457 void __iomem *virtbase = cohc->base->virtbase;
1458
1459 writel(conf,
1460 virtbase + COH901318_CX_CFG +
1461 COH901318_CX_CFG_SPACING*channel);
1462 return 0;
1463 }
1464
1465
1466 static int coh901318_start(struct coh901318_chan *cohc)
1467 {
1468 u32 val;
1469 int channel = cohc->id;
1470 void __iomem *virtbase = cohc->base->virtbase;
1471
1472 disable_powersave(cohc);
1473
1474 val = readl(virtbase + COH901318_CX_CFG +
1475 COH901318_CX_CFG_SPACING * channel);
1476
1477 /* Enable channel */
1478 val |= COH901318_CX_CFG_CH_ENABLE;
1479 writel(val, virtbase + COH901318_CX_CFG +
1480 COH901318_CX_CFG_SPACING * channel);
1481
1482 return 0;
1483 }
1484
1485 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
1486 struct coh901318_lli *lli)
1487 {
1488 int channel = cohc->id;
1489 void __iomem *virtbase = cohc->base->virtbase;
1490
1491 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1492 COH901318_CX_STAT_SPACING*channel) &
1493 COH901318_CX_STAT_ACTIVE);
1494
1495 writel(lli->src_addr,
1496 virtbase + COH901318_CX_SRC_ADDR +
1497 COH901318_CX_SRC_ADDR_SPACING * channel);
1498
1499 writel(lli->dst_addr, virtbase +
1500 COH901318_CX_DST_ADDR +
1501 COH901318_CX_DST_ADDR_SPACING * channel);
1502
1503 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
1504 COH901318_CX_LNK_ADDR_SPACING * channel);
1505
1506 writel(lli->control, virtbase + COH901318_CX_CTRL +
1507 COH901318_CX_CTRL_SPACING * channel);
1508
1509 return 0;
1510 }
1511
1512 static struct coh901318_desc *
1513 coh901318_desc_get(struct coh901318_chan *cohc)
1514 {
1515 struct coh901318_desc *desc;
1516
1517 if (list_empty(&cohc->free)) {
1518 /* alloc new desc because we're out of used ones
1519 * TODO: alloc a pile of descs instead of just one,
1520 * avoid many small allocations.
1521 */
1522 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
1523 if (desc == NULL)
1524 goto out;
1525 INIT_LIST_HEAD(&desc->node);
1526 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
1527 } else {
1528 /* Reuse an old desc. */
1529 desc = list_first_entry(&cohc->free,
1530 struct coh901318_desc,
1531 node);
1532 list_del(&desc->node);
1533 /* Initialize it a bit so it's not insane */
1534 desc->sg = NULL;
1535 desc->sg_len = 0;
1536 desc->desc.callback = NULL;
1537 desc->desc.callback_param = NULL;
1538 }
1539
1540 out:
1541 return desc;
1542 }
1543
1544 static void
1545 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1546 {
1547 list_add_tail(&cohd->node, &cohc->free);
1548 }
1549
1550 /* call with irq lock held */
1551 static void
1552 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1553 {
1554 list_add_tail(&desc->node, &cohc->active);
1555 }
1556
1557 static struct coh901318_desc *
1558 coh901318_first_active_get(struct coh901318_chan *cohc)
1559 {
1560 return list_first_entry_or_null(&cohc->active, struct coh901318_desc,
1561 node);
1562 }
1563
1564 static void
1565 coh901318_desc_remove(struct coh901318_desc *cohd)
1566 {
1567 list_del(&cohd->node);
1568 }
1569
1570 static void
1571 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1572 {
1573 list_add_tail(&desc->node, &cohc->queue);
1574 }
1575
1576 static struct coh901318_desc *
1577 coh901318_first_queued(struct coh901318_chan *cohc)
1578 {
1579 return list_first_entry_or_null(&cohc->queue, struct coh901318_desc,
1580 node);
1581 }
1582
1583 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1584 {
1585 struct coh901318_lli *lli = in_lli;
1586 u32 bytes = 0;
1587
1588 while (lli) {
1589 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1590 lli = lli->virt_link_addr;
1591 }
1592 return bytes;
1593 }
1594
1595 /*
1596 * Get the number of bytes left to transfer on this channel,
1597 * it is unwise to call this before stopping the channel for
1598 * absolute measures, but for a rough guess you can still call
1599 * it.
1600 */
1601 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
1602 {
1603 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1604 struct coh901318_desc *cohd;
1605 struct list_head *pos;
1606 unsigned long flags;
1607 u32 left = 0;
1608 int i = 0;
1609
1610 spin_lock_irqsave(&cohc->lock, flags);
1611
1612 /*
1613 * If there are many queued jobs, we iterate and add the
1614 * size of them all. We take a special look on the first
1615 * job though, since it is probably active.
1616 */
1617 list_for_each(pos, &cohc->active) {
1618 /*
1619 * The first job in the list will be working on the
1620 * hardware. The job can be stopped but still active,
1621 * so that the transfer counter is somewhere inside
1622 * the buffer.
1623 */
1624 cohd = list_entry(pos, struct coh901318_desc, node);
1625
1626 if (i == 0) {
1627 struct coh901318_lli *lli;
1628 dma_addr_t ladd;
1629
1630 /* Read current transfer count value */
1631 left = readl(cohc->base->virtbase +
1632 COH901318_CX_CTRL +
1633 COH901318_CX_CTRL_SPACING * cohc->id) &
1634 COH901318_CX_CTRL_TC_VALUE_MASK;
1635
1636 /* See if the transfer is linked... */
1637 ladd = readl(cohc->base->virtbase +
1638 COH901318_CX_LNK_ADDR +
1639 COH901318_CX_LNK_ADDR_SPACING *
1640 cohc->id) &
1641 ~COH901318_CX_LNK_LINK_IMMEDIATE;
1642 /* Single transaction */
1643 if (!ladd)
1644 continue;
1645
1646 /*
1647 * Linked transaction, follow the lli, find the
1648 * currently processing lli, and proceed to the next
1649 */
1650 lli = cohd->lli;
1651 while (lli && lli->link_addr != ladd)
1652 lli = lli->virt_link_addr;
1653
1654 if (lli)
1655 lli = lli->virt_link_addr;
1656
1657 /*
1658 * Follow remaining lli links around to count the total
1659 * number of bytes left
1660 */
1661 left += coh901318_get_bytes_in_lli(lli);
1662 } else {
1663 left += coh901318_get_bytes_in_lli(cohd->lli);
1664 }
1665 i++;
1666 }
1667
1668 /* Also count bytes in the queued jobs */
1669 list_for_each(pos, &cohc->queue) {
1670 cohd = list_entry(pos, struct coh901318_desc, node);
1671 left += coh901318_get_bytes_in_lli(cohd->lli);
1672 }
1673
1674 spin_unlock_irqrestore(&cohc->lock, flags);
1675
1676 return left;
1677 }
1678
1679 /*
1680 * Pauses a transfer without losing data. Enables power save.
1681 * Use this function in conjunction with coh901318_resume.
1682 */
1683 static int coh901318_pause(struct dma_chan *chan)
1684 {
1685 u32 val;
1686 unsigned long flags;
1687 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1688 int channel = cohc->id;
1689 void __iomem *virtbase = cohc->base->virtbase;
1690
1691 spin_lock_irqsave(&cohc->lock, flags);
1692
1693 /* Disable channel in HW */
1694 val = readl(virtbase + COH901318_CX_CFG +
1695 COH901318_CX_CFG_SPACING * channel);
1696
1697 /* Stopping infinite transfer */
1698 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1699 (val & COH901318_CX_CFG_CH_ENABLE))
1700 cohc->stopped = 1;
1701
1702
1703 val &= ~COH901318_CX_CFG_CH_ENABLE;
1704 /* Enable twice, HW bug work around */
1705 writel(val, virtbase + COH901318_CX_CFG +
1706 COH901318_CX_CFG_SPACING * channel);
1707 writel(val, virtbase + COH901318_CX_CFG +
1708 COH901318_CX_CFG_SPACING * channel);
1709
1710 /* Spin-wait for it to actually go inactive */
1711 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1712 channel) & COH901318_CX_STAT_ACTIVE)
1713 cpu_relax();
1714
1715 /* Check if we stopped an active job */
1716 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1717 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1718 cohc->stopped = 1;
1719
1720 enable_powersave(cohc);
1721
1722 spin_unlock_irqrestore(&cohc->lock, flags);
1723 return 0;
1724 }
1725
1726 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
1727 Power save is handled.
1728 */
1729 static int coh901318_resume(struct dma_chan *chan)
1730 {
1731 u32 val;
1732 unsigned long flags;
1733 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1734 int channel = cohc->id;
1735
1736 spin_lock_irqsave(&cohc->lock, flags);
1737
1738 disable_powersave(cohc);
1739
1740 if (cohc->stopped) {
1741 /* Enable channel in HW */
1742 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1743 COH901318_CX_CFG_SPACING * channel);
1744
1745 val |= COH901318_CX_CFG_CH_ENABLE;
1746
1747 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1748 COH901318_CX_CFG_SPACING*channel);
1749
1750 cohc->stopped = 0;
1751 }
1752
1753 spin_unlock_irqrestore(&cohc->lock, flags);
1754 return 0;
1755 }
1756
1757 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1758 {
1759 unsigned long ch_nr = (unsigned long) chan_id;
1760
1761 if (ch_nr == to_coh901318_chan(chan)->id)
1762 return true;
1763
1764 return false;
1765 }
1766 EXPORT_SYMBOL(coh901318_filter_id);
1767
1768 struct coh901318_filter_args {
1769 struct coh901318_base *base;
1770 unsigned int ch_nr;
1771 };
1772
1773 static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
1774 {
1775 struct coh901318_filter_args *args = data;
1776
1777 if (&args->base->dma_slave == chan->device &&
1778 args->ch_nr == to_coh901318_chan(chan)->id)
1779 return true;
1780
1781 return false;
1782 }
1783
1784 static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
1785 struct of_dma *ofdma)
1786 {
1787 struct coh901318_filter_args args = {
1788 .base = ofdma->of_dma_data,
1789 .ch_nr = dma_spec->args[0],
1790 };
1791 dma_cap_mask_t cap;
1792 dma_cap_zero(cap);
1793 dma_cap_set(DMA_SLAVE, cap);
1794
1795 return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
1796 }
1797 /*
1798 * DMA channel allocation
1799 */
1800 static int coh901318_config(struct coh901318_chan *cohc,
1801 struct coh901318_params *param)
1802 {
1803 const struct coh901318_params *p;
1804 int channel = cohc->id;
1805 void __iomem *virtbase = cohc->base->virtbase;
1806
1807 if (param)
1808 p = param;
1809 else
1810 p = cohc_chan_param(cohc);
1811
1812 /* Clear any pending BE or TC interrupt */
1813 if (channel < 32) {
1814 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1815 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1816 } else {
1817 writel(1 << (channel - 32), virtbase +
1818 COH901318_BE_INT_CLEAR2);
1819 writel(1 << (channel - 32), virtbase +
1820 COH901318_TC_INT_CLEAR2);
1821 }
1822
1823 coh901318_set_conf(cohc, p->config);
1824 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1825
1826 return 0;
1827 }
1828
1829 /* must lock when calling this function
1830 * start queued jobs, if any
1831 * TODO: start all queued jobs in one go
1832 *
1833 * Returns descriptor if queued job is started otherwise NULL.
1834 * If the queue is empty NULL is returned.
1835 */
1836 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1837 {
1838 struct coh901318_desc *cohd;
1839
1840 /*
1841 * start queued jobs, if any
1842 * TODO: transmit all queued jobs in one go
1843 */
1844 cohd = coh901318_first_queued(cohc);
1845
1846 if (cohd != NULL) {
1847 /* Remove from queue */
1848 coh901318_desc_remove(cohd);
1849 /* initiate DMA job */
1850 cohc->busy = 1;
1851
1852 coh901318_desc_submit(cohc, cohd);
1853
1854 /* Program the transaction head */
1855 coh901318_set_conf(cohc, cohd->head_config);
1856 coh901318_set_ctrl(cohc, cohd->head_ctrl);
1857 coh901318_prep_linked_list(cohc, cohd->lli);
1858
1859 /* start dma job on this channel */
1860 coh901318_start(cohc);
1861
1862 }
1863
1864 return cohd;
1865 }
1866
1867 /*
1868 * This tasklet is called from the interrupt handler to
1869 * handle each descriptor (DMA job) that is sent to a channel.
1870 */
1871 static void dma_tasklet(unsigned long data)
1872 {
1873 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1874 struct coh901318_desc *cohd_fin;
1875 unsigned long flags;
1876 struct dmaengine_desc_callback cb;
1877
1878 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1879 " nbr_active_done %ld\n", __func__,
1880 cohc->id, cohc->nbr_active_done);
1881
1882 spin_lock_irqsave(&cohc->lock, flags);
1883
1884 /* get first active descriptor entry from list */
1885 cohd_fin = coh901318_first_active_get(cohc);
1886
1887 if (cohd_fin == NULL)
1888 goto err;
1889
1890 /* locate callback to client */
1891 dmaengine_desc_get_callback(&cohd_fin->desc, &cb);
1892
1893 /* sign this job as completed on the channel */
1894 dma_cookie_complete(&cohd_fin->desc);
1895
1896 /* release the lli allocation and remove the descriptor */
1897 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
1898
1899 /* return desc to free-list */
1900 coh901318_desc_remove(cohd_fin);
1901 coh901318_desc_free(cohc, cohd_fin);
1902
1903 spin_unlock_irqrestore(&cohc->lock, flags);
1904
1905 /* Call the callback when we're done */
1906 dmaengine_desc_callback_invoke(&cb, NULL);
1907
1908 spin_lock_irqsave(&cohc->lock, flags);
1909
1910 /*
1911 * If another interrupt fired while the tasklet was scheduling,
1912 * we don't get called twice, so we have this number of active
1913 * counter that keep track of the number of IRQs expected to
1914 * be handled for this channel. If there happen to be more than
1915 * one IRQ to be ack:ed, we simply schedule this tasklet again.
1916 */
1917 cohc->nbr_active_done--;
1918 if (cohc->nbr_active_done) {
1919 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1920 "came in while we were scheduling this tasklet\n");
1921 if (cohc_chan_conf(cohc)->priority_high)
1922 tasklet_hi_schedule(&cohc->tasklet);
1923 else
1924 tasklet_schedule(&cohc->tasklet);
1925 }
1926
1927 spin_unlock_irqrestore(&cohc->lock, flags);
1928
1929 return;
1930
1931 err:
1932 spin_unlock_irqrestore(&cohc->lock, flags);
1933 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1934 }
1935
1936
1937 /* called from interrupt context */
1938 static void dma_tc_handle(struct coh901318_chan *cohc)
1939 {
1940 /*
1941 * If the channel is not allocated, then we shouldn't have
1942 * any TC interrupts on it.
1943 */
1944 if (!cohc->allocated) {
1945 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
1946 "unallocated channel\n");
1947 return;
1948 }
1949
1950 /*
1951 * When we reach this point, at least one queue item
1952 * should have been moved over from cohc->queue to
1953 * cohc->active and run to completion, that is why we're
1954 * getting a terminal count interrupt is it not?
1955 * If you get this BUG() the most probable cause is that
1956 * the individual nodes in the lli chain have IRQ enabled,
1957 * so check your platform config for lli chain ctrl.
1958 */
1959 BUG_ON(list_empty(&cohc->active));
1960
1961 cohc->nbr_active_done++;
1962
1963 /*
1964 * This attempt to take a job from cohc->queue, put it
1965 * into cohc->active and start it.
1966 */
1967 if (coh901318_queue_start(cohc) == NULL)
1968 cohc->busy = 0;
1969
1970 /*
1971 * This tasklet will remove items from cohc->active
1972 * and thus terminates them.
1973 */
1974 if (cohc_chan_conf(cohc)->priority_high)
1975 tasklet_hi_schedule(&cohc->tasklet);
1976 else
1977 tasklet_schedule(&cohc->tasklet);
1978 }
1979
1980
1981 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
1982 {
1983 u32 status1;
1984 u32 status2;
1985 int i;
1986 int ch;
1987 struct coh901318_base *base = dev_id;
1988 struct coh901318_chan *cohc;
1989 void __iomem *virtbase = base->virtbase;
1990
1991 status1 = readl(virtbase + COH901318_INT_STATUS1);
1992 status2 = readl(virtbase + COH901318_INT_STATUS2);
1993
1994 if (unlikely(status1 == 0 && status2 == 0)) {
1995 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
1996 return IRQ_HANDLED;
1997 }
1998
1999 /* TODO: consider handle IRQ in tasklet here to
2000 * minimize interrupt latency */
2001
2002 /* Check the first 32 DMA channels for IRQ */
2003 while (status1) {
2004 /* Find first bit set, return as a number. */
2005 i = ffs(status1) - 1;
2006 ch = i;
2007
2008 cohc = &base->chans[ch];
2009 spin_lock(&cohc->lock);
2010
2011 /* Mask off this bit */
2012 status1 &= ~(1 << i);
2013 /* Check the individual channel bits */
2014 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2015 dev_crit(COHC_2_DEV(cohc),
2016 "DMA bus error on channel %d!\n", ch);
2017 BUG_ON(1);
2018 /* Clear BE interrupt */
2019 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2020 } else {
2021 /* Caused by TC, really? */
2022 if (unlikely(!test_bit(i, virtbase +
2023 COH901318_TC_INT_STATUS1))) {
2024 dev_warn(COHC_2_DEV(cohc),
2025 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2026 /* Clear TC interrupt */
2027 BUG_ON(1);
2028 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2029 } else {
2030 /* Enable powersave if transfer has finished */
2031 if (!(readl(virtbase + COH901318_CX_STAT +
2032 COH901318_CX_STAT_SPACING*ch) &
2033 COH901318_CX_STAT_ENABLED)) {
2034 enable_powersave(cohc);
2035 }
2036
2037 /* Must clear TC interrupt before calling
2038 * dma_tc_handle
2039 * in case tc_handle initiate a new dma job
2040 */
2041 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2042
2043 dma_tc_handle(cohc);
2044 }
2045 }
2046 spin_unlock(&cohc->lock);
2047 }
2048
2049 /* Check the remaining 32 DMA channels for IRQ */
2050 while (status2) {
2051 /* Find first bit set, return as a number. */
2052 i = ffs(status2) - 1;
2053 ch = i + 32;
2054 cohc = &base->chans[ch];
2055 spin_lock(&cohc->lock);
2056
2057 /* Mask off this bit */
2058 status2 &= ~(1 << i);
2059 /* Check the individual channel bits */
2060 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2061 dev_crit(COHC_2_DEV(cohc),
2062 "DMA bus error on channel %d!\n", ch);
2063 /* Clear BE interrupt */
2064 BUG_ON(1);
2065 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2066 } else {
2067 /* Caused by TC, really? */
2068 if (unlikely(!test_bit(i, virtbase +
2069 COH901318_TC_INT_STATUS2))) {
2070 dev_warn(COHC_2_DEV(cohc),
2071 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2072 /* Clear TC interrupt */
2073 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2074 BUG_ON(1);
2075 } else {
2076 /* Enable powersave if transfer has finished */
2077 if (!(readl(virtbase + COH901318_CX_STAT +
2078 COH901318_CX_STAT_SPACING*ch) &
2079 COH901318_CX_STAT_ENABLED)) {
2080 enable_powersave(cohc);
2081 }
2082 /* Must clear TC interrupt before calling
2083 * dma_tc_handle
2084 * in case tc_handle initiate a new dma job
2085 */
2086 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2087
2088 dma_tc_handle(cohc);
2089 }
2090 }
2091 spin_unlock(&cohc->lock);
2092 }
2093
2094 return IRQ_HANDLED;
2095 }
2096
2097 static int coh901318_terminate_all(struct dma_chan *chan)
2098 {
2099 unsigned long flags;
2100 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2101 struct coh901318_desc *cohd;
2102 void __iomem *virtbase = cohc->base->virtbase;
2103
2104 /* The remainder of this function terminates the transfer */
2105 coh901318_pause(chan);
2106 spin_lock_irqsave(&cohc->lock, flags);
2107
2108 /* Clear any pending BE or TC interrupt */
2109 if (cohc->id < 32) {
2110 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2111 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2112 } else {
2113 writel(1 << (cohc->id - 32), virtbase +
2114 COH901318_BE_INT_CLEAR2);
2115 writel(1 << (cohc->id - 32), virtbase +
2116 COH901318_TC_INT_CLEAR2);
2117 }
2118
2119 enable_powersave(cohc);
2120
2121 while ((cohd = coh901318_first_active_get(cohc))) {
2122 /* release the lli allocation*/
2123 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2124
2125 /* return desc to free-list */
2126 coh901318_desc_remove(cohd);
2127 coh901318_desc_free(cohc, cohd);
2128 }
2129
2130 while ((cohd = coh901318_first_queued(cohc))) {
2131 /* release the lli allocation*/
2132 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
2133
2134 /* return desc to free-list */
2135 coh901318_desc_remove(cohd);
2136 coh901318_desc_free(cohc, cohd);
2137 }
2138
2139
2140 cohc->nbr_active_done = 0;
2141 cohc->busy = 0;
2142
2143 spin_unlock_irqrestore(&cohc->lock, flags);
2144
2145 return 0;
2146 }
2147
2148 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2149 {
2150 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2151 unsigned long flags;
2152
2153 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2154 __func__, cohc->id);
2155
2156 if (chan->client_count > 1)
2157 return -EBUSY;
2158
2159 spin_lock_irqsave(&cohc->lock, flags);
2160
2161 coh901318_config(cohc, NULL);
2162
2163 cohc->allocated = 1;
2164 dma_cookie_init(chan);
2165
2166 spin_unlock_irqrestore(&cohc->lock, flags);
2167
2168 return 1;
2169 }
2170
2171 static void
2172 coh901318_free_chan_resources(struct dma_chan *chan)
2173 {
2174 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2175 int channel = cohc->id;
2176 unsigned long flags;
2177
2178 spin_lock_irqsave(&cohc->lock, flags);
2179
2180 /* Disable HW */
2181 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2182 COH901318_CX_CFG_SPACING*channel);
2183 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2184 COH901318_CX_CTRL_SPACING*channel);
2185
2186 cohc->allocated = 0;
2187
2188 spin_unlock_irqrestore(&cohc->lock, flags);
2189
2190 coh901318_terminate_all(chan);
2191 }
2192
2193
2194 static dma_cookie_t
2195 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2196 {
2197 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2198 desc);
2199 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2200 unsigned long flags;
2201 dma_cookie_t cookie;
2202
2203 spin_lock_irqsave(&cohc->lock, flags);
2204 cookie = dma_cookie_assign(tx);
2205
2206 coh901318_desc_queue(cohc, cohd);
2207
2208 spin_unlock_irqrestore(&cohc->lock, flags);
2209
2210 return cookie;
2211 }
2212
2213 static struct dma_async_tx_descriptor *
2214 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2215 size_t size, unsigned long flags)
2216 {
2217 struct coh901318_lli *lli;
2218 struct coh901318_desc *cohd;
2219 unsigned long flg;
2220 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2221 int lli_len;
2222 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2223 int ret;
2224
2225 spin_lock_irqsave(&cohc->lock, flg);
2226
2227 dev_vdbg(COHC_2_DEV(cohc),
2228 "[%s] channel %d src %pad dest %pad size %zu\n",
2229 __func__, cohc->id, &src, &dest, size);
2230
2231 if (flags & DMA_PREP_INTERRUPT)
2232 /* Trigger interrupt after last lli */
2233 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2234
2235 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2236 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2237 lli_len++;
2238
2239 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
2240
2241 if (lli == NULL)
2242 goto err;
2243
2244 ret = coh901318_lli_fill_memcpy(
2245 &cohc->base->pool, lli, src, size, dest,
2246 cohc_chan_param(cohc)->ctrl_lli_chained,
2247 ctrl_last);
2248 if (ret)
2249 goto err;
2250
2251 COH_DBG(coh901318_list_print(cohc, lli));
2252
2253 /* Pick a descriptor to handle this transfer */
2254 cohd = coh901318_desc_get(cohc);
2255 cohd->lli = lli;
2256 cohd->flags = flags;
2257 cohd->desc.tx_submit = coh901318_tx_submit;
2258
2259 spin_unlock_irqrestore(&cohc->lock, flg);
2260
2261 return &cohd->desc;
2262 err:
2263 spin_unlock_irqrestore(&cohc->lock, flg);
2264 return NULL;
2265 }
2266
2267 static struct dma_async_tx_descriptor *
2268 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2269 unsigned int sg_len, enum dma_transfer_direction direction,
2270 unsigned long flags, void *context)
2271 {
2272 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2273 struct coh901318_lli *lli;
2274 struct coh901318_desc *cohd;
2275 const struct coh901318_params *params;
2276 struct scatterlist *sg;
2277 int len = 0;
2278 int size;
2279 int i;
2280 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2281 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2282 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
2283 u32 config;
2284 unsigned long flg;
2285 int ret;
2286
2287 if (!sgl)
2288 goto out;
2289 if (sg_dma_len(sgl) == 0)
2290 goto out;
2291
2292 spin_lock_irqsave(&cohc->lock, flg);
2293
2294 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2295 __func__, sg_len, direction);
2296
2297 if (flags & DMA_PREP_INTERRUPT)
2298 /* Trigger interrupt after last lli */
2299 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2300
2301 params = cohc_chan_param(cohc);
2302 config = params->config;
2303 /*
2304 * Add runtime-specific control on top, make
2305 * sure the bits you set per peripheral channel are
2306 * cleared in the default config from the platform.
2307 */
2308 ctrl_chained |= cohc->ctrl;
2309 ctrl_last |= cohc->ctrl;
2310 ctrl |= cohc->ctrl;
2311
2312 if (direction == DMA_MEM_TO_DEV) {
2313 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2314 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2315
2316 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
2317 ctrl_chained |= tx_flags;
2318 ctrl_last |= tx_flags;
2319 ctrl |= tx_flags;
2320 } else if (direction == DMA_DEV_TO_MEM) {
2321 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2322 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2323
2324 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
2325 ctrl_chained |= rx_flags;
2326 ctrl_last |= rx_flags;
2327 ctrl |= rx_flags;
2328 } else
2329 goto err_direction;
2330
2331 /* The dma only supports transmitting packages up to
2332 * MAX_DMA_PACKET_SIZE. Calculate to total number of
2333 * dma elemts required to send the entire sg list
2334 */
2335 for_each_sg(sgl, sg, sg_len, i) {
2336 unsigned int factor;
2337 size = sg_dma_len(sg);
2338
2339 if (size <= MAX_DMA_PACKET_SIZE) {
2340 len++;
2341 continue;
2342 }
2343
2344 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2345 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2346 factor++;
2347
2348 len += factor;
2349 }
2350
2351 pr_debug("Allocate %d lli:s for this transfer\n", len);
2352 lli = coh901318_lli_alloc(&cohc->base->pool, len);
2353
2354 if (lli == NULL)
2355 goto err_dma_alloc;
2356
2357 coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction);
2358
2359 /* initiate allocated lli list */
2360 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
2361 cohc->addr,
2362 ctrl_chained,
2363 ctrl,
2364 ctrl_last,
2365 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2366 if (ret)
2367 goto err_lli_fill;
2368
2369
2370 COH_DBG(coh901318_list_print(cohc, lli));
2371
2372 /* Pick a descriptor to handle this transfer */
2373 cohd = coh901318_desc_get(cohc);
2374 cohd->head_config = config;
2375 /*
2376 * Set the default head ctrl for the channel to the one from the
2377 * lli, things may have changed due to odd buffer alignment
2378 * etc.
2379 */
2380 cohd->head_ctrl = lli->control;
2381 cohd->dir = direction;
2382 cohd->flags = flags;
2383 cohd->desc.tx_submit = coh901318_tx_submit;
2384 cohd->lli = lli;
2385
2386 spin_unlock_irqrestore(&cohc->lock, flg);
2387
2388 return &cohd->desc;
2389 err_lli_fill:
2390 err_dma_alloc:
2391 err_direction:
2392 spin_unlock_irqrestore(&cohc->lock, flg);
2393 out:
2394 return NULL;
2395 }
2396
2397 static enum dma_status
2398 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2399 struct dma_tx_state *txstate)
2400 {
2401 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2402 enum dma_status ret;
2403
2404 ret = dma_cookie_status(chan, cookie, txstate);
2405 if (ret == DMA_COMPLETE || !txstate)
2406 return ret;
2407
2408 dma_set_residue(txstate, coh901318_get_bytes_left(chan));
2409
2410 if (ret == DMA_IN_PROGRESS && cohc->stopped)
2411 ret = DMA_PAUSED;
2412
2413 return ret;
2414 }
2415
2416 static void
2417 coh901318_issue_pending(struct dma_chan *chan)
2418 {
2419 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2420 unsigned long flags;
2421
2422 spin_lock_irqsave(&cohc->lock, flags);
2423
2424 /*
2425 * Busy means that pending jobs are already being processed,
2426 * and then there is no point in starting the queue: the
2427 * terminal count interrupt on the channel will take the next
2428 * job on the queue and execute it anyway.
2429 */
2430 if (!cohc->busy)
2431 coh901318_queue_start(cohc);
2432
2433 spin_unlock_irqrestore(&cohc->lock, flags);
2434 }
2435
2436 /*
2437 * Here we wrap in the runtime dma control interface
2438 */
2439 struct burst_table {
2440 int burst_8bit;
2441 int burst_16bit;
2442 int burst_32bit;
2443 u32 reg;
2444 };
2445
2446 static const struct burst_table burst_sizes[] = {
2447 {
2448 .burst_8bit = 64,
2449 .burst_16bit = 32,
2450 .burst_32bit = 16,
2451 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2452 },
2453 {
2454 .burst_8bit = 48,
2455 .burst_16bit = 24,
2456 .burst_32bit = 12,
2457 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2458 },
2459 {
2460 .burst_8bit = 32,
2461 .burst_16bit = 16,
2462 .burst_32bit = 8,
2463 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2464 },
2465 {
2466 .burst_8bit = 16,
2467 .burst_16bit = 8,
2468 .burst_32bit = 4,
2469 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2470 },
2471 {
2472 .burst_8bit = 8,
2473 .burst_16bit = 4,
2474 .burst_32bit = 2,
2475 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2476 },
2477 {
2478 .burst_8bit = 4,
2479 .burst_16bit = 2,
2480 .burst_32bit = 1,
2481 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2482 },
2483 {
2484 .burst_8bit = 2,
2485 .burst_16bit = 1,
2486 .burst_32bit = 0,
2487 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2488 },
2489 {
2490 .burst_8bit = 1,
2491 .burst_16bit = 0,
2492 .burst_32bit = 0,
2493 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2494 },
2495 };
2496
2497 static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2498 struct dma_slave_config *config,
2499 enum dma_transfer_direction direction)
2500 {
2501 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2502 dma_addr_t addr;
2503 enum dma_slave_buswidth addr_width;
2504 u32 maxburst;
2505 u32 ctrl = 0;
2506 int i = 0;
2507
2508 /* We only support mem to per or per to mem transfers */
2509 if (direction == DMA_DEV_TO_MEM) {
2510 addr = config->src_addr;
2511 addr_width = config->src_addr_width;
2512 maxburst = config->src_maxburst;
2513 } else if (direction == DMA_MEM_TO_DEV) {
2514 addr = config->dst_addr;
2515 addr_width = config->dst_addr_width;
2516 maxburst = config->dst_maxburst;
2517 } else {
2518 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2519 return -EINVAL;
2520 }
2521
2522 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2523 addr_width);
2524 switch (addr_width) {
2525 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2526 ctrl |=
2527 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2528 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2529
2530 while (i < ARRAY_SIZE(burst_sizes)) {
2531 if (burst_sizes[i].burst_8bit <= maxburst)
2532 break;
2533 i++;
2534 }
2535
2536 break;
2537 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2538 ctrl |=
2539 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2540 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2541
2542 while (i < ARRAY_SIZE(burst_sizes)) {
2543 if (burst_sizes[i].burst_16bit <= maxburst)
2544 break;
2545 i++;
2546 }
2547
2548 break;
2549 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2550 /* Direction doesn't matter here, it's 32/32 bits */
2551 ctrl |=
2552 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2553 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2554
2555 while (i < ARRAY_SIZE(burst_sizes)) {
2556 if (burst_sizes[i].burst_32bit <= maxburst)
2557 break;
2558 i++;
2559 }
2560
2561 break;
2562 default:
2563 dev_err(COHC_2_DEV(cohc),
2564 "bad runtimeconfig: alien address width\n");
2565 return -EINVAL;
2566 }
2567
2568 ctrl |= burst_sizes[i].reg;
2569 dev_dbg(COHC_2_DEV(cohc),
2570 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2571 burst_sizes[i].burst_8bit, addr_width, maxburst);
2572
2573 cohc->addr = addr;
2574 cohc->ctrl = ctrl;
2575
2576 return 0;
2577 }
2578
2579 static int coh901318_dma_slave_config(struct dma_chan *chan,
2580 struct dma_slave_config *config)
2581 {
2582 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2583
2584 memcpy(&cohc->config, config, sizeof(*config));
2585
2586 return 0;
2587 }
2588
2589 static void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2590 struct coh901318_base *base)
2591 {
2592 int chans_i;
2593 int i = 0;
2594 struct coh901318_chan *cohc;
2595
2596 INIT_LIST_HEAD(&dma->channels);
2597
2598 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2599 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2600 cohc = &base->chans[i];
2601
2602 cohc->base = base;
2603 cohc->chan.device = dma;
2604 cohc->id = i;
2605
2606 /* TODO: do we really need this lock if only one
2607 * client is connected to each channel?
2608 */
2609
2610 spin_lock_init(&cohc->lock);
2611
2612 cohc->nbr_active_done = 0;
2613 cohc->busy = 0;
2614 INIT_LIST_HEAD(&cohc->free);
2615 INIT_LIST_HEAD(&cohc->active);
2616 INIT_LIST_HEAD(&cohc->queue);
2617
2618 tasklet_init(&cohc->tasklet, dma_tasklet,
2619 (unsigned long) cohc);
2620
2621 list_add_tail(&cohc->chan.device_node,
2622 &dma->channels);
2623 }
2624 }
2625 }
2626
2627 static int __init coh901318_probe(struct platform_device *pdev)
2628 {
2629 int err = 0;
2630 struct coh901318_base *base;
2631 int irq;
2632 struct resource *io;
2633
2634 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2635 if (!io)
2636 return -ENODEV;
2637
2638 /* Map DMA controller registers to virtual memory */
2639 if (devm_request_mem_region(&pdev->dev,
2640 io->start,
2641 resource_size(io),
2642 pdev->dev.driver->name) == NULL)
2643 return -ENOMEM;
2644
2645 base = devm_kzalloc(&pdev->dev,
2646 ALIGN(sizeof(struct coh901318_base), 4) +
2647 U300_DMA_CHANNELS *
2648 sizeof(struct coh901318_chan),
2649 GFP_KERNEL);
2650 if (!base)
2651 return -ENOMEM;
2652
2653 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2654
2655 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2656 if (!base->virtbase)
2657 return -ENOMEM;
2658
2659 base->dev = &pdev->dev;
2660 spin_lock_init(&base->pm.lock);
2661 base->pm.started_channels = 0;
2662
2663 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2664
2665 irq = platform_get_irq(pdev, 0);
2666 if (irq < 0)
2667 return irq;
2668
2669 err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
2670 "coh901318", base);
2671 if (err)
2672 return err;
2673
2674 base->irq = irq;
2675
2676 err = coh901318_pool_create(&base->pool, &pdev->dev,
2677 sizeof(struct coh901318_lli),
2678 32);
2679 if (err)
2680 return err;
2681
2682 /* init channels for device transfers */
2683 coh901318_base_init(&base->dma_slave, dma_slave_channels,
2684 base);
2685
2686 dma_cap_zero(base->dma_slave.cap_mask);
2687 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2688
2689 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2690 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2691 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
2692 base->dma_slave.device_tx_status = coh901318_tx_status;
2693 base->dma_slave.device_issue_pending = coh901318_issue_pending;
2694 base->dma_slave.device_config = coh901318_dma_slave_config;
2695 base->dma_slave.device_pause = coh901318_pause;
2696 base->dma_slave.device_resume = coh901318_resume;
2697 base->dma_slave.device_terminate_all = coh901318_terminate_all;
2698 base->dma_slave.dev = &pdev->dev;
2699
2700 err = dma_async_device_register(&base->dma_slave);
2701
2702 if (err)
2703 goto err_register_slave;
2704
2705 /* init channels for memcpy */
2706 coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
2707 base);
2708
2709 dma_cap_zero(base->dma_memcpy.cap_mask);
2710 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2711
2712 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2713 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2714 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
2715 base->dma_memcpy.device_tx_status = coh901318_tx_status;
2716 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
2717 base->dma_memcpy.device_config = coh901318_dma_slave_config;
2718 base->dma_memcpy.device_pause = coh901318_pause;
2719 base->dma_memcpy.device_resume = coh901318_resume;
2720 base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
2721 base->dma_memcpy.dev = &pdev->dev;
2722 /*
2723 * This controller can only access address at even 32bit boundaries,
2724 * i.e. 2^2
2725 */
2726 base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2727 err = dma_async_device_register(&base->dma_memcpy);
2728
2729 if (err)
2730 goto err_register_memcpy;
2731
2732 err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
2733 base);
2734 if (err)
2735 goto err_register_of_dma;
2736
2737 platform_set_drvdata(pdev, base);
2738 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%p\n",
2739 base->virtbase);
2740
2741 return err;
2742
2743 err_register_of_dma:
2744 dma_async_device_unregister(&base->dma_memcpy);
2745 err_register_memcpy:
2746 dma_async_device_unregister(&base->dma_slave);
2747 err_register_slave:
2748 coh901318_pool_destroy(&base->pool);
2749 return err;
2750 }
2751 static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans)
2752 {
2753 int chans_i;
2754 int i = 0;
2755 struct coh901318_chan *cohc;
2756
2757 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2758 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2759 cohc = &base->chans[i];
2760
2761 tasklet_kill(&cohc->tasklet);
2762 }
2763 }
2764
2765 }
2766
2767 static int coh901318_remove(struct platform_device *pdev)
2768 {
2769 struct coh901318_base *base = platform_get_drvdata(pdev);
2770
2771 devm_free_irq(&pdev->dev, base->irq, base);
2772
2773 coh901318_base_remove(base, dma_slave_channels);
2774 coh901318_base_remove(base, dma_memcpy_channels);
2775
2776 of_dma_controller_free(pdev->dev.of_node);
2777 dma_async_device_unregister(&base->dma_memcpy);
2778 dma_async_device_unregister(&base->dma_slave);
2779 coh901318_pool_destroy(&base->pool);
2780 return 0;
2781 }
2782
2783 static const struct of_device_id coh901318_dt_match[] = {
2784 { .compatible = "stericsson,coh901318" },
2785 {},
2786 };
2787
2788 static struct platform_driver coh901318_driver = {
2789 .remove = coh901318_remove,
2790 .driver = {
2791 .name = "coh901318",
2792 .of_match_table = coh901318_dt_match,
2793 },
2794 };
2795
2796 static int __init coh901318_init(void)
2797 {
2798 return platform_driver_probe(&coh901318_driver, coh901318_probe);
2799 }
2800 subsys_initcall(coh901318_init);
2801
2802 static void __exit coh901318_exit(void)
2803 {
2804 platform_driver_unregister(&coh901318_driver);
2805 }
2806 module_exit(coh901318_exit);
2807
2808 MODULE_LICENSE("GPL");
2809 MODULE_AUTHOR("Per Friden");
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