1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
7 #include <linux/dmaengine.h>
8 #include <linux/dma-mapping.h>
10 #include <linux/init.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/irq.h>
17 #include <linux/clk.h>
21 #define JZ_DMA_NR_CHANS 6
23 #define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
24 #define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
25 #define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
26 #define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
27 #define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
28 #define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
29 #define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
31 #define JZ_REG_DMA_CTRL 0x300
32 #define JZ_REG_DMA_IRQ 0x304
33 #define JZ_REG_DMA_DOORBELL 0x308
34 #define JZ_REG_DMA_DOORBELL_SET 0x30C
36 #define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
37 #define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
38 #define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
39 #define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
40 #define JZ_DMA_STATUS_CTRL_HALT BIT(2)
41 #define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
42 #define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
44 #define JZ_DMA_CMD_SRC_INC BIT(23)
45 #define JZ_DMA_CMD_DST_INC BIT(22)
46 #define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
47 #define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
48 #define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
49 #define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
50 #define JZ_DMA_CMD_BLOCK_MODE BIT(7)
51 #define JZ_DMA_CMD_DESC_VALID BIT(4)
52 #define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
53 #define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
54 #define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
55 #define JZ_DMA_CMD_LINK_ENABLE BIT(0)
57 #define JZ_DMA_CMD_FLAGS_OFFSET 22
58 #define JZ_DMA_CMD_RDIL_OFFSET 16
59 #define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
60 #define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
61 #define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
62 #define JZ_DMA_CMD_MODE_OFFSET 7
64 #define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
65 #define JZ_DMA_CTRL_HALT BIT(3)
66 #define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
67 #define JZ_DMA_CTRL_ENABLE BIT(0)
69 enum jz4740_dma_width
{
70 JZ4740_DMA_WIDTH_32BIT
= 0,
71 JZ4740_DMA_WIDTH_8BIT
= 1,
72 JZ4740_DMA_WIDTH_16BIT
= 2,
75 enum jz4740_dma_transfer_size
{
76 JZ4740_DMA_TRANSFER_SIZE_4BYTE
= 0,
77 JZ4740_DMA_TRANSFER_SIZE_1BYTE
= 1,
78 JZ4740_DMA_TRANSFER_SIZE_2BYTE
= 2,
79 JZ4740_DMA_TRANSFER_SIZE_16BYTE
= 3,
80 JZ4740_DMA_TRANSFER_SIZE_32BYTE
= 4,
83 enum jz4740_dma_flags
{
84 JZ4740_DMA_SRC_AUTOINC
= 0x2,
85 JZ4740_DMA_DST_AUTOINC
= 0x1,
88 enum jz4740_dma_mode
{
89 JZ4740_DMA_MODE_SINGLE
= 0,
90 JZ4740_DMA_MODE_BLOCK
= 1,
93 struct jz4740_dma_sg
{
98 struct jz4740_dma_desc
{
99 struct virt_dma_desc vdesc
;
101 enum dma_transfer_direction direction
;
104 unsigned int num_sgs
;
105 struct jz4740_dma_sg sg
[];
108 struct jz4740_dmaengine_chan
{
109 struct virt_dma_chan vchan
;
111 struct dma_slave_config config
;
113 dma_addr_t fifo_addr
;
114 unsigned int transfer_shift
;
116 struct jz4740_dma_desc
*desc
;
117 unsigned int next_sg
;
120 struct jz4740_dma_dev
{
121 struct dma_device ddev
;
125 struct jz4740_dmaengine_chan chan
[JZ_DMA_NR_CHANS
];
128 static struct jz4740_dma_dev
*jz4740_dma_chan_get_dev(
129 struct jz4740_dmaengine_chan
*chan
)
131 return container_of(chan
->vchan
.chan
.device
, struct jz4740_dma_dev
,
135 static struct jz4740_dmaengine_chan
*to_jz4740_dma_chan(struct dma_chan
*c
)
137 return container_of(c
, struct jz4740_dmaengine_chan
, vchan
.chan
);
140 static struct jz4740_dma_desc
*to_jz4740_dma_desc(struct virt_dma_desc
*vdesc
)
142 return container_of(vdesc
, struct jz4740_dma_desc
, vdesc
);
145 static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev
*dmadev
,
148 return readl(dmadev
->base
+ reg
);
151 static inline void jz4740_dma_write(struct jz4740_dma_dev
*dmadev
,
152 unsigned reg
, uint32_t val
)
154 writel(val
, dmadev
->base
+ reg
);
157 static inline void jz4740_dma_write_mask(struct jz4740_dma_dev
*dmadev
,
158 unsigned int reg
, uint32_t val
, uint32_t mask
)
162 tmp
= jz4740_dma_read(dmadev
, reg
);
165 jz4740_dma_write(dmadev
, reg
, tmp
);
168 static struct jz4740_dma_desc
*jz4740_dma_alloc_desc(unsigned int num_sgs
)
170 return kzalloc(sizeof(struct jz4740_dma_desc
) +
171 sizeof(struct jz4740_dma_sg
) * num_sgs
, GFP_ATOMIC
);
174 static enum jz4740_dma_width
jz4740_dma_width(enum dma_slave_buswidth width
)
177 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
178 return JZ4740_DMA_WIDTH_8BIT
;
179 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
180 return JZ4740_DMA_WIDTH_16BIT
;
181 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
182 return JZ4740_DMA_WIDTH_32BIT
;
184 return JZ4740_DMA_WIDTH_32BIT
;
188 static enum jz4740_dma_transfer_size
jz4740_dma_maxburst(u32 maxburst
)
191 return JZ4740_DMA_TRANSFER_SIZE_1BYTE
;
192 else if (maxburst
<= 3)
193 return JZ4740_DMA_TRANSFER_SIZE_2BYTE
;
194 else if (maxburst
<= 15)
195 return JZ4740_DMA_TRANSFER_SIZE_4BYTE
;
196 else if (maxburst
<= 31)
197 return JZ4740_DMA_TRANSFER_SIZE_16BYTE
;
199 return JZ4740_DMA_TRANSFER_SIZE_32BYTE
;
202 static int jz4740_dma_slave_config_write(struct dma_chan
*c
,
203 struct dma_slave_config
*config
,
204 enum dma_transfer_direction direction
)
206 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
207 struct jz4740_dma_dev
*dmadev
= jz4740_dma_chan_get_dev(chan
);
208 enum jz4740_dma_width src_width
;
209 enum jz4740_dma_width dst_width
;
210 enum jz4740_dma_transfer_size transfer_size
;
211 enum jz4740_dma_flags flags
;
216 flags
= JZ4740_DMA_SRC_AUTOINC
;
217 transfer_size
= jz4740_dma_maxburst(config
->dst_maxburst
);
218 chan
->fifo_addr
= config
->dst_addr
;
221 flags
= JZ4740_DMA_DST_AUTOINC
;
222 transfer_size
= jz4740_dma_maxburst(config
->src_maxburst
);
223 chan
->fifo_addr
= config
->src_addr
;
229 src_width
= jz4740_dma_width(config
->src_addr_width
);
230 dst_width
= jz4740_dma_width(config
->dst_addr_width
);
232 switch (transfer_size
) {
233 case JZ4740_DMA_TRANSFER_SIZE_2BYTE
:
234 chan
->transfer_shift
= 1;
236 case JZ4740_DMA_TRANSFER_SIZE_4BYTE
:
237 chan
->transfer_shift
= 2;
239 case JZ4740_DMA_TRANSFER_SIZE_16BYTE
:
240 chan
->transfer_shift
= 4;
242 case JZ4740_DMA_TRANSFER_SIZE_32BYTE
:
243 chan
->transfer_shift
= 5;
246 chan
->transfer_shift
= 0;
250 cmd
= flags
<< JZ_DMA_CMD_FLAGS_OFFSET
;
251 cmd
|= src_width
<< JZ_DMA_CMD_SRC_WIDTH_OFFSET
;
252 cmd
|= dst_width
<< JZ_DMA_CMD_DST_WIDTH_OFFSET
;
253 cmd
|= transfer_size
<< JZ_DMA_CMD_TRANSFER_SIZE_OFFSET
;
254 cmd
|= JZ4740_DMA_MODE_SINGLE
<< JZ_DMA_CMD_MODE_OFFSET
;
255 cmd
|= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE
;
257 jz4740_dma_write(dmadev
, JZ_REG_DMA_CMD(chan
->id
), cmd
);
258 jz4740_dma_write(dmadev
, JZ_REG_DMA_STATUS_CTRL(chan
->id
), 0);
259 jz4740_dma_write(dmadev
, JZ_REG_DMA_REQ_TYPE(chan
->id
),
265 static int jz4740_dma_slave_config(struct dma_chan
*c
,
266 struct dma_slave_config
*config
)
268 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
270 memcpy(&chan
->config
, config
, sizeof(*config
));
274 static int jz4740_dma_terminate_all(struct dma_chan
*c
)
276 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
277 struct jz4740_dma_dev
*dmadev
= jz4740_dma_chan_get_dev(chan
);
281 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
282 jz4740_dma_write_mask(dmadev
, JZ_REG_DMA_STATUS_CTRL(chan
->id
), 0,
283 JZ_DMA_STATUS_CTRL_ENABLE
);
285 vchan_get_all_descriptors(&chan
->vchan
, &head
);
286 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
288 vchan_dma_desc_free_list(&chan
->vchan
, &head
);
293 static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan
*chan
)
295 struct jz4740_dma_dev
*dmadev
= jz4740_dma_chan_get_dev(chan
);
296 dma_addr_t src_addr
, dst_addr
;
297 struct virt_dma_desc
*vdesc
;
298 struct jz4740_dma_sg
*sg
;
300 jz4740_dma_write_mask(dmadev
, JZ_REG_DMA_STATUS_CTRL(chan
->id
), 0,
301 JZ_DMA_STATUS_CTRL_ENABLE
);
304 vdesc
= vchan_next_desc(&chan
->vchan
);
307 chan
->desc
= to_jz4740_dma_desc(vdesc
);
311 if (chan
->next_sg
== chan
->desc
->num_sgs
)
314 sg
= &chan
->desc
->sg
[chan
->next_sg
];
316 if (chan
->desc
->direction
== DMA_MEM_TO_DEV
) {
318 dst_addr
= chan
->fifo_addr
;
320 src_addr
= chan
->fifo_addr
;
323 jz4740_dma_write(dmadev
, JZ_REG_DMA_SRC_ADDR(chan
->id
), src_addr
);
324 jz4740_dma_write(dmadev
, JZ_REG_DMA_DST_ADDR(chan
->id
), dst_addr
);
325 jz4740_dma_write(dmadev
, JZ_REG_DMA_TRANSFER_COUNT(chan
->id
),
326 sg
->len
>> chan
->transfer_shift
);
330 jz4740_dma_write_mask(dmadev
, JZ_REG_DMA_STATUS_CTRL(chan
->id
),
331 JZ_DMA_STATUS_CTRL_NO_DESC
| JZ_DMA_STATUS_CTRL_ENABLE
,
332 JZ_DMA_STATUS_CTRL_HALT
| JZ_DMA_STATUS_CTRL_NO_DESC
|
333 JZ_DMA_STATUS_CTRL_ENABLE
);
335 jz4740_dma_write_mask(dmadev
, JZ_REG_DMA_CTRL
,
337 JZ_DMA_CTRL_HALT
| JZ_DMA_CTRL_ENABLE
);
342 static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan
*chan
)
344 spin_lock(&chan
->vchan
.lock
);
346 if (chan
->desc
->cyclic
) {
347 vchan_cyclic_callback(&chan
->desc
->vdesc
);
349 if (chan
->next_sg
== chan
->desc
->num_sgs
) {
350 list_del(&chan
->desc
->vdesc
.node
);
351 vchan_cookie_complete(&chan
->desc
->vdesc
);
356 jz4740_dma_start_transfer(chan
);
357 spin_unlock(&chan
->vchan
.lock
);
360 static irqreturn_t
jz4740_dma_irq(int irq
, void *devid
)
362 struct jz4740_dma_dev
*dmadev
= devid
;
366 irq_status
= readl(dmadev
->base
+ JZ_REG_DMA_IRQ
);
368 for (i
= 0; i
< 6; ++i
) {
369 if (irq_status
& (1 << i
)) {
370 jz4740_dma_write_mask(dmadev
,
371 JZ_REG_DMA_STATUS_CTRL(i
), 0,
372 JZ_DMA_STATUS_CTRL_ENABLE
|
373 JZ_DMA_STATUS_CTRL_TRANSFER_DONE
);
375 jz4740_dma_chan_irq(&dmadev
->chan
[i
]);
382 static void jz4740_dma_issue_pending(struct dma_chan
*c
)
384 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
387 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
388 if (vchan_issue_pending(&chan
->vchan
) && !chan
->desc
)
389 jz4740_dma_start_transfer(chan
);
390 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
393 static struct dma_async_tx_descriptor
*jz4740_dma_prep_slave_sg(
394 struct dma_chan
*c
, struct scatterlist
*sgl
,
395 unsigned int sg_len
, enum dma_transfer_direction direction
,
396 unsigned long flags
, void *context
)
398 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
399 struct jz4740_dma_desc
*desc
;
400 struct scatterlist
*sg
;
403 desc
= jz4740_dma_alloc_desc(sg_len
);
407 for_each_sg(sgl
, sg
, sg_len
, i
) {
408 desc
->sg
[i
].addr
= sg_dma_address(sg
);
409 desc
->sg
[i
].len
= sg_dma_len(sg
);
412 desc
->num_sgs
= sg_len
;
413 desc
->direction
= direction
;
414 desc
->cyclic
= false;
416 jz4740_dma_slave_config_write(c
, &chan
->config
, direction
);
418 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
421 static struct dma_async_tx_descriptor
*jz4740_dma_prep_dma_cyclic(
422 struct dma_chan
*c
, dma_addr_t buf_addr
, size_t buf_len
,
423 size_t period_len
, enum dma_transfer_direction direction
,
426 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
427 struct jz4740_dma_desc
*desc
;
428 unsigned int num_periods
, i
;
430 if (buf_len
% period_len
)
433 num_periods
= buf_len
/ period_len
;
435 desc
= jz4740_dma_alloc_desc(num_periods
);
439 for (i
= 0; i
< num_periods
; i
++) {
440 desc
->sg
[i
].addr
= buf_addr
;
441 desc
->sg
[i
].len
= period_len
;
442 buf_addr
+= period_len
;
445 desc
->num_sgs
= num_periods
;
446 desc
->direction
= direction
;
449 jz4740_dma_slave_config_write(c
, &chan
->config
, direction
);
451 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
454 static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan
*chan
,
455 struct jz4740_dma_desc
*desc
, unsigned int next_sg
)
457 struct jz4740_dma_dev
*dmadev
= jz4740_dma_chan_get_dev(chan
);
458 unsigned int residue
, count
;
463 for (i
= next_sg
; i
< desc
->num_sgs
; i
++)
464 residue
+= desc
->sg
[i
].len
;
467 count
= jz4740_dma_read(dmadev
,
468 JZ_REG_DMA_TRANSFER_COUNT(chan
->id
));
469 residue
+= count
<< chan
->transfer_shift
;
475 static enum dma_status
jz4740_dma_tx_status(struct dma_chan
*c
,
476 dma_cookie_t cookie
, struct dma_tx_state
*state
)
478 struct jz4740_dmaengine_chan
*chan
= to_jz4740_dma_chan(c
);
479 struct virt_dma_desc
*vdesc
;
480 enum dma_status status
;
483 status
= dma_cookie_status(c
, cookie
, state
);
484 if (status
== DMA_COMPLETE
|| !state
)
487 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
488 vdesc
= vchan_find_desc(&chan
->vchan
, cookie
);
489 if (cookie
== chan
->desc
->vdesc
.tx
.cookie
) {
490 state
->residue
= jz4740_dma_desc_residue(chan
, chan
->desc
,
493 state
->residue
= jz4740_dma_desc_residue(chan
,
494 to_jz4740_dma_desc(vdesc
), 0);
498 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
503 static void jz4740_dma_free_chan_resources(struct dma_chan
*c
)
505 vchan_free_chan_resources(to_virt_chan(c
));
508 static void jz4740_dma_desc_free(struct virt_dma_desc
*vdesc
)
510 kfree(container_of(vdesc
, struct jz4740_dma_desc
, vdesc
));
513 #define JZ4740_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
514 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
516 static int jz4740_dma_probe(struct platform_device
*pdev
)
518 struct jz4740_dmaengine_chan
*chan
;
519 struct jz4740_dma_dev
*dmadev
;
520 struct dma_device
*dd
;
522 struct resource
*res
;
526 dmadev
= devm_kzalloc(&pdev
->dev
, sizeof(*dmadev
), GFP_KERNEL
);
532 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
533 dmadev
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
534 if (IS_ERR(dmadev
->base
))
535 return PTR_ERR(dmadev
->base
);
537 dmadev
->clk
= clk_get(&pdev
->dev
, "dma");
538 if (IS_ERR(dmadev
->clk
))
539 return PTR_ERR(dmadev
->clk
);
541 clk_prepare_enable(dmadev
->clk
);
543 dma_cap_set(DMA_SLAVE
, dd
->cap_mask
);
544 dma_cap_set(DMA_CYCLIC
, dd
->cap_mask
);
545 dd
->device_free_chan_resources
= jz4740_dma_free_chan_resources
;
546 dd
->device_tx_status
= jz4740_dma_tx_status
;
547 dd
->device_issue_pending
= jz4740_dma_issue_pending
;
548 dd
->device_prep_slave_sg
= jz4740_dma_prep_slave_sg
;
549 dd
->device_prep_dma_cyclic
= jz4740_dma_prep_dma_cyclic
;
550 dd
->device_config
= jz4740_dma_slave_config
;
551 dd
->device_terminate_all
= jz4740_dma_terminate_all
;
552 dd
->src_addr_widths
= JZ4740_DMA_BUSWIDTHS
;
553 dd
->dst_addr_widths
= JZ4740_DMA_BUSWIDTHS
;
554 dd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
555 dd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
556 dd
->dev
= &pdev
->dev
;
557 INIT_LIST_HEAD(&dd
->channels
);
559 for (i
= 0; i
< JZ_DMA_NR_CHANS
; i
++) {
560 chan
= &dmadev
->chan
[i
];
562 chan
->vchan
.desc_free
= jz4740_dma_desc_free
;
563 vchan_init(&chan
->vchan
, dd
);
566 ret
= dma_async_device_register(dd
);
570 irq
= platform_get_irq(pdev
, 0);
571 ret
= request_irq(irq
, jz4740_dma_irq
, 0, dev_name(&pdev
->dev
), dmadev
);
575 platform_set_drvdata(pdev
, dmadev
);
580 dma_async_device_unregister(dd
);
582 clk_disable_unprepare(dmadev
->clk
);
586 static void jz4740_cleanup_vchan(struct dma_device
*dmadev
)
588 struct jz4740_dmaengine_chan
*chan
, *_chan
;
590 list_for_each_entry_safe(chan
, _chan
,
591 &dmadev
->channels
, vchan
.chan
.device_node
) {
592 list_del(&chan
->vchan
.chan
.device_node
);
593 tasklet_kill(&chan
->vchan
.task
);
598 static int jz4740_dma_remove(struct platform_device
*pdev
)
600 struct jz4740_dma_dev
*dmadev
= platform_get_drvdata(pdev
);
601 int irq
= platform_get_irq(pdev
, 0);
603 free_irq(irq
, dmadev
);
605 jz4740_cleanup_vchan(&dmadev
->ddev
);
606 dma_async_device_unregister(&dmadev
->ddev
);
607 clk_disable_unprepare(dmadev
->clk
);
612 static struct platform_driver jz4740_dma_driver
= {
613 .probe
= jz4740_dma_probe
,
614 .remove
= jz4740_dma_remove
,
616 .name
= "jz4740-dma",
619 module_platform_driver(jz4740_dma_driver
);
621 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
622 MODULE_DESCRIPTION("JZ4740 DMA driver");
623 MODULE_LICENSE("GPL v2");