1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 DMA controller
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Alex Smith <alex@alex-smith.me.uk>
10 #include <linux/dmapool.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/of_dma.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #include "dmaengine.h"
23 /* Global registers. */
24 #define JZ_DMA_REG_DMAC 0x00
25 #define JZ_DMA_REG_DIRQP 0x04
26 #define JZ_DMA_REG_DDR 0x08
27 #define JZ_DMA_REG_DDRS 0x0c
28 #define JZ_DMA_REG_DCKE 0x10
29 #define JZ_DMA_REG_DCKES 0x14
30 #define JZ_DMA_REG_DCKEC 0x18
31 #define JZ_DMA_REG_DMACP 0x1c
32 #define JZ_DMA_REG_DSIRQP 0x20
33 #define JZ_DMA_REG_DSIRQM 0x24
34 #define JZ_DMA_REG_DCIRQP 0x28
35 #define JZ_DMA_REG_DCIRQM 0x2c
37 /* Per-channel registers. */
38 #define JZ_DMA_REG_CHAN(n) (n * 0x20)
39 #define JZ_DMA_REG_DSA 0x00
40 #define JZ_DMA_REG_DTA 0x04
41 #define JZ_DMA_REG_DTC 0x08
42 #define JZ_DMA_REG_DRT 0x0c
43 #define JZ_DMA_REG_DCS 0x10
44 #define JZ_DMA_REG_DCM 0x14
45 #define JZ_DMA_REG_DDA 0x18
46 #define JZ_DMA_REG_DSD 0x1c
48 #define JZ_DMA_DMAC_DMAE BIT(0)
49 #define JZ_DMA_DMAC_AR BIT(2)
50 #define JZ_DMA_DMAC_HLT BIT(3)
51 #define JZ_DMA_DMAC_FAIC BIT(27)
52 #define JZ_DMA_DMAC_FMSC BIT(31)
54 #define JZ_DMA_DRT_AUTO 0x8
56 #define JZ_DMA_DCS_CTE BIT(0)
57 #define JZ_DMA_DCS_HLT BIT(2)
58 #define JZ_DMA_DCS_TT BIT(3)
59 #define JZ_DMA_DCS_AR BIT(4)
60 #define JZ_DMA_DCS_DES8 BIT(30)
62 #define JZ_DMA_DCM_LINK BIT(0)
63 #define JZ_DMA_DCM_TIE BIT(1)
64 #define JZ_DMA_DCM_STDE BIT(2)
65 #define JZ_DMA_DCM_TSZ_SHIFT 8
66 #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
67 #define JZ_DMA_DCM_DP_SHIFT 12
68 #define JZ_DMA_DCM_SP_SHIFT 14
69 #define JZ_DMA_DCM_DAI BIT(22)
70 #define JZ_DMA_DCM_SAI BIT(23)
72 #define JZ_DMA_SIZE_4_BYTE 0x0
73 #define JZ_DMA_SIZE_1_BYTE 0x1
74 #define JZ_DMA_SIZE_2_BYTE 0x2
75 #define JZ_DMA_SIZE_16_BYTE 0x3
76 #define JZ_DMA_SIZE_32_BYTE 0x4
77 #define JZ_DMA_SIZE_64_BYTE 0x5
78 #define JZ_DMA_SIZE_128_BYTE 0x6
80 #define JZ_DMA_WIDTH_32_BIT 0x0
81 #define JZ_DMA_WIDTH_8_BIT 0x1
82 #define JZ_DMA_WIDTH_16_BIT 0x2
84 #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
85 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
86 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
88 #define JZ4780_DMA_CTRL_OFFSET 0x1000
90 /* macros for use with jz4780_dma_soc_data.flags */
91 #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0)
92 #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1)
93 #define JZ_SOC_DATA_PER_CHAN_PM BIT(2)
94 #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3)
97 * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
98 * @dcm: value for the DCM (channel command) register
99 * @dsa: source address
100 * @dta: target address
101 * @dtc: transfer count (number of blocks of the transfer size specified in DCM
102 * to transfer) in the low 24 bits, offset of the next descriptor from the
103 * descriptor base address in the upper 8 bits.
105 struct jz4780_dma_hwdesc
{
112 /* Size of allocations for hardware descriptor blocks. */
113 #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE
114 #define JZ_DMA_MAX_DESC \
115 (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
117 struct jz4780_dma_desc
{
118 struct virt_dma_desc vdesc
;
120 struct jz4780_dma_hwdesc
*desc
;
121 dma_addr_t desc_phys
;
123 enum dma_transaction_type type
;
127 struct jz4780_dma_chan
{
128 struct virt_dma_chan vchan
;
130 struct dma_pool
*desc_pool
;
132 uint32_t transfer_type
;
133 uint32_t transfer_shift
;
134 struct dma_slave_config config
;
136 struct jz4780_dma_desc
*desc
;
137 unsigned int curr_hwdesc
;
140 struct jz4780_dma_soc_data
{
141 unsigned int nb_channels
;
142 unsigned int transfer_ord_max
;
146 struct jz4780_dma_dev
{
147 struct dma_device dma_device
;
148 void __iomem
*chn_base
;
149 void __iomem
*ctrl_base
;
152 const struct jz4780_dma_soc_data
*soc_data
;
154 uint32_t chan_reserved
;
155 struct jz4780_dma_chan chan
[];
158 struct jz4780_dma_filter_data
{
159 struct device_node
*of_node
;
160 uint32_t transfer_type
;
164 static inline struct jz4780_dma_chan
*to_jz4780_dma_chan(struct dma_chan
*chan
)
166 return container_of(chan
, struct jz4780_dma_chan
, vchan
.chan
);
169 static inline struct jz4780_dma_desc
*to_jz4780_dma_desc(
170 struct virt_dma_desc
*vdesc
)
172 return container_of(vdesc
, struct jz4780_dma_desc
, vdesc
);
175 static inline struct jz4780_dma_dev
*jz4780_dma_chan_parent(
176 struct jz4780_dma_chan
*jzchan
)
178 return container_of(jzchan
->vchan
.chan
.device
, struct jz4780_dma_dev
,
182 static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev
*jzdma
,
183 unsigned int chn
, unsigned int reg
)
185 return readl(jzdma
->chn_base
+ reg
+ JZ_DMA_REG_CHAN(chn
));
188 static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev
*jzdma
,
189 unsigned int chn
, unsigned int reg
, uint32_t val
)
191 writel(val
, jzdma
->chn_base
+ reg
+ JZ_DMA_REG_CHAN(chn
));
194 static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev
*jzdma
,
197 return readl(jzdma
->ctrl_base
+ reg
);
200 static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev
*jzdma
,
201 unsigned int reg
, uint32_t val
)
203 writel(val
, jzdma
->ctrl_base
+ reg
);
206 static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev
*jzdma
,
209 if (jzdma
->soc_data
->flags
& JZ_SOC_DATA_PER_CHAN_PM
) {
212 if (jzdma
->soc_data
->flags
& JZ_SOC_DATA_NO_DCKES_DCKEC
)
213 reg
= JZ_DMA_REG_DCKE
;
215 reg
= JZ_DMA_REG_DCKES
;
217 jz4780_dma_ctrl_writel(jzdma
, reg
, BIT(chn
));
221 static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev
*jzdma
,
224 if ((jzdma
->soc_data
->flags
& JZ_SOC_DATA_PER_CHAN_PM
) &&
225 !(jzdma
->soc_data
->flags
& JZ_SOC_DATA_NO_DCKES_DCKEC
))
226 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DCKEC
, BIT(chn
));
229 static struct jz4780_dma_desc
*jz4780_dma_desc_alloc(
230 struct jz4780_dma_chan
*jzchan
, unsigned int count
,
231 enum dma_transaction_type type
)
233 struct jz4780_dma_desc
*desc
;
235 if (count
> JZ_DMA_MAX_DESC
)
238 desc
= kzalloc(sizeof(*desc
), GFP_NOWAIT
);
242 desc
->desc
= dma_pool_alloc(jzchan
->desc_pool
, GFP_NOWAIT
,
254 static void jz4780_dma_desc_free(struct virt_dma_desc
*vdesc
)
256 struct jz4780_dma_desc
*desc
= to_jz4780_dma_desc(vdesc
);
257 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(vdesc
->tx
.chan
);
259 dma_pool_free(jzchan
->desc_pool
, desc
->desc
, desc
->desc_phys
);
263 static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan
*jzchan
,
264 unsigned long val
, uint32_t *shift
)
266 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
267 int ord
= ffs(val
) - 1;
270 * 8 byte transfer sizes unsupported so fall back on 4. If it's larger
271 * than the maximum, just limit it. It is perfectly safe to fall back
272 * in this way since we won't exceed the maximum burst size supported
273 * by the device, the only effect is reduced efficiency. This is better
274 * than refusing to perform the request at all.
278 else if (ord
> jzdma
->soc_data
->transfer_ord_max
)
279 ord
= jzdma
->soc_data
->transfer_ord_max
;
285 return JZ_DMA_SIZE_1_BYTE
;
287 return JZ_DMA_SIZE_2_BYTE
;
289 return JZ_DMA_SIZE_4_BYTE
;
291 return JZ_DMA_SIZE_16_BYTE
;
293 return JZ_DMA_SIZE_32_BYTE
;
295 return JZ_DMA_SIZE_64_BYTE
;
297 return JZ_DMA_SIZE_128_BYTE
;
301 static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan
*jzchan
,
302 struct jz4780_dma_hwdesc
*desc
, dma_addr_t addr
, size_t len
,
303 enum dma_transfer_direction direction
)
305 struct dma_slave_config
*config
= &jzchan
->config
;
306 uint32_t width
, maxburst
, tsz
;
308 if (direction
== DMA_MEM_TO_DEV
) {
309 desc
->dcm
= JZ_DMA_DCM_SAI
;
311 desc
->dta
= config
->dst_addr
;
313 width
= config
->dst_addr_width
;
314 maxburst
= config
->dst_maxburst
;
316 desc
->dcm
= JZ_DMA_DCM_DAI
;
317 desc
->dsa
= config
->src_addr
;
320 width
= config
->src_addr_width
;
321 maxburst
= config
->src_maxburst
;
325 * This calculates the maximum transfer size that can be used with the
326 * given address, length, width and maximum burst size. The address
327 * must be aligned to the transfer size, the total length must be
328 * divisible by the transfer size, and we must not use more than the
329 * maximum burst specified by the user.
331 tsz
= jz4780_dma_transfer_size(jzchan
, addr
| len
| (width
* maxburst
),
332 &jzchan
->transfer_shift
);
335 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
336 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
338 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
339 width
= JZ_DMA_WIDTH_32_BIT
;
345 desc
->dcm
|= tsz
<< JZ_DMA_DCM_TSZ_SHIFT
;
346 desc
->dcm
|= width
<< JZ_DMA_DCM_SP_SHIFT
;
347 desc
->dcm
|= width
<< JZ_DMA_DCM_DP_SHIFT
;
349 desc
->dtc
= len
>> jzchan
->transfer_shift
;
353 static struct dma_async_tx_descriptor
*jz4780_dma_prep_slave_sg(
354 struct dma_chan
*chan
, struct scatterlist
*sgl
, unsigned int sg_len
,
355 enum dma_transfer_direction direction
, unsigned long flags
,
358 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
359 struct jz4780_dma_desc
*desc
;
363 desc
= jz4780_dma_desc_alloc(jzchan
, sg_len
, DMA_SLAVE
);
367 for (i
= 0; i
< sg_len
; i
++) {
368 err
= jz4780_dma_setup_hwdesc(jzchan
, &desc
->desc
[i
],
369 sg_dma_address(&sgl
[i
]),
373 jz4780_dma_desc_free(&jzchan
->desc
->vdesc
);
377 desc
->desc
[i
].dcm
|= JZ_DMA_DCM_TIE
;
379 if (i
!= (sg_len
- 1)) {
380 /* Automatically proceeed to the next descriptor. */
381 desc
->desc
[i
].dcm
|= JZ_DMA_DCM_LINK
;
384 * The upper 8 bits of the DTC field in the descriptor
385 * must be set to (offset from descriptor base of next
389 (((i
+ 1) * sizeof(*desc
->desc
)) >> 4) << 24;
393 return vchan_tx_prep(&jzchan
->vchan
, &desc
->vdesc
, flags
);
396 static struct dma_async_tx_descriptor
*jz4780_dma_prep_dma_cyclic(
397 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
398 size_t period_len
, enum dma_transfer_direction direction
,
401 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
402 struct jz4780_dma_desc
*desc
;
403 unsigned int periods
, i
;
406 if (buf_len
% period_len
)
409 periods
= buf_len
/ period_len
;
411 desc
= jz4780_dma_desc_alloc(jzchan
, periods
, DMA_CYCLIC
);
415 for (i
= 0; i
< periods
; i
++) {
416 err
= jz4780_dma_setup_hwdesc(jzchan
, &desc
->desc
[i
], buf_addr
,
417 period_len
, direction
);
419 jz4780_dma_desc_free(&jzchan
->desc
->vdesc
);
423 buf_addr
+= period_len
;
426 * Set the link bit to indicate that the controller should
427 * automatically proceed to the next descriptor. In
428 * jz4780_dma_begin(), this will be cleared if we need to issue
429 * an interrupt after each period.
431 desc
->desc
[i
].dcm
|= JZ_DMA_DCM_TIE
| JZ_DMA_DCM_LINK
;
434 * The upper 8 bits of the DTC field in the descriptor must be
435 * set to (offset from descriptor base of next descriptor >> 4).
436 * If this is the last descriptor, link it back to the first,
437 * i.e. leave offset set to 0, otherwise point to the next one.
439 if (i
!= (periods
- 1)) {
441 (((i
+ 1) * sizeof(*desc
->desc
)) >> 4) << 24;
445 return vchan_tx_prep(&jzchan
->vchan
, &desc
->vdesc
, flags
);
448 static struct dma_async_tx_descriptor
*jz4780_dma_prep_dma_memcpy(
449 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
450 size_t len
, unsigned long flags
)
452 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
453 struct jz4780_dma_desc
*desc
;
456 desc
= jz4780_dma_desc_alloc(jzchan
, 1, DMA_MEMCPY
);
460 tsz
= jz4780_dma_transfer_size(jzchan
, dest
| src
| len
,
461 &jzchan
->transfer_shift
);
463 jzchan
->transfer_type
= JZ_DMA_DRT_AUTO
;
465 desc
->desc
[0].dsa
= src
;
466 desc
->desc
[0].dta
= dest
;
467 desc
->desc
[0].dcm
= JZ_DMA_DCM_TIE
| JZ_DMA_DCM_SAI
| JZ_DMA_DCM_DAI
|
468 tsz
<< JZ_DMA_DCM_TSZ_SHIFT
|
469 JZ_DMA_WIDTH_32_BIT
<< JZ_DMA_DCM_SP_SHIFT
|
470 JZ_DMA_WIDTH_32_BIT
<< JZ_DMA_DCM_DP_SHIFT
;
471 desc
->desc
[0].dtc
= len
>> jzchan
->transfer_shift
;
473 return vchan_tx_prep(&jzchan
->vchan
, &desc
->vdesc
, flags
);
476 static void jz4780_dma_begin(struct jz4780_dma_chan
*jzchan
)
478 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
479 struct virt_dma_desc
*vdesc
;
481 dma_addr_t desc_phys
;
484 vdesc
= vchan_next_desc(&jzchan
->vchan
);
488 list_del(&vdesc
->node
);
490 jzchan
->desc
= to_jz4780_dma_desc(vdesc
);
491 jzchan
->curr_hwdesc
= 0;
493 if (jzchan
->desc
->type
== DMA_CYCLIC
&& vdesc
->tx
.callback
) {
495 * The DMA controller doesn't support triggering an
496 * interrupt after processing each descriptor, only
497 * after processing an entire terminated list of
498 * descriptors. For a cyclic DMA setup the list of
499 * descriptors is not terminated so we can never get an
502 * If the user requested a callback for a cyclic DMA
503 * setup then we workaround this hardware limitation
504 * here by degrading to a set of unlinked descriptors
505 * which we will submit in sequence in response to the
506 * completion of processing the previous descriptor.
508 for (i
= 0; i
< jzchan
->desc
->count
; i
++)
509 jzchan
->desc
->desc
[i
].dcm
&= ~JZ_DMA_DCM_LINK
;
513 * There is an existing transfer, therefore this must be one
514 * for which we unlinked the descriptors above. Advance to the
515 * next one in the list.
517 jzchan
->curr_hwdesc
=
518 (jzchan
->curr_hwdesc
+ 1) % jzchan
->desc
->count
;
521 /* Enable the channel's clock. */
522 jz4780_dma_chan_enable(jzdma
, jzchan
->id
);
524 /* Use 4-word descriptors. */
525 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DCS
, 0);
527 /* Set transfer type. */
528 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DRT
,
529 jzchan
->transfer_type
);
532 * Set the transfer count. This is redundant for a descriptor-driven
533 * transfer. However, there can be a delay between the transfer start
534 * time and when DTCn reg contains the new transfer count. Setting
535 * it explicitly ensures residue is computed correctly at all times.
537 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DTC
,
538 jzchan
->desc
->desc
[jzchan
->curr_hwdesc
].dtc
);
540 /* Write descriptor address and initiate descriptor fetch. */
541 desc_phys
= jzchan
->desc
->desc_phys
+
542 (jzchan
->curr_hwdesc
* sizeof(*jzchan
->desc
->desc
));
543 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DDA
, desc_phys
);
544 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DDRS
, BIT(jzchan
->id
));
546 /* Enable the channel. */
547 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DCS
,
551 static void jz4780_dma_issue_pending(struct dma_chan
*chan
)
553 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
556 spin_lock_irqsave(&jzchan
->vchan
.lock
, flags
);
558 if (vchan_issue_pending(&jzchan
->vchan
) && !jzchan
->desc
)
559 jz4780_dma_begin(jzchan
);
561 spin_unlock_irqrestore(&jzchan
->vchan
.lock
, flags
);
564 static int jz4780_dma_terminate_all(struct dma_chan
*chan
)
566 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
567 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
571 spin_lock_irqsave(&jzchan
->vchan
.lock
, flags
);
573 /* Clear the DMA status and stop the transfer. */
574 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DCS
, 0);
576 vchan_terminate_vdesc(&jzchan
->desc
->vdesc
);
580 jz4780_dma_chan_disable(jzdma
, jzchan
->id
);
582 vchan_get_all_descriptors(&jzchan
->vchan
, &head
);
584 spin_unlock_irqrestore(&jzchan
->vchan
.lock
, flags
);
586 vchan_dma_desc_free_list(&jzchan
->vchan
, &head
);
590 static void jz4780_dma_synchronize(struct dma_chan
*chan
)
592 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
593 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
595 vchan_synchronize(&jzchan
->vchan
);
596 jz4780_dma_chan_disable(jzdma
, jzchan
->id
);
599 static int jz4780_dma_config(struct dma_chan
*chan
,
600 struct dma_slave_config
*config
)
602 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
604 if ((config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
605 || (config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
))
608 /* Copy the reset of the slave configuration, it is used later. */
609 memcpy(&jzchan
->config
, config
, sizeof(jzchan
->config
));
614 static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan
*jzchan
,
615 struct jz4780_dma_desc
*desc
, unsigned int next_sg
)
617 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
618 unsigned int count
= 0;
621 for (i
= next_sg
; i
< desc
->count
; i
++)
622 count
+= desc
->desc
[i
].dtc
& GENMASK(23, 0);
625 count
+= jz4780_dma_chn_readl(jzdma
, jzchan
->id
,
628 return count
<< jzchan
->transfer_shift
;
631 static enum dma_status
jz4780_dma_tx_status(struct dma_chan
*chan
,
632 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
634 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
635 struct virt_dma_desc
*vdesc
;
636 enum dma_status status
;
638 unsigned long residue
= 0;
640 status
= dma_cookie_status(chan
, cookie
, txstate
);
641 if ((status
== DMA_COMPLETE
) || (txstate
== NULL
))
644 spin_lock_irqsave(&jzchan
->vchan
.lock
, flags
);
646 vdesc
= vchan_find_desc(&jzchan
->vchan
, cookie
);
648 /* On the issued list, so hasn't been processed yet */
649 residue
= jz4780_dma_desc_residue(jzchan
,
650 to_jz4780_dma_desc(vdesc
), 0);
651 } else if (cookie
== jzchan
->desc
->vdesc
.tx
.cookie
) {
652 residue
= jz4780_dma_desc_residue(jzchan
, jzchan
->desc
,
653 jzchan
->curr_hwdesc
+ 1);
655 dma_set_residue(txstate
, residue
);
657 if (vdesc
&& jzchan
->desc
&& vdesc
== &jzchan
->desc
->vdesc
658 && jzchan
->desc
->status
& (JZ_DMA_DCS_AR
| JZ_DMA_DCS_HLT
))
661 spin_unlock_irqrestore(&jzchan
->vchan
.lock
, flags
);
665 static void jz4780_dma_chan_irq(struct jz4780_dma_dev
*jzdma
,
666 struct jz4780_dma_chan
*jzchan
)
670 spin_lock(&jzchan
->vchan
.lock
);
672 dcs
= jz4780_dma_chn_readl(jzdma
, jzchan
->id
, JZ_DMA_REG_DCS
);
673 jz4780_dma_chn_writel(jzdma
, jzchan
->id
, JZ_DMA_REG_DCS
, 0);
675 if (dcs
& JZ_DMA_DCS_AR
) {
676 dev_warn(&jzchan
->vchan
.chan
.dev
->device
,
677 "address error (DCS=0x%x)\n", dcs
);
680 if (dcs
& JZ_DMA_DCS_HLT
) {
681 dev_warn(&jzchan
->vchan
.chan
.dev
->device
,
682 "channel halt (DCS=0x%x)\n", dcs
);
686 jzchan
->desc
->status
= dcs
;
688 if ((dcs
& (JZ_DMA_DCS_AR
| JZ_DMA_DCS_HLT
)) == 0) {
689 if (jzchan
->desc
->type
== DMA_CYCLIC
) {
690 vchan_cyclic_callback(&jzchan
->desc
->vdesc
);
692 vchan_cookie_complete(&jzchan
->desc
->vdesc
);
696 jz4780_dma_begin(jzchan
);
699 dev_err(&jzchan
->vchan
.chan
.dev
->device
,
700 "channel IRQ with no active transfer\n");
703 spin_unlock(&jzchan
->vchan
.lock
);
706 static irqreturn_t
jz4780_dma_irq_handler(int irq
, void *data
)
708 struct jz4780_dma_dev
*jzdma
= data
;
709 uint32_t pending
, dmac
;
712 pending
= jz4780_dma_ctrl_readl(jzdma
, JZ_DMA_REG_DIRQP
);
714 for (i
= 0; i
< jzdma
->soc_data
->nb_channels
; i
++) {
715 if (!(pending
& (1<<i
)))
718 jz4780_dma_chan_irq(jzdma
, &jzdma
->chan
[i
]);
721 /* Clear halt and address error status of all channels. */
722 dmac
= jz4780_dma_ctrl_readl(jzdma
, JZ_DMA_REG_DMAC
);
723 dmac
&= ~(JZ_DMA_DMAC_HLT
| JZ_DMA_DMAC_AR
);
724 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DMAC
, dmac
);
726 /* Clear interrupt pending status. */
727 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DIRQP
, 0);
732 static int jz4780_dma_alloc_chan_resources(struct dma_chan
*chan
)
734 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
736 jzchan
->desc_pool
= dma_pool_create(dev_name(&chan
->dev
->device
),
738 JZ_DMA_DESC_BLOCK_SIZE
,
740 if (!jzchan
->desc_pool
) {
741 dev_err(&chan
->dev
->device
,
742 "failed to allocate descriptor pool\n");
749 static void jz4780_dma_free_chan_resources(struct dma_chan
*chan
)
751 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
753 vchan_free_chan_resources(&jzchan
->vchan
);
754 dma_pool_destroy(jzchan
->desc_pool
);
755 jzchan
->desc_pool
= NULL
;
758 static bool jz4780_dma_filter_fn(struct dma_chan
*chan
, void *param
)
760 struct jz4780_dma_chan
*jzchan
= to_jz4780_dma_chan(chan
);
761 struct jz4780_dma_dev
*jzdma
= jz4780_dma_chan_parent(jzchan
);
762 struct jz4780_dma_filter_data
*data
= param
;
764 if (jzdma
->dma_device
.dev
->of_node
!= data
->of_node
)
767 if (data
->channel
> -1) {
768 if (data
->channel
!= jzchan
->id
)
770 } else if (jzdma
->chan_reserved
& BIT(jzchan
->id
)) {
774 jzchan
->transfer_type
= data
->transfer_type
;
779 static struct dma_chan
*jz4780_of_dma_xlate(struct of_phandle_args
*dma_spec
,
780 struct of_dma
*ofdma
)
782 struct jz4780_dma_dev
*jzdma
= ofdma
->of_dma_data
;
783 dma_cap_mask_t mask
= jzdma
->dma_device
.cap_mask
;
784 struct jz4780_dma_filter_data data
;
786 if (dma_spec
->args_count
!= 2)
789 data
.of_node
= ofdma
->of_node
;
790 data
.transfer_type
= dma_spec
->args
[0];
791 data
.channel
= dma_spec
->args
[1];
793 if (data
.channel
> -1) {
794 if (data
.channel
>= jzdma
->soc_data
->nb_channels
) {
795 dev_err(jzdma
->dma_device
.dev
,
796 "device requested non-existent channel %u\n",
801 /* Can only select a channel marked as reserved. */
802 if (!(jzdma
->chan_reserved
& BIT(data
.channel
))) {
803 dev_err(jzdma
->dma_device
.dev
,
804 "device requested unreserved channel %u\n",
809 jzdma
->chan
[data
.channel
].transfer_type
= data
.transfer_type
;
811 return dma_get_slave_channel(
812 &jzdma
->chan
[data
.channel
].vchan
.chan
);
814 return dma_request_channel(mask
, jz4780_dma_filter_fn
, &data
);
818 static int jz4780_dma_probe(struct platform_device
*pdev
)
820 struct device
*dev
= &pdev
->dev
;
821 const struct jz4780_dma_soc_data
*soc_data
;
822 struct jz4780_dma_dev
*jzdma
;
823 struct jz4780_dma_chan
*jzchan
;
824 struct dma_device
*dd
;
825 struct resource
*res
;
829 dev_err(dev
, "This driver must be probed from devicetree\n");
833 soc_data
= device_get_match_data(dev
);
837 jzdma
= devm_kzalloc(dev
, struct_size(jzdma
, chan
,
838 soc_data
->nb_channels
), GFP_KERNEL
);
842 jzdma
->soc_data
= soc_data
;
843 platform_set_drvdata(pdev
, jzdma
);
845 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
847 dev_err(dev
, "failed to get I/O memory\n");
851 jzdma
->chn_base
= devm_ioremap_resource(dev
, res
);
852 if (IS_ERR(jzdma
->chn_base
))
853 return PTR_ERR(jzdma
->chn_base
);
855 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
857 jzdma
->ctrl_base
= devm_ioremap_resource(dev
, res
);
858 if (IS_ERR(jzdma
->ctrl_base
))
859 return PTR_ERR(jzdma
->ctrl_base
);
860 } else if (soc_data
->flags
& JZ_SOC_DATA_ALLOW_LEGACY_DT
) {
862 * On JZ4780, if the second memory resource was not supplied,
863 * assume we're using an old devicetree, and calculate the
864 * offset to the control registers.
866 jzdma
->ctrl_base
= jzdma
->chn_base
+ JZ4780_DMA_CTRL_OFFSET
;
868 dev_err(dev
, "failed to get I/O memory\n");
872 ret
= platform_get_irq(pdev
, 0);
874 dev_err(dev
, "failed to get IRQ: %d\n", ret
);
880 ret
= request_irq(jzdma
->irq
, jz4780_dma_irq_handler
, 0, dev_name(dev
),
883 dev_err(dev
, "failed to request IRQ %u!\n", jzdma
->irq
);
887 jzdma
->clk
= devm_clk_get(dev
, NULL
);
888 if (IS_ERR(jzdma
->clk
)) {
889 dev_err(dev
, "failed to get clock\n");
890 ret
= PTR_ERR(jzdma
->clk
);
894 clk_prepare_enable(jzdma
->clk
);
896 /* Property is optional, if it doesn't exist the value will remain 0. */
897 of_property_read_u32_index(dev
->of_node
, "ingenic,reserved-channels",
898 0, &jzdma
->chan_reserved
);
900 dd
= &jzdma
->dma_device
;
902 dma_cap_set(DMA_MEMCPY
, dd
->cap_mask
);
903 dma_cap_set(DMA_SLAVE
, dd
->cap_mask
);
904 dma_cap_set(DMA_CYCLIC
, dd
->cap_mask
);
907 dd
->copy_align
= DMAENGINE_ALIGN_4_BYTES
;
908 dd
->device_alloc_chan_resources
= jz4780_dma_alloc_chan_resources
;
909 dd
->device_free_chan_resources
= jz4780_dma_free_chan_resources
;
910 dd
->device_prep_slave_sg
= jz4780_dma_prep_slave_sg
;
911 dd
->device_prep_dma_cyclic
= jz4780_dma_prep_dma_cyclic
;
912 dd
->device_prep_dma_memcpy
= jz4780_dma_prep_dma_memcpy
;
913 dd
->device_config
= jz4780_dma_config
;
914 dd
->device_terminate_all
= jz4780_dma_terminate_all
;
915 dd
->device_synchronize
= jz4780_dma_synchronize
;
916 dd
->device_tx_status
= jz4780_dma_tx_status
;
917 dd
->device_issue_pending
= jz4780_dma_issue_pending
;
918 dd
->src_addr_widths
= JZ_DMA_BUSWIDTHS
;
919 dd
->dst_addr_widths
= JZ_DMA_BUSWIDTHS
;
920 dd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
921 dd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
924 * Enable DMA controller, mark all channels as not programmable.
925 * Also set the FMSC bit - it increases MSC performance, so it makes
926 * little sense not to enable it.
928 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DMAC
, JZ_DMA_DMAC_DMAE
|
929 JZ_DMA_DMAC_FAIC
| JZ_DMA_DMAC_FMSC
);
931 if (soc_data
->flags
& JZ_SOC_DATA_PROGRAMMABLE_DMA
)
932 jz4780_dma_ctrl_writel(jzdma
, JZ_DMA_REG_DMACP
, 0);
934 INIT_LIST_HEAD(&dd
->channels
);
936 for (i
= 0; i
< soc_data
->nb_channels
; i
++) {
937 jzchan
= &jzdma
->chan
[i
];
940 vchan_init(&jzchan
->vchan
, dd
);
941 jzchan
->vchan
.desc_free
= jz4780_dma_desc_free
;
944 ret
= dmaenginem_async_device_register(dd
);
946 dev_err(dev
, "failed to register device\n");
947 goto err_disable_clk
;
950 /* Register with OF DMA helpers. */
951 ret
= of_dma_controller_register(dev
->of_node
, jz4780_of_dma_xlate
,
954 dev_err(dev
, "failed to register OF DMA controller\n");
955 goto err_disable_clk
;
958 dev_info(dev
, "JZ4780 DMA controller initialised\n");
962 clk_disable_unprepare(jzdma
->clk
);
965 free_irq(jzdma
->irq
, jzdma
);
969 static int jz4780_dma_remove(struct platform_device
*pdev
)
971 struct jz4780_dma_dev
*jzdma
= platform_get_drvdata(pdev
);
974 of_dma_controller_free(pdev
->dev
.of_node
);
976 free_irq(jzdma
->irq
, jzdma
);
978 for (i
= 0; i
< jzdma
->soc_data
->nb_channels
; i
++)
979 tasklet_kill(&jzdma
->chan
[i
].vchan
.task
);
984 static const struct jz4780_dma_soc_data jz4740_dma_soc_data
= {
986 .transfer_ord_max
= 5,
989 static const struct jz4780_dma_soc_data jz4725b_dma_soc_data
= {
991 .transfer_ord_max
= 5,
992 .flags
= JZ_SOC_DATA_PER_CHAN_PM
| JZ_SOC_DATA_NO_DCKES_DCKEC
,
995 static const struct jz4780_dma_soc_data jz4770_dma_soc_data
= {
997 .transfer_ord_max
= 6,
998 .flags
= JZ_SOC_DATA_PER_CHAN_PM
,
1001 static const struct jz4780_dma_soc_data jz4780_dma_soc_data
= {
1003 .transfer_ord_max
= 7,
1004 .flags
= JZ_SOC_DATA_ALLOW_LEGACY_DT
| JZ_SOC_DATA_PROGRAMMABLE_DMA
,
1007 static const struct of_device_id jz4780_dma_dt_match
[] = {
1008 { .compatible
= "ingenic,jz4740-dma", .data
= &jz4740_dma_soc_data
},
1009 { .compatible
= "ingenic,jz4725b-dma", .data
= &jz4725b_dma_soc_data
},
1010 { .compatible
= "ingenic,jz4770-dma", .data
= &jz4770_dma_soc_data
},
1011 { .compatible
= "ingenic,jz4780-dma", .data
= &jz4780_dma_soc_data
},
1014 MODULE_DEVICE_TABLE(of
, jz4780_dma_dt_match
);
1016 static struct platform_driver jz4780_dma_driver
= {
1017 .probe
= jz4780_dma_probe
,
1018 .remove
= jz4780_dma_remove
,
1020 .name
= "jz4780-dma",
1021 .of_match_table
= of_match_ptr(jz4780_dma_dt_match
),
1025 static int __init
jz4780_dma_init(void)
1027 return platform_driver_register(&jz4780_dma_driver
);
1029 subsys_initcall(jz4780_dma_init
);
1031 static void __exit
jz4780_dma_exit(void)
1033 platform_driver_unregister(&jz4780_dma_driver
);
1035 module_exit(jz4780_dma_exit
);
1037 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
1038 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
1039 MODULE_LICENSE("GPL");