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1 /*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/freezer.h>
17 #include <linux/init.h>
18 #include <linux/kthread.h>
19 #include <linux/sched/task.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/random.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25
26 static unsigned int test_buf_size = 16384;
27 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
28 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
29
30 static char test_channel[20];
31 module_param_string(channel, test_channel, sizeof(test_channel),
32 S_IRUGO | S_IWUSR);
33 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
34
35 static char test_device[32];
36 module_param_string(device, test_device, sizeof(test_device),
37 S_IRUGO | S_IWUSR);
38 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
39
40 static unsigned int threads_per_chan = 1;
41 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(threads_per_chan,
43 "Number of threads to start per channel (default: 1)");
44
45 static unsigned int max_channels;
46 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
47 MODULE_PARM_DESC(max_channels,
48 "Maximum number of channels to use (default: all)");
49
50 static unsigned int iterations;
51 module_param(iterations, uint, S_IRUGO | S_IWUSR);
52 MODULE_PARM_DESC(iterations,
53 "Iterations before stopping test (default: infinite)");
54
55 static unsigned int sg_buffers = 1;
56 module_param(sg_buffers, uint, S_IRUGO | S_IWUSR);
57 MODULE_PARM_DESC(sg_buffers,
58 "Number of scatter gather buffers (default: 1)");
59
60 static unsigned int dmatest;
61 module_param(dmatest, uint, S_IRUGO | S_IWUSR);
62 MODULE_PARM_DESC(dmatest,
63 "dmatest 0-memcpy 1-slave_sg (default: 0)");
64
65 static unsigned int xor_sources = 3;
66 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
67 MODULE_PARM_DESC(xor_sources,
68 "Number of xor source buffers (default: 3)");
69
70 static unsigned int pq_sources = 3;
71 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
72 MODULE_PARM_DESC(pq_sources,
73 "Number of p+q source buffers (default: 3)");
74
75 static int timeout = 3000;
76 module_param(timeout, uint, S_IRUGO | S_IWUSR);
77 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
78 "Pass -1 for infinite timeout");
79
80 static bool noverify;
81 module_param(noverify, bool, S_IRUGO | S_IWUSR);
82 MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
83
84 static bool verbose;
85 module_param(verbose, bool, S_IRUGO | S_IWUSR);
86 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
87
88 /**
89 * struct dmatest_params - test parameters.
90 * @buf_size: size of the memcpy test buffer
91 * @channel: bus ID of the channel to test
92 * @device: bus ID of the DMA Engine to test
93 * @threads_per_chan: number of threads to start per channel
94 * @max_channels: maximum number of channels to use
95 * @iterations: iterations before stopping test
96 * @xor_sources: number of xor source buffers
97 * @pq_sources: number of p+q source buffers
98 * @timeout: transfer timeout in msec, -1 for infinite timeout
99 */
100 struct dmatest_params {
101 unsigned int buf_size;
102 char channel[20];
103 char device[32];
104 unsigned int threads_per_chan;
105 unsigned int max_channels;
106 unsigned int iterations;
107 unsigned int xor_sources;
108 unsigned int pq_sources;
109 int timeout;
110 bool noverify;
111 };
112
113 /**
114 * struct dmatest_info - test information.
115 * @params: test parameters
116 * @lock: access protection to the fields of this structure
117 */
118 static struct dmatest_info {
119 /* Test parameters */
120 struct dmatest_params params;
121
122 /* Internal state */
123 struct list_head channels;
124 unsigned int nr_channels;
125 struct mutex lock;
126 bool did_init;
127 } test_info = {
128 .channels = LIST_HEAD_INIT(test_info.channels),
129 .lock = __MUTEX_INITIALIZER(test_info.lock),
130 };
131
132 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
133 static int dmatest_run_get(char *val, const struct kernel_param *kp);
134 static const struct kernel_param_ops run_ops = {
135 .set = dmatest_run_set,
136 .get = dmatest_run_get,
137 };
138 static bool dmatest_run;
139 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
140 MODULE_PARM_DESC(run, "Run the test (default: false)");
141
142 /* Maximum amount of mismatched bytes in buffer to print */
143 #define MAX_ERROR_COUNT 32
144
145 /*
146 * Initialization patterns. All bytes in the source buffer has bit 7
147 * set, all bytes in the destination buffer has bit 7 cleared.
148 *
149 * Bit 6 is set for all bytes which are to be copied by the DMA
150 * engine. Bit 5 is set for all bytes which are to be overwritten by
151 * the DMA engine.
152 *
153 * The remaining bits are the inverse of a counter which increments by
154 * one for each byte address.
155 */
156 #define PATTERN_SRC 0x80
157 #define PATTERN_DST 0x00
158 #define PATTERN_COPY 0x40
159 #define PATTERN_OVERWRITE 0x20
160 #define PATTERN_COUNT_MASK 0x1f
161
162 struct dmatest_thread {
163 struct list_head node;
164 struct dmatest_info *info;
165 struct task_struct *task;
166 struct dma_chan *chan;
167 u8 **srcs;
168 u8 **usrcs;
169 u8 **dsts;
170 u8 **udsts;
171 enum dma_transaction_type type;
172 bool done;
173 };
174
175 struct dmatest_chan {
176 struct list_head node;
177 struct dma_chan *chan;
178 struct list_head threads;
179 };
180
181 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
182 static bool wait;
183
184 static bool is_threaded_test_run(struct dmatest_info *info)
185 {
186 struct dmatest_chan *dtc;
187
188 list_for_each_entry(dtc, &info->channels, node) {
189 struct dmatest_thread *thread;
190
191 list_for_each_entry(thread, &dtc->threads, node) {
192 if (!thread->done)
193 return true;
194 }
195 }
196
197 return false;
198 }
199
200 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
201 {
202 struct dmatest_info *info = &test_info;
203 struct dmatest_params *params = &info->params;
204
205 if (params->iterations)
206 wait_event(thread_wait, !is_threaded_test_run(info));
207 wait = true;
208 return param_get_bool(val, kp);
209 }
210
211 static const struct kernel_param_ops wait_ops = {
212 .get = dmatest_wait_get,
213 .set = param_set_bool,
214 };
215 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
216 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
217
218 static bool dmatest_match_channel(struct dmatest_params *params,
219 struct dma_chan *chan)
220 {
221 if (params->channel[0] == '\0')
222 return true;
223 return strcmp(dma_chan_name(chan), params->channel) == 0;
224 }
225
226 static bool dmatest_match_device(struct dmatest_params *params,
227 struct dma_device *device)
228 {
229 if (params->device[0] == '\0')
230 return true;
231 return strcmp(dev_name(device->dev), params->device) == 0;
232 }
233
234 static unsigned long dmatest_random(void)
235 {
236 unsigned long buf;
237
238 prandom_bytes(&buf, sizeof(buf));
239 return buf;
240 }
241
242 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
243 unsigned int buf_size)
244 {
245 unsigned int i;
246 u8 *buf;
247
248 for (; (buf = *bufs); bufs++) {
249 for (i = 0; i < start; i++)
250 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
251 for ( ; i < start + len; i++)
252 buf[i] = PATTERN_SRC | PATTERN_COPY
253 | (~i & PATTERN_COUNT_MASK);
254 for ( ; i < buf_size; i++)
255 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
256 buf++;
257 }
258 }
259
260 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
261 unsigned int buf_size)
262 {
263 unsigned int i;
264 u8 *buf;
265
266 for (; (buf = *bufs); bufs++) {
267 for (i = 0; i < start; i++)
268 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
269 for ( ; i < start + len; i++)
270 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
271 | (~i & PATTERN_COUNT_MASK);
272 for ( ; i < buf_size; i++)
273 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
274 }
275 }
276
277 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
278 unsigned int counter, bool is_srcbuf)
279 {
280 u8 diff = actual ^ pattern;
281 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
282 const char *thread_name = current->comm;
283
284 if (is_srcbuf)
285 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
286 thread_name, index, expected, actual);
287 else if ((pattern & PATTERN_COPY)
288 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
289 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
290 thread_name, index, expected, actual);
291 else if (diff & PATTERN_SRC)
292 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
293 thread_name, index, expected, actual);
294 else
295 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
296 thread_name, index, expected, actual);
297 }
298
299 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
300 unsigned int end, unsigned int counter, u8 pattern,
301 bool is_srcbuf)
302 {
303 unsigned int i;
304 unsigned int error_count = 0;
305 u8 actual;
306 u8 expected;
307 u8 *buf;
308 unsigned int counter_orig = counter;
309
310 for (; (buf = *bufs); bufs++) {
311 counter = counter_orig;
312 for (i = start; i < end; i++) {
313 actual = buf[i];
314 expected = pattern | (~counter & PATTERN_COUNT_MASK);
315 if (actual != expected) {
316 if (error_count < MAX_ERROR_COUNT)
317 dmatest_mismatch(actual, pattern, i,
318 counter, is_srcbuf);
319 error_count++;
320 }
321 counter++;
322 }
323 }
324
325 if (error_count > MAX_ERROR_COUNT)
326 pr_warn("%s: %u errors suppressed\n",
327 current->comm, error_count - MAX_ERROR_COUNT);
328
329 return error_count;
330 }
331
332 /* poor man's completion - we want to use wait_event_freezable() on it */
333 struct dmatest_done {
334 bool done;
335 wait_queue_head_t *wait;
336 };
337
338 static void dmatest_callback(void *arg)
339 {
340 struct dmatest_done *done = arg;
341
342 done->done = true;
343 wake_up_all(done->wait);
344 }
345
346 static unsigned int min_odd(unsigned int x, unsigned int y)
347 {
348 unsigned int val = min(x, y);
349
350 return val % 2 ? val : val - 1;
351 }
352
353 static void result(const char *err, unsigned int n, unsigned int src_off,
354 unsigned int dst_off, unsigned int len, unsigned long data)
355 {
356 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
357 current->comm, n, err, src_off, dst_off, len, data);
358 }
359
360 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
361 unsigned int dst_off, unsigned int len,
362 unsigned long data)
363 {
364 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
365 current->comm, n, err, src_off, dst_off, len, data);
366 }
367
368 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \
369 if (verbose) \
370 result(err, n, src_off, dst_off, len, data); \
371 else \
372 dbg_result(err, n, src_off, dst_off, len, data);\
373 })
374
375 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
376 {
377 unsigned long long per_sec = 1000000;
378
379 if (runtime <= 0)
380 return 0;
381
382 /* drop precision until runtime is 32-bits */
383 while (runtime > UINT_MAX) {
384 runtime >>= 1;
385 per_sec <<= 1;
386 }
387
388 per_sec *= val;
389 do_div(per_sec, runtime);
390 return per_sec;
391 }
392
393 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
394 {
395 return dmatest_persec(runtime, len >> 10);
396 }
397
398 /*
399 * This function repeatedly tests DMA transfers of various lengths and
400 * offsets for a given operation type until it is told to exit by
401 * kthread_stop(). There may be multiple threads running this function
402 * in parallel for a single channel, and there may be multiple channels
403 * being tested in parallel.
404 *
405 * Before each test, the source and destination buffer is initialized
406 * with a known pattern. This pattern is different depending on
407 * whether it's in an area which is supposed to be copied or
408 * overwritten, and different in the source and destination buffers.
409 * So if the DMA engine doesn't copy exactly what we tell it to copy,
410 * we'll notice.
411 */
412 static int dmatest_func(void *data)
413 {
414 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
415 struct dmatest_thread *thread = data;
416 struct dmatest_done done = { .wait = &done_wait };
417 struct dmatest_info *info;
418 struct dmatest_params *params;
419 struct dma_chan *chan;
420 struct dma_device *dev;
421 unsigned int error_count;
422 unsigned int failed_tests = 0;
423 unsigned int total_tests = 0;
424 dma_cookie_t cookie;
425 enum dma_status status;
426 enum dma_ctrl_flags flags;
427 u8 *pq_coefs = NULL;
428 int ret;
429 int src_cnt;
430 int dst_cnt;
431 int i;
432 ktime_t ktime, start, diff;
433 ktime_t filltime = 0;
434 ktime_t comparetime = 0;
435 s64 runtime = 0;
436 unsigned long long total_len = 0;
437 u8 align = 0;
438
439 set_freezable();
440
441 ret = -ENOMEM;
442
443 smp_rmb();
444 info = thread->info;
445 params = &info->params;
446 chan = thread->chan;
447 dev = chan->device;
448 if (thread->type == DMA_MEMCPY) {
449 align = dev->copy_align;
450 src_cnt = dst_cnt = 1;
451 } else if (thread->type == DMA_SG) {
452 align = dev->copy_align;
453 src_cnt = dst_cnt = sg_buffers;
454 } else if (thread->type == DMA_XOR) {
455 /* force odd to ensure dst = src */
456 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
457 dst_cnt = 1;
458 align = dev->xor_align;
459 } else if (thread->type == DMA_PQ) {
460 /* force odd to ensure dst = src */
461 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
462 dst_cnt = 2;
463 align = dev->pq_align;
464
465 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
466 if (!pq_coefs)
467 goto err_thread_type;
468
469 for (i = 0; i < src_cnt; i++)
470 pq_coefs[i] = 1;
471 } else
472 goto err_thread_type;
473
474 thread->srcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
475 if (!thread->srcs)
476 goto err_srcs;
477
478 thread->usrcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
479 if (!thread->usrcs)
480 goto err_usrcs;
481
482 for (i = 0; i < src_cnt; i++) {
483 thread->usrcs[i] = kmalloc(params->buf_size + align,
484 GFP_KERNEL);
485 if (!thread->usrcs[i])
486 goto err_srcbuf;
487
488 /* align srcs to alignment restriction */
489 if (align)
490 thread->srcs[i] = PTR_ALIGN(thread->usrcs[i], align);
491 else
492 thread->srcs[i] = thread->usrcs[i];
493 }
494 thread->srcs[i] = NULL;
495
496 thread->dsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
497 if (!thread->dsts)
498 goto err_dsts;
499
500 thread->udsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
501 if (!thread->udsts)
502 goto err_udsts;
503
504 for (i = 0; i < dst_cnt; i++) {
505 thread->udsts[i] = kmalloc(params->buf_size + align,
506 GFP_KERNEL);
507 if (!thread->udsts[i])
508 goto err_dstbuf;
509
510 /* align dsts to alignment restriction */
511 if (align)
512 thread->dsts[i] = PTR_ALIGN(thread->udsts[i], align);
513 else
514 thread->dsts[i] = thread->udsts[i];
515 }
516 thread->dsts[i] = NULL;
517
518 set_user_nice(current, 10);
519
520 /*
521 * src and dst buffers are freed by ourselves below
522 */
523 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
524
525 ktime = ktime_get();
526 while (!kthread_should_stop()
527 && !(params->iterations && total_tests >= params->iterations)) {
528 struct dma_async_tx_descriptor *tx = NULL;
529 struct dmaengine_unmap_data *um;
530 dma_addr_t srcs[src_cnt];
531 dma_addr_t *dsts;
532 unsigned int src_off, dst_off, len;
533 struct scatterlist tx_sg[src_cnt];
534 struct scatterlist rx_sg[src_cnt];
535
536 total_tests++;
537
538 if (1 << align > params->buf_size) {
539 pr_err("%u-byte buffer too small for %d-byte alignment\n",
540 params->buf_size, 1 << align);
541 break;
542 }
543
544 if (params->noverify)
545 len = params->buf_size;
546 else
547 len = dmatest_random() % params->buf_size + 1;
548
549 len = (len >> align) << align;
550 if (!len)
551 len = 1 << align;
552
553 total_len += len;
554
555 if (params->noverify) {
556 src_off = 0;
557 dst_off = 0;
558 } else {
559 start = ktime_get();
560 src_off = dmatest_random() % (params->buf_size - len + 1);
561 dst_off = dmatest_random() % (params->buf_size - len + 1);
562
563 src_off = (src_off >> align) << align;
564 dst_off = (dst_off >> align) << align;
565
566 dmatest_init_srcs(thread->srcs, src_off, len,
567 params->buf_size);
568 dmatest_init_dsts(thread->dsts, dst_off, len,
569 params->buf_size);
570
571 diff = ktime_sub(ktime_get(), start);
572 filltime = ktime_add(filltime, diff);
573 }
574
575 um = dmaengine_get_unmap_data(dev->dev, src_cnt + dst_cnt,
576 GFP_KERNEL);
577 if (!um) {
578 failed_tests++;
579 result("unmap data NULL", total_tests,
580 src_off, dst_off, len, ret);
581 continue;
582 }
583
584 um->len = params->buf_size;
585 for (i = 0; i < src_cnt; i++) {
586 void *buf = thread->srcs[i];
587 struct page *pg = virt_to_page(buf);
588 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
589
590 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
591 um->len, DMA_TO_DEVICE);
592 srcs[i] = um->addr[i] + src_off;
593 ret = dma_mapping_error(dev->dev, um->addr[i]);
594 if (ret) {
595 dmaengine_unmap_put(um);
596 result("src mapping error", total_tests,
597 src_off, dst_off, len, ret);
598 failed_tests++;
599 continue;
600 }
601 um->to_cnt++;
602 }
603 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
604 dsts = &um->addr[src_cnt];
605 for (i = 0; i < dst_cnt; i++) {
606 void *buf = thread->dsts[i];
607 struct page *pg = virt_to_page(buf);
608 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
609
610 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
611 DMA_BIDIRECTIONAL);
612 ret = dma_mapping_error(dev->dev, dsts[i]);
613 if (ret) {
614 dmaengine_unmap_put(um);
615 result("dst mapping error", total_tests,
616 src_off, dst_off, len, ret);
617 failed_tests++;
618 continue;
619 }
620 um->bidi_cnt++;
621 }
622
623 sg_init_table(tx_sg, src_cnt);
624 sg_init_table(rx_sg, src_cnt);
625 for (i = 0; i < src_cnt; i++) {
626 sg_dma_address(&rx_sg[i]) = srcs[i];
627 sg_dma_address(&tx_sg[i]) = dsts[i] + dst_off;
628 sg_dma_len(&tx_sg[i]) = len;
629 sg_dma_len(&rx_sg[i]) = len;
630 }
631
632 if (thread->type == DMA_MEMCPY)
633 tx = dev->device_prep_dma_memcpy(chan,
634 dsts[0] + dst_off,
635 srcs[0], len, flags);
636 else if (thread->type == DMA_SG)
637 tx = dev->device_prep_dma_sg(chan, tx_sg, src_cnt,
638 rx_sg, src_cnt, flags);
639 else if (thread->type == DMA_XOR)
640 tx = dev->device_prep_dma_xor(chan,
641 dsts[0] + dst_off,
642 srcs, src_cnt,
643 len, flags);
644 else if (thread->type == DMA_PQ) {
645 dma_addr_t dma_pq[dst_cnt];
646
647 for (i = 0; i < dst_cnt; i++)
648 dma_pq[i] = dsts[i] + dst_off;
649 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
650 src_cnt, pq_coefs,
651 len, flags);
652 }
653
654 if (!tx) {
655 dmaengine_unmap_put(um);
656 result("prep error", total_tests, src_off,
657 dst_off, len, ret);
658 msleep(100);
659 failed_tests++;
660 continue;
661 }
662
663 done.done = false;
664 tx->callback = dmatest_callback;
665 tx->callback_param = &done;
666 cookie = tx->tx_submit(tx);
667
668 if (dma_submit_error(cookie)) {
669 dmaengine_unmap_put(um);
670 result("submit error", total_tests, src_off,
671 dst_off, len, ret);
672 msleep(100);
673 failed_tests++;
674 continue;
675 }
676 dma_async_issue_pending(chan);
677
678 wait_event_freezable_timeout(done_wait, done.done,
679 msecs_to_jiffies(params->timeout));
680
681 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
682
683 if (!done.done) {
684 /*
685 * We're leaving the timed out dma operation with
686 * dangling pointer to done_wait. To make this
687 * correct, we'll need to allocate wait_done for
688 * each test iteration and perform "who's gonna
689 * free it this time?" dancing. For now, just
690 * leave it dangling.
691 */
692 dmaengine_unmap_put(um);
693 result("test timed out", total_tests, src_off, dst_off,
694 len, 0);
695 failed_tests++;
696 continue;
697 } else if (status != DMA_COMPLETE) {
698 dmaengine_unmap_put(um);
699 result(status == DMA_ERROR ?
700 "completion error status" :
701 "completion busy status", total_tests, src_off,
702 dst_off, len, ret);
703 failed_tests++;
704 continue;
705 }
706
707 dmaengine_unmap_put(um);
708
709 if (params->noverify) {
710 verbose_result("test passed", total_tests, src_off,
711 dst_off, len, 0);
712 continue;
713 }
714
715 start = ktime_get();
716 pr_debug("%s: verifying source buffer...\n", current->comm);
717 error_count = dmatest_verify(thread->srcs, 0, src_off,
718 0, PATTERN_SRC, true);
719 error_count += dmatest_verify(thread->srcs, src_off,
720 src_off + len, src_off,
721 PATTERN_SRC | PATTERN_COPY, true);
722 error_count += dmatest_verify(thread->srcs, src_off + len,
723 params->buf_size, src_off + len,
724 PATTERN_SRC, true);
725
726 pr_debug("%s: verifying dest buffer...\n", current->comm);
727 error_count += dmatest_verify(thread->dsts, 0, dst_off,
728 0, PATTERN_DST, false);
729 error_count += dmatest_verify(thread->dsts, dst_off,
730 dst_off + len, src_off,
731 PATTERN_SRC | PATTERN_COPY, false);
732 error_count += dmatest_verify(thread->dsts, dst_off + len,
733 params->buf_size, dst_off + len,
734 PATTERN_DST, false);
735
736 diff = ktime_sub(ktime_get(), start);
737 comparetime = ktime_add(comparetime, diff);
738
739 if (error_count) {
740 result("data error", total_tests, src_off, dst_off,
741 len, error_count);
742 failed_tests++;
743 } else {
744 verbose_result("test passed", total_tests, src_off,
745 dst_off, len, 0);
746 }
747 }
748 ktime = ktime_sub(ktime_get(), ktime);
749 ktime = ktime_sub(ktime, comparetime);
750 ktime = ktime_sub(ktime, filltime);
751 runtime = ktime_to_us(ktime);
752
753 ret = 0;
754 err_dstbuf:
755 for (i = 0; thread->udsts[i]; i++)
756 kfree(thread->udsts[i]);
757 kfree(thread->udsts);
758 err_udsts:
759 kfree(thread->dsts);
760 err_dsts:
761 err_srcbuf:
762 for (i = 0; thread->usrcs[i]; i++)
763 kfree(thread->usrcs[i]);
764 kfree(thread->usrcs);
765 err_usrcs:
766 kfree(thread->srcs);
767 err_srcs:
768 kfree(pq_coefs);
769 err_thread_type:
770 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
771 current->comm, total_tests, failed_tests,
772 dmatest_persec(runtime, total_tests),
773 dmatest_KBs(runtime, total_len), ret);
774
775 /* terminate all transfers on specified channels */
776 if (ret)
777 dmaengine_terminate_all(chan);
778
779 thread->done = true;
780 wake_up(&thread_wait);
781
782 return ret;
783 }
784
785 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
786 {
787 struct dmatest_thread *thread;
788 struct dmatest_thread *_thread;
789 int ret;
790
791 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
792 ret = kthread_stop(thread->task);
793 pr_debug("thread %s exited with status %d\n",
794 thread->task->comm, ret);
795 list_del(&thread->node);
796 put_task_struct(thread->task);
797 kfree(thread);
798 }
799
800 /* terminate all transfers on specified channels */
801 dmaengine_terminate_all(dtc->chan);
802
803 kfree(dtc);
804 }
805
806 static int dmatest_add_threads(struct dmatest_info *info,
807 struct dmatest_chan *dtc, enum dma_transaction_type type)
808 {
809 struct dmatest_params *params = &info->params;
810 struct dmatest_thread *thread;
811 struct dma_chan *chan = dtc->chan;
812 char *op;
813 unsigned int i;
814
815 if (type == DMA_MEMCPY)
816 op = "copy";
817 else if (type == DMA_SG)
818 op = "sg";
819 else if (type == DMA_XOR)
820 op = "xor";
821 else if (type == DMA_PQ)
822 op = "pq";
823 else
824 return -EINVAL;
825
826 for (i = 0; i < params->threads_per_chan; i++) {
827 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
828 if (!thread) {
829 pr_warn("No memory for %s-%s%u\n",
830 dma_chan_name(chan), op, i);
831 break;
832 }
833 thread->info = info;
834 thread->chan = dtc->chan;
835 thread->type = type;
836 smp_wmb();
837 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
838 dma_chan_name(chan), op, i);
839 if (IS_ERR(thread->task)) {
840 pr_warn("Failed to create thread %s-%s%u\n",
841 dma_chan_name(chan), op, i);
842 kfree(thread);
843 break;
844 }
845
846 /* srcbuf and dstbuf are allocated by the thread itself */
847 get_task_struct(thread->task);
848 list_add_tail(&thread->node, &dtc->threads);
849 wake_up_process(thread->task);
850 }
851
852 return i;
853 }
854
855 static int dmatest_add_channel(struct dmatest_info *info,
856 struct dma_chan *chan)
857 {
858 struct dmatest_chan *dtc;
859 struct dma_device *dma_dev = chan->device;
860 unsigned int thread_count = 0;
861 int cnt;
862
863 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
864 if (!dtc) {
865 pr_warn("No memory for %s\n", dma_chan_name(chan));
866 return -ENOMEM;
867 }
868
869 dtc->chan = chan;
870 INIT_LIST_HEAD(&dtc->threads);
871
872 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
873 if (dmatest == 0) {
874 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
875 thread_count += cnt > 0 ? cnt : 0;
876 }
877 }
878
879 if (dma_has_cap(DMA_SG, dma_dev->cap_mask)) {
880 if (dmatest == 1) {
881 cnt = dmatest_add_threads(info, dtc, DMA_SG);
882 thread_count += cnt > 0 ? cnt : 0;
883 }
884 }
885
886 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
887 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
888 thread_count += cnt > 0 ? cnt : 0;
889 }
890 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
891 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
892 thread_count += cnt > 0 ? cnt : 0;
893 }
894
895 pr_info("Started %u threads using %s\n",
896 thread_count, dma_chan_name(chan));
897
898 list_add_tail(&dtc->node, &info->channels);
899 info->nr_channels++;
900
901 return 0;
902 }
903
904 static bool filter(struct dma_chan *chan, void *param)
905 {
906 struct dmatest_params *params = param;
907
908 if (!dmatest_match_channel(params, chan) ||
909 !dmatest_match_device(params, chan->device))
910 return false;
911 else
912 return true;
913 }
914
915 static void request_channels(struct dmatest_info *info,
916 enum dma_transaction_type type)
917 {
918 dma_cap_mask_t mask;
919
920 dma_cap_zero(mask);
921 dma_cap_set(type, mask);
922 for (;;) {
923 struct dmatest_params *params = &info->params;
924 struct dma_chan *chan;
925
926 chan = dma_request_channel(mask, filter, params);
927 if (chan) {
928 if (dmatest_add_channel(info, chan)) {
929 dma_release_channel(chan);
930 break; /* add_channel failed, punt */
931 }
932 } else
933 break; /* no more channels available */
934 if (params->max_channels &&
935 info->nr_channels >= params->max_channels)
936 break; /* we have all we need */
937 }
938 }
939
940 static void run_threaded_test(struct dmatest_info *info)
941 {
942 struct dmatest_params *params = &info->params;
943
944 /* Copy test parameters */
945 params->buf_size = test_buf_size;
946 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
947 strlcpy(params->device, strim(test_device), sizeof(params->device));
948 params->threads_per_chan = threads_per_chan;
949 params->max_channels = max_channels;
950 params->iterations = iterations;
951 params->xor_sources = xor_sources;
952 params->pq_sources = pq_sources;
953 params->timeout = timeout;
954 params->noverify = noverify;
955
956 request_channels(info, DMA_MEMCPY);
957 request_channels(info, DMA_XOR);
958 request_channels(info, DMA_SG);
959 request_channels(info, DMA_PQ);
960 }
961
962 static void stop_threaded_test(struct dmatest_info *info)
963 {
964 struct dmatest_chan *dtc, *_dtc;
965 struct dma_chan *chan;
966
967 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
968 list_del(&dtc->node);
969 chan = dtc->chan;
970 dmatest_cleanup_channel(dtc);
971 pr_debug("dropped channel %s\n", dma_chan_name(chan));
972 dma_release_channel(chan);
973 }
974
975 info->nr_channels = 0;
976 }
977
978 static void restart_threaded_test(struct dmatest_info *info, bool run)
979 {
980 /* we might be called early to set run=, defer running until all
981 * parameters have been evaluated
982 */
983 if (!info->did_init)
984 return;
985
986 /* Stop any running test first */
987 stop_threaded_test(info);
988
989 /* Run test with new parameters */
990 run_threaded_test(info);
991 }
992
993 static int dmatest_run_get(char *val, const struct kernel_param *kp)
994 {
995 struct dmatest_info *info = &test_info;
996
997 mutex_lock(&info->lock);
998 if (is_threaded_test_run(info)) {
999 dmatest_run = true;
1000 } else {
1001 stop_threaded_test(info);
1002 dmatest_run = false;
1003 }
1004 mutex_unlock(&info->lock);
1005
1006 return param_get_bool(val, kp);
1007 }
1008
1009 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1010 {
1011 struct dmatest_info *info = &test_info;
1012 int ret;
1013
1014 mutex_lock(&info->lock);
1015 ret = param_set_bool(val, kp);
1016 if (ret) {
1017 mutex_unlock(&info->lock);
1018 return ret;
1019 }
1020
1021 if (is_threaded_test_run(info))
1022 ret = -EBUSY;
1023 else if (dmatest_run)
1024 restart_threaded_test(info, dmatest_run);
1025
1026 mutex_unlock(&info->lock);
1027
1028 return ret;
1029 }
1030
1031 static int __init dmatest_init(void)
1032 {
1033 struct dmatest_info *info = &test_info;
1034 struct dmatest_params *params = &info->params;
1035
1036 if (dmatest_run) {
1037 mutex_lock(&info->lock);
1038 run_threaded_test(info);
1039 mutex_unlock(&info->lock);
1040 }
1041
1042 if (params->iterations && wait)
1043 wait_event(thread_wait, !is_threaded_test_run(info));
1044
1045 /* module parameters are stable, inittime tests are started,
1046 * let userspace take over 'run' control
1047 */
1048 info->did_init = true;
1049
1050 return 0;
1051 }
1052 /* when compiled-in wait for drivers to load first */
1053 late_initcall(dmatest_init);
1054
1055 static void __exit dmatest_exit(void)
1056 {
1057 struct dmatest_info *info = &test_info;
1058
1059 mutex_lock(&info->lock);
1060 stop_threaded_test(info);
1061 mutex_unlock(&info->lock);
1062 }
1063 module_exit(dmatest_exit);
1064
1065 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1066 MODULE_LICENSE("GPL v2");