drivers/dma/dw/regs.h

   1 /*
   2  * Driver for the Synopsys DesignWare AHB DMA Controller
   3  *
   4  * Copyright (C) 2005-2007 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/dmaengine.h>
  14
  15 #define DW_DMA_MAX_NR_CHANNELS  8
  16 #define DW_DMA_MAX_NR_REQUESTS  16
  17
  18 /* flow controller */
  19 enum dw_dma_fc {
  20         DW_DMA_FC_D_M2M,
  21         DW_DMA_FC_D_M2P,
  22         DW_DMA_FC_D_P2M,
  23         DW_DMA_FC_D_P2P,
  24         DW_DMA_FC_P_P2M,
  25         DW_DMA_FC_SP_P2P,
  26         DW_DMA_FC_P_M2P,
  27         DW_DMA_FC_DP_P2P,
  28 };
  29
  30 /*
  31  * Redefine this macro to handle differences between 32- and 64-bit
  32  * addressing, big vs. little endian, etc.
  33  */
  34 #define DW_REG(name)            u32 name; u32 __pad_##name
  35
  36 /* Hardware register definitions. */
  37 struct dw_dma_chan_regs {
  38         DW_REG(SAR);            /* Source Address Register */
  39         DW_REG(DAR);            /* Destination Address Register */
  40         DW_REG(LLP);            /* Linked List Pointer */
  41         u32     CTL_LO;         /* Control Register Low */
  42         u32     CTL_HI;         /* Control Register High */
  43         DW_REG(SSTAT);
  44         DW_REG(DSTAT);
  45         DW_REG(SSTATAR);
  46         DW_REG(DSTATAR);
  47         u32     CFG_LO;         /* Configuration Register Low */
  48         u32     CFG_HI;         /* Configuration Register High */
  49         DW_REG(SGR);
  50         DW_REG(DSR);
  51 };
  52
  53 struct dw_dma_irq_regs {
  54         DW_REG(XFER);
  55         DW_REG(BLOCK);
  56         DW_REG(SRC_TRAN);
  57         DW_REG(DST_TRAN);
  58         DW_REG(ERROR);
  59 };
  60
  61 struct dw_dma_regs {
  62         /* per-channel registers */
  63         struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
  64
  65         /* irq handling */
  66         struct dw_dma_irq_regs  RAW;            /* r */
  67         struct dw_dma_irq_regs  STATUS;         /* r (raw & mask) */
  68         struct dw_dma_irq_regs  MASK;           /* rw (set = irq enabled) */
  69         struct dw_dma_irq_regs  CLEAR;          /* w (ack, affects "raw") */
  70
  71         DW_REG(STATUS_INT);                     /* r */
  72
  73         /* software handshaking */
  74         DW_REG(REQ_SRC);
  75         DW_REG(REQ_DST);
  76         DW_REG(SGL_REQ_SRC);
  77         DW_REG(SGL_REQ_DST);
  78         DW_REG(LAST_SRC);
  79         DW_REG(LAST_DST);
  80
  81         /* miscellaneous */
  82         DW_REG(CFG);
  83         DW_REG(CH_EN);
  84         DW_REG(ID);
  85         DW_REG(TEST);
  86
  87         /* reserved */
  88         DW_REG(__reserved0);
  89         DW_REG(__reserved1);
  90
  91         /* optional encoded params, 0x3c8..0x3f7 */
  92         u32     __reserved;
  93
  94         /* per-channel configuration registers */
  95         u32     DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
  96         u32     MULTI_BLK_TYPE;
  97         u32     MAX_BLK_SIZE;
  98
  99         /* top-level parameters */
 100         u32     DW_PARAMS;
 101 };
 102
 103 /*
 104  * Big endian I/O access when reading and writing to the DMA controller
 105  * registers.  This is needed on some platforms, like the Atmel AVR32
 106  * architecture.
 107  */
 108
 109 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 110 #define dma_readl_native ioread32be
 111 #define dma_writel_native iowrite32be
 112 #else
 113 #define dma_readl_native readl
 114 #define dma_writel_native writel
 115 #endif
 116
 117 /* To access the registers in early stage of probe */
 118 #define dma_read_byaddr(addr, name) \
 119         dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
 120
 121 /* Bitfields in DW_PARAMS */
 122 #define DW_PARAMS_NR_CHAN       8               /* number of channels */
 123 #define DW_PARAMS_NR_MASTER     11              /* number of AHB masters */
 124 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
 125 #define DW_PARAMS_DATA_WIDTH1   15              /* master 1 data width */
 126 #define DW_PARAMS_DATA_WIDTH2   17              /* master 2 data width */
 127 #define DW_PARAMS_DATA_WIDTH3   19              /* master 3 data width */
 128 #define DW_PARAMS_DATA_WIDTH4   21              /* master 4 data width */
 129 #define DW_PARAMS_EN            28              /* encoded parameters */
 130
 131 /* Bitfields in DWC_PARAMS */
 132 #define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
 133
 134 /* bursts size */
 135 enum dw_dma_msize {
 136         DW_DMA_MSIZE_1,
 137         DW_DMA_MSIZE_4,
 138         DW_DMA_MSIZE_8,
 139         DW_DMA_MSIZE_16,
 140         DW_DMA_MSIZE_32,
 141         DW_DMA_MSIZE_64,
 142         DW_DMA_MSIZE_128,
 143         DW_DMA_MSIZE_256,
 144 };
 145
 146 /* Bitfields in CTL_LO */
 147 #define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 148 #define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
 149 #define DWC_CTLL_SRC_WIDTH(n)   ((n)<<4)
 150 #define DWC_CTLL_DST_INC        (0<<7)          /* DAR update/not */
 151 #define DWC_CTLL_DST_DEC        (1<<7)
 152 #define DWC_CTLL_DST_FIX        (2<<7)
 153 #define DWC_CTLL_SRC_INC        (0<<7)          /* SAR update/not */
 154 #define DWC_CTLL_SRC_DEC        (1<<9)
 155 #define DWC_CTLL_SRC_FIX        (2<<9)
 156 #define DWC_CTLL_DST_MSIZE(n)   ((n)<<11)       /* burst, #elements */
 157 #define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
 158 #define DWC_CTLL_S_GATH_EN      (1 << 17)       /* src gather, !FIX */
 159 #define DWC_CTLL_D_SCAT_EN      (1 << 18)       /* dst scatter, !FIX */
 160 #define DWC_CTLL_FC(n)          ((n) << 20)
 161 #define DWC_CTLL_FC_M2M         (0 << 20)       /* mem-to-mem */
 162 #define DWC_CTLL_FC_M2P         (1 << 20)       /* mem-to-periph */
 163 #define DWC_CTLL_FC_P2M         (2 << 20)       /* periph-to-mem */
 164 #define DWC_CTLL_FC_P2P         (3 << 20)       /* periph-to-periph */
 165 /* plus 4 transfer types for peripheral-as-flow-controller */
 166 #define DWC_CTLL_DMS(n)         ((n)<<23)       /* dst master select */
 167 #define DWC_CTLL_SMS(n)         ((n)<<25)       /* src master select */
 168 #define DWC_CTLL_LLP_D_EN       (1 << 27)       /* dest block chain */
 169 #define DWC_CTLL_LLP_S_EN       (1 << 28)       /* src block chain */
 170
 171 /* Bitfields in CTL_HI */
 172 #define DWC_CTLH_DONE           0x00001000
 173 #define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 174
 175 /* Bitfields in CFG_LO */
 176 #define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
 177 #define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 178 #define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 179 #define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 180 #define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
 181 #define DWC_CFGL_HS_SRC         (1 << 11)       /* handshake w/src */
 182 #define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
 183 #define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
 184 #define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
 185 #define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
 186 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
 187 #define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
 188 #define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
 189 #define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
 190 #define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
 191 #define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
 192 #define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
 193 #define DWC_CFGL_RELOAD_SAR     (1 << 30)
 194 #define DWC_CFGL_RELOAD_DAR     (1 << 31)
 195
 196 /* Bitfields in CFG_HI */
 197 #define DWC_CFGH_FCMODE         (1 << 0)
 198 #define DWC_CFGH_FIFO_MODE      (1 << 1)
 199 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
 200 #define DWC_CFGH_DS_UPD_EN      (1 << 5)
 201 #define DWC_CFGH_SS_UPD_EN      (1 << 6)
 202 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
 203 #define DWC_CFGH_DST_PER(x)     ((x) << 11)
 204
 205 /* Bitfields in SGR */
 206 #define DWC_SGR_SGI(x)          ((x) << 0)
 207 #define DWC_SGR_SGC(x)          ((x) << 20)
 208
 209 /* Bitfields in DSR */
 210 #define DWC_DSR_DSI(x)          ((x) << 0)
 211 #define DWC_DSR_DSC(x)          ((x) << 20)
 212
 213 /* Bitfields in CFG */
 214 #define DW_CFG_DMA_EN           (1 << 0)
 215
 216 enum dw_dmac_flags {
 217         DW_DMA_IS_CYCLIC = 0,
 218         DW_DMA_IS_SOFT_LLP = 1,
 219 };
 220
 221 struct dw_dma_chan {
 222         struct dma_chan                 chan;
 223         void __iomem                    *ch_regs;
 224         u8                              mask;
 225         u8                              priority;
 226         enum dma_transfer_direction     direction;
 227         bool                            paused;
 228         bool                            initialized;
 229
 230         /* software emulation of the LLP transfers */
 231         struct list_head        *tx_node_active;
 232
 233         spinlock_t              lock;
 234
 235         /* these other elements are all protected by lock */
 236         unsigned long           flags;
 237         struct list_head        active_list;
 238         struct list_head        queue;
 239         struct list_head        free_list;
 240         u32                     residue;
 241         struct dw_cyclic_desc   *cdesc;
 242
 243         unsigned int            descs_allocated;
 244
 245         /* hardware configuration */
 246         unsigned int            block_size;
 247         bool                    nollp;
 248
 249         /* custom slave configuration */
 250         u8                      src_id;
 251         u8                      dst_id;
 252         u8                      src_master;
 253         u8                      dst_master;
 254
 255         /* configuration passed via DMA_SLAVE_CONFIG */
 256         struct dma_slave_config dma_sconfig;
 257 };
 258
 259 static inline struct dw_dma_chan_regs __iomem *
 260 __dwc_regs(struct dw_dma_chan *dwc)
 261 {
 262         return dwc->ch_regs;
 263 }
 264
 265 #define channel_readl(dwc, name) \
 266         dma_readl_native(&(__dwc_regs(dwc)->name))
 267 #define channel_writel(dwc, name, val) \
 268         dma_writel_native((val), &(__dwc_regs(dwc)->name))
 269
 270 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
 271 {
 272         return container_of(chan, struct dw_dma_chan, chan);
 273 }
 274
 275 struct dw_dma {
 276         struct dma_device       dma;
 277         void __iomem            *regs;
 278         struct dma_pool         *desc_pool;
 279         struct tasklet_struct   tasklet;
 280
 281         /* channels */
 282         struct dw_dma_chan      *chan;
 283         u8                      all_chan_mask;
 284         u8                      in_use;
 285
 286         /* hardware configuration */
 287         unsigned char           nr_masters;
 288         unsigned char           data_width[4];
 289 };
 290
 291 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
 292 {
 293         return dw->regs;
 294 }
 295
 296 #define dma_readl(dw, name) \
 297         dma_readl_native(&(__dw_regs(dw)->name))
 298 #define dma_writel(dw, name, val) \
 299         dma_writel_native((val), &(__dw_regs(dw)->name))
 300
 301 #define channel_set_bit(dw, reg, mask) \
 302         dma_writel(dw, reg, ((mask) << 8) | (mask))
 303 #define channel_clear_bit(dw, reg, mask) \
 304         dma_writel(dw, reg, ((mask) << 8) | 0)
 305
 306 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 307 {
 308         return container_of(ddev, struct dw_dma, dma);
 309 }
 310
 311 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
 312 struct dw_lli {
 313         /* values that are not changed by hardware */
 314         u32             sar;
 315         u32             dar;
 316         u32             llp;            /* chain to next lli */
 317         u32             ctllo;
 318         /* values that may get written back: */
 319         u32             ctlhi;
 320         /* sstat and dstat can snapshot peripheral register state.
 321          * silicon config may discard either or both...
 322          */
 323         u32             sstat;
 324         u32             dstat;
 325 };
 326
 327 struct dw_desc {
 328         /* FIRST values the hardware uses */
 329         struct dw_lli                   lli;
 330
 331         /* THEN values for driver housekeeping */
 332         struct list_head                desc_node;
 333         struct list_head                tx_list;
 334         struct dma_async_tx_descriptor  txd;
 335         size_t                          len;
 336         size_t                          total_len;
 337 };
 338
 339 #define to_dw_desc(h)   list_entry(h, struct dw_desc, desc_node)
 340
 341 static inline struct dw_desc *
 342 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
 343 {
 344         return container_of(txd, struct dw_desc, txd);
 345 }