2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/edma.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
28 #include <linux/of_dma.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/platform_data/edma.h>
36 #include "dmaengine.h"
39 /* Offsets matching "struct edmacc_param" */
42 #define PARM_A_B_CNT 0x08
44 #define PARM_SRC_DST_BIDX 0x10
45 #define PARM_LINK_BCNTRLD 0x14
46 #define PARM_SRC_DST_CIDX 0x18
47 #define PARM_CCNT 0x1c
49 #define PARM_SIZE 0x20
51 /* Offsets for EDMA CC global channel registers and their shadows */
52 #define SH_ER 0x00 /* 64 bits */
53 #define SH_ECR 0x08 /* 64 bits */
54 #define SH_ESR 0x10 /* 64 bits */
55 #define SH_CER 0x18 /* 64 bits */
56 #define SH_EER 0x20 /* 64 bits */
57 #define SH_EECR 0x28 /* 64 bits */
58 #define SH_EESR 0x30 /* 64 bits */
59 #define SH_SER 0x38 /* 64 bits */
60 #define SH_SECR 0x40 /* 64 bits */
61 #define SH_IER 0x50 /* 64 bits */
62 #define SH_IECR 0x58 /* 64 bits */
63 #define SH_IESR 0x60 /* 64 bits */
64 #define SH_IPR 0x68 /* 64 bits */
65 #define SH_ICR 0x70 /* 64 bits */
75 /* Offsets for EDMA CC global registers */
76 #define EDMA_REV 0x0000
77 #define EDMA_CCCFG 0x0004
78 #define EDMA_QCHMAP 0x0200 /* 8 registers */
79 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80 #define EDMA_QDMAQNUM 0x0260
81 #define EDMA_QUETCMAP 0x0280
82 #define EDMA_QUEPRI 0x0284
83 #define EDMA_EMR 0x0300 /* 64 bits */
84 #define EDMA_EMCR 0x0308 /* 64 bits */
85 #define EDMA_QEMR 0x0310
86 #define EDMA_QEMCR 0x0314
87 #define EDMA_CCERR 0x0318
88 #define EDMA_CCERRCLR 0x031c
89 #define EDMA_EEVAL 0x0320
90 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91 #define EDMA_QRAE 0x0380 /* 4 registers */
92 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93 #define EDMA_QSTAT 0x0600 /* 2 registers */
94 #define EDMA_QWMTHRA 0x0620
95 #define EDMA_QWMTHRB 0x0624
96 #define EDMA_CCSTAT 0x0640
98 #define EDMA_M 0x1000 /* global channel registers */
99 #define EDMA_ECR 0x1008
100 #define EDMA_ECRH 0x100C
101 #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102 #define EDMA_PARM 0x4000 /* PaRAM entries */
104 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
106 #define EDMA_DCHMAP 0x0100 /* 64 registers */
109 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST BIT(24)
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV BIT(4)
120 * Max of 20 segments per channel to conserve PaRAM slots
121 * Also note that MAX_NR_SG should be atleast the no.of periods
122 * that are required for ASoC, otherwise DMA prep calls will
123 * fail. Today davinci-pcm is the only user of this driver and
124 * requires atleast 17 slots, so we setup the default to 20.
127 #define EDMA_MAX_SLOTS MAX_NR_SG
128 #define EDMA_DESCRIPTORS 16
130 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY 1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
136 /* PaRAM slots are laid out like this */
137 struct edmacc_param
{
148 /* fields in edmacc_param.opt */
151 #define SYNCDIM BIT(2)
152 #define STATIC BIT(3)
153 #define EDMA_FWID (0x07 << 8)
154 #define TCCMODE BIT(11)
155 #define EDMA_TCC(t) ((t) << 12)
156 #define TCINTEN BIT(20)
157 #define ITCINTEN BIT(21)
158 #define TCCHEN BIT(22)
159 #define ITCCHEN BIT(23)
164 struct edmacc_param param
;
168 struct virt_dma_desc vdesc
;
169 struct list_head node
;
170 enum dma_transfer_direction direction
;
174 struct edma_chan
*echan
;
178 * The following 4 elements are used for residue accounting.
180 * - processed_stat: the number of SG elements we have traversed
181 * so far to cover accounting. This is updated directly to processed
182 * during edma_callback and is always <= processed, because processed
183 * refers to the number of pending transfer (programmed to EDMA
184 * controller), where as processed_stat tracks number of transfers
185 * accounted for so far.
187 * - residue: The amount of bytes we have left to transfer for this desc
189 * - residue_stat: The residue in bytes of data we have covered
190 * so far for accounting. This is updated directly to residue
191 * during callbacks to keep it current.
193 * - sg_len: Tracks the length of the current intermediate transfer,
194 * this is required to update the residue during intermediate transfer
195 * completion callback.
202 struct edma_pset pset
[0];
208 struct device_node
*node
;
213 struct virt_dma_chan vchan
;
214 struct list_head node
;
215 struct edma_desc
*edesc
;
221 int slot
[EDMA_MAX_SLOTS
];
223 struct dma_slave_config cfg
;
228 struct edma_soc_info
*info
;
233 /* eDMA3 resource information */
234 unsigned num_channels
;
235 unsigned num_qchannels
;
240 enum dma_event_q default_queue
;
243 unsigned int ccerrint
;
246 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
247 * in use by Linux or if it is allocated to be used by DSP.
249 unsigned long *slot_inuse
;
251 struct dma_device dma_slave
;
252 struct dma_device
*dma_memcpy
;
253 struct edma_chan
*slave_chans
;
254 struct edma_tc
*tc_list
;
258 /* dummy param set used to (re)initialize parameter RAM slots */
259 static const struct edmacc_param dummy_paramset
= {
260 .link_bcntrld
= 0xffff,
264 #define EDMA_BINDING_LEGACY 0
265 #define EDMA_BINDING_TPCC 1
266 static const u32 edma_binding_type
[] = {
267 [EDMA_BINDING_LEGACY
] = EDMA_BINDING_LEGACY
,
268 [EDMA_BINDING_TPCC
] = EDMA_BINDING_TPCC
,
271 static const struct of_device_id edma_of_ids
[] = {
273 .compatible
= "ti,edma3",
274 .data
= &edma_binding_type
[EDMA_BINDING_LEGACY
],
277 .compatible
= "ti,edma3-tpcc",
278 .data
= &edma_binding_type
[EDMA_BINDING_TPCC
],
282 MODULE_DEVICE_TABLE(of
, edma_of_ids
);
284 static const struct of_device_id edma_tptc_of_ids
[] = {
285 { .compatible
= "ti,edma3-tptc", },
288 MODULE_DEVICE_TABLE(of
, edma_tptc_of_ids
);
290 static inline unsigned int edma_read(struct edma_cc
*ecc
, int offset
)
292 return (unsigned int)__raw_readl(ecc
->base
+ offset
);
295 static inline void edma_write(struct edma_cc
*ecc
, int offset
, int val
)
297 __raw_writel(val
, ecc
->base
+ offset
);
300 static inline void edma_modify(struct edma_cc
*ecc
, int offset
, unsigned and,
303 unsigned val
= edma_read(ecc
, offset
);
307 edma_write(ecc
, offset
, val
);
310 static inline void edma_and(struct edma_cc
*ecc
, int offset
, unsigned and)
312 unsigned val
= edma_read(ecc
, offset
);
315 edma_write(ecc
, offset
, val
);
318 static inline void edma_or(struct edma_cc
*ecc
, int offset
, unsigned or)
320 unsigned val
= edma_read(ecc
, offset
);
323 edma_write(ecc
, offset
, val
);
326 static inline unsigned int edma_read_array(struct edma_cc
*ecc
, int offset
,
329 return edma_read(ecc
, offset
+ (i
<< 2));
332 static inline void edma_write_array(struct edma_cc
*ecc
, int offset
, int i
,
335 edma_write(ecc
, offset
+ (i
<< 2), val
);
338 static inline void edma_modify_array(struct edma_cc
*ecc
, int offset
, int i
,
339 unsigned and, unsigned or)
341 edma_modify(ecc
, offset
+ (i
<< 2), and, or);
344 static inline void edma_or_array(struct edma_cc
*ecc
, int offset
, int i
,
347 edma_or(ecc
, offset
+ (i
<< 2), or);
350 static inline void edma_or_array2(struct edma_cc
*ecc
, int offset
, int i
, int j
,
353 edma_or(ecc
, offset
+ ((i
* 2 + j
) << 2), or);
356 static inline void edma_write_array2(struct edma_cc
*ecc
, int offset
, int i
,
359 edma_write(ecc
, offset
+ ((i
* 2 + j
) << 2), val
);
362 static inline unsigned int edma_shadow0_read(struct edma_cc
*ecc
, int offset
)
364 return edma_read(ecc
, EDMA_SHADOW0
+ offset
);
367 static inline unsigned int edma_shadow0_read_array(struct edma_cc
*ecc
,
370 return edma_read(ecc
, EDMA_SHADOW0
+ offset
+ (i
<< 2));
373 static inline void edma_shadow0_write(struct edma_cc
*ecc
, int offset
,
376 edma_write(ecc
, EDMA_SHADOW0
+ offset
, val
);
379 static inline void edma_shadow0_write_array(struct edma_cc
*ecc
, int offset
,
382 edma_write(ecc
, EDMA_SHADOW0
+ offset
+ (i
<< 2), val
);
385 static inline unsigned int edma_param_read(struct edma_cc
*ecc
, int offset
,
388 return edma_read(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5));
391 static inline void edma_param_write(struct edma_cc
*ecc
, int offset
,
392 int param_no
, unsigned val
)
394 edma_write(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), val
);
397 static inline void edma_param_modify(struct edma_cc
*ecc
, int offset
,
398 int param_no
, unsigned and, unsigned or)
400 edma_modify(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), and, or);
403 static inline void edma_param_and(struct edma_cc
*ecc
, int offset
, int param_no
,
406 edma_and(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), and);
409 static inline void edma_param_or(struct edma_cc
*ecc
, int offset
, int param_no
,
412 edma_or(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), or);
415 static inline void set_bits(int offset
, int len
, unsigned long *p
)
417 for (; len
> 0; len
--)
418 set_bit(offset
+ (len
- 1), p
);
421 static inline void clear_bits(int offset
, int len
, unsigned long *p
)
423 for (; len
> 0; len
--)
424 clear_bit(offset
+ (len
- 1), p
);
427 static void edma_assign_priority_to_queue(struct edma_cc
*ecc
, int queue_no
,
430 int bit
= queue_no
* 4;
432 edma_modify(ecc
, EDMA_QUEPRI
, ~(0x7 << bit
), ((priority
& 0x7) << bit
));
435 static void edma_set_chmap(struct edma_chan
*echan
, int slot
)
437 struct edma_cc
*ecc
= echan
->ecc
;
438 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
440 if (ecc
->chmap_exist
) {
441 slot
= EDMA_CHAN_SLOT(slot
);
442 edma_write_array(ecc
, EDMA_DCHMAP
, channel
, (slot
<< 5));
446 static void edma_setup_interrupt(struct edma_chan
*echan
, bool enable
)
448 struct edma_cc
*ecc
= echan
->ecc
;
449 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
452 edma_shadow0_write_array(ecc
, SH_ICR
, channel
>> 5,
453 BIT(channel
& 0x1f));
454 edma_shadow0_write_array(ecc
, SH_IESR
, channel
>> 5,
455 BIT(channel
& 0x1f));
457 edma_shadow0_write_array(ecc
, SH_IECR
, channel
>> 5,
458 BIT(channel
& 0x1f));
463 * paRAM slot management functions
465 static void edma_write_slot(struct edma_cc
*ecc
, unsigned slot
,
466 const struct edmacc_param
*param
)
468 slot
= EDMA_CHAN_SLOT(slot
);
469 if (slot
>= ecc
->num_slots
)
471 memcpy_toio(ecc
->base
+ PARM_OFFSET(slot
), param
, PARM_SIZE
);
474 static void edma_read_slot(struct edma_cc
*ecc
, unsigned slot
,
475 struct edmacc_param
*param
)
477 slot
= EDMA_CHAN_SLOT(slot
);
478 if (slot
>= ecc
->num_slots
)
480 memcpy_fromio(param
, ecc
->base
+ PARM_OFFSET(slot
), PARM_SIZE
);
484 * edma_alloc_slot - allocate DMA parameter RAM
485 * @ecc: pointer to edma_cc struct
486 * @slot: specific slot to allocate; negative for "any unused slot"
488 * This allocates a parameter RAM slot, initializing it to hold a
489 * dummy transfer. Slots allocated using this routine have not been
490 * mapped to a hardware DMA channel, and will normally be used by
491 * linking to them from a slot associated with a DMA channel.
493 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
494 * slots may be allocated on behalf of DSP firmware.
496 * Returns the number of the slot, else negative errno.
498 static int edma_alloc_slot(struct edma_cc
*ecc
, int slot
)
501 slot
= EDMA_CHAN_SLOT(slot
);
502 /* Requesting entry paRAM slot for a HW triggered channel. */
503 if (ecc
->chmap_exist
&& slot
< ecc
->num_channels
)
504 slot
= EDMA_SLOT_ANY
;
508 if (ecc
->chmap_exist
)
511 slot
= ecc
->num_channels
;
513 slot
= find_next_zero_bit(ecc
->slot_inuse
,
516 if (slot
== ecc
->num_slots
)
518 if (!test_and_set_bit(slot
, ecc
->slot_inuse
))
521 } else if (slot
>= ecc
->num_slots
) {
523 } else if (test_and_set_bit(slot
, ecc
->slot_inuse
)) {
527 edma_write_slot(ecc
, slot
, &dummy_paramset
);
529 return EDMA_CTLR_CHAN(ecc
->id
, slot
);
532 static void edma_free_slot(struct edma_cc
*ecc
, unsigned slot
)
534 slot
= EDMA_CHAN_SLOT(slot
);
535 if (slot
>= ecc
->num_slots
)
538 edma_write_slot(ecc
, slot
, &dummy_paramset
);
539 clear_bit(slot
, ecc
->slot_inuse
);
543 * edma_link - link one parameter RAM slot to another
544 * @ecc: pointer to edma_cc struct
545 * @from: parameter RAM slot originating the link
546 * @to: parameter RAM slot which is the link target
548 * The originating slot should not be part of any active DMA transfer.
550 static void edma_link(struct edma_cc
*ecc
, unsigned from
, unsigned to
)
552 if (unlikely(EDMA_CTLR(from
) != EDMA_CTLR(to
)))
553 dev_warn(ecc
->dev
, "Ignoring eDMA instance for linking\n");
555 from
= EDMA_CHAN_SLOT(from
);
556 to
= EDMA_CHAN_SLOT(to
);
557 if (from
>= ecc
->num_slots
|| to
>= ecc
->num_slots
)
560 edma_param_modify(ecc
, PARM_LINK_BCNTRLD
, from
, 0xffff0000,
565 * edma_get_position - returns the current transfer point
566 * @ecc: pointer to edma_cc struct
567 * @slot: parameter RAM slot being examined
568 * @dst: true selects the dest position, false the source
570 * Returns the position of the current active slot
572 static dma_addr_t
edma_get_position(struct edma_cc
*ecc
, unsigned slot
,
577 slot
= EDMA_CHAN_SLOT(slot
);
578 offs
= PARM_OFFSET(slot
);
579 offs
+= dst
? PARM_DST
: PARM_SRC
;
581 return edma_read(ecc
, offs
);
585 * Channels with event associations will be triggered by their hardware
586 * events, and channels without such associations will be triggered by
587 * software. (At this writing there is no interface for using software
588 * triggers except with channels that don't support hardware triggers.)
590 static void edma_start(struct edma_chan
*echan
)
592 struct edma_cc
*ecc
= echan
->ecc
;
593 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
594 int j
= (channel
>> 5);
595 unsigned int mask
= BIT(channel
& 0x1f);
597 if (!echan
->hw_triggered
) {
598 /* EDMA channels without event association */
599 dev_dbg(ecc
->dev
, "ESR%d %08x\n", j
,
600 edma_shadow0_read_array(ecc
, SH_ESR
, j
));
601 edma_shadow0_write_array(ecc
, SH_ESR
, j
, mask
);
603 /* EDMA channel with event association */
604 dev_dbg(ecc
->dev
, "ER%d %08x\n", j
,
605 edma_shadow0_read_array(ecc
, SH_ER
, j
));
606 /* Clear any pending event or error */
607 edma_write_array(ecc
, EDMA_ECR
, j
, mask
);
608 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
610 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
611 edma_shadow0_write_array(ecc
, SH_EESR
, j
, mask
);
612 dev_dbg(ecc
->dev
, "EER%d %08x\n", j
,
613 edma_shadow0_read_array(ecc
, SH_EER
, j
));
617 static void edma_stop(struct edma_chan
*echan
)
619 struct edma_cc
*ecc
= echan
->ecc
;
620 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
621 int j
= (channel
>> 5);
622 unsigned int mask
= BIT(channel
& 0x1f);
624 edma_shadow0_write_array(ecc
, SH_EECR
, j
, mask
);
625 edma_shadow0_write_array(ecc
, SH_ECR
, j
, mask
);
626 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
627 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
629 /* clear possibly pending completion interrupt */
630 edma_shadow0_write_array(ecc
, SH_ICR
, j
, mask
);
632 dev_dbg(ecc
->dev
, "EER%d %08x\n", j
,
633 edma_shadow0_read_array(ecc
, SH_EER
, j
));
635 /* REVISIT: consider guarding against inappropriate event
636 * chaining by overwriting with dummy_paramset.
641 * Temporarily disable EDMA hardware events on the specified channel,
642 * preventing them from triggering new transfers
644 static void edma_pause(struct edma_chan
*echan
)
646 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
647 unsigned int mask
= BIT(channel
& 0x1f);
649 edma_shadow0_write_array(echan
->ecc
, SH_EECR
, channel
>> 5, mask
);
652 /* Re-enable EDMA hardware events on the specified channel. */
653 static void edma_resume(struct edma_chan
*echan
)
655 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
656 unsigned int mask
= BIT(channel
& 0x1f);
658 edma_shadow0_write_array(echan
->ecc
, SH_EESR
, channel
>> 5, mask
);
661 static void edma_trigger_channel(struct edma_chan
*echan
)
663 struct edma_cc
*ecc
= echan
->ecc
;
664 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
665 unsigned int mask
= BIT(channel
& 0x1f);
667 edma_shadow0_write_array(ecc
, SH_ESR
, (channel
>> 5), mask
);
669 dev_dbg(ecc
->dev
, "ESR%d %08x\n", (channel
>> 5),
670 edma_shadow0_read_array(ecc
, SH_ESR
, (channel
>> 5)));
673 static void edma_clean_channel(struct edma_chan
*echan
)
675 struct edma_cc
*ecc
= echan
->ecc
;
676 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
677 int j
= (channel
>> 5);
678 unsigned int mask
= BIT(channel
& 0x1f);
680 dev_dbg(ecc
->dev
, "EMR%d %08x\n", j
, edma_read_array(ecc
, EDMA_EMR
, j
));
681 edma_shadow0_write_array(ecc
, SH_ECR
, j
, mask
);
682 /* Clear the corresponding EMR bits */
683 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
685 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
686 edma_write(ecc
, EDMA_CCERRCLR
, BIT(16) | BIT(1) | BIT(0));
689 /* Move channel to a specific event queue */
690 static void edma_assign_channel_eventq(struct edma_chan
*echan
,
691 enum dma_event_q eventq_no
)
693 struct edma_cc
*ecc
= echan
->ecc
;
694 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
695 int bit
= (channel
& 0x7) * 4;
697 /* default to low priority queue */
698 if (eventq_no
== EVENTQ_DEFAULT
)
699 eventq_no
= ecc
->default_queue
;
700 if (eventq_no
>= ecc
->num_tc
)
704 edma_modify_array(ecc
, EDMA_DMAQNUM
, (channel
>> 3), ~(0x7 << bit
),
708 static int edma_alloc_channel(struct edma_chan
*echan
,
709 enum dma_event_q eventq_no
)
711 struct edma_cc
*ecc
= echan
->ecc
;
712 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
714 /* ensure access through shadow region 0 */
715 edma_or_array2(ecc
, EDMA_DRAE
, 0, channel
>> 5, BIT(channel
& 0x1f));
717 /* ensure no events are pending */
720 edma_setup_interrupt(echan
, true);
722 edma_assign_channel_eventq(echan
, eventq_no
);
727 static void edma_free_channel(struct edma_chan
*echan
)
729 /* ensure no events are pending */
731 /* REVISIT should probably take out of shadow region 0 */
732 edma_setup_interrupt(echan
, false);
735 static inline struct edma_cc
*to_edma_cc(struct dma_device
*d
)
737 return container_of(d
, struct edma_cc
, dma_slave
);
740 static inline struct edma_chan
*to_edma_chan(struct dma_chan
*c
)
742 return container_of(c
, struct edma_chan
, vchan
.chan
);
745 static inline struct edma_desc
*to_edma_desc(struct dma_async_tx_descriptor
*tx
)
747 return container_of(tx
, struct edma_desc
, vdesc
.tx
);
750 static void edma_desc_free(struct virt_dma_desc
*vdesc
)
752 kfree(container_of(vdesc
, struct edma_desc
, vdesc
));
755 /* Dispatch a queued descriptor to the controller (caller holds lock) */
756 static void edma_execute(struct edma_chan
*echan
)
758 struct edma_cc
*ecc
= echan
->ecc
;
759 struct virt_dma_desc
*vdesc
;
760 struct edma_desc
*edesc
;
761 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
762 int i
, j
, left
, nslots
;
765 /* Setup is needed for the first transfer */
766 vdesc
= vchan_next_desc(&echan
->vchan
);
769 list_del(&vdesc
->node
);
770 echan
->edesc
= to_edma_desc(&vdesc
->tx
);
773 edesc
= echan
->edesc
;
775 /* Find out how many left */
776 left
= edesc
->pset_nr
- edesc
->processed
;
777 nslots
= min(MAX_NR_SG
, left
);
780 /* Write descriptor PaRAM set(s) */
781 for (i
= 0; i
< nslots
; i
++) {
782 j
= i
+ edesc
->processed
;
783 edma_write_slot(ecc
, echan
->slot
[i
], &edesc
->pset
[j
].param
);
784 edesc
->sg_len
+= edesc
->pset
[j
].len
;
797 j
, echan
->ch_num
, echan
->slot
[i
],
798 edesc
->pset
[j
].param
.opt
,
799 edesc
->pset
[j
].param
.src
,
800 edesc
->pset
[j
].param
.dst
,
801 edesc
->pset
[j
].param
.a_b_cnt
,
802 edesc
->pset
[j
].param
.ccnt
,
803 edesc
->pset
[j
].param
.src_dst_bidx
,
804 edesc
->pset
[j
].param
.src_dst_cidx
,
805 edesc
->pset
[j
].param
.link_bcntrld
);
806 /* Link to the previous slot if not the last set */
807 if (i
!= (nslots
- 1))
808 edma_link(ecc
, echan
->slot
[i
], echan
->slot
[i
+ 1]);
811 edesc
->processed
+= nslots
;
814 * If this is either the last set in a set of SG-list transactions
815 * then setup a link to the dummy slot, this results in all future
816 * events being absorbed and that's OK because we're done
818 if (edesc
->processed
== edesc
->pset_nr
) {
820 edma_link(ecc
, echan
->slot
[nslots
- 1], echan
->slot
[1]);
822 edma_link(ecc
, echan
->slot
[nslots
- 1],
823 echan
->ecc
->dummy_slot
);
828 * This happens due to setup times between intermediate
829 * transfers in long SG lists which have to be broken up into
830 * transfers of MAX_NR_SG
832 dev_dbg(dev
, "missed event on channel %d\n", echan
->ch_num
);
833 edma_clean_channel(echan
);
836 edma_trigger_channel(echan
);
838 } else if (edesc
->processed
<= MAX_NR_SG
) {
839 dev_dbg(dev
, "first transfer starting on channel %d\n",
843 dev_dbg(dev
, "chan: %d: completed %d elements, resuming\n",
844 echan
->ch_num
, edesc
->processed
);
849 static int edma_terminate_all(struct dma_chan
*chan
)
851 struct edma_chan
*echan
= to_edma_chan(chan
);
855 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
858 * Stop DMA activity: we assume the callback will not be called
859 * after edma_dma() returns (even if it does, it will see
860 * echan->edesc is NULL and exit.)
864 /* Move the cyclic channel back to default queue */
865 if (!echan
->tc
&& echan
->edesc
->cyclic
)
866 edma_assign_channel_eventq(echan
, EVENTQ_DEFAULT
);
868 * free the running request descriptor
869 * since it is not in any of the vdesc lists
871 edma_desc_free(&echan
->edesc
->vdesc
);
875 vchan_get_all_descriptors(&echan
->vchan
, &head
);
876 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
877 vchan_dma_desc_free_list(&echan
->vchan
, &head
);
882 static void edma_synchronize(struct dma_chan
*chan
)
884 struct edma_chan
*echan
= to_edma_chan(chan
);
886 vchan_synchronize(&echan
->vchan
);
889 static int edma_slave_config(struct dma_chan
*chan
,
890 struct dma_slave_config
*cfg
)
892 struct edma_chan
*echan
= to_edma_chan(chan
);
894 if (cfg
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
895 cfg
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
898 memcpy(&echan
->cfg
, cfg
, sizeof(echan
->cfg
));
903 static int edma_dma_pause(struct dma_chan
*chan
)
905 struct edma_chan
*echan
= to_edma_chan(chan
);
914 static int edma_dma_resume(struct dma_chan
*chan
)
916 struct edma_chan
*echan
= to_edma_chan(chan
);
923 * A PaRAM set configuration abstraction used by other modes
924 * @chan: Channel who's PaRAM set we're configuring
925 * @pset: PaRAM set to initialize and setup.
926 * @src_addr: Source address of the DMA
927 * @dst_addr: Destination address of the DMA
928 * @burst: In units of dev_width, how much to send
929 * @dev_width: How much is the dev_width
930 * @dma_length: Total length of the DMA transfer
931 * @direction: Direction of the transfer
933 static int edma_config_pset(struct dma_chan
*chan
, struct edma_pset
*epset
,
934 dma_addr_t src_addr
, dma_addr_t dst_addr
, u32 burst
,
935 unsigned int acnt
, unsigned int dma_length
,
936 enum dma_transfer_direction direction
)
938 struct edma_chan
*echan
= to_edma_chan(chan
);
939 struct device
*dev
= chan
->device
->dev
;
940 struct edmacc_param
*param
= &epset
->param
;
941 int bcnt
, ccnt
, cidx
;
942 int src_bidx
, dst_bidx
, src_cidx
, dst_cidx
;
945 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
949 * If the maxburst is equal to the fifo width, use
950 * A-synced transfers. This allows for large contiguous
951 * buffer transfers using only one PaRAM set.
955 * For the A-sync case, bcnt and ccnt are the remainder
956 * and quotient respectively of the division of:
957 * (dma_length / acnt) by (SZ_64K -1). This is so
958 * that in case bcnt over flows, we have ccnt to use.
959 * Note: In A-sync tranfer only, bcntrld is used, but it
960 * only applies for sg_dma_len(sg) >= SZ_64K.
961 * In this case, the best way adopted is- bccnt for the
962 * first frame will be the remainder below. Then for
963 * every successive frame, bcnt will be SZ_64K-1. This
964 * is assured as bcntrld = 0xffff in end of function.
967 ccnt
= dma_length
/ acnt
/ (SZ_64K
- 1);
968 bcnt
= dma_length
/ acnt
- ccnt
* (SZ_64K
- 1);
970 * If bcnt is non-zero, we have a remainder and hence an
971 * extra frame to transfer, so increment ccnt.
980 * If maxburst is greater than the fifo address_width,
981 * use AB-synced transfers where A count is the fifo
982 * address_width and B count is the maxburst. In this
983 * case, we are limited to transfers of C count frames
984 * of (address_width * maxburst) where C count is limited
985 * to SZ_64K-1. This places an upper bound on the length
986 * of an SG segment that can be handled.
990 ccnt
= dma_length
/ (acnt
* bcnt
);
991 if (ccnt
> (SZ_64K
- 1)) {
992 dev_err(dev
, "Exceeded max SG segment size\n");
998 epset
->len
= dma_length
;
1000 if (direction
== DMA_MEM_TO_DEV
) {
1005 epset
->addr
= src_addr
;
1006 } else if (direction
== DMA_DEV_TO_MEM
) {
1011 epset
->addr
= dst_addr
;
1012 } else if (direction
== DMA_MEM_TO_MEM
) {
1018 dev_err(dev
, "%s: direction not implemented yet\n", __func__
);
1022 param
->opt
= EDMA_TCC(EDMA_CHAN_SLOT(echan
->ch_num
));
1023 /* Configure A or AB synchronized transfers */
1025 param
->opt
|= SYNCDIM
;
1027 param
->src
= src_addr
;
1028 param
->dst
= dst_addr
;
1030 param
->src_dst_bidx
= (dst_bidx
<< 16) | src_bidx
;
1031 param
->src_dst_cidx
= (dst_cidx
<< 16) | src_cidx
;
1033 param
->a_b_cnt
= bcnt
<< 16 | acnt
;
1036 * Only time when (bcntrld) auto reload is required is for
1037 * A-sync case, and in this case, a requirement of reload value
1038 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1039 * and then later will be populated by edma_execute.
1041 param
->link_bcntrld
= 0xffffffff;
1045 static struct dma_async_tx_descriptor
*edma_prep_slave_sg(
1046 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1047 unsigned int sg_len
, enum dma_transfer_direction direction
,
1048 unsigned long tx_flags
, void *context
)
1050 struct edma_chan
*echan
= to_edma_chan(chan
);
1051 struct device
*dev
= chan
->device
->dev
;
1052 struct edma_desc
*edesc
;
1053 dma_addr_t src_addr
= 0, dst_addr
= 0;
1054 enum dma_slave_buswidth dev_width
;
1056 struct scatterlist
*sg
;
1059 if (unlikely(!echan
|| !sgl
|| !sg_len
))
1062 if (direction
== DMA_DEV_TO_MEM
) {
1063 src_addr
= echan
->cfg
.src_addr
;
1064 dev_width
= echan
->cfg
.src_addr_width
;
1065 burst
= echan
->cfg
.src_maxburst
;
1066 } else if (direction
== DMA_MEM_TO_DEV
) {
1067 dst_addr
= echan
->cfg
.dst_addr
;
1068 dev_width
= echan
->cfg
.dst_addr_width
;
1069 burst
= echan
->cfg
.dst_maxburst
;
1071 dev_err(dev
, "%s: bad direction: %d\n", __func__
, direction
);
1075 if (dev_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
1076 dev_err(dev
, "%s: Undefined slave buswidth\n", __func__
);
1080 edesc
= kzalloc(sizeof(*edesc
) + sg_len
* sizeof(edesc
->pset
[0]),
1085 edesc
->pset_nr
= sg_len
;
1087 edesc
->direction
= direction
;
1088 edesc
->echan
= echan
;
1090 /* Allocate a PaRAM slot, if needed */
1091 nslots
= min_t(unsigned, MAX_NR_SG
, sg_len
);
1093 for (i
= 0; i
< nslots
; i
++) {
1094 if (echan
->slot
[i
] < 0) {
1096 edma_alloc_slot(echan
->ecc
, EDMA_SLOT_ANY
);
1097 if (echan
->slot
[i
] < 0) {
1099 dev_err(dev
, "%s: Failed to allocate slot\n",
1106 /* Configure PaRAM sets for each SG */
1107 for_each_sg(sgl
, sg
, sg_len
, i
) {
1108 /* Get address for each SG */
1109 if (direction
== DMA_DEV_TO_MEM
)
1110 dst_addr
= sg_dma_address(sg
);
1112 src_addr
= sg_dma_address(sg
);
1114 ret
= edma_config_pset(chan
, &edesc
->pset
[i
], src_addr
,
1115 dst_addr
, burst
, dev_width
,
1116 sg_dma_len(sg
), direction
);
1122 edesc
->absync
= ret
;
1123 edesc
->residue
+= sg_dma_len(sg
);
1125 if (i
== sg_len
- 1)
1126 /* Enable completion interrupt */
1127 edesc
->pset
[i
].param
.opt
|= TCINTEN
;
1128 else if (!((i
+1) % MAX_NR_SG
))
1130 * Enable early completion interrupt for the
1131 * intermediateset. In this case the driver will be
1132 * notified when the paRAM set is submitted to TC. This
1133 * will allow more time to set up the next set of slots.
1135 edesc
->pset
[i
].param
.opt
|= (TCINTEN
| TCCMODE
);
1137 edesc
->residue_stat
= edesc
->residue
;
1139 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1142 static struct dma_async_tx_descriptor
*edma_prep_dma_memcpy(
1143 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1144 size_t len
, unsigned long tx_flags
)
1147 struct edma_desc
*edesc
;
1148 struct device
*dev
= chan
->device
->dev
;
1149 struct edma_chan
*echan
= to_edma_chan(chan
);
1150 unsigned int width
, pset_len
;
1152 if (unlikely(!echan
|| !len
))
1157 * Transfer size less than 64K can be handled with one paRAM
1158 * slot and with one burst.
1166 * Transfer size bigger than 64K will be handled with maximum of
1168 * slot1: (full_length / 32767) times 32767 bytes bursts.
1169 * ACNT = 32767, length1: (full_length / 32767) * 32767
1170 * slot2: the remaining amount of data after slot1.
1171 * ACNT = full_length - length1, length2 = ACNT
1173 * When the full_length is multibple of 32767 one slot can be
1174 * used to complete the transfer.
1177 pset_len
= rounddown(len
, width
);
1178 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1179 if (unlikely(pset_len
== len
))
1185 edesc
= kzalloc(sizeof(*edesc
) + nslots
* sizeof(edesc
->pset
[0]),
1190 edesc
->pset_nr
= nslots
;
1191 edesc
->residue
= edesc
->residue_stat
= len
;
1192 edesc
->direction
= DMA_MEM_TO_MEM
;
1193 edesc
->echan
= echan
;
1195 ret
= edma_config_pset(chan
, &edesc
->pset
[0], src
, dest
, 1,
1196 width
, pset_len
, DMA_MEM_TO_MEM
);
1202 edesc
->absync
= ret
;
1204 edesc
->pset
[0].param
.opt
|= ITCCHEN
;
1206 /* Enable transfer complete interrupt */
1207 edesc
->pset
[0].param
.opt
|= TCINTEN
;
1209 /* Enable transfer complete chaining for the first slot */
1210 edesc
->pset
[0].param
.opt
|= TCCHEN
;
1212 if (echan
->slot
[1] < 0) {
1213 echan
->slot
[1] = edma_alloc_slot(echan
->ecc
,
1215 if (echan
->slot
[1] < 0) {
1217 dev_err(dev
, "%s: Failed to allocate slot\n",
1224 pset_len
= width
= len
% (SZ_32K
- 1);
1226 ret
= edma_config_pset(chan
, &edesc
->pset
[1], src
, dest
, 1,
1227 width
, pset_len
, DMA_MEM_TO_MEM
);
1233 edesc
->pset
[1].param
.opt
|= ITCCHEN
;
1234 edesc
->pset
[1].param
.opt
|= TCINTEN
;
1237 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1240 static struct dma_async_tx_descriptor
*edma_prep_dma_cyclic(
1241 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
1242 size_t period_len
, enum dma_transfer_direction direction
,
1243 unsigned long tx_flags
)
1245 struct edma_chan
*echan
= to_edma_chan(chan
);
1246 struct device
*dev
= chan
->device
->dev
;
1247 struct edma_desc
*edesc
;
1248 dma_addr_t src_addr
, dst_addr
;
1249 enum dma_slave_buswidth dev_width
;
1250 bool use_intermediate
= false;
1254 if (unlikely(!echan
|| !buf_len
|| !period_len
))
1257 if (direction
== DMA_DEV_TO_MEM
) {
1258 src_addr
= echan
->cfg
.src_addr
;
1259 dst_addr
= buf_addr
;
1260 dev_width
= echan
->cfg
.src_addr_width
;
1261 burst
= echan
->cfg
.src_maxburst
;
1262 } else if (direction
== DMA_MEM_TO_DEV
) {
1263 src_addr
= buf_addr
;
1264 dst_addr
= echan
->cfg
.dst_addr
;
1265 dev_width
= echan
->cfg
.dst_addr_width
;
1266 burst
= echan
->cfg
.dst_maxburst
;
1268 dev_err(dev
, "%s: bad direction: %d\n", __func__
, direction
);
1272 if (dev_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
1273 dev_err(dev
, "%s: Undefined slave buswidth\n", __func__
);
1277 if (unlikely(buf_len
% period_len
)) {
1278 dev_err(dev
, "Period should be multiple of Buffer length\n");
1282 nslots
= (buf_len
/ period_len
) + 1;
1285 * Cyclic DMA users such as audio cannot tolerate delays introduced
1286 * by cases where the number of periods is more than the maximum
1287 * number of SGs the EDMA driver can handle at a time. For DMA types
1288 * such as Slave SGs, such delays are tolerable and synchronized,
1289 * but the synchronization is difficult to achieve with Cyclic and
1290 * cannot be guaranteed, so we error out early.
1292 if (nslots
> MAX_NR_SG
) {
1294 * If the burst and period sizes are the same, we can put
1295 * the full buffer into a single period and activate
1296 * intermediate interrupts. This will produce interrupts
1297 * after each burst, which is also after each desired period.
1299 if (burst
== period_len
) {
1300 period_len
= buf_len
;
1302 use_intermediate
= true;
1308 edesc
= kzalloc(sizeof(*edesc
) + nslots
* sizeof(edesc
->pset
[0]),
1314 edesc
->pset_nr
= nslots
;
1315 edesc
->residue
= edesc
->residue_stat
= buf_len
;
1316 edesc
->direction
= direction
;
1317 edesc
->echan
= echan
;
1319 dev_dbg(dev
, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1320 __func__
, echan
->ch_num
, nslots
, period_len
, buf_len
);
1322 for (i
= 0; i
< nslots
; i
++) {
1323 /* Allocate a PaRAM slot, if needed */
1324 if (echan
->slot
[i
] < 0) {
1326 edma_alloc_slot(echan
->ecc
, EDMA_SLOT_ANY
);
1327 if (echan
->slot
[i
] < 0) {
1329 dev_err(dev
, "%s: Failed to allocate slot\n",
1335 if (i
== nslots
- 1) {
1336 memcpy(&edesc
->pset
[i
], &edesc
->pset
[0],
1337 sizeof(edesc
->pset
[0]));
1341 ret
= edma_config_pset(chan
, &edesc
->pset
[i
], src_addr
,
1342 dst_addr
, burst
, dev_width
, period_len
,
1349 if (direction
== DMA_DEV_TO_MEM
)
1350 dst_addr
+= period_len
;
1352 src_addr
+= period_len
;
1354 dev_vdbg(dev
, "%s: Configure period %d of buf:\n", __func__
, i
);
1367 i
, echan
->ch_num
, echan
->slot
[i
],
1368 edesc
->pset
[i
].param
.opt
,
1369 edesc
->pset
[i
].param
.src
,
1370 edesc
->pset
[i
].param
.dst
,
1371 edesc
->pset
[i
].param
.a_b_cnt
,
1372 edesc
->pset
[i
].param
.ccnt
,
1373 edesc
->pset
[i
].param
.src_dst_bidx
,
1374 edesc
->pset
[i
].param
.src_dst_cidx
,
1375 edesc
->pset
[i
].param
.link_bcntrld
);
1377 edesc
->absync
= ret
;
1380 * Enable period interrupt only if it is requested
1382 if (tx_flags
& DMA_PREP_INTERRUPT
) {
1383 edesc
->pset
[i
].param
.opt
|= TCINTEN
;
1385 /* Also enable intermediate interrupts if necessary */
1386 if (use_intermediate
)
1387 edesc
->pset
[i
].param
.opt
|= ITCINTEN
;
1391 /* Place the cyclic channel to highest priority queue */
1393 edma_assign_channel_eventq(echan
, EVENTQ_0
);
1395 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1398 static void edma_completion_handler(struct edma_chan
*echan
)
1400 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
1401 struct edma_desc
*edesc
;
1403 spin_lock(&echan
->vchan
.lock
);
1404 edesc
= echan
->edesc
;
1406 if (edesc
->cyclic
) {
1407 vchan_cyclic_callback(&edesc
->vdesc
);
1408 spin_unlock(&echan
->vchan
.lock
);
1410 } else if (edesc
->processed
== edesc
->pset_nr
) {
1413 vchan_cookie_complete(&edesc
->vdesc
);
1414 echan
->edesc
= NULL
;
1416 dev_dbg(dev
, "Transfer completed on channel %d\n",
1419 dev_dbg(dev
, "Sub transfer completed on channel %d\n",
1424 /* Update statistics for tx_status */
1425 edesc
->residue
-= edesc
->sg_len
;
1426 edesc
->residue_stat
= edesc
->residue
;
1427 edesc
->processed_stat
= edesc
->processed
;
1429 edma_execute(echan
);
1432 spin_unlock(&echan
->vchan
.lock
);
1435 /* eDMA interrupt handler */
1436 static irqreturn_t
dma_irq_handler(int irq
, void *data
)
1438 struct edma_cc
*ecc
= data
;
1448 dev_vdbg(ecc
->dev
, "dma_irq_handler\n");
1450 sh_ipr
= edma_shadow0_read_array(ecc
, SH_IPR
, 0);
1452 sh_ipr
= edma_shadow0_read_array(ecc
, SH_IPR
, 1);
1455 sh_ier
= edma_shadow0_read_array(ecc
, SH_IER
, 1);
1458 sh_ier
= edma_shadow0_read_array(ecc
, SH_IER
, 0);
1466 slot
= __ffs(sh_ipr
);
1467 sh_ipr
&= ~(BIT(slot
));
1469 if (sh_ier
& BIT(slot
)) {
1470 channel
= (bank
<< 5) | slot
;
1471 /* Clear the corresponding IPR bits */
1472 edma_shadow0_write_array(ecc
, SH_ICR
, bank
, BIT(slot
));
1473 edma_completion_handler(&ecc
->slave_chans
[channel
]);
1477 edma_shadow0_write(ecc
, SH_IEVAL
, 1);
1481 static void edma_error_handler(struct edma_chan
*echan
)
1483 struct edma_cc
*ecc
= echan
->ecc
;
1484 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
1485 struct edmacc_param p
;
1490 spin_lock(&echan
->vchan
.lock
);
1492 edma_read_slot(ecc
, echan
->slot
[0], &p
);
1494 * Issue later based on missed flag which will be sure
1496 * (1) we finished transmitting an intermediate slot and
1497 * edma_execute is coming up.
1498 * (2) or we finished current transfer and issue will
1499 * call edma_execute.
1501 * Important note: issuing can be dangerous here and
1502 * lead to some nasty recursion when we are in a NULL
1503 * slot. So we avoid doing so and set the missed flag.
1505 if (p
.a_b_cnt
== 0 && p
.ccnt
== 0) {
1506 dev_dbg(dev
, "Error on null slot, setting miss\n");
1510 * The slot is already programmed but the event got
1511 * missed, so its safe to issue it here.
1513 dev_dbg(dev
, "Missed event, TRIGGERING\n");
1514 edma_clean_channel(echan
);
1517 edma_trigger_channel(echan
);
1519 spin_unlock(&echan
->vchan
.lock
);
1522 static inline bool edma_error_pending(struct edma_cc
*ecc
)
1524 if (edma_read_array(ecc
, EDMA_EMR
, 0) ||
1525 edma_read_array(ecc
, EDMA_EMR
, 1) ||
1526 edma_read(ecc
, EDMA_QEMR
) || edma_read(ecc
, EDMA_CCERR
))
1532 /* eDMA error interrupt handler */
1533 static irqreturn_t
dma_ccerr_handler(int irq
, void *data
)
1535 struct edma_cc
*ecc
= data
;
1538 unsigned int cnt
= 0;
1545 dev_vdbg(ecc
->dev
, "dma_ccerr_handler\n");
1547 if (!edma_error_pending(ecc
)) {
1549 * The registers indicate no pending error event but the irq
1550 * handler has been called.
1551 * Ask eDMA to re-evaluate the error registers.
1553 dev_err(ecc
->dev
, "%s: Error interrupt without error event!\n",
1555 edma_write(ecc
, EDMA_EEVAL
, 1);
1560 /* Event missed register(s) */
1561 for (j
= 0; j
< 2; j
++) {
1564 val
= edma_read_array(ecc
, EDMA_EMR
, j
);
1568 dev_dbg(ecc
->dev
, "EMR%d 0x%08x\n", j
, val
);
1570 for (i
= find_next_bit(&emr
, 32, 0); i
< 32;
1571 i
= find_next_bit(&emr
, 32, i
+ 1)) {
1572 int k
= (j
<< 5) + i
;
1574 /* Clear the corresponding EMR bits */
1575 edma_write_array(ecc
, EDMA_EMCR
, j
, BIT(i
));
1577 edma_shadow0_write_array(ecc
, SH_SECR
, j
,
1579 edma_error_handler(&ecc
->slave_chans
[k
]);
1583 val
= edma_read(ecc
, EDMA_QEMR
);
1585 dev_dbg(ecc
->dev
, "QEMR 0x%02x\n", val
);
1586 /* Not reported, just clear the interrupt reason. */
1587 edma_write(ecc
, EDMA_QEMCR
, val
);
1588 edma_shadow0_write(ecc
, SH_QSECR
, val
);
1591 val
= edma_read(ecc
, EDMA_CCERR
);
1593 dev_warn(ecc
->dev
, "CCERR 0x%08x\n", val
);
1594 /* Not reported, just clear the interrupt reason. */
1595 edma_write(ecc
, EDMA_CCERRCLR
, val
);
1598 if (!edma_error_pending(ecc
))
1604 edma_write(ecc
, EDMA_EEVAL
, 1);
1608 /* Alloc channel resources */
1609 static int edma_alloc_chan_resources(struct dma_chan
*chan
)
1611 struct edma_chan
*echan
= to_edma_chan(chan
);
1612 struct edma_cc
*ecc
= echan
->ecc
;
1613 struct device
*dev
= ecc
->dev
;
1614 enum dma_event_q eventq_no
= EVENTQ_DEFAULT
;
1618 eventq_no
= echan
->tc
->id
;
1619 } else if (ecc
->tc_list
) {
1620 /* memcpy channel */
1621 echan
->tc
= &ecc
->tc_list
[ecc
->info
->default_queue
];
1622 eventq_no
= echan
->tc
->id
;
1625 ret
= edma_alloc_channel(echan
, eventq_no
);
1629 echan
->slot
[0] = edma_alloc_slot(ecc
, echan
->ch_num
);
1630 if (echan
->slot
[0] < 0) {
1631 dev_err(dev
, "Entry slot allocation failed for channel %u\n",
1632 EDMA_CHAN_SLOT(echan
->ch_num
));
1636 /* Set up channel -> slot mapping for the entry slot */
1637 edma_set_chmap(echan
, echan
->slot
[0]);
1638 echan
->alloced
= true;
1640 dev_dbg(dev
, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1641 EDMA_CHAN_SLOT(echan
->ch_num
), chan
->chan_id
,
1642 echan
->hw_triggered
? "HW" : "SW");
1647 edma_free_channel(echan
);
1651 /* Free channel resources */
1652 static void edma_free_chan_resources(struct dma_chan
*chan
)
1654 struct edma_chan
*echan
= to_edma_chan(chan
);
1655 struct device
*dev
= echan
->ecc
->dev
;
1658 /* Terminate transfers */
1661 vchan_free_chan_resources(&echan
->vchan
);
1663 /* Free EDMA PaRAM slots */
1664 for (i
= 0; i
< EDMA_MAX_SLOTS
; i
++) {
1665 if (echan
->slot
[i
] >= 0) {
1666 edma_free_slot(echan
->ecc
, echan
->slot
[i
]);
1667 echan
->slot
[i
] = -1;
1671 /* Set entry slot to the dummy slot */
1672 edma_set_chmap(echan
, echan
->ecc
->dummy_slot
);
1674 /* Free EDMA channel */
1675 if (echan
->alloced
) {
1676 edma_free_channel(echan
);
1677 echan
->alloced
= false;
1681 echan
->hw_triggered
= false;
1683 dev_dbg(dev
, "Free eDMA channel %d for virt channel %d\n",
1684 EDMA_CHAN_SLOT(echan
->ch_num
), chan
->chan_id
);
1687 /* Send pending descriptor to hardware */
1688 static void edma_issue_pending(struct dma_chan
*chan
)
1690 struct edma_chan
*echan
= to_edma_chan(chan
);
1691 unsigned long flags
;
1693 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
1694 if (vchan_issue_pending(&echan
->vchan
) && !echan
->edesc
)
1695 edma_execute(echan
);
1696 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
1700 * This limit exists to avoid a possible infinite loop when waiting for proof
1701 * that a particular transfer is completed. This limit can be hit if there
1702 * are large bursts to/from slow devices or the CPU is never able to catch
1703 * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1704 * RX-FIFO, as many as 55 loops have been seen.
1706 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1708 static u32
edma_residue(struct edma_desc
*edesc
)
1710 bool dst
= edesc
->direction
== DMA_DEV_TO_MEM
;
1711 int loop_count
= EDMA_MAX_TR_WAIT_LOOPS
;
1712 struct edma_chan
*echan
= edesc
->echan
;
1713 struct edma_pset
*pset
= edesc
->pset
;
1714 dma_addr_t done
, pos
;
1718 * We always read the dst/src position from the first RamPar
1719 * pset. That's the one which is active now.
1721 pos
= edma_get_position(echan
->ecc
, echan
->slot
[0], dst
);
1724 * "pos" may represent a transfer request that is still being
1725 * processed by the EDMACC or EDMATC. We will busy wait until
1726 * any one of the situations occurs:
1727 * 1. the DMA hardware is idle
1728 * 2. a new transfer request is setup
1729 * 3. we hit the loop limit
1731 while (edma_read(echan
->ecc
, EDMA_CCSTAT
) & EDMA_CCSTAT_ACTV
) {
1732 /* check if a new transfer request is setup */
1733 if (edma_get_position(echan
->ecc
,
1734 echan
->slot
[0], dst
) != pos
) {
1738 if (!--loop_count
) {
1739 dev_dbg_ratelimited(echan
->vchan
.chan
.device
->dev
,
1740 "%s: timeout waiting for PaRAM update\n",
1749 * Cyclic is simple. Just subtract pset[0].addr from pos.
1751 * We never update edesc->residue in the cyclic case, so we
1752 * can tell the remaining room to the end of the circular
1755 if (edesc
->cyclic
) {
1756 done
= pos
- pset
->addr
;
1757 edesc
->residue_stat
= edesc
->residue
- done
;
1758 return edesc
->residue_stat
;
1762 * For SG operation we catch up with the last processed
1765 pset
+= edesc
->processed_stat
;
1767 for (i
= edesc
->processed_stat
; i
< edesc
->processed
; i
++, pset
++) {
1769 * If we are inside this pset address range, we know
1770 * this is the active one. Get the current delta and
1771 * stop walking the psets.
1773 if (pos
>= pset
->addr
&& pos
< pset
->addr
+ pset
->len
)
1774 return edesc
->residue_stat
- (pos
- pset
->addr
);
1776 /* Otherwise mark it done and update residue_stat. */
1777 edesc
->processed_stat
++;
1778 edesc
->residue_stat
-= pset
->len
;
1780 return edesc
->residue_stat
;
1783 /* Check request completion status */
1784 static enum dma_status
edma_tx_status(struct dma_chan
*chan
,
1785 dma_cookie_t cookie
,
1786 struct dma_tx_state
*txstate
)
1788 struct edma_chan
*echan
= to_edma_chan(chan
);
1789 struct virt_dma_desc
*vdesc
;
1790 enum dma_status ret
;
1791 unsigned long flags
;
1793 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1794 if (ret
== DMA_COMPLETE
|| !txstate
)
1797 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
1798 if (echan
->edesc
&& echan
->edesc
->vdesc
.tx
.cookie
== cookie
)
1799 txstate
->residue
= edma_residue(echan
->edesc
);
1800 else if ((vdesc
= vchan_find_desc(&echan
->vchan
, cookie
)))
1801 txstate
->residue
= to_edma_desc(&vdesc
->tx
)->residue
;
1802 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
1807 static bool edma_is_memcpy_channel(int ch_num
, s32
*memcpy_channels
)
1809 if (!memcpy_channels
)
1811 while (*memcpy_channels
!= -1) {
1812 if (*memcpy_channels
== ch_num
)
1819 #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1820 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1821 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1822 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1824 static void edma_dma_init(struct edma_cc
*ecc
, bool legacy_mode
)
1826 struct dma_device
*s_ddev
= &ecc
->dma_slave
;
1827 struct dma_device
*m_ddev
= NULL
;
1828 s32
*memcpy_channels
= ecc
->info
->memcpy_channels
;
1831 dma_cap_zero(s_ddev
->cap_mask
);
1832 dma_cap_set(DMA_SLAVE
, s_ddev
->cap_mask
);
1833 dma_cap_set(DMA_CYCLIC
, s_ddev
->cap_mask
);
1834 if (ecc
->legacy_mode
&& !memcpy_channels
) {
1836 "Legacy memcpy is enabled, things might not work\n");
1838 dma_cap_set(DMA_MEMCPY
, s_ddev
->cap_mask
);
1839 s_ddev
->device_prep_dma_memcpy
= edma_prep_dma_memcpy
;
1840 s_ddev
->directions
= BIT(DMA_MEM_TO_MEM
);
1843 s_ddev
->device_prep_slave_sg
= edma_prep_slave_sg
;
1844 s_ddev
->device_prep_dma_cyclic
= edma_prep_dma_cyclic
;
1845 s_ddev
->device_alloc_chan_resources
= edma_alloc_chan_resources
;
1846 s_ddev
->device_free_chan_resources
= edma_free_chan_resources
;
1847 s_ddev
->device_issue_pending
= edma_issue_pending
;
1848 s_ddev
->device_tx_status
= edma_tx_status
;
1849 s_ddev
->device_config
= edma_slave_config
;
1850 s_ddev
->device_pause
= edma_dma_pause
;
1851 s_ddev
->device_resume
= edma_dma_resume
;
1852 s_ddev
->device_terminate_all
= edma_terminate_all
;
1853 s_ddev
->device_synchronize
= edma_synchronize
;
1855 s_ddev
->src_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1856 s_ddev
->dst_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1857 s_ddev
->directions
|= (BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
));
1858 s_ddev
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1860 s_ddev
->dev
= ecc
->dev
;
1861 INIT_LIST_HEAD(&s_ddev
->channels
);
1863 if (memcpy_channels
) {
1864 m_ddev
= devm_kzalloc(ecc
->dev
, sizeof(*m_ddev
), GFP_KERNEL
);
1865 ecc
->dma_memcpy
= m_ddev
;
1867 dma_cap_zero(m_ddev
->cap_mask
);
1868 dma_cap_set(DMA_MEMCPY
, m_ddev
->cap_mask
);
1870 m_ddev
->device_prep_dma_memcpy
= edma_prep_dma_memcpy
;
1871 m_ddev
->device_alloc_chan_resources
= edma_alloc_chan_resources
;
1872 m_ddev
->device_free_chan_resources
= edma_free_chan_resources
;
1873 m_ddev
->device_issue_pending
= edma_issue_pending
;
1874 m_ddev
->device_tx_status
= edma_tx_status
;
1875 m_ddev
->device_config
= edma_slave_config
;
1876 m_ddev
->device_pause
= edma_dma_pause
;
1877 m_ddev
->device_resume
= edma_dma_resume
;
1878 m_ddev
->device_terminate_all
= edma_terminate_all
;
1879 m_ddev
->device_synchronize
= edma_synchronize
;
1881 m_ddev
->src_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1882 m_ddev
->dst_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1883 m_ddev
->directions
= BIT(DMA_MEM_TO_MEM
);
1884 m_ddev
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1886 m_ddev
->dev
= ecc
->dev
;
1887 INIT_LIST_HEAD(&m_ddev
->channels
);
1888 } else if (!ecc
->legacy_mode
) {
1889 dev_info(ecc
->dev
, "memcpy is disabled\n");
1892 for (i
= 0; i
< ecc
->num_channels
; i
++) {
1893 struct edma_chan
*echan
= &ecc
->slave_chans
[i
];
1894 echan
->ch_num
= EDMA_CTLR_CHAN(ecc
->id
, i
);
1896 echan
->vchan
.desc_free
= edma_desc_free
;
1898 if (m_ddev
&& edma_is_memcpy_channel(i
, memcpy_channels
))
1899 vchan_init(&echan
->vchan
, m_ddev
);
1901 vchan_init(&echan
->vchan
, s_ddev
);
1903 INIT_LIST_HEAD(&echan
->node
);
1904 for (j
= 0; j
< EDMA_MAX_SLOTS
; j
++)
1905 echan
->slot
[j
] = -1;
1909 static int edma_setup_from_hw(struct device
*dev
, struct edma_soc_info
*pdata
,
1910 struct edma_cc
*ecc
)
1914 s8 (*queue_priority_map
)[2];
1916 /* Decode the eDMA3 configuration from CCCFG register */
1917 cccfg
= edma_read(ecc
, EDMA_CCCFG
);
1919 value
= GET_NUM_REGN(cccfg
);
1920 ecc
->num_region
= BIT(value
);
1922 value
= GET_NUM_DMACH(cccfg
);
1923 ecc
->num_channels
= BIT(value
+ 1);
1925 value
= GET_NUM_QDMACH(cccfg
);
1926 ecc
->num_qchannels
= value
* 2;
1928 value
= GET_NUM_PAENTRY(cccfg
);
1929 ecc
->num_slots
= BIT(value
+ 4);
1931 value
= GET_NUM_EVQUE(cccfg
);
1932 ecc
->num_tc
= value
+ 1;
1934 ecc
->chmap_exist
= (cccfg
& CHMAP_EXIST
) ? true : false;
1936 dev_dbg(dev
, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg
);
1937 dev_dbg(dev
, "num_region: %u\n", ecc
->num_region
);
1938 dev_dbg(dev
, "num_channels: %u\n", ecc
->num_channels
);
1939 dev_dbg(dev
, "num_qchannels: %u\n", ecc
->num_qchannels
);
1940 dev_dbg(dev
, "num_slots: %u\n", ecc
->num_slots
);
1941 dev_dbg(dev
, "num_tc: %u\n", ecc
->num_tc
);
1942 dev_dbg(dev
, "chmap_exist: %s\n", ecc
->chmap_exist
? "yes" : "no");
1944 /* Nothing need to be done if queue priority is provided */
1945 if (pdata
->queue_priority_mapping
)
1949 * Configure TC/queue priority as follows:
1954 * The meaning of priority numbers: 0 highest priority, 7 lowest
1955 * priority. So Q0 is the highest priority queue and the last queue has
1956 * the lowest priority.
1958 queue_priority_map
= devm_kcalloc(dev
, ecc
->num_tc
+ 1, sizeof(s8
),
1960 if (!queue_priority_map
)
1963 for (i
= 0; i
< ecc
->num_tc
; i
++) {
1964 queue_priority_map
[i
][0] = i
;
1965 queue_priority_map
[i
][1] = i
;
1967 queue_priority_map
[i
][0] = -1;
1968 queue_priority_map
[i
][1] = -1;
1970 pdata
->queue_priority_mapping
= queue_priority_map
;
1971 /* Default queue has the lowest priority */
1972 pdata
->default_queue
= i
- 1;
1977 #if IS_ENABLED(CONFIG_OF)
1978 static int edma_xbar_event_map(struct device
*dev
, struct edma_soc_info
*pdata
,
1981 const char pname
[] = "ti,edma-xbar-event-map";
1982 struct resource res
;
1984 s16 (*xbar_chans
)[2];
1985 size_t nelm
= sz
/ sizeof(s16
);
1986 u32 shift
, offset
, mux
;
1989 xbar_chans
= devm_kcalloc(dev
, nelm
+ 2, sizeof(s16
), GFP_KERNEL
);
1993 ret
= of_address_to_resource(dev
->of_node
, 1, &res
);
1997 xbar
= devm_ioremap(dev
, res
.start
, resource_size(&res
));
2001 ret
= of_property_read_u16_array(dev
->of_node
, pname
, (u16
*)xbar_chans
,
2006 /* Invalidate last entry for the other user of this mess */
2008 xbar_chans
[nelm
][0] = -1;
2009 xbar_chans
[nelm
][1] = -1;
2011 for (i
= 0; i
< nelm
; i
++) {
2012 shift
= (xbar_chans
[i
][1] & 0x03) << 3;
2013 offset
= xbar_chans
[i
][1] & 0xfffffffc;
2014 mux
= readl(xbar
+ offset
);
2015 mux
&= ~(0xff << shift
);
2016 mux
|= xbar_chans
[i
][0] << shift
;
2017 writel(mux
, (xbar
+ offset
));
2020 pdata
->xbar_chans
= (const s16 (*)[2]) xbar_chans
;
2024 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
2027 struct edma_soc_info
*info
;
2028 struct property
*prop
;
2031 info
= devm_kzalloc(dev
, sizeof(struct edma_soc_info
), GFP_KERNEL
);
2033 return ERR_PTR(-ENOMEM
);
2036 prop
= of_find_property(dev
->of_node
, "ti,edma-xbar-event-map",
2039 ret
= edma_xbar_event_map(dev
, info
, sz
);
2041 return ERR_PTR(ret
);
2046 /* Get the list of channels allocated to be used for memcpy */
2047 prop
= of_find_property(dev
->of_node
, "ti,edma-memcpy-channels", &sz
);
2049 const char pname
[] = "ti,edma-memcpy-channels";
2050 size_t nelm
= sz
/ sizeof(s32
);
2053 memcpy_ch
= devm_kcalloc(dev
, nelm
+ 1, sizeof(s32
),
2056 return ERR_PTR(-ENOMEM
);
2058 ret
= of_property_read_u32_array(dev
->of_node
, pname
,
2059 (u32
*)memcpy_ch
, nelm
);
2061 return ERR_PTR(ret
);
2063 memcpy_ch
[nelm
] = -1;
2064 info
->memcpy_channels
= memcpy_ch
;
2067 prop
= of_find_property(dev
->of_node
, "ti,edma-reserved-slot-ranges",
2070 const char pname
[] = "ti,edma-reserved-slot-ranges";
2072 s16 (*rsv_slots
)[2];
2073 size_t nelm
= sz
/ sizeof(*tmp
);
2074 struct edma_rsv_info
*rsv_info
;
2080 tmp
= kcalloc(nelm
, sizeof(*tmp
), GFP_KERNEL
);
2082 return ERR_PTR(-ENOMEM
);
2084 rsv_info
= devm_kzalloc(dev
, sizeof(*rsv_info
), GFP_KERNEL
);
2087 return ERR_PTR(-ENOMEM
);
2090 rsv_slots
= devm_kcalloc(dev
, nelm
+ 1, sizeof(*rsv_slots
),
2094 return ERR_PTR(-ENOMEM
);
2097 ret
= of_property_read_u32_array(dev
->of_node
, pname
,
2098 (u32
*)tmp
, nelm
* 2);
2101 return ERR_PTR(ret
);
2104 for (i
= 0; i
< nelm
; i
++) {
2105 rsv_slots
[i
][0] = tmp
[i
][0];
2106 rsv_slots
[i
][1] = tmp
[i
][1];
2108 rsv_slots
[nelm
][0] = -1;
2109 rsv_slots
[nelm
][1] = -1;
2111 info
->rsv
= rsv_info
;
2112 info
->rsv
->rsv_slots
= (const s16 (*)[2])rsv_slots
;
2120 static struct dma_chan
*of_edma_xlate(struct of_phandle_args
*dma_spec
,
2121 struct of_dma
*ofdma
)
2123 struct edma_cc
*ecc
= ofdma
->of_dma_data
;
2124 struct dma_chan
*chan
= NULL
;
2125 struct edma_chan
*echan
;
2128 if (!ecc
|| dma_spec
->args_count
< 1)
2131 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2132 echan
= &ecc
->slave_chans
[i
];
2133 if (echan
->ch_num
== dma_spec
->args
[0]) {
2134 chan
= &echan
->vchan
.chan
;
2142 if (echan
->ecc
->legacy_mode
&& dma_spec
->args_count
== 1)
2145 if (!echan
->ecc
->legacy_mode
&& dma_spec
->args_count
== 2 &&
2146 dma_spec
->args
[1] < echan
->ecc
->num_tc
) {
2147 echan
->tc
= &echan
->ecc
->tc_list
[dma_spec
->args
[1]];
2153 /* The channel is going to be used as HW synchronized */
2154 echan
->hw_triggered
= true;
2155 return dma_get_slave_channel(chan
);
2158 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
2161 return ERR_PTR(-EINVAL
);
2164 static struct dma_chan
*of_edma_xlate(struct of_phandle_args
*dma_spec
,
2165 struct of_dma
*ofdma
)
2171 static int edma_probe(struct platform_device
*pdev
)
2173 struct edma_soc_info
*info
= pdev
->dev
.platform_data
;
2174 s8 (*queue_priority_mapping
)[2];
2176 const s16 (*rsv_slots
)[2];
2177 const s16 (*xbar_chans
)[2];
2180 struct resource
*mem
;
2181 struct device_node
*node
= pdev
->dev
.of_node
;
2182 struct device
*dev
= &pdev
->dev
;
2183 struct edma_cc
*ecc
;
2184 bool legacy_mode
= true;
2188 const struct of_device_id
*match
;
2190 match
= of_match_node(edma_of_ids
, node
);
2191 if (match
&& (*(u32
*)match
->data
) == EDMA_BINDING_TPCC
)
2192 legacy_mode
= false;
2194 info
= edma_setup_info_from_dt(dev
, legacy_mode
);
2196 dev_err(dev
, "failed to get DT data\n");
2197 return PTR_ERR(info
);
2204 pm_runtime_enable(dev
);
2205 ret
= pm_runtime_get_sync(dev
);
2207 dev_err(dev
, "pm_runtime_get_sync() failed\n");
2211 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
2215 ecc
= devm_kzalloc(dev
, sizeof(*ecc
), GFP_KERNEL
);
2221 ecc
->legacy_mode
= legacy_mode
;
2222 /* When booting with DT the pdev->id is -1 */
2226 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "edma3_cc");
2228 dev_dbg(dev
, "mem resource not found, using index 0\n");
2229 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2231 dev_err(dev
, "no mem resource?\n");
2235 ecc
->base
= devm_ioremap_resource(dev
, mem
);
2236 if (IS_ERR(ecc
->base
))
2237 return PTR_ERR(ecc
->base
);
2239 platform_set_drvdata(pdev
, ecc
);
2241 /* Get eDMA3 configuration from IP */
2242 ret
= edma_setup_from_hw(dev
, info
, ecc
);
2246 /* Allocate memory based on the information we got from the IP */
2247 ecc
->slave_chans
= devm_kcalloc(dev
, ecc
->num_channels
,
2248 sizeof(*ecc
->slave_chans
), GFP_KERNEL
);
2249 if (!ecc
->slave_chans
)
2252 ecc
->slot_inuse
= devm_kcalloc(dev
, BITS_TO_LONGS(ecc
->num_slots
),
2253 sizeof(unsigned long), GFP_KERNEL
);
2254 if (!ecc
->slot_inuse
)
2257 ecc
->default_queue
= info
->default_queue
;
2259 for (i
= 0; i
< ecc
->num_slots
; i
++)
2260 edma_write_slot(ecc
, i
, &dummy_paramset
);
2263 /* Set the reserved slots in inuse list */
2264 rsv_slots
= info
->rsv
->rsv_slots
;
2266 for (i
= 0; rsv_slots
[i
][0] != -1; i
++) {
2267 off
= rsv_slots
[i
][0];
2268 ln
= rsv_slots
[i
][1];
2269 set_bits(off
, ln
, ecc
->slot_inuse
);
2274 /* Clear the xbar mapped channels in unused list */
2275 xbar_chans
= info
->xbar_chans
;
2277 for (i
= 0; xbar_chans
[i
][1] != -1; i
++) {
2278 off
= xbar_chans
[i
][1];
2282 irq
= platform_get_irq_byname(pdev
, "edma3_ccint");
2283 if (irq
< 0 && node
)
2284 irq
= irq_of_parse_and_map(node
, 0);
2287 irq_name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s_ccint",
2289 ret
= devm_request_irq(dev
, irq
, dma_irq_handler
, 0, irq_name
,
2292 dev_err(dev
, "CCINT (%d) failed --> %d\n", irq
, ret
);
2298 irq
= platform_get_irq_byname(pdev
, "edma3_ccerrint");
2299 if (irq
< 0 && node
)
2300 irq
= irq_of_parse_and_map(node
, 2);
2303 irq_name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s_ccerrint",
2305 ret
= devm_request_irq(dev
, irq
, dma_ccerr_handler
, 0, irq_name
,
2308 dev_err(dev
, "CCERRINT (%d) failed --> %d\n", irq
, ret
);
2311 ecc
->ccerrint
= irq
;
2314 ecc
->dummy_slot
= edma_alloc_slot(ecc
, EDMA_SLOT_ANY
);
2315 if (ecc
->dummy_slot
< 0) {
2316 dev_err(dev
, "Can't allocate PaRAM dummy slot\n");
2317 return ecc
->dummy_slot
;
2320 queue_priority_mapping
= info
->queue_priority_mapping
;
2322 if (!ecc
->legacy_mode
) {
2323 int lowest_priority
= 0;
2324 struct of_phandle_args tc_args
;
2326 ecc
->tc_list
= devm_kcalloc(dev
, ecc
->num_tc
,
2327 sizeof(*ecc
->tc_list
), GFP_KERNEL
);
2332 ret
= of_parse_phandle_with_fixed_args(node
, "ti,tptcs",
2334 if (ret
|| i
== ecc
->num_tc
)
2337 ecc
->tc_list
[i
].node
= tc_args
.np
;
2338 ecc
->tc_list
[i
].id
= i
;
2339 queue_priority_mapping
[i
][1] = tc_args
.args
[0];
2340 if (queue_priority_mapping
[i
][1] > lowest_priority
) {
2341 lowest_priority
= queue_priority_mapping
[i
][1];
2342 info
->default_queue
= i
;
2347 /* Event queue priority mapping */
2348 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
2349 edma_assign_priority_to_queue(ecc
, queue_priority_mapping
[i
][0],
2350 queue_priority_mapping
[i
][1]);
2352 for (i
= 0; i
< ecc
->num_region
; i
++) {
2353 edma_write_array2(ecc
, EDMA_DRAE
, i
, 0, 0x0);
2354 edma_write_array2(ecc
, EDMA_DRAE
, i
, 1, 0x0);
2355 edma_write_array(ecc
, EDMA_QRAE
, i
, 0x0);
2359 /* Init the dma device and channels */
2360 edma_dma_init(ecc
, legacy_mode
);
2362 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2363 /* Assign all channels to the default queue */
2364 edma_assign_channel_eventq(&ecc
->slave_chans
[i
],
2365 info
->default_queue
);
2366 /* Set entry slot to the dummy slot */
2367 edma_set_chmap(&ecc
->slave_chans
[i
], ecc
->dummy_slot
);
2370 ecc
->dma_slave
.filter
.map
= info
->slave_map
;
2371 ecc
->dma_slave
.filter
.mapcnt
= info
->slavecnt
;
2372 ecc
->dma_slave
.filter
.fn
= edma_filter_fn
;
2374 ret
= dma_async_device_register(&ecc
->dma_slave
);
2376 dev_err(dev
, "slave ddev registration failed (%d)\n", ret
);
2380 if (ecc
->dma_memcpy
) {
2381 ret
= dma_async_device_register(ecc
->dma_memcpy
);
2383 dev_err(dev
, "memcpy ddev registration failed (%d)\n",
2385 dma_async_device_unregister(&ecc
->dma_slave
);
2391 of_dma_controller_register(node
, of_edma_xlate
, ecc
);
2393 dev_info(dev
, "TI EDMA DMA engine driver\n");
2398 edma_free_slot(ecc
, ecc
->dummy_slot
);
2402 static void edma_cleanupp_vchan(struct dma_device
*dmadev
)
2404 struct edma_chan
*echan
, *_echan
;
2406 list_for_each_entry_safe(echan
, _echan
,
2407 &dmadev
->channels
, vchan
.chan
.device_node
) {
2408 list_del(&echan
->vchan
.chan
.device_node
);
2409 tasklet_kill(&echan
->vchan
.task
);
2413 static int edma_remove(struct platform_device
*pdev
)
2415 struct device
*dev
= &pdev
->dev
;
2416 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2418 devm_free_irq(dev
, ecc
->ccint
, ecc
);
2419 devm_free_irq(dev
, ecc
->ccerrint
, ecc
);
2421 edma_cleanupp_vchan(&ecc
->dma_slave
);
2424 of_dma_controller_free(dev
->of_node
);
2425 dma_async_device_unregister(&ecc
->dma_slave
);
2426 if (ecc
->dma_memcpy
)
2427 dma_async_device_unregister(ecc
->dma_memcpy
);
2428 edma_free_slot(ecc
, ecc
->dummy_slot
);
2433 #ifdef CONFIG_PM_SLEEP
2434 static int edma_pm_suspend(struct device
*dev
)
2436 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2437 struct edma_chan
*echan
= ecc
->slave_chans
;
2440 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2441 if (echan
[i
].alloced
)
2442 edma_setup_interrupt(&echan
[i
], false);
2448 static int edma_pm_resume(struct device
*dev
)
2450 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2451 struct edma_chan
*echan
= ecc
->slave_chans
;
2453 s8 (*queue_priority_mapping
)[2];
2455 queue_priority_mapping
= ecc
->info
->queue_priority_mapping
;
2457 /* Event queue priority mapping */
2458 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
2459 edma_assign_priority_to_queue(ecc
, queue_priority_mapping
[i
][0],
2460 queue_priority_mapping
[i
][1]);
2462 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2463 if (echan
[i
].alloced
) {
2464 /* ensure access through shadow region 0 */
2465 edma_or_array2(ecc
, EDMA_DRAE
, 0, i
>> 5,
2468 edma_setup_interrupt(&echan
[i
], true);
2470 /* Set up channel -> slot mapping for the entry slot */
2471 edma_set_chmap(&echan
[i
], echan
[i
].slot
[0]);
2479 static const struct dev_pm_ops edma_pm_ops
= {
2480 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend
, edma_pm_resume
)
2483 static struct platform_driver edma_driver
= {
2484 .probe
= edma_probe
,
2485 .remove
= edma_remove
,
2489 .of_match_table
= edma_of_ids
,
2493 static int edma_tptc_probe(struct platform_device
*pdev
)
2495 pm_runtime_enable(&pdev
->dev
);
2496 return pm_runtime_get_sync(&pdev
->dev
);
2499 static struct platform_driver edma_tptc_driver
= {
2500 .probe
= edma_tptc_probe
,
2502 .name
= "edma3-tptc",
2503 .of_match_table
= edma_tptc_of_ids
,
2507 bool edma_filter_fn(struct dma_chan
*chan
, void *param
)
2511 if (chan
->device
->dev
->driver
== &edma_driver
.driver
) {
2512 struct edma_chan
*echan
= to_edma_chan(chan
);
2513 unsigned ch_req
= *(unsigned *)param
;
2514 if (ch_req
== echan
->ch_num
) {
2515 /* The channel is going to be used as HW synchronized */
2516 echan
->hw_triggered
= true;
2522 EXPORT_SYMBOL(edma_filter_fn
);
2524 static int edma_init(void)
2528 ret
= platform_driver_register(&edma_tptc_driver
);
2532 return platform_driver_register(&edma_driver
);
2534 subsys_initcall(edma_init
);
2536 static void __exit
edma_exit(void)
2538 platform_driver_unregister(&edma_driver
);
2539 platform_driver_unregister(&edma_tptc_driver
);
2541 module_exit(edma_exit
);
2543 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2544 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2545 MODULE_LICENSE("GPL v2");