drivers/dma/idxd/device.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #include <linux/init.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/io-64-nonatomic-lo-hi.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/irq.h>
  10 #include <linux/msi.h>
  11 #include <uapi/linux/idxd.h>
  12 #include "../dmaengine.h"
  13 #include "idxd.h"
  14 #include "registers.h"
  15
  16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
  17                           u32 *status);
  18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
  19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
  20
  21 /* Interrupt control bits */
  22 void idxd_unmask_error_interrupts(struct idxd_device *idxd)
  23 {
  24         union genctrl_reg genctrl;
  25
  26         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  27         genctrl.softerr_int_en = 1;
  28         genctrl.halt_int_en = 1;
  29         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  30 }
  31
  32 void idxd_mask_error_interrupts(struct idxd_device *idxd)
  33 {
  34         union genctrl_reg genctrl;
  35
  36         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  37         genctrl.softerr_int_en = 0;
  38         genctrl.halt_int_en = 0;
  39         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  40 }
  41
  42 static void free_hw_descs(struct idxd_wq *wq)
  43 {
  44         int i;
  45
  46         for (i = 0; i < wq->num_descs; i++)
  47                 kfree(wq->hw_descs[i]);
  48
  49         kfree(wq->hw_descs);
  50 }
  51
  52 static int alloc_hw_descs(struct idxd_wq *wq, int num)
  53 {
  54         struct device *dev = &wq->idxd->pdev->dev;
  55         int i;
  56         int node = dev_to_node(dev);
  57
  58         wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
  59                                     GFP_KERNEL, node);
  60         if (!wq->hw_descs)
  61                 return -ENOMEM;
  62
  63         for (i = 0; i < num; i++) {
  64                 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
  65                                                GFP_KERNEL, node);
  66                 if (!wq->hw_descs[i]) {
  67                         free_hw_descs(wq);
  68                         return -ENOMEM;
  69                 }
  70         }
  71
  72         return 0;
  73 }
  74
  75 static void free_descs(struct idxd_wq *wq)
  76 {
  77         int i;
  78
  79         for (i = 0; i < wq->num_descs; i++)
  80                 kfree(wq->descs[i]);
  81
  82         kfree(wq->descs);
  83 }
  84
  85 static int alloc_descs(struct idxd_wq *wq, int num)
  86 {
  87         struct device *dev = &wq->idxd->pdev->dev;
  88         int i;
  89         int node = dev_to_node(dev);
  90
  91         wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
  92                                  GFP_KERNEL, node);
  93         if (!wq->descs)
  94                 return -ENOMEM;
  95
  96         for (i = 0; i < num; i++) {
  97                 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
  98                                             GFP_KERNEL, node);
  99                 if (!wq->descs[i]) {
 100                         free_descs(wq);
 101                         return -ENOMEM;
 102                 }
 103         }
 104
 105         return 0;
 106 }
 107
 108 /* WQ control bits */
 109 int idxd_wq_alloc_resources(struct idxd_wq *wq)
 110 {
 111         struct idxd_device *idxd = wq->idxd;
 112         struct device *dev = &idxd->pdev->dev;
 113         int rc, num_descs, i;
 114
 115         if (wq->type != IDXD_WQT_KERNEL)
 116                 return 0;
 117
 118         num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
 119         wq->num_descs = num_descs;
 120
 121         rc = alloc_hw_descs(wq, num_descs);
 122         if (rc < 0)
 123                 return rc;
 124
 125         wq->compls_size = num_descs * idxd->data->compl_size;
 126         wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL);
 127         if (!wq->compls) {
 128                 rc = -ENOMEM;
 129                 goto fail_alloc_compls;
 130         }
 131
 132         rc = alloc_descs(wq, num_descs);
 133         if (rc < 0)
 134                 goto fail_alloc_descs;
 135
 136         rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
 137                                      dev_to_node(dev));
 138         if (rc < 0)
 139                 goto fail_sbitmap_init;
 140
 141         for (i = 0; i < num_descs; i++) {
 142                 struct idxd_desc *desc = wq->descs[i];
 143
 144                 desc->hw = wq->hw_descs[i];
 145                 if (idxd->data->type == IDXD_TYPE_DSA)
 146                         desc->completion = &wq->compls[i];
 147                 else if (idxd->data->type == IDXD_TYPE_IAX)
 148                         desc->iax_completion = &wq->iax_compls[i];
 149                 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
 150                 desc->id = i;
 151                 desc->wq = wq;
 152                 desc->cpu = -1;
 153         }
 154
 155         return 0;
 156
 157  fail_sbitmap_init:
 158         free_descs(wq);
 159  fail_alloc_descs:
 160         dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 161  fail_alloc_compls:
 162         free_hw_descs(wq);
 163         return rc;
 164 }
 165
 166 void idxd_wq_free_resources(struct idxd_wq *wq)
 167 {
 168         struct device *dev = &wq->idxd->pdev->dev;
 169
 170         if (wq->type != IDXD_WQT_KERNEL)
 171                 return;
 172
 173         free_hw_descs(wq);
 174         free_descs(wq);
 175         dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 176         sbitmap_queue_free(&wq->sbq);
 177 }
 178
 179 int idxd_wq_enable(struct idxd_wq *wq)
 180 {
 181         struct idxd_device *idxd = wq->idxd;
 182         struct device *dev = &idxd->pdev->dev;
 183         u32 status;
 184
 185         if (wq->state == IDXD_WQ_ENABLED) {
 186                 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
 187                 return 0;
 188         }
 189
 190         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
 191
 192         if (status != IDXD_CMDSTS_SUCCESS &&
 193             status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
 194                 dev_dbg(dev, "WQ enable failed: %#x\n", status);
 195                 return -ENXIO;
 196         }
 197
 198         wq->state = IDXD_WQ_ENABLED;
 199         dev_dbg(dev, "WQ %d enabled\n", wq->id);
 200         return 0;
 201 }
 202
 203 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
 204 {
 205         struct idxd_device *idxd = wq->idxd;
 206         struct device *dev = &idxd->pdev->dev;
 207         u32 status, operand;
 208
 209         dev_dbg(dev, "Disabling WQ %d\n", wq->id);
 210
 211         if (wq->state != IDXD_WQ_ENABLED) {
 212                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 213                 return 0;
 214         }
 215
 216         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 217         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
 218
 219         if (status != IDXD_CMDSTS_SUCCESS) {
 220                 dev_dbg(dev, "WQ disable failed: %#x\n", status);
 221                 return -ENXIO;
 222         }
 223
 224         if (reset_config)
 225                 idxd_wq_disable_cleanup(wq);
 226         wq->state = IDXD_WQ_DISABLED;
 227         dev_dbg(dev, "WQ %d disabled\n", wq->id);
 228         return 0;
 229 }
 230
 231 void idxd_wq_drain(struct idxd_wq *wq)
 232 {
 233         struct idxd_device *idxd = wq->idxd;
 234         struct device *dev = &idxd->pdev->dev;
 235         u32 operand;
 236
 237         if (wq->state != IDXD_WQ_ENABLED) {
 238                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 239                 return;
 240         }
 241
 242         dev_dbg(dev, "Draining WQ %d\n", wq->id);
 243         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 244         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
 245 }
 246
 247 void idxd_wq_reset(struct idxd_wq *wq)
 248 {
 249         struct idxd_device *idxd = wq->idxd;
 250         struct device *dev = &idxd->pdev->dev;
 251         u32 operand;
 252
 253         if (wq->state != IDXD_WQ_ENABLED) {
 254                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 255                 return;
 256         }
 257
 258         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 259         idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
 260         idxd_wq_disable_cleanup(wq);
 261         wq->state = IDXD_WQ_DISABLED;
 262 }
 263
 264 int idxd_wq_map_portal(struct idxd_wq *wq)
 265 {
 266         struct idxd_device *idxd = wq->idxd;
 267         struct pci_dev *pdev = idxd->pdev;
 268         struct device *dev = &pdev->dev;
 269         resource_size_t start;
 270
 271         start = pci_resource_start(pdev, IDXD_WQ_BAR);
 272         start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
 273
 274         wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
 275         if (!wq->portal)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 void idxd_wq_unmap_portal(struct idxd_wq *wq)
 282 {
 283         struct device *dev = &wq->idxd->pdev->dev;
 284
 285         devm_iounmap(dev, wq->portal);
 286         wq->portal = NULL;
 287         wq->portal_offset = 0;
 288 }
 289
 290 void idxd_wqs_unmap_portal(struct idxd_device *idxd)
 291 {
 292         int i;
 293
 294         for (i = 0; i < idxd->max_wqs; i++) {
 295                 struct idxd_wq *wq = idxd->wqs[i];
 296
 297                 if (wq->portal)
 298                         idxd_wq_unmap_portal(wq);
 299         }
 300 }
 301
 302 static void __idxd_wq_set_priv_locked(struct idxd_wq *wq, int priv)
 303 {
 304         struct idxd_device *idxd = wq->idxd;
 305         union wqcfg wqcfg;
 306         unsigned int offset;
 307
 308         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PRIVL_IDX);
 309         spin_lock(&idxd->dev_lock);
 310         wqcfg.bits[WQCFG_PRIVL_IDX] = ioread32(idxd->reg_base + offset);
 311         wqcfg.priv = priv;
 312         wq->wqcfg->bits[WQCFG_PRIVL_IDX] = wqcfg.bits[WQCFG_PRIVL_IDX];
 313         iowrite32(wqcfg.bits[WQCFG_PRIVL_IDX], idxd->reg_base + offset);
 314         spin_unlock(&idxd->dev_lock);
 315 }
 316
 317 static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid)
 318 {
 319         struct idxd_device *idxd = wq->idxd;
 320         union wqcfg wqcfg;
 321         unsigned int offset;
 322
 323         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 324         spin_lock(&idxd->dev_lock);
 325         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 326         wqcfg.pasid_en = 1;
 327         wqcfg.pasid = pasid;
 328         wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX];
 329         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 330         spin_unlock(&idxd->dev_lock);
 331 }
 332
 333 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
 334 {
 335         int rc;
 336
 337         rc = idxd_wq_disable(wq, false);
 338         if (rc < 0)
 339                 return rc;
 340
 341         __idxd_wq_set_pasid_locked(wq, pasid);
 342
 343         rc = idxd_wq_enable(wq);
 344         if (rc < 0)
 345                 return rc;
 346
 347         return 0;
 348 }
 349
 350 int idxd_wq_disable_pasid(struct idxd_wq *wq)
 351 {
 352         struct idxd_device *idxd = wq->idxd;
 353         int rc;
 354         union wqcfg wqcfg;
 355         unsigned int offset;
 356
 357         rc = idxd_wq_disable(wq, false);
 358         if (rc < 0)
 359                 return rc;
 360
 361         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 362         spin_lock(&idxd->dev_lock);
 363         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 364         wqcfg.pasid_en = 0;
 365         wqcfg.pasid = 0;
 366         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 367         spin_unlock(&idxd->dev_lock);
 368
 369         rc = idxd_wq_enable(wq);
 370         if (rc < 0)
 371                 return rc;
 372
 373         return 0;
 374 }
 375
 376 static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
 377 {
 378         struct idxd_device *idxd = wq->idxd;
 379
 380         lockdep_assert_held(&wq->wq_lock);
 381         memset(wq->wqcfg, 0, idxd->wqcfg_size);
 382         wq->type = IDXD_WQT_NONE;
 383         wq->threshold = 0;
 384         wq->priority = 0;
 385         wq->ats_dis = 0;
 386         wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
 387         clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
 388         clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
 389         memset(wq->name, 0, WQ_NAME_SIZE);
 390         wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
 391         wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
 392 }
 393
 394 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
 395 {
 396         lockdep_assert_held(&wq->wq_lock);
 397
 398         wq->size = 0;
 399         wq->group = NULL;
 400 }
 401
 402 static void idxd_wq_ref_release(struct percpu_ref *ref)
 403 {
 404         struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
 405
 406         complete(&wq->wq_dead);
 407 }
 408
 409 int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
 410 {
 411         int rc;
 412
 413         memset(&wq->wq_active, 0, sizeof(wq->wq_active));
 414         rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release,
 415                              PERCPU_REF_ALLOW_REINIT, GFP_KERNEL);
 416         if (rc < 0)
 417                 return rc;
 418         reinit_completion(&wq->wq_dead);
 419         reinit_completion(&wq->wq_resurrect);
 420         return 0;
 421 }
 422
 423 void __idxd_wq_quiesce(struct idxd_wq *wq)
 424 {
 425         lockdep_assert_held(&wq->wq_lock);
 426         reinit_completion(&wq->wq_resurrect);
 427         percpu_ref_kill(&wq->wq_active);
 428         complete_all(&wq->wq_resurrect);
 429         wait_for_completion(&wq->wq_dead);
 430 }
 431
 432 void idxd_wq_quiesce(struct idxd_wq *wq)
 433 {
 434         mutex_lock(&wq->wq_lock);
 435         __idxd_wq_quiesce(wq);
 436         mutex_unlock(&wq->wq_lock);
 437 }
 438
 439 /* Device control bits */
 440 static inline bool idxd_is_enabled(struct idxd_device *idxd)
 441 {
 442         union gensts_reg gensts;
 443
 444         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 445
 446         if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
 447                 return true;
 448         return false;
 449 }
 450
 451 static inline bool idxd_device_is_halted(struct idxd_device *idxd)
 452 {
 453         union gensts_reg gensts;
 454
 455         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 456
 457         return (gensts.state == IDXD_DEVICE_STATE_HALT);
 458 }
 459
 460 /*
 461  * This is function is only used for reset during probe and will
 462  * poll for completion. Once the device is setup with interrupts,
 463  * all commands will be done via interrupt completion.
 464  */
 465 int idxd_device_init_reset(struct idxd_device *idxd)
 466 {
 467         struct device *dev = &idxd->pdev->dev;
 468         union idxd_command_reg cmd;
 469
 470         if (idxd_device_is_halted(idxd)) {
 471                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 472                 return -ENXIO;
 473         }
 474
 475         memset(&cmd, 0, sizeof(cmd));
 476         cmd.cmd = IDXD_CMD_RESET_DEVICE;
 477         dev_dbg(dev, "%s: sending reset for init.\n", __func__);
 478         spin_lock(&idxd->cmd_lock);
 479         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 480
 481         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
 482                IDXD_CMDSTS_ACTIVE)
 483                 cpu_relax();
 484         spin_unlock(&idxd->cmd_lock);
 485         return 0;
 486 }
 487
 488 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
 489                           u32 *status)
 490 {
 491         union idxd_command_reg cmd;
 492         DECLARE_COMPLETION_ONSTACK(done);
 493         u32 stat;
 494
 495         if (idxd_device_is_halted(idxd)) {
 496                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 497                 if (status)
 498                         *status = IDXD_CMDSTS_HW_ERR;
 499                 return;
 500         }
 501
 502         memset(&cmd, 0, sizeof(cmd));
 503         cmd.cmd = cmd_code;
 504         cmd.operand = operand;
 505         cmd.int_req = 1;
 506
 507         spin_lock(&idxd->cmd_lock);
 508         wait_event_lock_irq(idxd->cmd_waitq,
 509                             !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
 510                             idxd->cmd_lock);
 511
 512         dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
 513                 __func__, cmd_code, operand);
 514
 515         idxd->cmd_status = 0;
 516         __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 517         idxd->cmd_done = &done;
 518         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 519
 520         /*
 521          * After command submitted, release lock and go to sleep until
 522          * the command completes via interrupt.
 523          */
 524         spin_unlock(&idxd->cmd_lock);
 525         wait_for_completion(&done);
 526         stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 527         spin_lock(&idxd->cmd_lock);
 528         if (status)
 529                 *status = stat;
 530         idxd->cmd_status = stat & GENMASK(7, 0);
 531
 532         __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 533         /* Wake up other pending commands */
 534         wake_up(&idxd->cmd_waitq);
 535         spin_unlock(&idxd->cmd_lock);
 536 }
 537
 538 int idxd_device_enable(struct idxd_device *idxd)
 539 {
 540         struct device *dev = &idxd->pdev->dev;
 541         u32 status;
 542
 543         if (idxd_is_enabled(idxd)) {
 544                 dev_dbg(dev, "Device already enabled\n");
 545                 return -ENXIO;
 546         }
 547
 548         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
 549
 550         /* If the command is successful or if the device was enabled */
 551         if (status != IDXD_CMDSTS_SUCCESS &&
 552             status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
 553                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 554                 return -ENXIO;
 555         }
 556
 557         idxd->state = IDXD_DEV_ENABLED;
 558         return 0;
 559 }
 560
 561 int idxd_device_disable(struct idxd_device *idxd)
 562 {
 563         struct device *dev = &idxd->pdev->dev;
 564         u32 status;
 565
 566         if (!idxd_is_enabled(idxd)) {
 567                 dev_dbg(dev, "Device is not enabled\n");
 568                 return 0;
 569         }
 570
 571         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
 572
 573         /* If the command is successful or if the device was disabled */
 574         if (status != IDXD_CMDSTS_SUCCESS &&
 575             !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
 576                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 577                 return -ENXIO;
 578         }
 579
 580         idxd_device_clear_state(idxd);
 581         return 0;
 582 }
 583
 584 void idxd_device_reset(struct idxd_device *idxd)
 585 {
 586         idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
 587         idxd_device_clear_state(idxd);
 588         spin_lock(&idxd->dev_lock);
 589         idxd_unmask_error_interrupts(idxd);
 590         spin_unlock(&idxd->dev_lock);
 591 }
 592
 593 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
 594 {
 595         struct device *dev = &idxd->pdev->dev;
 596         u32 operand;
 597
 598         operand = pasid;
 599         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
 600         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
 601         dev_dbg(dev, "pasid %d drained\n", pasid);
 602 }
 603
 604 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
 605                                    enum idxd_interrupt_type irq_type)
 606 {
 607         struct device *dev = &idxd->pdev->dev;
 608         u32 operand, status;
 609
 610         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
 611                 return -EOPNOTSUPP;
 612
 613         dev_dbg(dev, "get int handle, idx %d\n", idx);
 614
 615         operand = idx & GENMASK(15, 0);
 616         if (irq_type == IDXD_IRQ_IMS)
 617                 operand |= CMD_INT_HANDLE_IMS;
 618
 619         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
 620
 621         idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
 622
 623         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 624                 dev_dbg(dev, "request int handle failed: %#x\n", status);
 625                 return -ENXIO;
 626         }
 627
 628         *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
 629
 630         dev_dbg(dev, "int handle acquired: %u\n", *handle);
 631         return 0;
 632 }
 633
 634 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
 635                                    enum idxd_interrupt_type irq_type)
 636 {
 637         struct device *dev = &idxd->pdev->dev;
 638         u32 operand, status;
 639         union idxd_command_reg cmd;
 640
 641         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
 642                 return -EOPNOTSUPP;
 643
 644         dev_dbg(dev, "release int handle, handle %d\n", handle);
 645
 646         memset(&cmd, 0, sizeof(cmd));
 647         operand = handle & GENMASK(15, 0);
 648
 649         if (irq_type == IDXD_IRQ_IMS)
 650                 operand |= CMD_INT_HANDLE_IMS;
 651
 652         cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
 653         cmd.operand = operand;
 654
 655         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
 656
 657         spin_lock(&idxd->cmd_lock);
 658         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 659
 660         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
 661                 cpu_relax();
 662         status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 663         spin_unlock(&idxd->cmd_lock);
 664
 665         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 666                 dev_dbg(dev, "release int handle failed: %#x\n", status);
 667                 return -ENXIO;
 668         }
 669
 670         dev_dbg(dev, "int handle released.\n");
 671         return 0;
 672 }
 673
 674 /* Device configuration bits */
 675 static void idxd_engines_clear_state(struct idxd_device *idxd)
 676 {
 677         struct idxd_engine *engine;
 678         int i;
 679
 680         lockdep_assert_held(&idxd->dev_lock);
 681         for (i = 0; i < idxd->max_engines; i++) {
 682                 engine = idxd->engines[i];
 683                 engine->group = NULL;
 684         }
 685 }
 686
 687 static void idxd_groups_clear_state(struct idxd_device *idxd)
 688 {
 689         struct idxd_group *group;
 690         int i;
 691
 692         lockdep_assert_held(&idxd->dev_lock);
 693         for (i = 0; i < idxd->max_groups; i++) {
 694                 group = idxd->groups[i];
 695                 memset(&group->grpcfg, 0, sizeof(group->grpcfg));
 696                 group->num_engines = 0;
 697                 group->num_wqs = 0;
 698                 group->use_rdbuf_limit = false;
 699                 group->rdbufs_allowed = 0;
 700                 group->rdbufs_reserved = 0;
 701                 if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) {
 702                         group->tc_a = 1;
 703                         group->tc_b = 1;
 704                 } else {
 705                         group->tc_a = -1;
 706                         group->tc_b = -1;
 707                 }
 708         }
 709 }
 710
 711 static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
 712 {
 713         int i;
 714
 715         for (i = 0; i < idxd->max_wqs; i++) {
 716                 struct idxd_wq *wq = idxd->wqs[i];
 717
 718                 if (wq->state == IDXD_WQ_ENABLED) {
 719                         mutex_lock(&wq->wq_lock);
 720                         idxd_wq_disable_cleanup(wq);
 721                         idxd_wq_device_reset_cleanup(wq);
 722                         wq->state = IDXD_WQ_DISABLED;
 723                         mutex_unlock(&wq->wq_lock);
 724                 }
 725         }
 726 }
 727
 728 void idxd_device_clear_state(struct idxd_device *idxd)
 729 {
 730         idxd_device_wqs_clear_state(idxd);
 731         spin_lock(&idxd->dev_lock);
 732         idxd_groups_clear_state(idxd);
 733         idxd_engines_clear_state(idxd);
 734         idxd->state = IDXD_DEV_DISABLED;
 735         spin_unlock(&idxd->dev_lock);
 736 }
 737
 738 static void idxd_group_config_write(struct idxd_group *group)
 739 {
 740         struct idxd_device *idxd = group->idxd;
 741         struct device *dev = &idxd->pdev->dev;
 742         int i;
 743         u32 grpcfg_offset;
 744
 745         dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
 746
 747         /* setup GRPWQCFG */
 748         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
 749                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
 750                 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
 751                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
 752                         group->id, i, grpcfg_offset,
 753                         ioread64(idxd->reg_base + grpcfg_offset));
 754         }
 755
 756         /* setup GRPENGCFG */
 757         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
 758         iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
 759         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
 760                 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
 761
 762         /* setup GRPFLAGS */
 763         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
 764         iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
 765         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
 766                 group->id, grpcfg_offset,
 767                 ioread32(idxd->reg_base + grpcfg_offset));
 768 }
 769
 770 static int idxd_groups_config_write(struct idxd_device *idxd)
 771
 772 {
 773         union gencfg_reg reg;
 774         int i;
 775         struct device *dev = &idxd->pdev->dev;
 776
 777         /* Setup bandwidth rdbuf limit */
 778         if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) {
 779                 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 780                 reg.rdbuf_limit = idxd->rdbuf_limit;
 781                 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 782         }
 783
 784         dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
 785                 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
 786
 787         for (i = 0; i < idxd->max_groups; i++) {
 788                 struct idxd_group *group = idxd->groups[i];
 789
 790                 idxd_group_config_write(group);
 791         }
 792
 793         return 0;
 794 }
 795
 796 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
 797 {
 798         struct pci_dev *pdev = idxd->pdev;
 799
 800         if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
 801                 return true;
 802         return false;
 803 }
 804
 805 static int idxd_wq_config_write(struct idxd_wq *wq)
 806 {
 807         struct idxd_device *idxd = wq->idxd;
 808         struct device *dev = &idxd->pdev->dev;
 809         u32 wq_offset;
 810         int i;
 811
 812         if (!wq->group)
 813                 return 0;
 814
 815         /*
 816          * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
 817          * wq reset. This will copy back the sticky values that are present on some devices.
 818          */
 819         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 820                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 821                 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset);
 822         }
 823
 824         if (wq->size == 0 && wq->type != IDXD_WQT_NONE)
 825                 wq->size = WQ_DEFAULT_QUEUE_DEPTH;
 826
 827         /* byte 0-3 */
 828         wq->wqcfg->wq_size = wq->size;
 829
 830         /* bytes 4-7 */
 831         wq->wqcfg->wq_thresh = wq->threshold;
 832
 833         /* byte 8-11 */
 834         if (wq_dedicated(wq))
 835                 wq->wqcfg->mode = 1;
 836
 837         /*
 838          * The WQ priv bit is set depending on the WQ type. priv = 1 if the
 839          * WQ type is kernel to indicate privileged access. This setting only
 840          * matters for dedicated WQ. According to the DSA spec:
 841          * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
 842          * Privileged Mode Enable field of the PCI Express PASID capability
 843          * is 0, this field must be 0.
 844          *
 845          * In the case of a dedicated kernel WQ that is not able to support
 846          * the PASID cap, then the configuration will be rejected.
 847          */
 848         if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
 849             !idxd_device_pasid_priv_enabled(idxd) &&
 850             wq->type == IDXD_WQT_KERNEL) {
 851                 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
 852                 return -EOPNOTSUPP;
 853         }
 854
 855         wq->wqcfg->priority = wq->priority;
 856
 857         if (idxd->hw.gen_cap.block_on_fault &&
 858             test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags))
 859                 wq->wqcfg->bof = 1;
 860
 861         if (idxd->hw.wq_cap.wq_ats_support)
 862                 wq->wqcfg->wq_ats_disable = wq->ats_dis;
 863
 864         /* bytes 12-15 */
 865         wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
 866         wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
 867
 868         dev_dbg(dev, "WQ %d CFGs\n", wq->id);
 869         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 870                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 871                 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
 872                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
 873                         wq->id, i, wq_offset,
 874                         ioread32(idxd->reg_base + wq_offset));
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int idxd_wqs_config_write(struct idxd_device *idxd)
 881 {
 882         int i, rc;
 883
 884         for (i = 0; i < idxd->max_wqs; i++) {
 885                 struct idxd_wq *wq = idxd->wqs[i];
 886
 887                 rc = idxd_wq_config_write(wq);
 888                 if (rc < 0)
 889                         return rc;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static void idxd_group_flags_setup(struct idxd_device *idxd)
 896 {
 897         int i;
 898
 899         /* TC-A 0 and TC-B 1 should be defaults */
 900         for (i = 0; i < idxd->max_groups; i++) {
 901                 struct idxd_group *group = idxd->groups[i];
 902
 903                 if (group->tc_a == -1)
 904                         group->tc_a = group->grpcfg.flags.tc_a = 0;
 905                 else
 906                         group->grpcfg.flags.tc_a = group->tc_a;
 907                 if (group->tc_b == -1)
 908                         group->tc_b = group->grpcfg.flags.tc_b = 1;
 909                 else
 910                         group->grpcfg.flags.tc_b = group->tc_b;
 911                 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
 912                 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
 913                 if (group->rdbufs_allowed)
 914                         group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
 915                 else
 916                         group->grpcfg.flags.rdbufs_allowed = idxd->max_rdbufs;
 917         }
 918 }
 919
 920 static int idxd_engines_setup(struct idxd_device *idxd)
 921 {
 922         int i, engines = 0;
 923         struct idxd_engine *eng;
 924         struct idxd_group *group;
 925
 926         for (i = 0; i < idxd->max_groups; i++) {
 927                 group = idxd->groups[i];
 928                 group->grpcfg.engines = 0;
 929         }
 930
 931         for (i = 0; i < idxd->max_engines; i++) {
 932                 eng = idxd->engines[i];
 933                 group = eng->group;
 934
 935                 if (!group)
 936                         continue;
 937
 938                 group->grpcfg.engines |= BIT(eng->id);
 939                 engines++;
 940         }
 941
 942         if (!engines)
 943                 return -EINVAL;
 944
 945         return 0;
 946 }
 947
 948 static int idxd_wqs_setup(struct idxd_device *idxd)
 949 {
 950         struct idxd_wq *wq;
 951         struct idxd_group *group;
 952         int i, j, configured = 0;
 953         struct device *dev = &idxd->pdev->dev;
 954
 955         for (i = 0; i < idxd->max_groups; i++) {
 956                 group = idxd->groups[i];
 957                 for (j = 0; j < 4; j++)
 958                         group->grpcfg.wqs[j] = 0;
 959         }
 960
 961         for (i = 0; i < idxd->max_wqs; i++) {
 962                 wq = idxd->wqs[i];
 963                 group = wq->group;
 964
 965                 if (!wq->group)
 966                         continue;
 967
 968                 if (wq_shared(wq) && !wq_shared_supported(wq)) {
 969                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
 970                         dev_warn(dev, "No shared wq support but configured.\n");
 971                         return -EINVAL;
 972                 }
 973
 974                 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
 975                 configured++;
 976         }
 977
 978         if (configured == 0) {
 979                 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
 980                 return -EINVAL;
 981         }
 982
 983         return 0;
 984 }
 985
 986 int idxd_device_config(struct idxd_device *idxd)
 987 {
 988         int rc;
 989
 990         lockdep_assert_held(&idxd->dev_lock);
 991         rc = idxd_wqs_setup(idxd);
 992         if (rc < 0)
 993                 return rc;
 994
 995         rc = idxd_engines_setup(idxd);
 996         if (rc < 0)
 997                 return rc;
 998
 999         idxd_group_flags_setup(idxd);
1000
1001         rc = idxd_wqs_config_write(idxd);
1002         if (rc < 0)
1003                 return rc;
1004
1005         rc = idxd_groups_config_write(idxd);
1006         if (rc < 0)
1007                 return rc;
1008
1009         return 0;
1010 }
1011
1012 static int idxd_wq_load_config(struct idxd_wq *wq)
1013 {
1014         struct idxd_device *idxd = wq->idxd;
1015         struct device *dev = &idxd->pdev->dev;
1016         int wqcfg_offset;
1017         int i;
1018
1019         wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1020         memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1021
1022         wq->size = wq->wqcfg->wq_size;
1023         wq->threshold = wq->wqcfg->wq_thresh;
1024
1025         /* The driver does not support shared WQ mode in read-only config yet */
1026         if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1027                 return -EOPNOTSUPP;
1028
1029         set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1030
1031         wq->priority = wq->wqcfg->priority;
1032
1033         wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
1034         wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift;
1035
1036         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1037                 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1038                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1039         }
1040
1041         return 0;
1042 }
1043
1044 static void idxd_group_load_config(struct idxd_group *group)
1045 {
1046         struct idxd_device *idxd = group->idxd;
1047         struct device *dev = &idxd->pdev->dev;
1048         int i, j, grpcfg_offset;
1049
1050         /*
1051          * Load WQS bit fields
1052          * Iterate through all 256 bits 64 bits at a time
1053          */
1054         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1055                 struct idxd_wq *wq;
1056
1057                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1058                 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1059                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1060                         group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1061
1062                 if (i * 64 >= idxd->max_wqs)
1063                         break;
1064
1065                 /* Iterate through all 64 bits and check for wq set */
1066                 for (j = 0; j < 64; j++) {
1067                         int id = i * 64 + j;
1068
1069                         /* No need to check beyond max wqs */
1070                         if (id >= idxd->max_wqs)
1071                                 break;
1072
1073                         /* Set group assignment for wq if wq bit is set */
1074                         if (group->grpcfg.wqs[i] & BIT(j)) {
1075                                 wq = idxd->wqs[id];
1076                                 wq->group = group;
1077                         }
1078                 }
1079         }
1080
1081         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1082         group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1083         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1084                 grpcfg_offset, group->grpcfg.engines);
1085
1086         /* Iterate through all 64 bits to check engines set */
1087         for (i = 0; i < 64; i++) {
1088                 if (i >= idxd->max_engines)
1089                         break;
1090
1091                 if (group->grpcfg.engines & BIT(i)) {
1092                         struct idxd_engine *engine = idxd->engines[i];
1093
1094                         engine->group = group;
1095                 }
1096         }
1097
1098         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1099         group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset);
1100         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
1101                 group->id, grpcfg_offset, group->grpcfg.flags.bits);
1102 }
1103
1104 int idxd_device_load_config(struct idxd_device *idxd)
1105 {
1106         union gencfg_reg reg;
1107         int i, rc;
1108
1109         reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
1110         idxd->rdbuf_limit = reg.rdbuf_limit;
1111
1112         for (i = 0; i < idxd->max_groups; i++) {
1113                 struct idxd_group *group = idxd->groups[i];
1114
1115                 idxd_group_load_config(group);
1116         }
1117
1118         for (i = 0; i < idxd->max_wqs; i++) {
1119                 struct idxd_wq *wq = idxd->wqs[i];
1120
1121                 rc = idxd_wq_load_config(wq);
1122                 if (rc < 0)
1123                         return rc;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static void idxd_flush_pending_descs(struct idxd_irq_entry *ie)
1130 {
1131         struct idxd_desc *desc, *itr;
1132         struct llist_node *head;
1133         LIST_HEAD(flist);
1134         enum idxd_complete_type ctype;
1135
1136         spin_lock(&ie->list_lock);
1137         head = llist_del_all(&ie->pending_llist);
1138         if (head) {
1139                 llist_for_each_entry_safe(desc, itr, head, llnode)
1140                         list_add_tail(&desc->list, &ie->work_list);
1141         }
1142
1143         list_for_each_entry_safe(desc, itr, &ie->work_list, list)
1144                 list_move_tail(&desc->list, &flist);
1145         spin_unlock(&ie->list_lock);
1146
1147         list_for_each_entry_safe(desc, itr, &flist, list) {
1148                 list_del(&desc->list);
1149                 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT;
1150                 idxd_dma_complete_txd(desc, ctype, true);
1151         }
1152 }
1153
1154 static void idxd_device_set_perm_entry(struct idxd_device *idxd,
1155                                        struct idxd_irq_entry *ie)
1156 {
1157         union msix_perm mperm;
1158
1159         if (ie->pasid == INVALID_IOASID)
1160                 return;
1161
1162         mperm.bits = 0;
1163         mperm.pasid = ie->pasid;
1164         mperm.pasid_en = 1;
1165         iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1166 }
1167
1168 static void idxd_device_clear_perm_entry(struct idxd_device *idxd,
1169                                          struct idxd_irq_entry *ie)
1170 {
1171         iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1172 }
1173
1174 void idxd_wq_free_irq(struct idxd_wq *wq)
1175 {
1176         struct idxd_device *idxd = wq->idxd;
1177         struct idxd_irq_entry *ie = &wq->ie;
1178
1179         if (wq->type != IDXD_WQT_KERNEL)
1180                 return;
1181
1182         free_irq(ie->vector, ie);
1183         idxd_flush_pending_descs(ie);
1184         if (idxd->request_int_handles)
1185                 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1186         idxd_device_clear_perm_entry(idxd, ie);
1187         ie->vector = -1;
1188         ie->int_handle = INVALID_INT_HANDLE;
1189         ie->pasid = INVALID_IOASID;
1190 }
1191
1192 int idxd_wq_request_irq(struct idxd_wq *wq)
1193 {
1194         struct idxd_device *idxd = wq->idxd;
1195         struct pci_dev *pdev = idxd->pdev;
1196         struct device *dev = &pdev->dev;
1197         struct idxd_irq_entry *ie;
1198         int rc;
1199
1200         if (wq->type != IDXD_WQT_KERNEL)
1201                 return 0;
1202
1203         ie = &wq->ie;
1204         ie->vector = pci_irq_vector(pdev, ie->id);
1205         ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : INVALID_IOASID;
1206         idxd_device_set_perm_entry(idxd, ie);
1207
1208         rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie);
1209         if (rc < 0) {
1210                 dev_err(dev, "Failed to request irq %d.\n", ie->vector);
1211                 goto err_irq;
1212         }
1213
1214         if (idxd->request_int_handles) {
1215                 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle,
1216                                                     IDXD_IRQ_MSIX);
1217                 if (rc < 0)
1218                         goto err_int_handle;
1219         } else {
1220                 ie->int_handle = ie->id;
1221         }
1222
1223         return 0;
1224
1225 err_int_handle:
1226         ie->int_handle = INVALID_INT_HANDLE;
1227         free_irq(ie->vector, ie);
1228 err_irq:
1229         idxd_device_clear_perm_entry(idxd, ie);
1230         ie->pasid = INVALID_IOASID;
1231         return rc;
1232 }
1233
1234 int drv_enable_wq(struct idxd_wq *wq)
1235 {
1236         struct idxd_device *idxd = wq->idxd;
1237         struct device *dev = &idxd->pdev->dev;
1238         int rc = -ENXIO;
1239
1240         lockdep_assert_held(&wq->wq_lock);
1241
1242         if (idxd->state != IDXD_DEV_ENABLED) {
1243                 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
1244                 goto err;
1245         }
1246
1247         if (wq->state != IDXD_WQ_DISABLED) {
1248                 dev_dbg(dev, "wq %d already enabled.\n", wq->id);
1249                 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
1250                 rc = -EBUSY;
1251                 goto err;
1252         }
1253
1254         if (!wq->group) {
1255                 dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
1256                 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
1257                 goto err;
1258         }
1259
1260         if (strlen(wq->name) == 0) {
1261                 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
1262                 dev_dbg(dev, "wq %d name not set.\n", wq->id);
1263                 goto err;
1264         }
1265
1266         /* Shared WQ checks */
1267         if (wq_shared(wq)) {
1268                 if (!wq_shared_supported(wq)) {
1269                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
1270                         dev_dbg(dev, "PASID not enabled and shared wq.\n");
1271                         goto err;
1272                 }
1273                 /*
1274                  * Shared wq with the threshold set to 0 means the user
1275                  * did not set the threshold or transitioned from a
1276                  * dedicated wq but did not set threshold. A value
1277                  * of 0 would effectively disable the shared wq. The
1278                  * driver does not allow a value of 0 to be set for
1279                  * threshold via sysfs.
1280                  */
1281                 if (wq->threshold == 0) {
1282                         idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
1283                         dev_dbg(dev, "Shared wq and threshold 0.\n");
1284                         goto err;
1285                 }
1286         }
1287
1288         /*
1289          * In the event that the WQ is configurable for pasid and priv bits.
1290          * For kernel wq, the driver should setup the pasid, pasid_en, and priv bit.
1291          * However, for non-kernel wq, the driver should only set the pasid_en bit for
1292          * shared wq. A dedicated wq that is not 'kernel' type will configure pasid and
1293          * pasid_en later on so there is no need to setup.
1294          */
1295         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
1296                 int priv = 0;
1297
1298                 if (wq_pasid_enabled(wq)) {
1299                         if (is_idxd_wq_kernel(wq) || wq_shared(wq)) {
1300                                 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0;
1301
1302                                 __idxd_wq_set_pasid_locked(wq, pasid);
1303                         }
1304                 }
1305
1306                 if (is_idxd_wq_kernel(wq))
1307                         priv = 1;
1308                 __idxd_wq_set_priv_locked(wq, priv);
1309         }
1310
1311         rc = 0;
1312         spin_lock(&idxd->dev_lock);
1313         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1314                 rc = idxd_device_config(idxd);
1315         spin_unlock(&idxd->dev_lock);
1316         if (rc < 0) {
1317                 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1318                 goto err;
1319         }
1320
1321         rc = idxd_wq_enable(wq);
1322         if (rc < 0) {
1323                 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1324                 goto err;
1325         }
1326
1327         rc = idxd_wq_map_portal(wq);
1328         if (rc < 0) {
1329                 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
1330                 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1331                 goto err_map_portal;
1332         }
1333
1334         wq->client_count = 0;
1335
1336         rc = idxd_wq_request_irq(wq);
1337         if (rc < 0) {
1338                 idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR;
1339                 dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc);
1340                 goto err_irq;
1341         }
1342
1343         rc = idxd_wq_alloc_resources(wq);
1344         if (rc < 0) {
1345                 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR;
1346                 dev_dbg(dev, "WQ resource alloc failed\n");
1347                 goto err_res_alloc;
1348         }
1349
1350         rc = idxd_wq_init_percpu_ref(wq);
1351         if (rc < 0) {
1352                 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR;
1353                 dev_dbg(dev, "percpu_ref setup failed\n");
1354                 goto err_ref;
1355         }
1356
1357         return 0;
1358
1359 err_ref:
1360         idxd_wq_free_resources(wq);
1361 err_res_alloc:
1362         idxd_wq_free_irq(wq);
1363 err_irq:
1364         idxd_wq_unmap_portal(wq);
1365 err_map_portal:
1366         rc = idxd_wq_disable(wq, false);
1367         if (rc < 0)
1368                 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1369 err:
1370         return rc;
1371 }
1372
1373 void drv_disable_wq(struct idxd_wq *wq)
1374 {
1375         struct idxd_device *idxd = wq->idxd;
1376         struct device *dev = &idxd->pdev->dev;
1377
1378         lockdep_assert_held(&wq->wq_lock);
1379
1380         if (idxd_wq_refcount(wq))
1381                 dev_warn(dev, "Clients has claim on wq %d: %d\n",
1382                          wq->id, idxd_wq_refcount(wq));
1383
1384         idxd_wq_free_resources(wq);
1385         idxd_wq_unmap_portal(wq);
1386         idxd_wq_drain(wq);
1387         idxd_wq_free_irq(wq);
1388         idxd_wq_reset(wq);
1389         percpu_ref_exit(&wq->wq_active);
1390         wq->type = IDXD_WQT_NONE;
1391         wq->client_count = 0;
1392 }
1393
1394 int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1395 {
1396         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1397         int rc = 0;
1398
1399         /*
1400          * Device should be in disabled state for the idxd_drv to load. If it's in
1401          * enabled state, then the device was altered outside of driver's control.
1402          * If the state is in halted state, then we don't want to proceed.
1403          */
1404         if (idxd->state != IDXD_DEV_DISABLED) {
1405                 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
1406                 return -ENXIO;
1407         }
1408
1409         /* Device configuration */
1410         spin_lock(&idxd->dev_lock);
1411         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1412                 rc = idxd_device_config(idxd);
1413         spin_unlock(&idxd->dev_lock);
1414         if (rc < 0)
1415                 return -ENXIO;
1416
1417         /* Start device */
1418         rc = idxd_device_enable(idxd);
1419         if (rc < 0)
1420                 return rc;
1421
1422         /* Setup DMA device without channels */
1423         rc = idxd_register_dma_device(idxd);
1424         if (rc < 0) {
1425                 idxd_device_disable(idxd);
1426                 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
1427                 return rc;
1428         }
1429
1430         idxd->cmd_status = 0;
1431         return 0;
1432 }
1433
1434 void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1435 {
1436         struct device *dev = &idxd_dev->conf_dev;
1437         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1438         int i;
1439
1440         for (i = 0; i < idxd->max_wqs; i++) {
1441                 struct idxd_wq *wq = idxd->wqs[i];
1442                 struct device *wq_dev = wq_confdev(wq);
1443
1444                 if (wq->state == IDXD_WQ_DISABLED)
1445                         continue;
1446                 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1447                 device_release_driver(wq_dev);
1448         }
1449
1450         idxd_unregister_dma_device(idxd);
1451         idxd_device_disable(idxd);
1452         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1453                 idxd_device_reset(idxd);
1454 }
1455
1456 static enum idxd_dev_type dev_types[] = {
1457         IDXD_DEV_DSA,
1458         IDXD_DEV_IAX,
1459         IDXD_DEV_NONE,
1460 };
1461
1462 struct idxd_device_driver idxd_drv = {
1463         .type = dev_types,
1464         .probe = idxd_device_drv_probe,
1465         .remove = idxd_device_drv_remove,
1466         .name = "idxd",
1467 };
1468 EXPORT_SYMBOL_GPL(idxd_drv);