2 * drivers/dma/imx-dma.c
4 * This file contains a driver for the Freescale i.MX DMA engine
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
34 #include <linux/platform_data/dma-imx.h>
36 #include "dmaengine.h"
37 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
38 #define IMX_DMA_CHANNELS 16
40 #define IMX_DMA_2D_SLOTS 2
41 #define IMX_DMA_2D_SLOT_A 0
42 #define IMX_DMA_2D_SLOT_B 1
44 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
45 #define IMX_DMA_MEMSIZE_32 (0 << 4)
46 #define IMX_DMA_MEMSIZE_8 (1 << 4)
47 #define IMX_DMA_MEMSIZE_16 (2 << 4)
48 #define IMX_DMA_TYPE_LINEAR (0 << 10)
49 #define IMX_DMA_TYPE_2D (1 << 10)
50 #define IMX_DMA_TYPE_FIFO (2 << 10)
52 #define IMX_DMA_ERR_BURST (1 << 0)
53 #define IMX_DMA_ERR_REQUEST (1 << 1)
54 #define IMX_DMA_ERR_TRANSFER (1 << 2)
55 #define IMX_DMA_ERR_BUFFER (1 << 3)
56 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
58 #define DMA_DCR 0x00 /* Control Register */
59 #define DMA_DISR 0x04 /* Interrupt status Register */
60 #define DMA_DIMR 0x08 /* Interrupt mask Register */
61 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
62 #define DMA_DRTOSR 0x10 /* Request timeout Register */
63 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
64 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
65 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
66 #define DMA_WSRA 0x40 /* W-Size Register A */
67 #define DMA_XSRA 0x44 /* X-Size Register A */
68 #define DMA_YSRA 0x48 /* Y-Size Register A */
69 #define DMA_WSRB 0x4c /* W-Size Register B */
70 #define DMA_XSRB 0x50 /* X-Size Register B */
71 #define DMA_YSRB 0x54 /* Y-Size Register B */
72 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
73 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
74 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
75 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
76 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
77 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
78 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
79 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
80 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
82 #define DCR_DRST (1<<1)
83 #define DCR_DEN (1<<0)
84 #define DBTOCR_EN (1<<15)
85 #define DBTOCR_CNT(x) ((x) & 0x7fff)
86 #define CNTR_CNT(x) ((x) & 0xffffff)
87 #define CCR_ACRPT (1<<14)
88 #define CCR_DMOD_LINEAR (0x0 << 12)
89 #define CCR_DMOD_2D (0x1 << 12)
90 #define CCR_DMOD_FIFO (0x2 << 12)
91 #define CCR_DMOD_EOBFIFO (0x3 << 12)
92 #define CCR_SMOD_LINEAR (0x0 << 10)
93 #define CCR_SMOD_2D (0x1 << 10)
94 #define CCR_SMOD_FIFO (0x2 << 10)
95 #define CCR_SMOD_EOBFIFO (0x3 << 10)
96 #define CCR_MDIR_DEC (1<<9)
97 #define CCR_MSEL_B (1<<8)
98 #define CCR_DSIZ_32 (0x0 << 6)
99 #define CCR_DSIZ_8 (0x1 << 6)
100 #define CCR_DSIZ_16 (0x2 << 6)
101 #define CCR_SSIZ_32 (0x0 << 4)
102 #define CCR_SSIZ_8 (0x1 << 4)
103 #define CCR_SSIZ_16 (0x2 << 4)
104 #define CCR_REN (1<<3)
105 #define CCR_RPT (1<<2)
106 #define CCR_FRC (1<<1)
107 #define CCR_CEN (1<<0)
108 #define RTOR_EN (1<<15)
109 #define RTOR_CLK (1<<14)
110 #define RTOR_PSC (1<<13)
112 enum imxdma_prep_type
{
114 IMXDMA_DESC_INTERLEAVED
,
115 IMXDMA_DESC_SLAVE_SG
,
119 struct imx_dma_2d_config
{
127 struct list_head node
;
128 struct dma_async_tx_descriptor desc
;
129 enum dma_status status
;
133 enum dma_transfer_direction direction
;
134 enum imxdma_prep_type type
;
135 /* For memcpy and interleaved */
136 unsigned int config_port
;
137 unsigned int config_mem
;
138 /* For interleaved transfers */
142 /* For slave sg and cyclic */
143 struct scatterlist
*sg
;
144 unsigned int sgcount
;
147 struct imxdma_channel
{
149 struct timer_list watchdog
;
150 struct imxdma_engine
*imxdma
;
151 unsigned int channel
;
153 struct tasklet_struct dma_tasklet
;
154 struct list_head ld_free
;
155 struct list_head ld_queue
;
156 struct list_head ld_active
;
158 enum dma_slave_buswidth word_size
;
159 dma_addr_t per_address
;
161 struct dma_chan chan
;
162 struct dma_async_tx_descriptor desc
;
163 enum dma_status status
;
165 struct scatterlist
*sg_list
;
178 struct imxdma_engine
{
180 struct device_dma_parameters dma_parms
;
181 struct dma_device dma_device
;
186 struct imx_dma_2d_config slots_2d
[IMX_DMA_2D_SLOTS
];
187 struct imxdma_channel channel
[IMX_DMA_CHANNELS
];
188 enum imx_dma_type devtype
;
191 struct imxdma_filter_data
{
192 struct imxdma_engine
*imxdma
;
196 static struct platform_device_id imx_dma_devtype
[] = {
199 .driver_data
= IMX1_DMA
,
202 .driver_data
= IMX21_DMA
,
205 .driver_data
= IMX27_DMA
,
210 MODULE_DEVICE_TABLE(platform
, imx_dma_devtype
);
212 static const struct of_device_id imx_dma_of_dev_id
[] = {
214 .compatible
= "fsl,imx1-dma",
215 .data
= &imx_dma_devtype
[IMX1_DMA
],
217 .compatible
= "fsl,imx21-dma",
218 .data
= &imx_dma_devtype
[IMX21_DMA
],
220 .compatible
= "fsl,imx27-dma",
221 .data
= &imx_dma_devtype
[IMX27_DMA
],
226 MODULE_DEVICE_TABLE(of
, imx_dma_of_dev_id
);
228 static inline int is_imx1_dma(struct imxdma_engine
*imxdma
)
230 return imxdma
->devtype
== IMX1_DMA
;
233 static inline int is_imx21_dma(struct imxdma_engine
*imxdma
)
235 return imxdma
->devtype
== IMX21_DMA
;
238 static inline int is_imx27_dma(struct imxdma_engine
*imxdma
)
240 return imxdma
->devtype
== IMX27_DMA
;
243 static struct imxdma_channel
*to_imxdma_chan(struct dma_chan
*chan
)
245 return container_of(chan
, struct imxdma_channel
, chan
);
248 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel
*imxdmac
)
250 struct imxdma_desc
*desc
;
252 if (!list_empty(&imxdmac
->ld_active
)) {
253 desc
= list_first_entry(&imxdmac
->ld_active
, struct imxdma_desc
,
255 if (desc
->type
== IMXDMA_DESC_CYCLIC
)
263 static void imx_dmav1_writel(struct imxdma_engine
*imxdma
, unsigned val
,
266 __raw_writel(val
, imxdma
->base
+ offset
);
269 static unsigned imx_dmav1_readl(struct imxdma_engine
*imxdma
, unsigned offset
)
271 return __raw_readl(imxdma
->base
+ offset
);
274 static int imxdma_hw_chain(struct imxdma_channel
*imxdmac
)
276 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
278 if (is_imx27_dma(imxdma
))
279 return imxdmac
->hw_chaining
;
285 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
287 static inline int imxdma_sg_next(struct imxdma_desc
*d
)
289 struct imxdma_channel
*imxdmac
= to_imxdma_chan(d
->desc
.chan
);
290 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
291 struct scatterlist
*sg
= d
->sg
;
294 now
= min(d
->len
, sg_dma_len(sg
));
295 if (d
->len
!= IMX_DMA_LENGTH_LOOP
)
298 if (d
->direction
== DMA_DEV_TO_MEM
)
299 imx_dmav1_writel(imxdma
, sg
->dma_address
,
300 DMA_DAR(imxdmac
->channel
));
302 imx_dmav1_writel(imxdma
, sg
->dma_address
,
303 DMA_SAR(imxdmac
->channel
));
305 imx_dmav1_writel(imxdma
, now
, DMA_CNTR(imxdmac
->channel
));
307 dev_dbg(imxdma
->dev
, " %s channel: %d dst 0x%08x, src 0x%08x, "
308 "size 0x%08x\n", __func__
, imxdmac
->channel
,
309 imx_dmav1_readl(imxdma
, DMA_DAR(imxdmac
->channel
)),
310 imx_dmav1_readl(imxdma
, DMA_SAR(imxdmac
->channel
)),
311 imx_dmav1_readl(imxdma
, DMA_CNTR(imxdmac
->channel
)));
316 static void imxdma_enable_hw(struct imxdma_desc
*d
)
318 struct imxdma_channel
*imxdmac
= to_imxdma_chan(d
->desc
.chan
);
319 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
320 int channel
= imxdmac
->channel
;
323 dev_dbg(imxdma
->dev
, "%s channel %d\n", __func__
, channel
);
325 local_irq_save(flags
);
327 imx_dmav1_writel(imxdma
, 1 << channel
, DMA_DISR
);
328 imx_dmav1_writel(imxdma
, imx_dmav1_readl(imxdma
, DMA_DIMR
) &
329 ~(1 << channel
), DMA_DIMR
);
330 imx_dmav1_writel(imxdma
, imx_dmav1_readl(imxdma
, DMA_CCR(channel
)) |
331 CCR_CEN
| CCR_ACRPT
, DMA_CCR(channel
));
333 if (!is_imx1_dma(imxdma
) &&
334 d
->sg
&& imxdma_hw_chain(imxdmac
)) {
335 d
->sg
= sg_next(d
->sg
);
339 tmp
= imx_dmav1_readl(imxdma
, DMA_CCR(channel
));
340 imx_dmav1_writel(imxdma
, tmp
| CCR_RPT
| CCR_ACRPT
,
345 local_irq_restore(flags
);
348 static void imxdma_disable_hw(struct imxdma_channel
*imxdmac
)
350 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
351 int channel
= imxdmac
->channel
;
354 dev_dbg(imxdma
->dev
, "%s channel %d\n", __func__
, channel
);
356 if (imxdma_hw_chain(imxdmac
))
357 del_timer(&imxdmac
->watchdog
);
359 local_irq_save(flags
);
360 imx_dmav1_writel(imxdma
, imx_dmav1_readl(imxdma
, DMA_DIMR
) |
361 (1 << channel
), DMA_DIMR
);
362 imx_dmav1_writel(imxdma
, imx_dmav1_readl(imxdma
, DMA_CCR(channel
)) &
363 ~CCR_CEN
, DMA_CCR(channel
));
364 imx_dmav1_writel(imxdma
, 1 << channel
, DMA_DISR
);
365 local_irq_restore(flags
);
368 static void imxdma_watchdog(unsigned long data
)
370 struct imxdma_channel
*imxdmac
= (struct imxdma_channel
*)data
;
371 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
372 int channel
= imxdmac
->channel
;
374 imx_dmav1_writel(imxdma
, 0, DMA_CCR(channel
));
376 /* Tasklet watchdog error handler */
377 tasklet_schedule(&imxdmac
->dma_tasklet
);
378 dev_dbg(imxdma
->dev
, "channel %d: watchdog timeout!\n",
382 static irqreturn_t
imxdma_err_handler(int irq
, void *dev_id
)
384 struct imxdma_engine
*imxdma
= dev_id
;
385 unsigned int err_mask
;
389 disr
= imx_dmav1_readl(imxdma
, DMA_DISR
);
391 err_mask
= imx_dmav1_readl(imxdma
, DMA_DBTOSR
) |
392 imx_dmav1_readl(imxdma
, DMA_DRTOSR
) |
393 imx_dmav1_readl(imxdma
, DMA_DSESR
) |
394 imx_dmav1_readl(imxdma
, DMA_DBOSR
);
399 imx_dmav1_writel(imxdma
, disr
& err_mask
, DMA_DISR
);
401 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
402 if (!(err_mask
& (1 << i
)))
406 if (imx_dmav1_readl(imxdma
, DMA_DBTOSR
) & (1 << i
)) {
407 imx_dmav1_writel(imxdma
, 1 << i
, DMA_DBTOSR
);
408 errcode
|= IMX_DMA_ERR_BURST
;
410 if (imx_dmav1_readl(imxdma
, DMA_DRTOSR
) & (1 << i
)) {
411 imx_dmav1_writel(imxdma
, 1 << i
, DMA_DRTOSR
);
412 errcode
|= IMX_DMA_ERR_REQUEST
;
414 if (imx_dmav1_readl(imxdma
, DMA_DSESR
) & (1 << i
)) {
415 imx_dmav1_writel(imxdma
, 1 << i
, DMA_DSESR
);
416 errcode
|= IMX_DMA_ERR_TRANSFER
;
418 if (imx_dmav1_readl(imxdma
, DMA_DBOSR
) & (1 << i
)) {
419 imx_dmav1_writel(imxdma
, 1 << i
, DMA_DBOSR
);
420 errcode
|= IMX_DMA_ERR_BUFFER
;
422 /* Tasklet error handler */
423 tasklet_schedule(&imxdma
->channel
[i
].dma_tasklet
);
426 "DMA timeout on channel %d -%s%s%s%s\n", i
,
427 errcode
& IMX_DMA_ERR_BURST
? " burst" : "",
428 errcode
& IMX_DMA_ERR_REQUEST
? " request" : "",
429 errcode
& IMX_DMA_ERR_TRANSFER
? " transfer" : "",
430 errcode
& IMX_DMA_ERR_BUFFER
? " buffer" : "");
435 static void dma_irq_handle_channel(struct imxdma_channel
*imxdmac
)
437 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
438 int chno
= imxdmac
->channel
;
439 struct imxdma_desc
*desc
;
441 spin_lock(&imxdma
->lock
);
442 if (list_empty(&imxdmac
->ld_active
)) {
443 spin_unlock(&imxdma
->lock
);
447 desc
= list_first_entry(&imxdmac
->ld_active
,
450 spin_unlock(&imxdma
->lock
);
454 desc
->sg
= sg_next(desc
->sg
);
457 imxdma_sg_next(desc
);
459 tmp
= imx_dmav1_readl(imxdma
, DMA_CCR(chno
));
461 if (imxdma_hw_chain(imxdmac
)) {
462 /* FIXME: The timeout should probably be
465 mod_timer(&imxdmac
->watchdog
,
466 jiffies
+ msecs_to_jiffies(500));
468 tmp
|= CCR_CEN
| CCR_RPT
| CCR_ACRPT
;
469 imx_dmav1_writel(imxdma
, tmp
, DMA_CCR(chno
));
471 imx_dmav1_writel(imxdma
, tmp
& ~CCR_CEN
,
476 imx_dmav1_writel(imxdma
, tmp
, DMA_CCR(chno
));
478 if (imxdma_chan_is_doing_cyclic(imxdmac
))
479 /* Tasklet progression */
480 tasklet_schedule(&imxdmac
->dma_tasklet
);
485 if (imxdma_hw_chain(imxdmac
)) {
486 del_timer(&imxdmac
->watchdog
);
492 imx_dmav1_writel(imxdma
, 0, DMA_CCR(chno
));
494 tasklet_schedule(&imxdmac
->dma_tasklet
);
497 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
499 struct imxdma_engine
*imxdma
= dev_id
;
502 if (!is_imx1_dma(imxdma
))
503 imxdma_err_handler(irq
, dev_id
);
505 disr
= imx_dmav1_readl(imxdma
, DMA_DISR
);
507 dev_dbg(imxdma
->dev
, "%s called, disr=0x%08x\n", __func__
, disr
);
509 imx_dmav1_writel(imxdma
, disr
, DMA_DISR
);
510 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
512 dma_irq_handle_channel(&imxdma
->channel
[i
]);
518 static int imxdma_xfer_desc(struct imxdma_desc
*d
)
520 struct imxdma_channel
*imxdmac
= to_imxdma_chan(d
->desc
.chan
);
521 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
526 /* Configure and enable */
528 case IMXDMA_DESC_INTERLEAVED
:
529 /* Try to get a free 2D slot */
530 spin_lock_irqsave(&imxdma
->lock
, flags
);
531 for (i
= 0; i
< IMX_DMA_2D_SLOTS
; i
++) {
532 if ((imxdma
->slots_2d
[i
].count
> 0) &&
533 ((imxdma
->slots_2d
[i
].xsr
!= d
->x
) ||
534 (imxdma
->slots_2d
[i
].ysr
!= d
->y
) ||
535 (imxdma
->slots_2d
[i
].wsr
!= d
->w
)))
541 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
545 imxdma
->slots_2d
[slot
].xsr
= d
->x
;
546 imxdma
->slots_2d
[slot
].ysr
= d
->y
;
547 imxdma
->slots_2d
[slot
].wsr
= d
->w
;
548 imxdma
->slots_2d
[slot
].count
++;
550 imxdmac
->slot_2d
= slot
;
551 imxdmac
->enabled_2d
= true;
552 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
554 if (slot
== IMX_DMA_2D_SLOT_A
) {
555 d
->config_mem
&= ~CCR_MSEL_B
;
556 d
->config_port
&= ~CCR_MSEL_B
;
557 imx_dmav1_writel(imxdma
, d
->x
, DMA_XSRA
);
558 imx_dmav1_writel(imxdma
, d
->y
, DMA_YSRA
);
559 imx_dmav1_writel(imxdma
, d
->w
, DMA_WSRA
);
561 d
->config_mem
|= CCR_MSEL_B
;
562 d
->config_port
|= CCR_MSEL_B
;
563 imx_dmav1_writel(imxdma
, d
->x
, DMA_XSRB
);
564 imx_dmav1_writel(imxdma
, d
->y
, DMA_YSRB
);
565 imx_dmav1_writel(imxdma
, d
->w
, DMA_WSRB
);
568 * We fall-through here intentionally, since a 2D transfer is
569 * similar to MEMCPY just adding the 2D slot configuration.
571 case IMXDMA_DESC_MEMCPY
:
572 imx_dmav1_writel(imxdma
, d
->src
, DMA_SAR(imxdmac
->channel
));
573 imx_dmav1_writel(imxdma
, d
->dest
, DMA_DAR(imxdmac
->channel
));
574 imx_dmav1_writel(imxdma
, d
->config_mem
| (d
->config_port
<< 2),
575 DMA_CCR(imxdmac
->channel
));
577 imx_dmav1_writel(imxdma
, d
->len
, DMA_CNTR(imxdmac
->channel
));
579 dev_dbg(imxdma
->dev
, "%s channel: %d dest=0x%08x src=0x%08x "
580 "dma_length=%d\n", __func__
, imxdmac
->channel
,
581 d
->dest
, d
->src
, d
->len
);
584 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
585 case IMXDMA_DESC_CYCLIC
:
586 case IMXDMA_DESC_SLAVE_SG
:
587 if (d
->direction
== DMA_DEV_TO_MEM
) {
588 imx_dmav1_writel(imxdma
, imxdmac
->per_address
,
589 DMA_SAR(imxdmac
->channel
));
590 imx_dmav1_writel(imxdma
, imxdmac
->ccr_from_device
,
591 DMA_CCR(imxdmac
->channel
));
593 dev_dbg(imxdma
->dev
, "%s channel: %d sg=%p sgcount=%d "
594 "total length=%d dev_addr=0x%08x (dev2mem)\n",
595 __func__
, imxdmac
->channel
, d
->sg
, d
->sgcount
,
596 d
->len
, imxdmac
->per_address
);
597 } else if (d
->direction
== DMA_MEM_TO_DEV
) {
598 imx_dmav1_writel(imxdma
, imxdmac
->per_address
,
599 DMA_DAR(imxdmac
->channel
));
600 imx_dmav1_writel(imxdma
, imxdmac
->ccr_to_device
,
601 DMA_CCR(imxdmac
->channel
));
603 dev_dbg(imxdma
->dev
, "%s channel: %d sg=%p sgcount=%d "
604 "total length=%d dev_addr=0x%08x (mem2dev)\n",
605 __func__
, imxdmac
->channel
, d
->sg
, d
->sgcount
,
606 d
->len
, imxdmac
->per_address
);
608 dev_err(imxdma
->dev
, "%s channel: %d bad dma mode\n",
609 __func__
, imxdmac
->channel
);
623 static void imxdma_tasklet(unsigned long data
)
625 struct imxdma_channel
*imxdmac
= (void *)data
;
626 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
627 struct imxdma_desc
*desc
;
629 spin_lock(&imxdma
->lock
);
631 if (list_empty(&imxdmac
->ld_active
)) {
632 /* Someone might have called terminate all */
635 desc
= list_first_entry(&imxdmac
->ld_active
, struct imxdma_desc
, node
);
637 if (desc
->desc
.callback
)
638 desc
->desc
.callback(desc
->desc
.callback_param
);
640 /* If we are dealing with a cyclic descriptor, keep it on ld_active
641 * and dont mark the descriptor as complete.
642 * Only in non-cyclic cases it would be marked as complete
644 if (imxdma_chan_is_doing_cyclic(imxdmac
))
647 dma_cookie_complete(&desc
->desc
);
649 /* Free 2D slot if it was an interleaved transfer */
650 if (imxdmac
->enabled_2d
) {
651 imxdma
->slots_2d
[imxdmac
->slot_2d
].count
--;
652 imxdmac
->enabled_2d
= false;
655 list_move_tail(imxdmac
->ld_active
.next
, &imxdmac
->ld_free
);
657 if (!list_empty(&imxdmac
->ld_queue
)) {
658 desc
= list_first_entry(&imxdmac
->ld_queue
, struct imxdma_desc
,
660 list_move_tail(imxdmac
->ld_queue
.next
, &imxdmac
->ld_active
);
661 if (imxdma_xfer_desc(desc
) < 0)
662 dev_warn(imxdma
->dev
, "%s: channel: %d couldn't xfer desc\n",
663 __func__
, imxdmac
->channel
);
666 spin_unlock(&imxdma
->lock
);
669 static int imxdma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
672 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
673 struct dma_slave_config
*dmaengine_cfg
= (void *)arg
;
674 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
676 unsigned int mode
= 0;
679 case DMA_TERMINATE_ALL
:
680 imxdma_disable_hw(imxdmac
);
682 spin_lock_irqsave(&imxdma
->lock
, flags
);
683 list_splice_tail_init(&imxdmac
->ld_active
, &imxdmac
->ld_free
);
684 list_splice_tail_init(&imxdmac
->ld_queue
, &imxdmac
->ld_free
);
685 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
687 case DMA_SLAVE_CONFIG
:
688 if (dmaengine_cfg
->direction
== DMA_DEV_TO_MEM
) {
689 imxdmac
->per_address
= dmaengine_cfg
->src_addr
;
690 imxdmac
->watermark_level
= dmaengine_cfg
->src_maxburst
;
691 imxdmac
->word_size
= dmaengine_cfg
->src_addr_width
;
693 imxdmac
->per_address
= dmaengine_cfg
->dst_addr
;
694 imxdmac
->watermark_level
= dmaengine_cfg
->dst_maxburst
;
695 imxdmac
->word_size
= dmaengine_cfg
->dst_addr_width
;
698 switch (imxdmac
->word_size
) {
699 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
700 mode
= IMX_DMA_MEMSIZE_8
;
702 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
703 mode
= IMX_DMA_MEMSIZE_16
;
706 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
707 mode
= IMX_DMA_MEMSIZE_32
;
711 imxdmac
->hw_chaining
= 0;
713 imxdmac
->ccr_from_device
= (mode
| IMX_DMA_TYPE_FIFO
) |
714 ((IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
) << 2) |
716 imxdmac
->ccr_to_device
=
717 (IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
) |
718 ((mode
| IMX_DMA_TYPE_FIFO
) << 2) | CCR_REN
;
719 imx_dmav1_writel(imxdma
, imxdmac
->dma_request
,
720 DMA_RSSR(imxdmac
->channel
));
722 /* Set burst length */
723 imx_dmav1_writel(imxdma
, imxdmac
->watermark_level
*
724 imxdmac
->word_size
, DMA_BLR(imxdmac
->channel
));
734 static enum dma_status
imxdma_tx_status(struct dma_chan
*chan
,
736 struct dma_tx_state
*txstate
)
738 return dma_cookie_status(chan
, cookie
, txstate
);
741 static dma_cookie_t
imxdma_tx_submit(struct dma_async_tx_descriptor
*tx
)
743 struct imxdma_channel
*imxdmac
= to_imxdma_chan(tx
->chan
);
744 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
748 spin_lock_irqsave(&imxdma
->lock
, flags
);
749 list_move_tail(imxdmac
->ld_free
.next
, &imxdmac
->ld_queue
);
750 cookie
= dma_cookie_assign(tx
);
751 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
756 static int imxdma_alloc_chan_resources(struct dma_chan
*chan
)
758 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
759 struct imx_dma_data
*data
= chan
->private;
762 imxdmac
->dma_request
= data
->dma_request
;
764 while (imxdmac
->descs_allocated
< IMXDMA_MAX_CHAN_DESCRIPTORS
) {
765 struct imxdma_desc
*desc
;
767 desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
770 __memzero(&desc
->desc
, sizeof(struct dma_async_tx_descriptor
));
771 dma_async_tx_descriptor_init(&desc
->desc
, chan
);
772 desc
->desc
.tx_submit
= imxdma_tx_submit
;
773 /* txd.flags will be overwritten in prep funcs */
774 desc
->desc
.flags
= DMA_CTRL_ACK
;
775 desc
->status
= DMA_SUCCESS
;
777 list_add_tail(&desc
->node
, &imxdmac
->ld_free
);
778 imxdmac
->descs_allocated
++;
781 if (!imxdmac
->descs_allocated
)
784 return imxdmac
->descs_allocated
;
787 static void imxdma_free_chan_resources(struct dma_chan
*chan
)
789 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
790 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
791 struct imxdma_desc
*desc
, *_desc
;
794 spin_lock_irqsave(&imxdma
->lock
, flags
);
796 imxdma_disable_hw(imxdmac
);
797 list_splice_tail_init(&imxdmac
->ld_active
, &imxdmac
->ld_free
);
798 list_splice_tail_init(&imxdmac
->ld_queue
, &imxdmac
->ld_free
);
800 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
802 list_for_each_entry_safe(desc
, _desc
, &imxdmac
->ld_free
, node
) {
804 imxdmac
->descs_allocated
--;
806 INIT_LIST_HEAD(&imxdmac
->ld_free
);
808 if (imxdmac
->sg_list
) {
809 kfree(imxdmac
->sg_list
);
810 imxdmac
->sg_list
= NULL
;
814 static struct dma_async_tx_descriptor
*imxdma_prep_slave_sg(
815 struct dma_chan
*chan
, struct scatterlist
*sgl
,
816 unsigned int sg_len
, enum dma_transfer_direction direction
,
817 unsigned long flags
, void *context
)
819 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
820 struct scatterlist
*sg
;
821 int i
, dma_length
= 0;
822 struct imxdma_desc
*desc
;
824 if (list_empty(&imxdmac
->ld_free
) ||
825 imxdma_chan_is_doing_cyclic(imxdmac
))
828 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
830 for_each_sg(sgl
, sg
, sg_len
, i
) {
831 dma_length
+= sg_dma_len(sg
);
834 switch (imxdmac
->word_size
) {
835 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
836 if (sg_dma_len(sgl
) & 3 || sgl
->dma_address
& 3)
839 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
840 if (sg_dma_len(sgl
) & 1 || sgl
->dma_address
& 1)
843 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
849 desc
->type
= IMXDMA_DESC_SLAVE_SG
;
851 desc
->sgcount
= sg_len
;
852 desc
->len
= dma_length
;
853 desc
->direction
= direction
;
854 if (direction
== DMA_DEV_TO_MEM
) {
855 desc
->src
= imxdmac
->per_address
;
857 desc
->dest
= imxdmac
->per_address
;
859 desc
->desc
.callback
= NULL
;
860 desc
->desc
.callback_param
= NULL
;
865 static struct dma_async_tx_descriptor
*imxdma_prep_dma_cyclic(
866 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
867 size_t period_len
, enum dma_transfer_direction direction
,
868 unsigned long flags
, void *context
)
870 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
871 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
872 struct imxdma_desc
*desc
;
874 unsigned int periods
= buf_len
/ period_len
;
876 dev_dbg(imxdma
->dev
, "%s channel: %d buf_len=%d period_len=%d\n",
877 __func__
, imxdmac
->channel
, buf_len
, period_len
);
879 if (list_empty(&imxdmac
->ld_free
) ||
880 imxdma_chan_is_doing_cyclic(imxdmac
))
883 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
885 kfree(imxdmac
->sg_list
);
887 imxdmac
->sg_list
= kcalloc(periods
+ 1,
888 sizeof(struct scatterlist
), GFP_KERNEL
);
889 if (!imxdmac
->sg_list
)
892 sg_init_table(imxdmac
->sg_list
, periods
);
894 for (i
= 0; i
< periods
; i
++) {
895 imxdmac
->sg_list
[i
].page_link
= 0;
896 imxdmac
->sg_list
[i
].offset
= 0;
897 imxdmac
->sg_list
[i
].dma_address
= dma_addr
;
898 sg_dma_len(&imxdmac
->sg_list
[i
]) = period_len
;
899 dma_addr
+= period_len
;
903 imxdmac
->sg_list
[periods
].offset
= 0;
904 sg_dma_len(&imxdmac
->sg_list
[periods
]) = 0;
905 imxdmac
->sg_list
[periods
].page_link
=
906 ((unsigned long)imxdmac
->sg_list
| 0x01) & ~0x02;
908 desc
->type
= IMXDMA_DESC_CYCLIC
;
909 desc
->sg
= imxdmac
->sg_list
;
910 desc
->sgcount
= periods
;
911 desc
->len
= IMX_DMA_LENGTH_LOOP
;
912 desc
->direction
= direction
;
913 if (direction
== DMA_DEV_TO_MEM
) {
914 desc
->src
= imxdmac
->per_address
;
916 desc
->dest
= imxdmac
->per_address
;
918 desc
->desc
.callback
= NULL
;
919 desc
->desc
.callback_param
= NULL
;
924 static struct dma_async_tx_descriptor
*imxdma_prep_dma_memcpy(
925 struct dma_chan
*chan
, dma_addr_t dest
,
926 dma_addr_t src
, size_t len
, unsigned long flags
)
928 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
929 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
930 struct imxdma_desc
*desc
;
932 dev_dbg(imxdma
->dev
, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
933 __func__
, imxdmac
->channel
, src
, dest
, len
);
935 if (list_empty(&imxdmac
->ld_free
) ||
936 imxdma_chan_is_doing_cyclic(imxdmac
))
939 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
941 desc
->type
= IMXDMA_DESC_MEMCPY
;
945 desc
->direction
= DMA_MEM_TO_MEM
;
946 desc
->config_port
= IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
;
947 desc
->config_mem
= IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
;
948 desc
->desc
.callback
= NULL
;
949 desc
->desc
.callback_param
= NULL
;
954 static struct dma_async_tx_descriptor
*imxdma_prep_dma_interleaved(
955 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
958 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
959 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
960 struct imxdma_desc
*desc
;
962 dev_dbg(imxdma
->dev
, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
963 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__
,
964 imxdmac
->channel
, xt
->src_start
, xt
->dst_start
,
965 xt
->src_sgl
? "true" : "false", xt
->dst_sgl
? "true" : "false",
966 xt
->numf
, xt
->frame_size
);
968 if (list_empty(&imxdmac
->ld_free
) ||
969 imxdma_chan_is_doing_cyclic(imxdmac
))
972 if (xt
->frame_size
!= 1 || xt
->numf
<= 0 || xt
->dir
!= DMA_MEM_TO_MEM
)
975 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
977 desc
->type
= IMXDMA_DESC_INTERLEAVED
;
978 desc
->src
= xt
->src_start
;
979 desc
->dest
= xt
->dst_start
;
980 desc
->x
= xt
->sgl
[0].size
;
982 desc
->w
= xt
->sgl
[0].icg
+ desc
->x
;
983 desc
->len
= desc
->x
* desc
->y
;
984 desc
->direction
= DMA_MEM_TO_MEM
;
985 desc
->config_port
= IMX_DMA_MEMSIZE_32
;
986 desc
->config_mem
= IMX_DMA_MEMSIZE_32
;
988 desc
->config_mem
|= IMX_DMA_TYPE_2D
;
990 desc
->config_port
|= IMX_DMA_TYPE_2D
;
991 desc
->desc
.callback
= NULL
;
992 desc
->desc
.callback_param
= NULL
;
997 static void imxdma_issue_pending(struct dma_chan
*chan
)
999 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
1000 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
1001 struct imxdma_desc
*desc
;
1002 unsigned long flags
;
1004 spin_lock_irqsave(&imxdma
->lock
, flags
);
1005 if (list_empty(&imxdmac
->ld_active
) &&
1006 !list_empty(&imxdmac
->ld_queue
)) {
1007 desc
= list_first_entry(&imxdmac
->ld_queue
,
1008 struct imxdma_desc
, node
);
1010 if (imxdma_xfer_desc(desc
) < 0) {
1011 dev_warn(imxdma
->dev
,
1012 "%s: channel: %d couldn't issue DMA xfer\n",
1013 __func__
, imxdmac
->channel
);
1015 list_move_tail(imxdmac
->ld_queue
.next
,
1016 &imxdmac
->ld_active
);
1019 spin_unlock_irqrestore(&imxdma
->lock
, flags
);
1022 static bool imxdma_filter_fn(struct dma_chan
*chan
, void *param
)
1024 struct imxdma_filter_data
*fdata
= param
;
1025 struct imxdma_channel
*imxdma_chan
= to_imxdma_chan(chan
);
1027 if (chan
->device
->dev
!= fdata
->imxdma
->dev
)
1030 imxdma_chan
->dma_request
= fdata
->request
;
1031 chan
->private = NULL
;
1036 static struct dma_chan
*imxdma_xlate(struct of_phandle_args
*dma_spec
,
1037 struct of_dma
*ofdma
)
1039 int count
= dma_spec
->args_count
;
1040 struct imxdma_engine
*imxdma
= ofdma
->of_dma_data
;
1041 struct imxdma_filter_data fdata
= {
1048 fdata
.request
= dma_spec
->args
[0];
1050 return dma_request_channel(imxdma
->dma_device
.cap_mask
,
1051 imxdma_filter_fn
, &fdata
);
1054 static int __init
imxdma_probe(struct platform_device
*pdev
)
1056 struct imxdma_engine
*imxdma
;
1057 struct resource
*res
;
1058 const struct of_device_id
*of_id
;
1062 of_id
= of_match_device(imx_dma_of_dev_id
, &pdev
->dev
);
1064 pdev
->id_entry
= of_id
->data
;
1066 imxdma
= devm_kzalloc(&pdev
->dev
, sizeof(*imxdma
), GFP_KERNEL
);
1070 imxdma
->devtype
= pdev
->id_entry
->driver_data
;
1072 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1073 imxdma
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1074 if (IS_ERR(imxdma
->base
))
1075 return PTR_ERR(imxdma
->base
);
1077 irq
= platform_get_irq(pdev
, 0);
1081 imxdma
->dma_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
1082 if (IS_ERR(imxdma
->dma_ipg
))
1083 return PTR_ERR(imxdma
->dma_ipg
);
1085 imxdma
->dma_ahb
= devm_clk_get(&pdev
->dev
, "ahb");
1086 if (IS_ERR(imxdma
->dma_ahb
))
1087 return PTR_ERR(imxdma
->dma_ahb
);
1089 clk_prepare_enable(imxdma
->dma_ipg
);
1090 clk_prepare_enable(imxdma
->dma_ahb
);
1092 /* reset DMA module */
1093 imx_dmav1_writel(imxdma
, DCR_DRST
, DMA_DCR
);
1095 if (is_imx1_dma(imxdma
)) {
1096 ret
= devm_request_irq(&pdev
->dev
, irq
,
1097 dma_irq_handler
, 0, "DMA", imxdma
);
1099 dev_warn(imxdma
->dev
, "Can't register IRQ for DMA\n");
1103 irq_err
= platform_get_irq(pdev
, 1);
1109 ret
= devm_request_irq(&pdev
->dev
, irq_err
,
1110 imxdma_err_handler
, 0, "DMA", imxdma
);
1112 dev_warn(imxdma
->dev
, "Can't register ERRIRQ for DMA\n");
1117 /* enable DMA module */
1118 imx_dmav1_writel(imxdma
, DCR_DEN
, DMA_DCR
);
1120 /* clear all interrupts */
1121 imx_dmav1_writel(imxdma
, (1 << IMX_DMA_CHANNELS
) - 1, DMA_DISR
);
1123 /* disable interrupts */
1124 imx_dmav1_writel(imxdma
, (1 << IMX_DMA_CHANNELS
) - 1, DMA_DIMR
);
1126 INIT_LIST_HEAD(&imxdma
->dma_device
.channels
);
1128 dma_cap_set(DMA_SLAVE
, imxdma
->dma_device
.cap_mask
);
1129 dma_cap_set(DMA_CYCLIC
, imxdma
->dma_device
.cap_mask
);
1130 dma_cap_set(DMA_MEMCPY
, imxdma
->dma_device
.cap_mask
);
1131 dma_cap_set(DMA_INTERLEAVE
, imxdma
->dma_device
.cap_mask
);
1133 /* Initialize 2D global parameters */
1134 for (i
= 0; i
< IMX_DMA_2D_SLOTS
; i
++)
1135 imxdma
->slots_2d
[i
].count
= 0;
1137 spin_lock_init(&imxdma
->lock
);
1139 /* Initialize channel parameters */
1140 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
1141 struct imxdma_channel
*imxdmac
= &imxdma
->channel
[i
];
1143 if (!is_imx1_dma(imxdma
)) {
1144 ret
= devm_request_irq(&pdev
->dev
, irq
+ i
,
1145 dma_irq_handler
, 0, "DMA", imxdma
);
1147 dev_warn(imxdma
->dev
, "Can't register IRQ %d "
1148 "for DMA channel %d\n",
1152 init_timer(&imxdmac
->watchdog
);
1153 imxdmac
->watchdog
.function
= &imxdma_watchdog
;
1154 imxdmac
->watchdog
.data
= (unsigned long)imxdmac
;
1157 imxdmac
->imxdma
= imxdma
;
1159 INIT_LIST_HEAD(&imxdmac
->ld_queue
);
1160 INIT_LIST_HEAD(&imxdmac
->ld_free
);
1161 INIT_LIST_HEAD(&imxdmac
->ld_active
);
1163 tasklet_init(&imxdmac
->dma_tasklet
, imxdma_tasklet
,
1164 (unsigned long)imxdmac
);
1165 imxdmac
->chan
.device
= &imxdma
->dma_device
;
1166 dma_cookie_init(&imxdmac
->chan
);
1167 imxdmac
->channel
= i
;
1169 /* Add the channel to the DMAC list */
1170 list_add_tail(&imxdmac
->chan
.device_node
,
1171 &imxdma
->dma_device
.channels
);
1174 imxdma
->dev
= &pdev
->dev
;
1175 imxdma
->dma_device
.dev
= &pdev
->dev
;
1177 imxdma
->dma_device
.device_alloc_chan_resources
= imxdma_alloc_chan_resources
;
1178 imxdma
->dma_device
.device_free_chan_resources
= imxdma_free_chan_resources
;
1179 imxdma
->dma_device
.device_tx_status
= imxdma_tx_status
;
1180 imxdma
->dma_device
.device_prep_slave_sg
= imxdma_prep_slave_sg
;
1181 imxdma
->dma_device
.device_prep_dma_cyclic
= imxdma_prep_dma_cyclic
;
1182 imxdma
->dma_device
.device_prep_dma_memcpy
= imxdma_prep_dma_memcpy
;
1183 imxdma
->dma_device
.device_prep_interleaved_dma
= imxdma_prep_dma_interleaved
;
1184 imxdma
->dma_device
.device_control
= imxdma_control
;
1185 imxdma
->dma_device
.device_issue_pending
= imxdma_issue_pending
;
1187 platform_set_drvdata(pdev
, imxdma
);
1189 imxdma
->dma_device
.copy_align
= 2; /* 2^2 = 4 bytes alignment */
1190 imxdma
->dma_device
.dev
->dma_parms
= &imxdma
->dma_parms
;
1191 dma_set_max_seg_size(imxdma
->dma_device
.dev
, 0xffffff);
1193 ret
= dma_async_device_register(&imxdma
->dma_device
);
1195 dev_err(&pdev
->dev
, "unable to register\n");
1199 if (pdev
->dev
.of_node
) {
1200 ret
= of_dma_controller_register(pdev
->dev
.of_node
,
1201 imxdma_xlate
, imxdma
);
1203 dev_err(&pdev
->dev
, "unable to register of_dma_controller\n");
1204 goto err_of_dma_controller
;
1210 err_of_dma_controller
:
1211 dma_async_device_unregister(&imxdma
->dma_device
);
1213 clk_disable_unprepare(imxdma
->dma_ipg
);
1214 clk_disable_unprepare(imxdma
->dma_ahb
);
1218 static int imxdma_remove(struct platform_device
*pdev
)
1220 struct imxdma_engine
*imxdma
= platform_get_drvdata(pdev
);
1222 dma_async_device_unregister(&imxdma
->dma_device
);
1224 if (pdev
->dev
.of_node
)
1225 of_dma_controller_free(pdev
->dev
.of_node
);
1227 clk_disable_unprepare(imxdma
->dma_ipg
);
1228 clk_disable_unprepare(imxdma
->dma_ahb
);
1233 static struct platform_driver imxdma_driver
= {
1236 .of_match_table
= imx_dma_of_dev_id
,
1238 .id_table
= imx_dma_devtype
,
1239 .remove
= imxdma_remove
,
1242 static int __init
imxdma_module_init(void)
1244 return platform_driver_probe(&imxdma_driver
, imxdma_probe
);
1246 subsys_initcall(imxdma_module_init
);
1248 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1249 MODULE_DESCRIPTION("i.MX dma driver");
1250 MODULE_LICENSE("GPL");