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Merge branch 'akpm' (Andrew's patch-bomb)
[mirror_ubuntu-artful-kernel.git] / drivers / dma / imx-sdma.c
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
24 #include <linux/mm.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/wait.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39
40 #include <asm/irq.h>
41 #include <mach/sdma.h>
42 #include <mach/dma.h>
43 #include <mach/hardware.h>
44
45 #include "dmaengine.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * Mode/Count of data node descriptors - IPCv2
128 */
129 struct sdma_mode_count {
130 u32 count : 16; /* size of the buffer pointed by this BD */
131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command : 8; /* command mostlky used for channel 0 */
133 };
134
135 /*
136 * Buffer descriptor
137 */
138 struct sdma_buffer_descriptor {
139 struct sdma_mode_count mode;
140 u32 buffer_addr; /* address of the buffer described */
141 u32 ext_buffer_addr; /* extended buffer address */
142 } __attribute__ ((packed));
143
144 /**
145 * struct sdma_channel_control - Channel control Block
146 *
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
150 * control blocks
151 */
152 struct sdma_channel_control {
153 u32 current_bd_ptr;
154 u32 base_bd_ptr;
155 u32 unused[2];
156 } __attribute__ ((packed));
157
158 /**
159 * struct sdma_state_registers - SDMA context for a channel
160 *
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
168 * @lm: loop mode
169 */
170 struct sdma_state_registers {
171 u32 pc :14;
172 u32 unused1: 1;
173 u32 t : 1;
174 u32 rpc :14;
175 u32 unused0: 1;
176 u32 sf : 1;
177 u32 spc :14;
178 u32 unused2: 1;
179 u32 df : 1;
180 u32 epc :14;
181 u32 lm : 2;
182 } __attribute__ ((packed));
183
184 /**
185 * struct sdma_context_data - sdma context specific to a channel
186 *
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
203 */
204 struct sdma_context_data {
205 struct sdma_state_registers channel_state;
206 u32 gReg[8];
207 u32 mda;
208 u32 msa;
209 u32 ms;
210 u32 md;
211 u32 pda;
212 u32 psa;
213 u32 ps;
214 u32 pd;
215 u32 ca;
216 u32 cs;
217 u32 dda;
218 u32 dsa;
219 u32 ds;
220 u32 dd;
221 u32 scratch0;
222 u32 scratch1;
223 u32 scratch2;
224 u32 scratch3;
225 u32 scratch4;
226 u32 scratch5;
227 u32 scratch6;
228 u32 scratch7;
229 } __attribute__ ((packed));
230
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232
233 struct sdma_engine;
234
235 /**
236 * struct sdma_channel - housekeeping for a SDMA channel
237 *
238 * @sdma pointer to the SDMA engine for this channel
239 * @channel the channel number, matches dmaengine chan_id + 1
240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
246 * @done channel completion
247 * @num_bd max NUM_BD. number of descriptors currently handling
248 */
249 struct sdma_channel {
250 struct sdma_engine *sdma;
251 unsigned int channel;
252 enum dma_transfer_direction direction;
253 enum sdma_peripheral_type peripheral_type;
254 unsigned int event_id0;
255 unsigned int event_id1;
256 enum dma_slave_buswidth word_size;
257 unsigned int buf_tail;
258 struct completion done;
259 unsigned int num_bd;
260 struct sdma_buffer_descriptor *bd;
261 dma_addr_t bd_phys;
262 unsigned int pc_from_device, pc_to_device;
263 unsigned long flags;
264 dma_addr_t per_address;
265 unsigned long event_mask[2];
266 unsigned long watermark_level;
267 u32 shp_addr, per_addr;
268 struct dma_chan chan;
269 spinlock_t lock;
270 struct dma_async_tx_descriptor desc;
271 enum dma_status status;
272 unsigned int chn_count;
273 unsigned int chn_real_count;
274 };
275
276 #define IMX_DMA_SG_LOOP BIT(0)
277
278 #define MAX_DMA_CHANNELS 32
279 #define MXC_SDMA_DEFAULT_PRIORITY 1
280 #define MXC_SDMA_MIN_PRIORITY 1
281 #define MXC_SDMA_MAX_PRIORITY 7
282
283 #define SDMA_FIRMWARE_MAGIC 0x414d4453
284
285 /**
286 * struct sdma_firmware_header - Layout of the firmware image
287 *
288 * @magic "SDMA"
289 * @version_major increased whenever layout of struct sdma_script_start_addrs
290 * changes.
291 * @version_minor firmware minor version (for binary compatible changes)
292 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
293 * @num_script_addrs Number of script addresses in this image
294 * @ram_code_start offset of SDMA ram image in this firmware image
295 * @ram_code_size size of SDMA ram image
296 * @script_addrs Stores the start address of the SDMA scripts
297 * (in SDMA memory space)
298 */
299 struct sdma_firmware_header {
300 u32 magic;
301 u32 version_major;
302 u32 version_minor;
303 u32 script_addrs_start;
304 u32 num_script_addrs;
305 u32 ram_code_start;
306 u32 ram_code_size;
307 };
308
309 enum sdma_devtype {
310 IMX31_SDMA, /* runs on i.mx31 */
311 IMX35_SDMA, /* runs on i.mx35 and later */
312 };
313
314 struct sdma_engine {
315 struct device *dev;
316 struct device_dma_parameters dma_parms;
317 struct sdma_channel channel[MAX_DMA_CHANNELS];
318 struct sdma_channel_control *channel_control;
319 void __iomem *regs;
320 enum sdma_devtype devtype;
321 unsigned int num_events;
322 struct sdma_context_data *context;
323 dma_addr_t context_phys;
324 struct dma_device dma_device;
325 struct clk *clk;
326 struct mutex channel_0_lock;
327 struct sdma_script_start_addrs *script_addrs;
328 };
329
330 static struct platform_device_id sdma_devtypes[] = {
331 {
332 .name = "imx31-sdma",
333 .driver_data = IMX31_SDMA,
334 }, {
335 .name = "imx35-sdma",
336 .driver_data = IMX35_SDMA,
337 }, {
338 /* sentinel */
339 }
340 };
341 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
342
343 static const struct of_device_id sdma_dt_ids[] = {
344 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
345 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
346 { /* sentinel */ }
347 };
348 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
349
350 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
351 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
352 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
353 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
354
355 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
356 {
357 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
358 SDMA_CHNENBL0_IMX35);
359 return chnenbl0 + event * 4;
360 }
361
362 static int sdma_config_ownership(struct sdma_channel *sdmac,
363 bool event_override, bool mcu_override, bool dsp_override)
364 {
365 struct sdma_engine *sdma = sdmac->sdma;
366 int channel = sdmac->channel;
367 unsigned long evt, mcu, dsp;
368
369 if (event_override && mcu_override && dsp_override)
370 return -EINVAL;
371
372 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
373 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
374 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
375
376 if (dsp_override)
377 __clear_bit(channel, &dsp);
378 else
379 __set_bit(channel, &dsp);
380
381 if (event_override)
382 __clear_bit(channel, &evt);
383 else
384 __set_bit(channel, &evt);
385
386 if (mcu_override)
387 __clear_bit(channel, &mcu);
388 else
389 __set_bit(channel, &mcu);
390
391 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
392 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
393 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
394
395 return 0;
396 }
397
398 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
399 {
400 writel(BIT(channel), sdma->regs + SDMA_H_START);
401 }
402
403 /*
404 * sdma_run_channel - run a channel and wait till it's done
405 */
406 static int sdma_run_channel(struct sdma_channel *sdmac)
407 {
408 struct sdma_engine *sdma = sdmac->sdma;
409 int channel = sdmac->channel;
410 int ret;
411
412 init_completion(&sdmac->done);
413
414 sdma_enable_channel(sdma, channel);
415
416 ret = wait_for_completion_timeout(&sdmac->done, HZ);
417
418 return ret ? 0 : -ETIMEDOUT;
419 }
420
421 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
422 u32 address)
423 {
424 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
425 void *buf_virt;
426 dma_addr_t buf_phys;
427 int ret;
428
429 mutex_lock(&sdma->channel_0_lock);
430
431 buf_virt = dma_alloc_coherent(NULL,
432 size,
433 &buf_phys, GFP_KERNEL);
434 if (!buf_virt) {
435 ret = -ENOMEM;
436 goto err_out;
437 }
438
439 bd0->mode.command = C0_SETPM;
440 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
441 bd0->mode.count = size / 2;
442 bd0->buffer_addr = buf_phys;
443 bd0->ext_buffer_addr = address;
444
445 memcpy(buf_virt, buf, size);
446
447 ret = sdma_run_channel(&sdma->channel[0]);
448
449 dma_free_coherent(NULL, size, buf_virt, buf_phys);
450
451 err_out:
452 mutex_unlock(&sdma->channel_0_lock);
453
454 return ret;
455 }
456
457 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
458 {
459 struct sdma_engine *sdma = sdmac->sdma;
460 int channel = sdmac->channel;
461 unsigned long val;
462 u32 chnenbl = chnenbl_ofs(sdma, event);
463
464 val = readl_relaxed(sdma->regs + chnenbl);
465 __set_bit(channel, &val);
466 writel_relaxed(val, sdma->regs + chnenbl);
467 }
468
469 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
470 {
471 struct sdma_engine *sdma = sdmac->sdma;
472 int channel = sdmac->channel;
473 u32 chnenbl = chnenbl_ofs(sdma, event);
474 unsigned long val;
475
476 val = readl_relaxed(sdma->regs + chnenbl);
477 __clear_bit(channel, &val);
478 writel_relaxed(val, sdma->regs + chnenbl);
479 }
480
481 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
482 {
483 struct sdma_buffer_descriptor *bd;
484
485 /*
486 * loop mode. Iterate over descriptors, re-setup them and
487 * call callback function.
488 */
489 while (1) {
490 bd = &sdmac->bd[sdmac->buf_tail];
491
492 if (bd->mode.status & BD_DONE)
493 break;
494
495 if (bd->mode.status & BD_RROR)
496 sdmac->status = DMA_ERROR;
497 else
498 sdmac->status = DMA_IN_PROGRESS;
499
500 bd->mode.status |= BD_DONE;
501 sdmac->buf_tail++;
502 sdmac->buf_tail %= sdmac->num_bd;
503
504 if (sdmac->desc.callback)
505 sdmac->desc.callback(sdmac->desc.callback_param);
506 }
507 }
508
509 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
510 {
511 struct sdma_buffer_descriptor *bd;
512 int i, error = 0;
513
514 sdmac->chn_real_count = 0;
515 /*
516 * non loop mode. Iterate over all descriptors, collect
517 * errors and call callback function
518 */
519 for (i = 0; i < sdmac->num_bd; i++) {
520 bd = &sdmac->bd[i];
521
522 if (bd->mode.status & (BD_DONE | BD_RROR))
523 error = -EIO;
524 sdmac->chn_real_count += bd->mode.count;
525 }
526
527 if (error)
528 sdmac->status = DMA_ERROR;
529 else
530 sdmac->status = DMA_SUCCESS;
531
532 dma_cookie_complete(&sdmac->desc);
533 if (sdmac->desc.callback)
534 sdmac->desc.callback(sdmac->desc.callback_param);
535 }
536
537 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
538 {
539 complete(&sdmac->done);
540
541 /* not interested in channel 0 interrupts */
542 if (sdmac->channel == 0)
543 return;
544
545 if (sdmac->flags & IMX_DMA_SG_LOOP)
546 sdma_handle_channel_loop(sdmac);
547 else
548 mxc_sdma_handle_channel_normal(sdmac);
549 }
550
551 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
552 {
553 struct sdma_engine *sdma = dev_id;
554 unsigned long stat;
555
556 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
557 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
558
559 while (stat) {
560 int channel = fls(stat) - 1;
561 struct sdma_channel *sdmac = &sdma->channel[channel];
562
563 mxc_sdma_handle_channel(sdmac);
564
565 __clear_bit(channel, &stat);
566 }
567
568 return IRQ_HANDLED;
569 }
570
571 /*
572 * sets the pc of SDMA script according to the peripheral type
573 */
574 static void sdma_get_pc(struct sdma_channel *sdmac,
575 enum sdma_peripheral_type peripheral_type)
576 {
577 struct sdma_engine *sdma = sdmac->sdma;
578 int per_2_emi = 0, emi_2_per = 0;
579 /*
580 * These are needed once we start to support transfers between
581 * two peripherals or memory-to-memory transfers
582 */
583 int per_2_per = 0, emi_2_emi = 0;
584
585 sdmac->pc_from_device = 0;
586 sdmac->pc_to_device = 0;
587
588 switch (peripheral_type) {
589 case IMX_DMATYPE_MEMORY:
590 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
591 break;
592 case IMX_DMATYPE_DSP:
593 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
594 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
595 break;
596 case IMX_DMATYPE_FIRI:
597 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
598 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
599 break;
600 case IMX_DMATYPE_UART:
601 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
602 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
603 break;
604 case IMX_DMATYPE_UART_SP:
605 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
606 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
607 break;
608 case IMX_DMATYPE_ATA:
609 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
610 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
611 break;
612 case IMX_DMATYPE_CSPI:
613 case IMX_DMATYPE_EXT:
614 case IMX_DMATYPE_SSI:
615 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
616 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
617 break;
618 case IMX_DMATYPE_SSI_SP:
619 case IMX_DMATYPE_MMC:
620 case IMX_DMATYPE_SDHC:
621 case IMX_DMATYPE_CSPI_SP:
622 case IMX_DMATYPE_ESAI:
623 case IMX_DMATYPE_MSHC_SP:
624 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
625 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
626 break;
627 case IMX_DMATYPE_ASRC:
628 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
629 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
630 per_2_per = sdma->script_addrs->per_2_per_addr;
631 break;
632 case IMX_DMATYPE_MSHC:
633 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
634 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
635 break;
636 case IMX_DMATYPE_CCM:
637 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
638 break;
639 case IMX_DMATYPE_SPDIF:
640 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
641 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
642 break;
643 case IMX_DMATYPE_IPU_MEMORY:
644 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
645 break;
646 default:
647 break;
648 }
649
650 sdmac->pc_from_device = per_2_emi;
651 sdmac->pc_to_device = emi_2_per;
652 }
653
654 static int sdma_load_context(struct sdma_channel *sdmac)
655 {
656 struct sdma_engine *sdma = sdmac->sdma;
657 int channel = sdmac->channel;
658 int load_address;
659 struct sdma_context_data *context = sdma->context;
660 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
661 int ret;
662
663 if (sdmac->direction == DMA_DEV_TO_MEM) {
664 load_address = sdmac->pc_from_device;
665 } else {
666 load_address = sdmac->pc_to_device;
667 }
668
669 if (load_address < 0)
670 return load_address;
671
672 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
673 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
674 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
675 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
676 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
677 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
678
679 mutex_lock(&sdma->channel_0_lock);
680
681 memset(context, 0, sizeof(*context));
682 context->channel_state.pc = load_address;
683
684 /* Send by context the event mask,base address for peripheral
685 * and watermark level
686 */
687 context->gReg[0] = sdmac->event_mask[1];
688 context->gReg[1] = sdmac->event_mask[0];
689 context->gReg[2] = sdmac->per_addr;
690 context->gReg[6] = sdmac->shp_addr;
691 context->gReg[7] = sdmac->watermark_level;
692
693 bd0->mode.command = C0_SETDM;
694 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
695 bd0->mode.count = sizeof(*context) / 4;
696 bd0->buffer_addr = sdma->context_phys;
697 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
698
699 ret = sdma_run_channel(&sdma->channel[0]);
700
701 mutex_unlock(&sdma->channel_0_lock);
702
703 return ret;
704 }
705
706 static void sdma_disable_channel(struct sdma_channel *sdmac)
707 {
708 struct sdma_engine *sdma = sdmac->sdma;
709 int channel = sdmac->channel;
710
711 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
712 sdmac->status = DMA_ERROR;
713 }
714
715 static int sdma_config_channel(struct sdma_channel *sdmac)
716 {
717 int ret;
718
719 sdma_disable_channel(sdmac);
720
721 sdmac->event_mask[0] = 0;
722 sdmac->event_mask[1] = 0;
723 sdmac->shp_addr = 0;
724 sdmac->per_addr = 0;
725
726 if (sdmac->event_id0) {
727 if (sdmac->event_id0 >= sdmac->sdma->num_events)
728 return -EINVAL;
729 sdma_event_enable(sdmac, sdmac->event_id0);
730 }
731
732 switch (sdmac->peripheral_type) {
733 case IMX_DMATYPE_DSP:
734 sdma_config_ownership(sdmac, false, true, true);
735 break;
736 case IMX_DMATYPE_MEMORY:
737 sdma_config_ownership(sdmac, false, true, false);
738 break;
739 default:
740 sdma_config_ownership(sdmac, true, true, false);
741 break;
742 }
743
744 sdma_get_pc(sdmac, sdmac->peripheral_type);
745
746 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
747 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
748 /* Handle multiple event channels differently */
749 if (sdmac->event_id1) {
750 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
751 if (sdmac->event_id1 > 31)
752 __set_bit(31, &sdmac->watermark_level);
753 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
754 if (sdmac->event_id0 > 31)
755 __set_bit(30, &sdmac->watermark_level);
756 } else {
757 __set_bit(sdmac->event_id0, sdmac->event_mask);
758 }
759 /* Watermark Level */
760 sdmac->watermark_level |= sdmac->watermark_level;
761 /* Address */
762 sdmac->shp_addr = sdmac->per_address;
763 } else {
764 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
765 }
766
767 ret = sdma_load_context(sdmac);
768
769 return ret;
770 }
771
772 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
773 unsigned int priority)
774 {
775 struct sdma_engine *sdma = sdmac->sdma;
776 int channel = sdmac->channel;
777
778 if (priority < MXC_SDMA_MIN_PRIORITY
779 || priority > MXC_SDMA_MAX_PRIORITY) {
780 return -EINVAL;
781 }
782
783 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
784
785 return 0;
786 }
787
788 static int sdma_request_channel(struct sdma_channel *sdmac)
789 {
790 struct sdma_engine *sdma = sdmac->sdma;
791 int channel = sdmac->channel;
792 int ret = -EBUSY;
793
794 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
795 if (!sdmac->bd) {
796 ret = -ENOMEM;
797 goto out;
798 }
799
800 memset(sdmac->bd, 0, PAGE_SIZE);
801
802 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
803 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
804
805 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
806
807 init_completion(&sdmac->done);
808
809 sdmac->buf_tail = 0;
810
811 return 0;
812 out:
813
814 return ret;
815 }
816
817 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
818 {
819 return container_of(chan, struct sdma_channel, chan);
820 }
821
822 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
823 {
824 unsigned long flags;
825 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
826 dma_cookie_t cookie;
827
828 spin_lock_irqsave(&sdmac->lock, flags);
829
830 cookie = dma_cookie_assign(tx);
831
832 spin_unlock_irqrestore(&sdmac->lock, flags);
833
834 return cookie;
835 }
836
837 static int sdma_alloc_chan_resources(struct dma_chan *chan)
838 {
839 struct sdma_channel *sdmac = to_sdma_chan(chan);
840 struct imx_dma_data *data = chan->private;
841 int prio, ret;
842
843 if (!data)
844 return -EINVAL;
845
846 switch (data->priority) {
847 case DMA_PRIO_HIGH:
848 prio = 3;
849 break;
850 case DMA_PRIO_MEDIUM:
851 prio = 2;
852 break;
853 case DMA_PRIO_LOW:
854 default:
855 prio = 1;
856 break;
857 }
858
859 sdmac->peripheral_type = data->peripheral_type;
860 sdmac->event_id0 = data->dma_request;
861
862 clk_enable(sdmac->sdma->clk);
863
864 ret = sdma_request_channel(sdmac);
865 if (ret)
866 return ret;
867
868 ret = sdma_set_channel_priority(sdmac, prio);
869 if (ret)
870 return ret;
871
872 dma_async_tx_descriptor_init(&sdmac->desc, chan);
873 sdmac->desc.tx_submit = sdma_tx_submit;
874 /* txd.flags will be overwritten in prep funcs */
875 sdmac->desc.flags = DMA_CTRL_ACK;
876
877 return 0;
878 }
879
880 static void sdma_free_chan_resources(struct dma_chan *chan)
881 {
882 struct sdma_channel *sdmac = to_sdma_chan(chan);
883 struct sdma_engine *sdma = sdmac->sdma;
884
885 sdma_disable_channel(sdmac);
886
887 if (sdmac->event_id0)
888 sdma_event_disable(sdmac, sdmac->event_id0);
889 if (sdmac->event_id1)
890 sdma_event_disable(sdmac, sdmac->event_id1);
891
892 sdmac->event_id0 = 0;
893 sdmac->event_id1 = 0;
894
895 sdma_set_channel_priority(sdmac, 0);
896
897 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
898
899 clk_disable(sdma->clk);
900 }
901
902 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
903 struct dma_chan *chan, struct scatterlist *sgl,
904 unsigned int sg_len, enum dma_transfer_direction direction,
905 unsigned long flags, void *context)
906 {
907 struct sdma_channel *sdmac = to_sdma_chan(chan);
908 struct sdma_engine *sdma = sdmac->sdma;
909 int ret, i, count;
910 int channel = sdmac->channel;
911 struct scatterlist *sg;
912
913 if (sdmac->status == DMA_IN_PROGRESS)
914 return NULL;
915 sdmac->status = DMA_IN_PROGRESS;
916
917 sdmac->flags = 0;
918
919 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
920 sg_len, channel);
921
922 sdmac->direction = direction;
923 ret = sdma_load_context(sdmac);
924 if (ret)
925 goto err_out;
926
927 if (sg_len > NUM_BD) {
928 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
929 channel, sg_len, NUM_BD);
930 ret = -EINVAL;
931 goto err_out;
932 }
933
934 sdmac->chn_count = 0;
935 for_each_sg(sgl, sg, sg_len, i) {
936 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
937 int param;
938
939 bd->buffer_addr = sg->dma_address;
940
941 count = sg->length;
942
943 if (count > 0xffff) {
944 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
945 channel, count, 0xffff);
946 ret = -EINVAL;
947 goto err_out;
948 }
949
950 bd->mode.count = count;
951 sdmac->chn_count += count;
952
953 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
954 ret = -EINVAL;
955 goto err_out;
956 }
957
958 switch (sdmac->word_size) {
959 case DMA_SLAVE_BUSWIDTH_4_BYTES:
960 bd->mode.command = 0;
961 if (count & 3 || sg->dma_address & 3)
962 return NULL;
963 break;
964 case DMA_SLAVE_BUSWIDTH_2_BYTES:
965 bd->mode.command = 2;
966 if (count & 1 || sg->dma_address & 1)
967 return NULL;
968 break;
969 case DMA_SLAVE_BUSWIDTH_1_BYTE:
970 bd->mode.command = 1;
971 break;
972 default:
973 return NULL;
974 }
975
976 param = BD_DONE | BD_EXTD | BD_CONT;
977
978 if (i + 1 == sg_len) {
979 param |= BD_INTR;
980 param |= BD_LAST;
981 param &= ~BD_CONT;
982 }
983
984 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
985 i, count, sg->dma_address,
986 param & BD_WRAP ? "wrap" : "",
987 param & BD_INTR ? " intr" : "");
988
989 bd->mode.status = param;
990 }
991
992 sdmac->num_bd = sg_len;
993 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
994
995 return &sdmac->desc;
996 err_out:
997 sdmac->status = DMA_ERROR;
998 return NULL;
999 }
1000
1001 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1002 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1003 size_t period_len, enum dma_transfer_direction direction,
1004 void *context)
1005 {
1006 struct sdma_channel *sdmac = to_sdma_chan(chan);
1007 struct sdma_engine *sdma = sdmac->sdma;
1008 int num_periods = buf_len / period_len;
1009 int channel = sdmac->channel;
1010 int ret, i = 0, buf = 0;
1011
1012 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1013
1014 if (sdmac->status == DMA_IN_PROGRESS)
1015 return NULL;
1016
1017 sdmac->status = DMA_IN_PROGRESS;
1018
1019 sdmac->flags |= IMX_DMA_SG_LOOP;
1020 sdmac->direction = direction;
1021 ret = sdma_load_context(sdmac);
1022 if (ret)
1023 goto err_out;
1024
1025 if (num_periods > NUM_BD) {
1026 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1027 channel, num_periods, NUM_BD);
1028 goto err_out;
1029 }
1030
1031 if (period_len > 0xffff) {
1032 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1033 channel, period_len, 0xffff);
1034 goto err_out;
1035 }
1036
1037 while (buf < buf_len) {
1038 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1039 int param;
1040
1041 bd->buffer_addr = dma_addr;
1042
1043 bd->mode.count = period_len;
1044
1045 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1046 goto err_out;
1047 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1048 bd->mode.command = 0;
1049 else
1050 bd->mode.command = sdmac->word_size;
1051
1052 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1053 if (i + 1 == num_periods)
1054 param |= BD_WRAP;
1055
1056 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1057 i, period_len, dma_addr,
1058 param & BD_WRAP ? "wrap" : "",
1059 param & BD_INTR ? " intr" : "");
1060
1061 bd->mode.status = param;
1062
1063 dma_addr += period_len;
1064 buf += period_len;
1065
1066 i++;
1067 }
1068
1069 sdmac->num_bd = num_periods;
1070 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1071
1072 return &sdmac->desc;
1073 err_out:
1074 sdmac->status = DMA_ERROR;
1075 return NULL;
1076 }
1077
1078 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1079 unsigned long arg)
1080 {
1081 struct sdma_channel *sdmac = to_sdma_chan(chan);
1082 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1083
1084 switch (cmd) {
1085 case DMA_TERMINATE_ALL:
1086 sdma_disable_channel(sdmac);
1087 return 0;
1088 case DMA_SLAVE_CONFIG:
1089 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1090 sdmac->per_address = dmaengine_cfg->src_addr;
1091 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1092 dmaengine_cfg->src_addr_width;
1093 sdmac->word_size = dmaengine_cfg->src_addr_width;
1094 } else {
1095 sdmac->per_address = dmaengine_cfg->dst_addr;
1096 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1097 dmaengine_cfg->dst_addr_width;
1098 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1099 }
1100 sdmac->direction = dmaengine_cfg->direction;
1101 return sdma_config_channel(sdmac);
1102 default:
1103 return -ENOSYS;
1104 }
1105
1106 return -EINVAL;
1107 }
1108
1109 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1110 dma_cookie_t cookie,
1111 struct dma_tx_state *txstate)
1112 {
1113 struct sdma_channel *sdmac = to_sdma_chan(chan);
1114 dma_cookie_t last_used;
1115
1116 last_used = chan->cookie;
1117
1118 dma_set_tx_state(txstate, chan->completed_cookie, last_used,
1119 sdmac->chn_count - sdmac->chn_real_count);
1120
1121 return sdmac->status;
1122 }
1123
1124 static void sdma_issue_pending(struct dma_chan *chan)
1125 {
1126 struct sdma_channel *sdmac = to_sdma_chan(chan);
1127 struct sdma_engine *sdma = sdmac->sdma;
1128
1129 if (sdmac->status == DMA_IN_PROGRESS)
1130 sdma_enable_channel(sdma, sdmac->channel);
1131 }
1132
1133 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1134
1135 static void sdma_add_scripts(struct sdma_engine *sdma,
1136 const struct sdma_script_start_addrs *addr)
1137 {
1138 s32 *addr_arr = (u32 *)addr;
1139 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1140 int i;
1141
1142 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1143 if (addr_arr[i] > 0)
1144 saddr_arr[i] = addr_arr[i];
1145 }
1146
1147 static void sdma_load_firmware(const struct firmware *fw, void *context)
1148 {
1149 struct sdma_engine *sdma = context;
1150 const struct sdma_firmware_header *header;
1151 const struct sdma_script_start_addrs *addr;
1152 unsigned short *ram_code;
1153
1154 if (!fw) {
1155 dev_err(sdma->dev, "firmware not found\n");
1156 return;
1157 }
1158
1159 if (fw->size < sizeof(*header))
1160 goto err_firmware;
1161
1162 header = (struct sdma_firmware_header *)fw->data;
1163
1164 if (header->magic != SDMA_FIRMWARE_MAGIC)
1165 goto err_firmware;
1166 if (header->ram_code_start + header->ram_code_size > fw->size)
1167 goto err_firmware;
1168
1169 addr = (void *)header + header->script_addrs_start;
1170 ram_code = (void *)header + header->ram_code_start;
1171
1172 clk_enable(sdma->clk);
1173 /* download the RAM image for SDMA */
1174 sdma_load_script(sdma, ram_code,
1175 header->ram_code_size,
1176 addr->ram_code_start_addr);
1177 clk_disable(sdma->clk);
1178
1179 sdma_add_scripts(sdma, addr);
1180
1181 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1182 header->version_major,
1183 header->version_minor);
1184
1185 err_firmware:
1186 release_firmware(fw);
1187 }
1188
1189 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1190 const char *fw_name)
1191 {
1192 int ret;
1193
1194 ret = request_firmware_nowait(THIS_MODULE,
1195 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1196 GFP_KERNEL, sdma, sdma_load_firmware);
1197
1198 return ret;
1199 }
1200
1201 static int __init sdma_init(struct sdma_engine *sdma)
1202 {
1203 int i, ret;
1204 dma_addr_t ccb_phys;
1205
1206 switch (sdma->devtype) {
1207 case IMX31_SDMA:
1208 sdma->num_events = 32;
1209 break;
1210 case IMX35_SDMA:
1211 sdma->num_events = 48;
1212 break;
1213 default:
1214 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1215 sdma->devtype);
1216 return -ENODEV;
1217 }
1218
1219 clk_enable(sdma->clk);
1220
1221 /* Be sure SDMA has not started yet */
1222 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1223
1224 sdma->channel_control = dma_alloc_coherent(NULL,
1225 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1226 sizeof(struct sdma_context_data),
1227 &ccb_phys, GFP_KERNEL);
1228
1229 if (!sdma->channel_control) {
1230 ret = -ENOMEM;
1231 goto err_dma_alloc;
1232 }
1233
1234 sdma->context = (void *)sdma->channel_control +
1235 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1236 sdma->context_phys = ccb_phys +
1237 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1238
1239 /* Zero-out the CCB structures array just allocated */
1240 memset(sdma->channel_control, 0,
1241 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1242
1243 /* disable all channels */
1244 for (i = 0; i < sdma->num_events; i++)
1245 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1246
1247 /* All channels have priority 0 */
1248 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1249 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1250
1251 ret = sdma_request_channel(&sdma->channel[0]);
1252 if (ret)
1253 goto err_dma_alloc;
1254
1255 sdma_config_ownership(&sdma->channel[0], false, true, false);
1256
1257 /* Set Command Channel (Channel Zero) */
1258 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1259
1260 /* Set bits of CONFIG register but with static context switching */
1261 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1262 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1263
1264 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1265
1266 /* Set bits of CONFIG register with given context switching mode */
1267 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1268
1269 /* Initializes channel's priorities */
1270 sdma_set_channel_priority(&sdma->channel[0], 7);
1271
1272 clk_disable(sdma->clk);
1273
1274 return 0;
1275
1276 err_dma_alloc:
1277 clk_disable(sdma->clk);
1278 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1279 return ret;
1280 }
1281
1282 static int __init sdma_probe(struct platform_device *pdev)
1283 {
1284 const struct of_device_id *of_id =
1285 of_match_device(sdma_dt_ids, &pdev->dev);
1286 struct device_node *np = pdev->dev.of_node;
1287 const char *fw_name;
1288 int ret;
1289 int irq;
1290 struct resource *iores;
1291 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1292 int i;
1293 struct sdma_engine *sdma;
1294 s32 *saddr_arr;
1295
1296 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1297 if (!sdma)
1298 return -ENOMEM;
1299
1300 mutex_init(&sdma->channel_0_lock);
1301
1302 sdma->dev = &pdev->dev;
1303
1304 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305 irq = platform_get_irq(pdev, 0);
1306 if (!iores || irq < 0) {
1307 ret = -EINVAL;
1308 goto err_irq;
1309 }
1310
1311 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1312 ret = -EBUSY;
1313 goto err_request_region;
1314 }
1315
1316 sdma->clk = clk_get(&pdev->dev, NULL);
1317 if (IS_ERR(sdma->clk)) {
1318 ret = PTR_ERR(sdma->clk);
1319 goto err_clk;
1320 }
1321
1322 sdma->regs = ioremap(iores->start, resource_size(iores));
1323 if (!sdma->regs) {
1324 ret = -ENOMEM;
1325 goto err_ioremap;
1326 }
1327
1328 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1329 if (ret)
1330 goto err_request_irq;
1331
1332 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1333 if (!sdma->script_addrs) {
1334 ret = -ENOMEM;
1335 goto err_alloc;
1336 }
1337
1338 /* initially no scripts available */
1339 saddr_arr = (s32 *)sdma->script_addrs;
1340 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1341 saddr_arr[i] = -EINVAL;
1342
1343 if (of_id)
1344 pdev->id_entry = of_id->data;
1345 sdma->devtype = pdev->id_entry->driver_data;
1346
1347 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1348 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1349
1350 INIT_LIST_HEAD(&sdma->dma_device.channels);
1351 /* Initialize channel parameters */
1352 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1353 struct sdma_channel *sdmac = &sdma->channel[i];
1354
1355 sdmac->sdma = sdma;
1356 spin_lock_init(&sdmac->lock);
1357
1358 sdmac->chan.device = &sdma->dma_device;
1359 dma_cookie_init(&sdmac->chan);
1360 sdmac->channel = i;
1361
1362 /*
1363 * Add the channel to the DMAC list. Do not add channel 0 though
1364 * because we need it internally in the SDMA driver. This also means
1365 * that channel 0 in dmaengine counting matches sdma channel 1.
1366 */
1367 if (i)
1368 list_add_tail(&sdmac->chan.device_node,
1369 &sdma->dma_device.channels);
1370 }
1371
1372 ret = sdma_init(sdma);
1373 if (ret)
1374 goto err_init;
1375
1376 if (pdata && pdata->script_addrs)
1377 sdma_add_scripts(sdma, pdata->script_addrs);
1378
1379 if (pdata) {
1380 ret = sdma_get_firmware(sdma, pdata->fw_name);
1381 if (ret)
1382 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1383 } else {
1384 /*
1385 * Because that device tree does not encode ROM script address,
1386 * the RAM script in firmware is mandatory for device tree
1387 * probe, otherwise it fails.
1388 */
1389 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1390 &fw_name);
1391 if (ret)
1392 dev_warn(&pdev->dev, "failed to get firmware name\n");
1393 else {
1394 ret = sdma_get_firmware(sdma, fw_name);
1395 if (ret)
1396 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1397 }
1398 }
1399
1400 sdma->dma_device.dev = &pdev->dev;
1401
1402 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1403 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1404 sdma->dma_device.device_tx_status = sdma_tx_status;
1405 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1406 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1407 sdma->dma_device.device_control = sdma_control;
1408 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1409 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1410 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1411
1412 ret = dma_async_device_register(&sdma->dma_device);
1413 if (ret) {
1414 dev_err(&pdev->dev, "unable to register\n");
1415 goto err_init;
1416 }
1417
1418 dev_info(sdma->dev, "initialized\n");
1419
1420 return 0;
1421
1422 err_init:
1423 kfree(sdma->script_addrs);
1424 err_alloc:
1425 free_irq(irq, sdma);
1426 err_request_irq:
1427 iounmap(sdma->regs);
1428 err_ioremap:
1429 clk_put(sdma->clk);
1430 err_clk:
1431 release_mem_region(iores->start, resource_size(iores));
1432 err_request_region:
1433 err_irq:
1434 kfree(sdma);
1435 return ret;
1436 }
1437
1438 static int __exit sdma_remove(struct platform_device *pdev)
1439 {
1440 return -EBUSY;
1441 }
1442
1443 static struct platform_driver sdma_driver = {
1444 .driver = {
1445 .name = "imx-sdma",
1446 .of_match_table = sdma_dt_ids,
1447 },
1448 .id_table = sdma_devtypes,
1449 .remove = __exit_p(sdma_remove),
1450 };
1451
1452 static int __init sdma_module_init(void)
1453 {
1454 return platform_driver_probe(&sdma_driver, sdma_probe);
1455 }
1456 module_init(sdma_module_init);
1457
1458 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1459 MODULE_DESCRIPTION("i.MX SDMA driver");
1460 MODULE_LICENSE("GPL");
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