2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/interrupt.h>
33 #include <linux/dmaengine.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/workqueue.h>
37 #include <linux/prefetch.h>
38 #include <linux/i7300_idle.h>
40 #include "registers.h"
43 #include "../dmaengine.h"
45 int ioat_pending_level
= 4;
46 module_param(ioat_pending_level
, int, 0644);
47 MODULE_PARM_DESC(ioat_pending_level
,
48 "high-water mark for pushing ioat descriptors (default: 4)");
50 /* internal functions */
51 static void ioat1_cleanup(struct ioat_dma_chan
*ioat
);
52 static void ioat1_dma_start_null_desc(struct ioat_dma_chan
*ioat
);
55 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
57 * @data: interrupt data
59 static irqreturn_t
ioat_dma_do_interrupt(int irq
, void *data
)
61 struct ioatdma_device
*instance
= data
;
62 struct ioat_chan_common
*chan
;
63 unsigned long attnstatus
;
67 intrctrl
= readb(instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
69 if (!(intrctrl
& IOAT_INTRCTRL_MASTER_INT_EN
))
72 if (!(intrctrl
& IOAT_INTRCTRL_INT_STATUS
)) {
73 writeb(intrctrl
, instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
77 attnstatus
= readl(instance
->reg_base
+ IOAT_ATTNSTATUS_OFFSET
);
78 for_each_set_bit(bit
, &attnstatus
, BITS_PER_LONG
) {
79 chan
= ioat_chan_by_index(instance
, bit
);
80 tasklet_schedule(&chan
->cleanup_task
);
83 writeb(intrctrl
, instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
88 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
90 * @data: interrupt data
92 static irqreturn_t
ioat_dma_do_interrupt_msix(int irq
, void *data
)
94 struct ioat_chan_common
*chan
= data
;
96 tasklet_schedule(&chan
->cleanup_task
);
101 /* common channel initialization */
102 void ioat_init_channel(struct ioatdma_device
*device
, struct ioat_chan_common
*chan
, int idx
)
104 struct dma_device
*dma
= &device
->common
;
105 struct dma_chan
*c
= &chan
->common
;
106 unsigned long data
= (unsigned long) c
;
108 chan
->device
= device
;
109 chan
->reg_base
= device
->reg_base
+ (0x80 * (idx
+ 1));
110 spin_lock_init(&chan
->cleanup_lock
);
111 chan
->common
.device
= dma
;
112 list_add_tail(&chan
->common
.device_node
, &dma
->channels
);
113 device
->idx
[idx
] = chan
;
114 init_timer(&chan
->timer
);
115 chan
->timer
.function
= device
->timer_fn
;
116 chan
->timer
.data
= data
;
117 tasklet_init(&chan
->cleanup_task
, device
->cleanup_fn
, data
);
118 tasklet_disable(&chan
->cleanup_task
);
122 * ioat1_dma_enumerate_channels - find and initialize the device's channels
123 * @device: the device to be enumerated
125 static int ioat1_enumerate_channels(struct ioatdma_device
*device
)
130 struct ioat_dma_chan
*ioat
;
131 struct device
*dev
= &device
->pdev
->dev
;
132 struct dma_device
*dma
= &device
->common
;
134 INIT_LIST_HEAD(&dma
->channels
);
135 dma
->chancnt
= readb(device
->reg_base
+ IOAT_CHANCNT_OFFSET
);
136 dma
->chancnt
&= 0x1f; /* bits [4:0] valid */
137 if (dma
->chancnt
> ARRAY_SIZE(device
->idx
)) {
138 dev_warn(dev
, "(%d) exceeds max supported channels (%zu)\n",
139 dma
->chancnt
, ARRAY_SIZE(device
->idx
));
140 dma
->chancnt
= ARRAY_SIZE(device
->idx
);
142 xfercap_scale
= readb(device
->reg_base
+ IOAT_XFERCAP_OFFSET
);
143 xfercap_scale
&= 0x1f; /* bits [4:0] valid */
144 xfercap
= (xfercap_scale
== 0 ? -1 : (1UL << xfercap_scale
));
145 dev_dbg(dev
, "%s: xfercap = %d\n", __func__
, xfercap
);
147 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
148 if (i7300_idle_platform_probe(NULL
, NULL
, 1) == 0)
151 for (i
= 0; i
< dma
->chancnt
; i
++) {
152 ioat
= devm_kzalloc(dev
, sizeof(*ioat
), GFP_KERNEL
);
156 ioat_init_channel(device
, &ioat
->base
, i
);
157 ioat
->xfercap
= xfercap
;
158 spin_lock_init(&ioat
->desc_lock
);
159 INIT_LIST_HEAD(&ioat
->free_desc
);
160 INIT_LIST_HEAD(&ioat
->used_desc
);
167 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
169 * @chan: DMA channel handle
172 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan
*ioat
)
174 void __iomem
*reg_base
= ioat
->base
.reg_base
;
176 dev_dbg(to_dev(&ioat
->base
), "%s: pending: %d\n",
177 __func__
, ioat
->pending
);
179 writeb(IOAT_CHANCMD_APPEND
, reg_base
+ IOAT1_CHANCMD_OFFSET
);
182 static void ioat1_dma_memcpy_issue_pending(struct dma_chan
*chan
)
184 struct ioat_dma_chan
*ioat
= to_ioat_chan(chan
);
186 if (ioat
->pending
> 0) {
187 spin_lock_bh(&ioat
->desc_lock
);
188 __ioat1_dma_memcpy_issue_pending(ioat
);
189 spin_unlock_bh(&ioat
->desc_lock
);
194 * ioat1_reset_channel - restart a channel
195 * @ioat: IOAT DMA channel handle
197 static void ioat1_reset_channel(struct ioat_dma_chan
*ioat
)
199 struct ioat_chan_common
*chan
= &ioat
->base
;
200 void __iomem
*reg_base
= chan
->reg_base
;
201 u32 chansts
, chanerr
;
203 dev_warn(to_dev(chan
), "reset\n");
204 chanerr
= readl(reg_base
+ IOAT_CHANERR_OFFSET
);
205 chansts
= *chan
->completion
& IOAT_CHANSTS_STATUS
;
207 dev_err(to_dev(chan
),
208 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
209 chan_num(chan
), chansts
, chanerr
);
210 writel(chanerr
, reg_base
+ IOAT_CHANERR_OFFSET
);
214 * whack it upside the head with a reset
215 * and wait for things to settle out.
216 * force the pending count to a really big negative
217 * to make sure no one forces an issue_pending
218 * while we're waiting.
221 ioat
->pending
= INT_MIN
;
222 writeb(IOAT_CHANCMD_RESET
,
223 reg_base
+ IOAT_CHANCMD_OFFSET(chan
->device
->version
));
224 set_bit(IOAT_RESET_PENDING
, &chan
->state
);
225 mod_timer(&chan
->timer
, jiffies
+ RESET_DELAY
);
228 static dma_cookie_t
ioat1_tx_submit(struct dma_async_tx_descriptor
*tx
)
230 struct dma_chan
*c
= tx
->chan
;
231 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
232 struct ioat_desc_sw
*desc
= tx_to_ioat_desc(tx
);
233 struct ioat_chan_common
*chan
= &ioat
->base
;
234 struct ioat_desc_sw
*first
;
235 struct ioat_desc_sw
*chain_tail
;
238 spin_lock_bh(&ioat
->desc_lock
);
239 /* cookie incr and addition to used_list must be atomic */
246 dev_dbg(to_dev(&ioat
->base
), "%s: cookie: %d\n", __func__
, cookie
);
248 /* write address into NextDescriptor field of last desc in chain */
249 first
= to_ioat_desc(desc
->tx_list
.next
);
250 chain_tail
= to_ioat_desc(ioat
->used_desc
.prev
);
251 /* make descriptor updates globally visible before chaining */
253 chain_tail
->hw
->next
= first
->txd
.phys
;
254 list_splice_tail_init(&desc
->tx_list
, &ioat
->used_desc
);
255 dump_desc_dbg(ioat
, chain_tail
);
256 dump_desc_dbg(ioat
, first
);
258 if (!test_and_set_bit(IOAT_COMPLETION_PENDING
, &chan
->state
))
259 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
261 ioat
->active
+= desc
->hw
->tx_cnt
;
262 ioat
->pending
+= desc
->hw
->tx_cnt
;
263 if (ioat
->pending
>= ioat_pending_level
)
264 __ioat1_dma_memcpy_issue_pending(ioat
);
265 spin_unlock_bh(&ioat
->desc_lock
);
271 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
272 * @ioat: the channel supplying the memory pool for the descriptors
273 * @flags: allocation flags
275 static struct ioat_desc_sw
*
276 ioat_dma_alloc_descriptor(struct ioat_dma_chan
*ioat
, gfp_t flags
)
278 struct ioat_dma_descriptor
*desc
;
279 struct ioat_desc_sw
*desc_sw
;
280 struct ioatdma_device
*ioatdma_device
;
283 ioatdma_device
= ioat
->base
.device
;
284 desc
= pci_pool_alloc(ioatdma_device
->dma_pool
, flags
, &phys
);
288 desc_sw
= kzalloc(sizeof(*desc_sw
), flags
);
289 if (unlikely(!desc_sw
)) {
290 pci_pool_free(ioatdma_device
->dma_pool
, desc
, phys
);
294 memset(desc
, 0, sizeof(*desc
));
296 INIT_LIST_HEAD(&desc_sw
->tx_list
);
297 dma_async_tx_descriptor_init(&desc_sw
->txd
, &ioat
->base
.common
);
298 desc_sw
->txd
.tx_submit
= ioat1_tx_submit
;
300 desc_sw
->txd
.phys
= phys
;
301 set_desc_id(desc_sw
, -1);
306 static int ioat_initial_desc_count
= 256;
307 module_param(ioat_initial_desc_count
, int, 0644);
308 MODULE_PARM_DESC(ioat_initial_desc_count
,
309 "ioat1: initial descriptors per channel (default: 256)");
311 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
312 * @chan: the channel to be filled out
314 static int ioat1_dma_alloc_chan_resources(struct dma_chan
*c
)
316 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
317 struct ioat_chan_common
*chan
= &ioat
->base
;
318 struct ioat_desc_sw
*desc
;
323 /* have we already been set up? */
324 if (!list_empty(&ioat
->free_desc
))
325 return ioat
->desccount
;
327 /* Setup register to interrupt and write completion status on error */
328 writew(IOAT_CHANCTRL_RUN
, chan
->reg_base
+ IOAT_CHANCTRL_OFFSET
);
330 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
332 dev_err(to_dev(chan
), "CHANERR = %x, clearing\n", chanerr
);
333 writel(chanerr
, chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
336 /* Allocate descriptors */
337 for (i
= 0; i
< ioat_initial_desc_count
; i
++) {
338 desc
= ioat_dma_alloc_descriptor(ioat
, GFP_KERNEL
);
340 dev_err(to_dev(chan
), "Only %d initial descriptors\n", i
);
343 set_desc_id(desc
, i
);
344 list_add_tail(&desc
->node
, &tmp_list
);
346 spin_lock_bh(&ioat
->desc_lock
);
348 list_splice(&tmp_list
, &ioat
->free_desc
);
349 spin_unlock_bh(&ioat
->desc_lock
);
351 /* allocate a completion writeback area */
352 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
353 chan
->completion
= pci_pool_alloc(chan
->device
->completion_pool
,
354 GFP_KERNEL
, &chan
->completion_dma
);
355 memset(chan
->completion
, 0, sizeof(*chan
->completion
));
356 writel(((u64
) chan
->completion_dma
) & 0x00000000FFFFFFFF,
357 chan
->reg_base
+ IOAT_CHANCMP_OFFSET_LOW
);
358 writel(((u64
) chan
->completion_dma
) >> 32,
359 chan
->reg_base
+ IOAT_CHANCMP_OFFSET_HIGH
);
361 tasklet_enable(&chan
->cleanup_task
);
362 ioat1_dma_start_null_desc(ioat
); /* give chain to dma device */
363 dev_dbg(to_dev(chan
), "%s: allocated %d descriptors\n",
364 __func__
, ioat
->desccount
);
365 return ioat
->desccount
;
369 * ioat1_dma_free_chan_resources - release all the descriptors
370 * @chan: the channel to be cleaned
372 static void ioat1_dma_free_chan_resources(struct dma_chan
*c
)
374 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
375 struct ioat_chan_common
*chan
= &ioat
->base
;
376 struct ioatdma_device
*ioatdma_device
= chan
->device
;
377 struct ioat_desc_sw
*desc
, *_desc
;
378 int in_use_descs
= 0;
380 /* Before freeing channel resources first check
381 * if they have been previously allocated for this channel.
383 if (ioat
->desccount
== 0)
386 tasklet_disable(&chan
->cleanup_task
);
387 del_timer_sync(&chan
->timer
);
390 /* Delay 100ms after reset to allow internal DMA logic to quiesce
391 * before removing DMA descriptor resources.
393 writeb(IOAT_CHANCMD_RESET
,
394 chan
->reg_base
+ IOAT_CHANCMD_OFFSET(chan
->device
->version
));
397 spin_lock_bh(&ioat
->desc_lock
);
398 list_for_each_entry_safe(desc
, _desc
, &ioat
->used_desc
, node
) {
399 dev_dbg(to_dev(chan
), "%s: freeing %d from used list\n",
400 __func__
, desc_id(desc
));
401 dump_desc_dbg(ioat
, desc
);
403 list_del(&desc
->node
);
404 pci_pool_free(ioatdma_device
->dma_pool
, desc
->hw
,
408 list_for_each_entry_safe(desc
, _desc
,
409 &ioat
->free_desc
, node
) {
410 list_del(&desc
->node
);
411 pci_pool_free(ioatdma_device
->dma_pool
, desc
->hw
,
415 spin_unlock_bh(&ioat
->desc_lock
);
417 pci_pool_free(ioatdma_device
->completion_pool
,
419 chan
->completion_dma
);
421 /* one is ok since we left it on there on purpose */
422 if (in_use_descs
> 1)
423 dev_err(to_dev(chan
), "Freeing %d in use descriptors!\n",
426 chan
->last_completion
= 0;
427 chan
->completion_dma
= 0;
433 * ioat1_dma_get_next_descriptor - return the next available descriptor
434 * @ioat: IOAT DMA channel handle
436 * Gets the next descriptor from the chain, and must be called with the
437 * channel's desc_lock held. Allocates more descriptors if the channel
440 static struct ioat_desc_sw
*
441 ioat1_dma_get_next_descriptor(struct ioat_dma_chan
*ioat
)
443 struct ioat_desc_sw
*new;
445 if (!list_empty(&ioat
->free_desc
)) {
446 new = to_ioat_desc(ioat
->free_desc
.next
);
447 list_del(&new->node
);
449 /* try to get another desc */
450 new = ioat_dma_alloc_descriptor(ioat
, GFP_ATOMIC
);
452 dev_err(to_dev(&ioat
->base
), "alloc failed\n");
456 dev_dbg(to_dev(&ioat
->base
), "%s: allocated: %d\n",
457 __func__
, desc_id(new));
462 static struct dma_async_tx_descriptor
*
463 ioat1_dma_prep_memcpy(struct dma_chan
*c
, dma_addr_t dma_dest
,
464 dma_addr_t dma_src
, size_t len
, unsigned long flags
)
466 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
467 struct ioat_desc_sw
*desc
;
470 dma_addr_t src
= dma_src
;
471 dma_addr_t dest
= dma_dest
;
472 size_t total_len
= len
;
473 struct ioat_dma_descriptor
*hw
= NULL
;
476 spin_lock_bh(&ioat
->desc_lock
);
477 desc
= ioat1_dma_get_next_descriptor(ioat
);
483 copy
= min_t(size_t, len
, ioat
->xfercap
);
491 list_add_tail(&desc
->node
, &chain
);
497 struct ioat_desc_sw
*next
;
499 async_tx_ack(&desc
->txd
);
500 next
= ioat1_dma_get_next_descriptor(ioat
);
501 hw
->next
= next
? next
->txd
.phys
: 0;
502 dump_desc_dbg(ioat
, desc
);
509 struct ioat_chan_common
*chan
= &ioat
->base
;
511 dev_err(to_dev(chan
),
512 "chan%d - get_next_desc failed\n", chan_num(chan
));
513 list_splice(&chain
, &ioat
->free_desc
);
514 spin_unlock_bh(&ioat
->desc_lock
);
517 spin_unlock_bh(&ioat
->desc_lock
);
519 desc
->txd
.flags
= flags
;
520 desc
->len
= total_len
;
521 list_splice(&chain
, &desc
->tx_list
);
522 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
523 hw
->ctl_f
.compl_write
= 1;
525 dump_desc_dbg(ioat
, desc
);
530 static void ioat1_cleanup_event(unsigned long data
)
532 struct ioat_dma_chan
*ioat
= to_ioat_chan((void *) data
);
535 writew(IOAT_CHANCTRL_RUN
, ioat
->base
.reg_base
+ IOAT_CHANCTRL_OFFSET
);
538 void ioat_dma_unmap(struct ioat_chan_common
*chan
, enum dma_ctrl_flags flags
,
539 size_t len
, struct ioat_dma_descriptor
*hw
)
541 struct pci_dev
*pdev
= chan
->device
->pdev
;
542 size_t offset
= len
- hw
->size
;
544 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
))
545 ioat_unmap(pdev
, hw
->dst_addr
- offset
, len
,
546 PCI_DMA_FROMDEVICE
, flags
, 1);
548 if (!(flags
& DMA_COMPL_SKIP_SRC_UNMAP
))
549 ioat_unmap(pdev
, hw
->src_addr
- offset
, len
,
550 PCI_DMA_TODEVICE
, flags
, 0);
553 unsigned long ioat_get_current_completion(struct ioat_chan_common
*chan
)
555 unsigned long phys_complete
;
558 completion
= *chan
->completion
;
559 phys_complete
= ioat_chansts_to_addr(completion
);
561 dev_dbg(to_dev(chan
), "%s: phys_complete: %#llx\n", __func__
,
562 (unsigned long long) phys_complete
);
564 if (is_ioat_halted(completion
)) {
565 u32 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
566 dev_err(to_dev(chan
), "Channel halted, chanerr = %x\n",
569 /* TODO do something to salvage the situation */
572 return phys_complete
;
575 bool ioat_cleanup_preamble(struct ioat_chan_common
*chan
,
576 unsigned long *phys_complete
)
578 *phys_complete
= ioat_get_current_completion(chan
);
579 if (*phys_complete
== chan
->last_completion
)
581 clear_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
582 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
587 static void __cleanup(struct ioat_dma_chan
*ioat
, unsigned long phys_complete
)
589 struct ioat_chan_common
*chan
= &ioat
->base
;
590 struct list_head
*_desc
, *n
;
591 struct dma_async_tx_descriptor
*tx
;
593 dev_dbg(to_dev(chan
), "%s: phys_complete: %lx\n",
594 __func__
, phys_complete
);
595 list_for_each_safe(_desc
, n
, &ioat
->used_desc
) {
596 struct ioat_desc_sw
*desc
;
599 desc
= list_entry(_desc
, typeof(*desc
), node
);
602 * Incoming DMA requests may use multiple descriptors,
603 * due to exceeding xfercap, perhaps. If so, only the
604 * last one will have a cookie, and require unmapping.
606 dump_desc_dbg(ioat
, desc
);
608 chan
->common
.completed_cookie
= tx
->cookie
;
610 ioat_dma_unmap(chan
, tx
->flags
, desc
->len
, desc
->hw
);
611 ioat
->active
-= desc
->hw
->tx_cnt
;
613 tx
->callback(tx
->callback_param
);
618 if (tx
->phys
!= phys_complete
) {
620 * a completed entry, but not the last, so clean
621 * up if the client is done with the descriptor
623 if (async_tx_test_ack(tx
))
624 list_move_tail(&desc
->node
, &ioat
->free_desc
);
627 * last used desc. Do not remove, so we can
631 /* if nothing else is pending, cancel the
634 if (n
== &ioat
->used_desc
) {
635 dev_dbg(to_dev(chan
),
636 "%s cancel completion timeout\n",
638 clear_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
641 /* TODO check status bits? */
646 chan
->last_completion
= phys_complete
;
650 * ioat1_cleanup - cleanup up finished descriptors
651 * @chan: ioat channel to be cleaned up
653 * To prevent lock contention we defer cleanup when the locks are
654 * contended with a terminal timeout that forces cleanup and catches
655 * completion notification errors.
657 static void ioat1_cleanup(struct ioat_dma_chan
*ioat
)
659 struct ioat_chan_common
*chan
= &ioat
->base
;
660 unsigned long phys_complete
;
662 prefetch(chan
->completion
);
664 if (!spin_trylock_bh(&chan
->cleanup_lock
))
667 if (!ioat_cleanup_preamble(chan
, &phys_complete
)) {
668 spin_unlock_bh(&chan
->cleanup_lock
);
672 if (!spin_trylock_bh(&ioat
->desc_lock
)) {
673 spin_unlock_bh(&chan
->cleanup_lock
);
677 __cleanup(ioat
, phys_complete
);
679 spin_unlock_bh(&ioat
->desc_lock
);
680 spin_unlock_bh(&chan
->cleanup_lock
);
683 static void ioat1_timer_event(unsigned long data
)
685 struct ioat_dma_chan
*ioat
= to_ioat_chan((void *) data
);
686 struct ioat_chan_common
*chan
= &ioat
->base
;
688 dev_dbg(to_dev(chan
), "%s: state: %lx\n", __func__
, chan
->state
);
690 spin_lock_bh(&chan
->cleanup_lock
);
691 if (test_and_clear_bit(IOAT_RESET_PENDING
, &chan
->state
)) {
692 struct ioat_desc_sw
*desc
;
694 spin_lock_bh(&ioat
->desc_lock
);
696 /* restart active descriptors */
697 desc
= to_ioat_desc(ioat
->used_desc
.prev
);
698 ioat_set_chainaddr(ioat
, desc
->txd
.phys
);
702 set_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
703 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
704 spin_unlock_bh(&ioat
->desc_lock
);
705 } else if (test_bit(IOAT_COMPLETION_PENDING
, &chan
->state
)) {
706 unsigned long phys_complete
;
708 spin_lock_bh(&ioat
->desc_lock
);
709 /* if we haven't made progress and we have already
710 * acknowledged a pending completion once, then be more
711 * forceful with a restart
713 if (ioat_cleanup_preamble(chan
, &phys_complete
))
714 __cleanup(ioat
, phys_complete
);
715 else if (test_bit(IOAT_COMPLETION_ACK
, &chan
->state
))
716 ioat1_reset_channel(ioat
);
718 u64 status
= ioat_chansts(chan
);
720 /* manually update the last completion address */
721 if (ioat_chansts_to_addr(status
) != 0)
722 *chan
->completion
= status
;
724 set_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
725 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
727 spin_unlock_bh(&ioat
->desc_lock
);
729 spin_unlock_bh(&chan
->cleanup_lock
);
733 ioat_dma_tx_status(struct dma_chan
*c
, dma_cookie_t cookie
,
734 struct dma_tx_state
*txstate
)
736 struct ioat_chan_common
*chan
= to_chan_common(c
);
737 struct ioatdma_device
*device
= chan
->device
;
739 if (ioat_tx_status(c
, cookie
, txstate
) == DMA_SUCCESS
)
742 device
->cleanup_fn((unsigned long) c
);
744 return ioat_tx_status(c
, cookie
, txstate
);
747 static void ioat1_dma_start_null_desc(struct ioat_dma_chan
*ioat
)
749 struct ioat_chan_common
*chan
= &ioat
->base
;
750 struct ioat_desc_sw
*desc
;
751 struct ioat_dma_descriptor
*hw
;
753 spin_lock_bh(&ioat
->desc_lock
);
755 desc
= ioat1_dma_get_next_descriptor(ioat
);
758 dev_err(to_dev(chan
),
759 "Unable to start null desc - get next desc failed\n");
760 spin_unlock_bh(&ioat
->desc_lock
);
767 hw
->ctl_f
.int_en
= 1;
768 hw
->ctl_f
.compl_write
= 1;
769 /* set size to non-zero value (channel returns error when size is 0) */
770 hw
->size
= NULL_DESC_BUFFER_SIZE
;
773 async_tx_ack(&desc
->txd
);
775 list_add_tail(&desc
->node
, &ioat
->used_desc
);
776 dump_desc_dbg(ioat
, desc
);
778 ioat_set_chainaddr(ioat
, desc
->txd
.phys
);
780 spin_unlock_bh(&ioat
->desc_lock
);
784 * Perform a IOAT transaction to verify the HW works.
786 #define IOAT_TEST_SIZE 2000
788 static void __devinit
ioat_dma_test_callback(void *dma_async_param
)
790 struct completion
*cmp
= dma_async_param
;
796 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
797 * @device: device to be tested
799 int __devinit
ioat_dma_self_test(struct ioatdma_device
*device
)
804 struct dma_device
*dma
= &device
->common
;
805 struct device
*dev
= &device
->pdev
->dev
;
806 struct dma_chan
*dma_chan
;
807 struct dma_async_tx_descriptor
*tx
;
808 dma_addr_t dma_dest
, dma_src
;
811 struct completion cmp
;
815 src
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
818 dest
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
824 /* Fill in src buffer */
825 for (i
= 0; i
< IOAT_TEST_SIZE
; i
++)
828 /* Start copy, using first DMA channel */
829 dma_chan
= container_of(dma
->channels
.next
, struct dma_chan
,
831 if (dma
->device_alloc_chan_resources(dma_chan
) < 1) {
832 dev_err(dev
, "selftest cannot allocate chan resource\n");
837 dma_src
= dma_map_single(dev
, src
, IOAT_TEST_SIZE
, DMA_TO_DEVICE
);
838 dma_dest
= dma_map_single(dev
, dest
, IOAT_TEST_SIZE
, DMA_FROM_DEVICE
);
839 flags
= DMA_COMPL_SRC_UNMAP_SINGLE
| DMA_COMPL_DEST_UNMAP_SINGLE
|
841 tx
= device
->common
.device_prep_dma_memcpy(dma_chan
, dma_dest
, dma_src
,
842 IOAT_TEST_SIZE
, flags
);
844 dev_err(dev
, "Self-test prep failed, disabling\n");
850 init_completion(&cmp
);
851 tx
->callback
= ioat_dma_test_callback
;
852 tx
->callback_param
= &cmp
;
853 cookie
= tx
->tx_submit(tx
);
855 dev_err(dev
, "Self-test setup failed, disabling\n");
859 dma
->device_issue_pending(dma_chan
);
861 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
864 dma
->device_tx_status(dma_chan
, cookie
, NULL
)
866 dev_err(dev
, "Self-test copy timed out, disabling\n");
870 if (memcmp(src
, dest
, IOAT_TEST_SIZE
)) {
871 dev_err(dev
, "Self-test copy failed compare, disabling\n");
877 dma
->device_free_chan_resources(dma_chan
);
884 static char ioat_interrupt_style
[32] = "msix";
885 module_param_string(ioat_interrupt_style
, ioat_interrupt_style
,
886 sizeof(ioat_interrupt_style
), 0644);
887 MODULE_PARM_DESC(ioat_interrupt_style
,
888 "set ioat interrupt style: msix (default), "
889 "msix-single-vector, msi, intx)");
892 * ioat_dma_setup_interrupts - setup interrupt handler
893 * @device: ioat device
895 static int ioat_dma_setup_interrupts(struct ioatdma_device
*device
)
897 struct ioat_chan_common
*chan
;
898 struct pci_dev
*pdev
= device
->pdev
;
899 struct device
*dev
= &pdev
->dev
;
900 struct msix_entry
*msix
;
905 if (!strcmp(ioat_interrupt_style
, "msix"))
907 if (!strcmp(ioat_interrupt_style
, "msix-single-vector"))
908 goto msix_single_vector
;
909 if (!strcmp(ioat_interrupt_style
, "msi"))
911 if (!strcmp(ioat_interrupt_style
, "intx"))
913 dev_err(dev
, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style
);
917 /* The number of MSI-X vectors should equal the number of channels */
918 msixcnt
= device
->common
.chancnt
;
919 for (i
= 0; i
< msixcnt
; i
++)
920 device
->msix_entries
[i
].entry
= i
;
922 err
= pci_enable_msix(pdev
, device
->msix_entries
, msixcnt
);
926 goto msix_single_vector
;
928 for (i
= 0; i
< msixcnt
; i
++) {
929 msix
= &device
->msix_entries
[i
];
930 chan
= ioat_chan_by_index(device
, i
);
931 err
= devm_request_irq(dev
, msix
->vector
,
932 ioat_dma_do_interrupt_msix
, 0,
935 for (j
= 0; j
< i
; j
++) {
936 msix
= &device
->msix_entries
[j
];
937 chan
= ioat_chan_by_index(device
, j
);
938 devm_free_irq(dev
, msix
->vector
, chan
);
940 goto msix_single_vector
;
943 intrctrl
|= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL
;
947 msix
= &device
->msix_entries
[0];
949 err
= pci_enable_msix(pdev
, device
->msix_entries
, 1);
953 err
= devm_request_irq(dev
, msix
->vector
, ioat_dma_do_interrupt
, 0,
954 "ioat-msix", device
);
956 pci_disable_msix(pdev
);
962 err
= pci_enable_msi(pdev
);
966 err
= devm_request_irq(dev
, pdev
->irq
, ioat_dma_do_interrupt
, 0,
969 pci_disable_msi(pdev
);
975 err
= devm_request_irq(dev
, pdev
->irq
, ioat_dma_do_interrupt
,
976 IRQF_SHARED
, "ioat-intx", device
);
981 if (device
->intr_quirk
)
982 device
->intr_quirk(device
);
983 intrctrl
|= IOAT_INTRCTRL_MASTER_INT_EN
;
984 writeb(intrctrl
, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
988 /* Disable all interrupt generation */
989 writeb(0, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
990 dev_err(dev
, "no usable interrupts\n");
994 static void ioat_disable_interrupts(struct ioatdma_device
*device
)
996 /* Disable all interrupt generation */
997 writeb(0, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
1000 int __devinit
ioat_probe(struct ioatdma_device
*device
)
1003 struct dma_device
*dma
= &device
->common
;
1004 struct pci_dev
*pdev
= device
->pdev
;
1005 struct device
*dev
= &pdev
->dev
;
1007 /* DMA coherent memory pool for DMA descriptor allocations */
1008 device
->dma_pool
= pci_pool_create("dma_desc_pool", pdev
,
1009 sizeof(struct ioat_dma_descriptor
),
1011 if (!device
->dma_pool
) {
1016 device
->completion_pool
= pci_pool_create("completion_pool", pdev
,
1017 sizeof(u64
), SMP_CACHE_BYTES
,
1020 if (!device
->completion_pool
) {
1022 goto err_completion_pool
;
1025 device
->enumerate_channels(device
);
1027 dma_cap_set(DMA_MEMCPY
, dma
->cap_mask
);
1028 dma
->dev
= &pdev
->dev
;
1030 if (!dma
->chancnt
) {
1031 dev_err(dev
, "channel enumeration error\n");
1032 goto err_setup_interrupts
;
1035 err
= ioat_dma_setup_interrupts(device
);
1037 goto err_setup_interrupts
;
1039 err
= device
->self_test(device
);
1046 ioat_disable_interrupts(device
);
1047 err_setup_interrupts
:
1048 pci_pool_destroy(device
->completion_pool
);
1049 err_completion_pool
:
1050 pci_pool_destroy(device
->dma_pool
);
1055 int __devinit
ioat_register(struct ioatdma_device
*device
)
1057 int err
= dma_async_device_register(&device
->common
);
1060 ioat_disable_interrupts(device
);
1061 pci_pool_destroy(device
->completion_pool
);
1062 pci_pool_destroy(device
->dma_pool
);
1068 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1069 static void ioat1_intr_quirk(struct ioatdma_device
*device
)
1071 struct pci_dev
*pdev
= device
->pdev
;
1074 pci_read_config_dword(pdev
, IOAT_PCI_DMACTRL_OFFSET
, &dmactrl
);
1075 if (pdev
->msi_enabled
)
1076 dmactrl
|= IOAT_PCI_DMACTRL_MSI_EN
;
1078 dmactrl
&= ~IOAT_PCI_DMACTRL_MSI_EN
;
1079 pci_write_config_dword(pdev
, IOAT_PCI_DMACTRL_OFFSET
, dmactrl
);
1082 static ssize_t
ring_size_show(struct dma_chan
*c
, char *page
)
1084 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
1086 return sprintf(page
, "%d\n", ioat
->desccount
);
1088 static struct ioat_sysfs_entry ring_size_attr
= __ATTR_RO(ring_size
);
1090 static ssize_t
ring_active_show(struct dma_chan
*c
, char *page
)
1092 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
1094 return sprintf(page
, "%d\n", ioat
->active
);
1096 static struct ioat_sysfs_entry ring_active_attr
= __ATTR_RO(ring_active
);
1098 static ssize_t
cap_show(struct dma_chan
*c
, char *page
)
1100 struct dma_device
*dma
= c
->device
;
1102 return sprintf(page
, "copy%s%s%s%s%s%s\n",
1103 dma_has_cap(DMA_PQ
, dma
->cap_mask
) ? " pq" : "",
1104 dma_has_cap(DMA_PQ_VAL
, dma
->cap_mask
) ? " pq_val" : "",
1105 dma_has_cap(DMA_XOR
, dma
->cap_mask
) ? " xor" : "",
1106 dma_has_cap(DMA_XOR_VAL
, dma
->cap_mask
) ? " xor_val" : "",
1107 dma_has_cap(DMA_MEMSET
, dma
->cap_mask
) ? " fill" : "",
1108 dma_has_cap(DMA_INTERRUPT
, dma
->cap_mask
) ? " intr" : "");
1111 struct ioat_sysfs_entry ioat_cap_attr
= __ATTR_RO(cap
);
1113 static ssize_t
version_show(struct dma_chan
*c
, char *page
)
1115 struct dma_device
*dma
= c
->device
;
1116 struct ioatdma_device
*device
= to_ioatdma_device(dma
);
1118 return sprintf(page
, "%d.%d\n",
1119 device
->version
>> 4, device
->version
& 0xf);
1121 struct ioat_sysfs_entry ioat_version_attr
= __ATTR_RO(version
);
1123 static struct attribute
*ioat1_attrs
[] = {
1124 &ring_size_attr
.attr
,
1125 &ring_active_attr
.attr
,
1126 &ioat_cap_attr
.attr
,
1127 &ioat_version_attr
.attr
,
1132 ioat_attr_show(struct kobject
*kobj
, struct attribute
*attr
, char *page
)
1134 struct ioat_sysfs_entry
*entry
;
1135 struct ioat_chan_common
*chan
;
1137 entry
= container_of(attr
, struct ioat_sysfs_entry
, attr
);
1138 chan
= container_of(kobj
, struct ioat_chan_common
, kobj
);
1142 return entry
->show(&chan
->common
, page
);
1145 const struct sysfs_ops ioat_sysfs_ops
= {
1146 .show
= ioat_attr_show
,
1149 static struct kobj_type ioat1_ktype
= {
1150 .sysfs_ops
= &ioat_sysfs_ops
,
1151 .default_attrs
= ioat1_attrs
,
1154 void ioat_kobject_add(struct ioatdma_device
*device
, struct kobj_type
*type
)
1156 struct dma_device
*dma
= &device
->common
;
1159 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1160 struct ioat_chan_common
*chan
= to_chan_common(c
);
1161 struct kobject
*parent
= &c
->dev
->device
.kobj
;
1164 err
= kobject_init_and_add(&chan
->kobj
, type
, parent
, "quickdata");
1166 dev_warn(to_dev(chan
),
1167 "sysfs init error (%d), continuing...\n", err
);
1168 kobject_put(&chan
->kobj
);
1169 set_bit(IOAT_KOBJ_INIT_FAIL
, &chan
->state
);
1174 void ioat_kobject_del(struct ioatdma_device
*device
)
1176 struct dma_device
*dma
= &device
->common
;
1179 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1180 struct ioat_chan_common
*chan
= to_chan_common(c
);
1182 if (!test_bit(IOAT_KOBJ_INIT_FAIL
, &chan
->state
)) {
1183 kobject_del(&chan
->kobj
);
1184 kobject_put(&chan
->kobj
);
1189 int __devinit
ioat1_dma_probe(struct ioatdma_device
*device
, int dca
)
1191 struct pci_dev
*pdev
= device
->pdev
;
1192 struct dma_device
*dma
;
1195 device
->intr_quirk
= ioat1_intr_quirk
;
1196 device
->enumerate_channels
= ioat1_enumerate_channels
;
1197 device
->self_test
= ioat_dma_self_test
;
1198 device
->timer_fn
= ioat1_timer_event
;
1199 device
->cleanup_fn
= ioat1_cleanup_event
;
1200 dma
= &device
->common
;
1201 dma
->device_prep_dma_memcpy
= ioat1_dma_prep_memcpy
;
1202 dma
->device_issue_pending
= ioat1_dma_memcpy_issue_pending
;
1203 dma
->device_alloc_chan_resources
= ioat1_dma_alloc_chan_resources
;
1204 dma
->device_free_chan_resources
= ioat1_dma_free_chan_resources
;
1205 dma
->device_tx_status
= ioat_dma_tx_status
;
1207 err
= ioat_probe(device
);
1210 ioat_set_tcp_copy_break(4096);
1211 err
= ioat_register(device
);
1214 ioat_kobject_add(device
, &ioat1_ktype
);
1217 device
->dca
= ioat_dca_init(pdev
, device
->reg_base
);
1222 void __devexit
ioat_dma_remove(struct ioatdma_device
*device
)
1224 struct dma_device
*dma
= &device
->common
;
1226 ioat_disable_interrupts(device
);
1228 ioat_kobject_del(device
);
1230 dma_async_device_unregister(dma
);
1232 pci_pool_destroy(device
->dma_pool
);
1233 pci_pool_destroy(device
->completion_pool
);
1235 INIT_LIST_HEAD(&dma
->channels
);