2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/memory.h>
28 #include <linux/clk.h>
30 #include <linux/of_irq.h>
31 #include <linux/irqdomain.h>
32 #include <linux/platform_data/dma-mv_xor.h>
34 #include "dmaengine.h"
37 static void mv_xor_issue_pending(struct dma_chan
*chan
);
39 #define to_mv_xor_chan(chan) \
40 container_of(chan, struct mv_xor_chan, dmachan)
42 #define to_mv_xor_slot(tx) \
43 container_of(tx, struct mv_xor_desc_slot, async_tx)
45 #define mv_chan_to_devp(chan) \
48 static void mv_desc_init(struct mv_xor_desc_slot
*desc
, unsigned long flags
)
50 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
52 hw_desc
->status
= (1 << 31);
53 hw_desc
->phy_next_desc
= 0;
54 hw_desc
->desc_command
= (1 << 31);
57 static void mv_desc_set_byte_count(struct mv_xor_desc_slot
*desc
,
60 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
61 hw_desc
->byte_count
= byte_count
;
64 static void mv_desc_set_next_desc(struct mv_xor_desc_slot
*desc
,
67 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
68 BUG_ON(hw_desc
->phy_next_desc
);
69 hw_desc
->phy_next_desc
= next_desc_addr
;
72 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot
*desc
)
74 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
75 hw_desc
->phy_next_desc
= 0;
78 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot
*desc
,
81 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
82 hw_desc
->phy_dest_addr
= addr
;
85 static int mv_chan_memset_slot_count(size_t len
)
90 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
92 static void mv_desc_set_src_addr(struct mv_xor_desc_slot
*desc
,
93 int index
, dma_addr_t addr
)
95 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
96 hw_desc
->phy_src_addr
[mv_phy_src_idx(index
)] = addr
;
97 if (desc
->type
== DMA_XOR
)
98 hw_desc
->desc_command
|= (1 << index
);
101 static u32
mv_chan_get_current_desc(struct mv_xor_chan
*chan
)
103 return readl_relaxed(XOR_CURR_DESC(chan
));
106 static void mv_chan_set_next_descriptor(struct mv_xor_chan
*chan
,
109 writel_relaxed(next_desc_addr
, XOR_NEXT_DESC(chan
));
112 static void mv_chan_unmask_interrupts(struct mv_xor_chan
*chan
)
114 u32 val
= readl_relaxed(XOR_INTR_MASK(chan
));
115 val
|= XOR_INTR_MASK_VALUE
<< (chan
->idx
* 16);
116 writel_relaxed(val
, XOR_INTR_MASK(chan
));
119 static u32
mv_chan_get_intr_cause(struct mv_xor_chan
*chan
)
121 u32 intr_cause
= readl_relaxed(XOR_INTR_CAUSE(chan
));
122 intr_cause
= (intr_cause
>> (chan
->idx
* 16)) & 0xFFFF;
126 static int mv_is_err_intr(u32 intr_cause
)
128 if (intr_cause
& ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
134 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan
*chan
)
136 u32 val
= ~(1 << (chan
->idx
* 16));
137 dev_dbg(mv_chan_to_devp(chan
), "%s, val 0x%08x\n", __func__
, val
);
138 writel_relaxed(val
, XOR_INTR_CAUSE(chan
));
141 static void mv_xor_device_clear_err_status(struct mv_xor_chan
*chan
)
143 u32 val
= 0xFFFF0000 >> (chan
->idx
* 16);
144 writel_relaxed(val
, XOR_INTR_CAUSE(chan
));
147 static int mv_can_chain(struct mv_xor_desc_slot
*desc
)
149 struct mv_xor_desc_slot
*chain_old_tail
= list_entry(
150 desc
->chain_node
.prev
, struct mv_xor_desc_slot
, chain_node
);
152 if (chain_old_tail
->type
!= desc
->type
)
158 static void mv_set_mode(struct mv_xor_chan
*chan
,
159 enum dma_transaction_type type
)
162 u32 config
= readl_relaxed(XOR_CONFIG(chan
));
166 op_mode
= XOR_OPERATION_MODE_XOR
;
169 op_mode
= XOR_OPERATION_MODE_MEMCPY
;
172 dev_err(mv_chan_to_devp(chan
),
173 "error: unsupported operation %d\n",
182 #if defined(__BIG_ENDIAN)
183 config
|= XOR_DESCRIPTOR_SWAP
;
185 config
&= ~XOR_DESCRIPTOR_SWAP
;
188 writel_relaxed(config
, XOR_CONFIG(chan
));
189 chan
->current_type
= type
;
192 static void mv_chan_activate(struct mv_xor_chan
*chan
)
194 dev_dbg(mv_chan_to_devp(chan
), " activate chan.\n");
196 /* writel ensures all descriptors are flushed before activation */
197 writel(BIT(0), XOR_ACTIVATION(chan
));
200 static char mv_chan_is_busy(struct mv_xor_chan
*chan
)
202 u32 state
= readl_relaxed(XOR_ACTIVATION(chan
));
204 state
= (state
>> 4) & 0x3;
206 return (state
== 1) ? 1 : 0;
209 static int mv_chan_xor_slot_count(size_t len
, int src_cnt
)
215 * mv_xor_free_slots - flags descriptor slots for reuse
216 * @slot: Slot to free
217 * Caller must hold &mv_chan->lock while calling this function
219 static void mv_xor_free_slots(struct mv_xor_chan
*mv_chan
,
220 struct mv_xor_desc_slot
*slot
)
222 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d slot %p\n",
223 __func__
, __LINE__
, slot
);
225 slot
->slots_per_op
= 0;
230 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
232 * Caller must hold &mv_chan->lock while calling this function
234 static void mv_xor_start_new_chain(struct mv_xor_chan
*mv_chan
,
235 struct mv_xor_desc_slot
*sw_desc
)
237 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d: sw_desc %p\n",
238 __func__
, __LINE__
, sw_desc
);
239 if (sw_desc
->type
!= mv_chan
->current_type
)
240 mv_set_mode(mv_chan
, sw_desc
->type
);
242 /* set the hardware chain */
243 mv_chan_set_next_descriptor(mv_chan
, sw_desc
->async_tx
.phys
);
245 mv_chan
->pending
+= sw_desc
->slot_cnt
;
246 mv_xor_issue_pending(&mv_chan
->dmachan
);
250 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot
*desc
,
251 struct mv_xor_chan
*mv_chan
, dma_cookie_t cookie
)
253 BUG_ON(desc
->async_tx
.cookie
< 0);
255 if (desc
->async_tx
.cookie
> 0) {
256 cookie
= desc
->async_tx
.cookie
;
258 /* call the callback (must not sleep or submit new
259 * operations to this channel)
261 if (desc
->async_tx
.callback
)
262 desc
->async_tx
.callback(
263 desc
->async_tx
.callback_param
);
265 dma_descriptor_unmap(&desc
->async_tx
);
266 if (desc
->group_head
)
267 desc
->group_head
= NULL
;
270 /* run dependent operations */
271 dma_run_dependencies(&desc
->async_tx
);
277 mv_xor_clean_completed_slots(struct mv_xor_chan
*mv_chan
)
279 struct mv_xor_desc_slot
*iter
, *_iter
;
281 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d\n", __func__
, __LINE__
);
282 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
285 if (async_tx_test_ack(&iter
->async_tx
)) {
286 list_del(&iter
->completed_node
);
287 mv_xor_free_slots(mv_chan
, iter
);
294 mv_xor_clean_slot(struct mv_xor_desc_slot
*desc
,
295 struct mv_xor_chan
*mv_chan
)
297 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d: desc %p flags %d\n",
298 __func__
, __LINE__
, desc
, desc
->async_tx
.flags
);
299 list_del(&desc
->chain_node
);
300 /* the client is allowed to attach dependent operations
303 if (!async_tx_test_ack(&desc
->async_tx
)) {
304 /* move this slot to the completed_slots */
305 list_add_tail(&desc
->completed_node
, &mv_chan
->completed_slots
);
309 mv_xor_free_slots(mv_chan
, desc
);
313 /* This function must be called with the mv_xor_chan spinlock held */
314 static void mv_xor_slot_cleanup(struct mv_xor_chan
*mv_chan
)
316 struct mv_xor_desc_slot
*iter
, *_iter
;
317 dma_cookie_t cookie
= 0;
318 int busy
= mv_chan_is_busy(mv_chan
);
319 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
320 int seen_current
= 0;
322 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d\n", __func__
, __LINE__
);
323 dev_dbg(mv_chan_to_devp(mv_chan
), "current_desc %x\n", current_desc
);
324 mv_xor_clean_completed_slots(mv_chan
);
326 /* free completed slots from the chain starting with
327 * the oldest descriptor
330 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
333 prefetch(&_iter
->async_tx
);
335 /* do not advance past the current descriptor loaded into the
336 * hardware channel, subsequent descriptors are either in
337 * process or have not been submitted
342 /* stop the search if we reach the current descriptor and the
345 if (iter
->async_tx
.phys
== current_desc
) {
351 cookie
= mv_xor_run_tx_complete_actions(iter
, mv_chan
, cookie
);
353 if (mv_xor_clean_slot(iter
, mv_chan
))
357 if ((busy
== 0) && !list_empty(&mv_chan
->chain
)) {
358 struct mv_xor_desc_slot
*chain_head
;
359 chain_head
= list_entry(mv_chan
->chain
.next
,
360 struct mv_xor_desc_slot
,
363 mv_xor_start_new_chain(mv_chan
, chain_head
);
367 mv_chan
->dmachan
.completed_cookie
= cookie
;
370 static void mv_xor_tasklet(unsigned long data
)
372 struct mv_xor_chan
*chan
= (struct mv_xor_chan
*) data
;
374 spin_lock_bh(&chan
->lock
);
375 mv_xor_slot_cleanup(chan
);
376 spin_unlock_bh(&chan
->lock
);
379 static struct mv_xor_desc_slot
*
380 mv_xor_alloc_slots(struct mv_xor_chan
*mv_chan
, int num_slots
,
383 struct mv_xor_desc_slot
*iter
, *_iter
, *alloc_start
= NULL
;
385 int slots_found
, retry
= 0;
387 /* start search from the last allocated descrtiptor
388 * if a contiguous allocation can not be found start searching
389 * from the beginning of the list
394 iter
= mv_chan
->last_used
;
396 iter
= list_entry(&mv_chan
->all_slots
,
397 struct mv_xor_desc_slot
,
400 list_for_each_entry_safe_continue(
401 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
403 prefetch(&_iter
->async_tx
);
404 if (iter
->slots_per_op
) {
405 /* give up after finding the first busy slot
406 * on the second pass through the list
415 /* start the allocation if the slot is correctly aligned */
419 if (slots_found
== num_slots
) {
420 struct mv_xor_desc_slot
*alloc_tail
= NULL
;
421 struct mv_xor_desc_slot
*last_used
= NULL
;
426 /* pre-ack all but the last descriptor */
427 async_tx_ack(&iter
->async_tx
);
429 list_add_tail(&iter
->chain_node
, &chain
);
431 iter
->async_tx
.cookie
= 0;
432 iter
->slot_cnt
= num_slots
;
433 iter
->xor_check_result
= NULL
;
434 for (i
= 0; i
< slots_per_op
; i
++) {
435 iter
->slots_per_op
= slots_per_op
- i
;
437 iter
= list_entry(iter
->slot_node
.next
,
438 struct mv_xor_desc_slot
,
441 num_slots
-= slots_per_op
;
443 alloc_tail
->group_head
= alloc_start
;
444 alloc_tail
->async_tx
.cookie
= -EBUSY
;
445 list_splice(&chain
, &alloc_tail
->tx_list
);
446 mv_chan
->last_used
= last_used
;
447 mv_desc_clear_next_desc(alloc_start
);
448 mv_desc_clear_next_desc(alloc_tail
);
455 /* try to free some slots if the allocation fails */
456 tasklet_schedule(&mv_chan
->irq_tasklet
);
461 /************************ DMA engine API functions ****************************/
463 mv_xor_tx_submit(struct dma_async_tx_descriptor
*tx
)
465 struct mv_xor_desc_slot
*sw_desc
= to_mv_xor_slot(tx
);
466 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(tx
->chan
);
467 struct mv_xor_desc_slot
*grp_start
, *old_chain_tail
;
469 int new_hw_chain
= 1;
471 dev_dbg(mv_chan_to_devp(mv_chan
),
472 "%s sw_desc %p: async_tx %p\n",
473 __func__
, sw_desc
, &sw_desc
->async_tx
);
475 grp_start
= sw_desc
->group_head
;
477 spin_lock_bh(&mv_chan
->lock
);
478 cookie
= dma_cookie_assign(tx
);
480 if (list_empty(&mv_chan
->chain
))
481 list_splice_init(&sw_desc
->tx_list
, &mv_chan
->chain
);
485 old_chain_tail
= list_entry(mv_chan
->chain
.prev
,
486 struct mv_xor_desc_slot
,
488 list_splice_init(&grp_start
->tx_list
,
489 &old_chain_tail
->chain_node
);
491 if (!mv_can_chain(grp_start
))
494 dev_dbg(mv_chan_to_devp(mv_chan
), "Append to last desc %pa\n",
495 &old_chain_tail
->async_tx
.phys
);
497 /* fix up the hardware chain */
498 mv_desc_set_next_desc(old_chain_tail
, grp_start
->async_tx
.phys
);
500 /* if the channel is not busy */
501 if (!mv_chan_is_busy(mv_chan
)) {
502 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
504 * and the curren desc is the end of the chain before
505 * the append, then we need to start the channel
507 if (current_desc
== old_chain_tail
->async_tx
.phys
)
513 mv_xor_start_new_chain(mv_chan
, grp_start
);
516 spin_unlock_bh(&mv_chan
->lock
);
521 /* returns the number of allocated descriptors */
522 static int mv_xor_alloc_chan_resources(struct dma_chan
*chan
)
527 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
528 struct mv_xor_desc_slot
*slot
= NULL
;
529 int num_descs_in_pool
= MV_XOR_POOL_SIZE
/MV_XOR_SLOT_SIZE
;
531 /* Allocate descriptor slots */
532 idx
= mv_chan
->slots_allocated
;
533 while (idx
< num_descs_in_pool
) {
534 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
536 printk(KERN_INFO
"MV XOR Channel only initialized"
537 " %d descriptor slots", idx
);
540 virt_desc
= mv_chan
->dma_desc_pool_virt
;
541 slot
->hw_desc
= virt_desc
+ idx
* MV_XOR_SLOT_SIZE
;
543 dma_async_tx_descriptor_init(&slot
->async_tx
, chan
);
544 slot
->async_tx
.tx_submit
= mv_xor_tx_submit
;
545 INIT_LIST_HEAD(&slot
->chain_node
);
546 INIT_LIST_HEAD(&slot
->slot_node
);
547 INIT_LIST_HEAD(&slot
->tx_list
);
548 dma_desc
= mv_chan
->dma_desc_pool
;
549 slot
->async_tx
.phys
= dma_desc
+ idx
* MV_XOR_SLOT_SIZE
;
552 spin_lock_bh(&mv_chan
->lock
);
553 mv_chan
->slots_allocated
= idx
;
554 list_add_tail(&slot
->slot_node
, &mv_chan
->all_slots
);
555 spin_unlock_bh(&mv_chan
->lock
);
558 if (mv_chan
->slots_allocated
&& !mv_chan
->last_used
)
559 mv_chan
->last_used
= list_entry(mv_chan
->all_slots
.next
,
560 struct mv_xor_desc_slot
,
563 dev_dbg(mv_chan_to_devp(mv_chan
),
564 "allocated %d descriptor slots last_used: %p\n",
565 mv_chan
->slots_allocated
, mv_chan
->last_used
);
567 return mv_chan
->slots_allocated
? : -ENOMEM
;
570 static struct dma_async_tx_descriptor
*
571 mv_xor_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
572 size_t len
, unsigned long flags
)
574 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
575 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
578 dev_dbg(mv_chan_to_devp(mv_chan
),
579 "%s dest: %pad src %pad len: %u flags: %ld\n",
580 __func__
, &dest
, &src
, len
, flags
);
581 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
584 BUG_ON(len
> MV_XOR_MAX_BYTE_COUNT
);
586 spin_lock_bh(&mv_chan
->lock
);
587 slot_cnt
= mv_chan_memcpy_slot_count(len
);
588 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
590 sw_desc
->type
= DMA_MEMCPY
;
591 sw_desc
->async_tx
.flags
= flags
;
592 grp_start
= sw_desc
->group_head
;
593 mv_desc_init(grp_start
, flags
);
594 mv_desc_set_byte_count(grp_start
, len
);
595 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
596 mv_desc_set_src_addr(grp_start
, 0, src
);
597 sw_desc
->unmap_src_cnt
= 1;
598 sw_desc
->unmap_len
= len
;
600 spin_unlock_bh(&mv_chan
->lock
);
602 dev_dbg(mv_chan_to_devp(mv_chan
),
603 "%s sw_desc %p async_tx %p\n",
604 __func__
, sw_desc
, sw_desc
? &sw_desc
->async_tx
: NULL
);
606 return sw_desc
? &sw_desc
->async_tx
: NULL
;
609 static struct dma_async_tx_descriptor
*
610 mv_xor_prep_dma_xor(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
611 unsigned int src_cnt
, size_t len
, unsigned long flags
)
613 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
614 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
617 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
620 BUG_ON(len
> MV_XOR_MAX_BYTE_COUNT
);
622 dev_dbg(mv_chan_to_devp(mv_chan
),
623 "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
624 __func__
, src_cnt
, len
, &dest
, flags
);
626 spin_lock_bh(&mv_chan
->lock
);
627 slot_cnt
= mv_chan_xor_slot_count(len
, src_cnt
);
628 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
630 sw_desc
->type
= DMA_XOR
;
631 sw_desc
->async_tx
.flags
= flags
;
632 grp_start
= sw_desc
->group_head
;
633 mv_desc_init(grp_start
, flags
);
634 /* the byte count field is the same as in memcpy desc*/
635 mv_desc_set_byte_count(grp_start
, len
);
636 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
637 sw_desc
->unmap_src_cnt
= src_cnt
;
638 sw_desc
->unmap_len
= len
;
640 mv_desc_set_src_addr(grp_start
, src_cnt
, src
[src_cnt
]);
642 spin_unlock_bh(&mv_chan
->lock
);
643 dev_dbg(mv_chan_to_devp(mv_chan
),
644 "%s sw_desc %p async_tx %p \n",
645 __func__
, sw_desc
, &sw_desc
->async_tx
);
646 return sw_desc
? &sw_desc
->async_tx
: NULL
;
649 static void mv_xor_free_chan_resources(struct dma_chan
*chan
)
651 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
652 struct mv_xor_desc_slot
*iter
, *_iter
;
653 int in_use_descs
= 0;
655 spin_lock_bh(&mv_chan
->lock
);
657 mv_xor_slot_cleanup(mv_chan
);
659 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
662 list_del(&iter
->chain_node
);
664 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
667 list_del(&iter
->completed_node
);
669 list_for_each_entry_safe_reverse(
670 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
671 list_del(&iter
->slot_node
);
673 mv_chan
->slots_allocated
--;
675 mv_chan
->last_used
= NULL
;
677 dev_dbg(mv_chan_to_devp(mv_chan
), "%s slots_allocated %d\n",
678 __func__
, mv_chan
->slots_allocated
);
679 spin_unlock_bh(&mv_chan
->lock
);
682 dev_err(mv_chan_to_devp(mv_chan
),
683 "freeing %d in use descriptors!\n", in_use_descs
);
687 * mv_xor_status - poll the status of an XOR transaction
688 * @chan: XOR channel handle
689 * @cookie: XOR transaction identifier
690 * @txstate: XOR transactions state holder (or NULL)
692 static enum dma_status
mv_xor_status(struct dma_chan
*chan
,
694 struct dma_tx_state
*txstate
)
696 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
699 ret
= dma_cookie_status(chan
, cookie
, txstate
);
700 if (ret
== DMA_COMPLETE
)
703 spin_lock_bh(&mv_chan
->lock
);
704 mv_xor_slot_cleanup(mv_chan
);
705 spin_unlock_bh(&mv_chan
->lock
);
707 return dma_cookie_status(chan
, cookie
, txstate
);
710 static void mv_dump_xor_regs(struct mv_xor_chan
*chan
)
714 val
= readl_relaxed(XOR_CONFIG(chan
));
715 dev_err(mv_chan_to_devp(chan
), "config 0x%08x\n", val
);
717 val
= readl_relaxed(XOR_ACTIVATION(chan
));
718 dev_err(mv_chan_to_devp(chan
), "activation 0x%08x\n", val
);
720 val
= readl_relaxed(XOR_INTR_CAUSE(chan
));
721 dev_err(mv_chan_to_devp(chan
), "intr cause 0x%08x\n", val
);
723 val
= readl_relaxed(XOR_INTR_MASK(chan
));
724 dev_err(mv_chan_to_devp(chan
), "intr mask 0x%08x\n", val
);
726 val
= readl_relaxed(XOR_ERROR_CAUSE(chan
));
727 dev_err(mv_chan_to_devp(chan
), "error cause 0x%08x\n", val
);
729 val
= readl_relaxed(XOR_ERROR_ADDR(chan
));
730 dev_err(mv_chan_to_devp(chan
), "error addr 0x%08x\n", val
);
733 static void mv_xor_err_interrupt_handler(struct mv_xor_chan
*chan
,
736 if (intr_cause
& (1 << 4)) {
737 dev_dbg(mv_chan_to_devp(chan
),
738 "ignore this error\n");
742 dev_err(mv_chan_to_devp(chan
),
743 "error on chan %d. intr cause 0x%08x\n",
744 chan
->idx
, intr_cause
);
746 mv_dump_xor_regs(chan
);
750 static irqreturn_t
mv_xor_interrupt_handler(int irq
, void *data
)
752 struct mv_xor_chan
*chan
= data
;
753 u32 intr_cause
= mv_chan_get_intr_cause(chan
);
755 dev_dbg(mv_chan_to_devp(chan
), "intr cause %x\n", intr_cause
);
757 if (mv_is_err_intr(intr_cause
))
758 mv_xor_err_interrupt_handler(chan
, intr_cause
);
760 tasklet_schedule(&chan
->irq_tasklet
);
762 mv_xor_device_clear_eoc_cause(chan
);
767 static void mv_xor_issue_pending(struct dma_chan
*chan
)
769 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
771 if (mv_chan
->pending
>= MV_XOR_THRESHOLD
) {
772 mv_chan
->pending
= 0;
773 mv_chan_activate(mv_chan
);
778 * Perform a transaction to verify the HW works.
781 static int mv_xor_memcpy_self_test(struct mv_xor_chan
*mv_chan
)
785 dma_addr_t src_dma
, dest_dma
;
786 struct dma_chan
*dma_chan
;
788 struct dma_async_tx_descriptor
*tx
;
789 struct dmaengine_unmap_data
*unmap
;
792 src
= kmalloc(sizeof(u8
) * PAGE_SIZE
, GFP_KERNEL
);
796 dest
= kzalloc(sizeof(u8
) * PAGE_SIZE
, GFP_KERNEL
);
802 /* Fill in src buffer */
803 for (i
= 0; i
< PAGE_SIZE
; i
++)
804 ((u8
*) src
)[i
] = (u8
)i
;
806 dma_chan
= &mv_chan
->dmachan
;
807 if (mv_xor_alloc_chan_resources(dma_chan
) < 1) {
812 unmap
= dmaengine_get_unmap_data(dma_chan
->device
->dev
, 2, GFP_KERNEL
);
818 src_dma
= dma_map_page(dma_chan
->device
->dev
, virt_to_page(src
), 0,
819 PAGE_SIZE
, DMA_TO_DEVICE
);
820 unmap
->addr
[0] = src_dma
;
822 ret
= dma_mapping_error(dma_chan
->device
->dev
, src_dma
);
829 dest_dma
= dma_map_page(dma_chan
->device
->dev
, virt_to_page(dest
), 0,
830 PAGE_SIZE
, DMA_FROM_DEVICE
);
831 unmap
->addr
[1] = dest_dma
;
833 ret
= dma_mapping_error(dma_chan
->device
->dev
, dest_dma
);
839 unmap
->len
= PAGE_SIZE
;
841 tx
= mv_xor_prep_dma_memcpy(dma_chan
, dest_dma
, src_dma
,
844 dev_err(dma_chan
->device
->dev
,
845 "Self-test cannot prepare operation, disabling\n");
850 cookie
= mv_xor_tx_submit(tx
);
851 if (dma_submit_error(cookie
)) {
852 dev_err(dma_chan
->device
->dev
,
853 "Self-test submit error, disabling\n");
858 mv_xor_issue_pending(dma_chan
);
862 if (mv_xor_status(dma_chan
, cookie
, NULL
) !=
864 dev_err(dma_chan
->device
->dev
,
865 "Self-test copy timed out, disabling\n");
870 dma_sync_single_for_cpu(dma_chan
->device
->dev
, dest_dma
,
871 PAGE_SIZE
, DMA_FROM_DEVICE
);
872 if (memcmp(src
, dest
, PAGE_SIZE
)) {
873 dev_err(dma_chan
->device
->dev
,
874 "Self-test copy failed compare, disabling\n");
880 dmaengine_unmap_put(unmap
);
881 mv_xor_free_chan_resources(dma_chan
);
888 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
890 mv_xor_xor_self_test(struct mv_xor_chan
*mv_chan
)
894 struct page
*xor_srcs
[MV_XOR_NUM_SRC_TEST
];
895 dma_addr_t dma_srcs
[MV_XOR_NUM_SRC_TEST
];
897 struct dma_async_tx_descriptor
*tx
;
898 struct dmaengine_unmap_data
*unmap
;
899 struct dma_chan
*dma_chan
;
904 int src_count
= MV_XOR_NUM_SRC_TEST
;
906 for (src_idx
= 0; src_idx
< src_count
; src_idx
++) {
907 xor_srcs
[src_idx
] = alloc_page(GFP_KERNEL
);
908 if (!xor_srcs
[src_idx
]) {
910 __free_page(xor_srcs
[src_idx
]);
915 dest
= alloc_page(GFP_KERNEL
);
918 __free_page(xor_srcs
[src_idx
]);
922 /* Fill in src buffers */
923 for (src_idx
= 0; src_idx
< src_count
; src_idx
++) {
924 u8
*ptr
= page_address(xor_srcs
[src_idx
]);
925 for (i
= 0; i
< PAGE_SIZE
; i
++)
926 ptr
[i
] = (1 << src_idx
);
929 for (src_idx
= 0; src_idx
< src_count
; src_idx
++)
930 cmp_byte
^= (u8
) (1 << src_idx
);
932 cmp_word
= (cmp_byte
<< 24) | (cmp_byte
<< 16) |
933 (cmp_byte
<< 8) | cmp_byte
;
935 memset(page_address(dest
), 0, PAGE_SIZE
);
937 dma_chan
= &mv_chan
->dmachan
;
938 if (mv_xor_alloc_chan_resources(dma_chan
) < 1) {
943 unmap
= dmaengine_get_unmap_data(dma_chan
->device
->dev
, src_count
+ 1,
951 for (i
= 0; i
< src_count
; i
++) {
952 unmap
->addr
[i
] = dma_map_page(dma_chan
->device
->dev
, xor_srcs
[i
],
953 0, PAGE_SIZE
, DMA_TO_DEVICE
);
954 dma_srcs
[i
] = unmap
->addr
[i
];
955 ret
= dma_mapping_error(dma_chan
->device
->dev
, unmap
->addr
[i
]);
963 unmap
->addr
[src_count
] = dma_map_page(dma_chan
->device
->dev
, dest
, 0, PAGE_SIZE
,
965 dest_dma
= unmap
->addr
[src_count
];
966 ret
= dma_mapping_error(dma_chan
->device
->dev
, unmap
->addr
[src_count
]);
972 unmap
->len
= PAGE_SIZE
;
974 tx
= mv_xor_prep_dma_xor(dma_chan
, dest_dma
, dma_srcs
,
975 src_count
, PAGE_SIZE
, 0);
977 dev_err(dma_chan
->device
->dev
,
978 "Self-test cannot prepare operation, disabling\n");
983 cookie
= mv_xor_tx_submit(tx
);
984 if (dma_submit_error(cookie
)) {
985 dev_err(dma_chan
->device
->dev
,
986 "Self-test submit error, disabling\n");
991 mv_xor_issue_pending(dma_chan
);
995 if (mv_xor_status(dma_chan
, cookie
, NULL
) !=
997 dev_err(dma_chan
->device
->dev
,
998 "Self-test xor timed out, disabling\n");
1000 goto free_resources
;
1003 dma_sync_single_for_cpu(dma_chan
->device
->dev
, dest_dma
,
1004 PAGE_SIZE
, DMA_FROM_DEVICE
);
1005 for (i
= 0; i
< (PAGE_SIZE
/ sizeof(u32
)); i
++) {
1006 u32
*ptr
= page_address(dest
);
1007 if (ptr
[i
] != cmp_word
) {
1008 dev_err(dma_chan
->device
->dev
,
1009 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
1010 i
, ptr
[i
], cmp_word
);
1012 goto free_resources
;
1017 dmaengine_unmap_put(unmap
);
1018 mv_xor_free_chan_resources(dma_chan
);
1020 src_idx
= src_count
;
1022 __free_page(xor_srcs
[src_idx
]);
1027 /* This driver does not implement any of the optional DMA operations. */
1029 mv_xor_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1035 static int mv_xor_channel_remove(struct mv_xor_chan
*mv_chan
)
1037 struct dma_chan
*chan
, *_chan
;
1038 struct device
*dev
= mv_chan
->dmadev
.dev
;
1040 dma_async_device_unregister(&mv_chan
->dmadev
);
1042 dma_free_coherent(dev
, MV_XOR_POOL_SIZE
,
1043 mv_chan
->dma_desc_pool_virt
, mv_chan
->dma_desc_pool
);
1045 list_for_each_entry_safe(chan
, _chan
, &mv_chan
->dmadev
.channels
,
1047 list_del(&chan
->device_node
);
1050 free_irq(mv_chan
->irq
, mv_chan
);
1055 static struct mv_xor_chan
*
1056 mv_xor_channel_add(struct mv_xor_device
*xordev
,
1057 struct platform_device
*pdev
,
1058 int idx
, dma_cap_mask_t cap_mask
, int irq
)
1061 struct mv_xor_chan
*mv_chan
;
1062 struct dma_device
*dma_dev
;
1064 mv_chan
= devm_kzalloc(&pdev
->dev
, sizeof(*mv_chan
), GFP_KERNEL
);
1066 return ERR_PTR(-ENOMEM
);
1071 dma_dev
= &mv_chan
->dmadev
;
1073 /* allocate coherent memory for hardware descriptors
1074 * note: writecombine gives slightly better performance, but
1075 * requires that we explicitly flush the writes
1077 mv_chan
->dma_desc_pool_virt
=
1078 dma_alloc_writecombine(&pdev
->dev
, MV_XOR_POOL_SIZE
,
1079 &mv_chan
->dma_desc_pool
, GFP_KERNEL
);
1080 if (!mv_chan
->dma_desc_pool_virt
)
1081 return ERR_PTR(-ENOMEM
);
1083 /* discover transaction capabilites from the platform data */
1084 dma_dev
->cap_mask
= cap_mask
;
1086 INIT_LIST_HEAD(&dma_dev
->channels
);
1088 /* set base routines */
1089 dma_dev
->device_alloc_chan_resources
= mv_xor_alloc_chan_resources
;
1090 dma_dev
->device_free_chan_resources
= mv_xor_free_chan_resources
;
1091 dma_dev
->device_tx_status
= mv_xor_status
;
1092 dma_dev
->device_issue_pending
= mv_xor_issue_pending
;
1093 dma_dev
->device_control
= mv_xor_control
;
1094 dma_dev
->dev
= &pdev
->dev
;
1096 /* set prep routines based on capability */
1097 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
))
1098 dma_dev
->device_prep_dma_memcpy
= mv_xor_prep_dma_memcpy
;
1099 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1100 dma_dev
->max_xor
= 8;
1101 dma_dev
->device_prep_dma_xor
= mv_xor_prep_dma_xor
;
1104 mv_chan
->mmr_base
= xordev
->xor_base
;
1105 mv_chan
->mmr_high_base
= xordev
->xor_high_base
;
1106 tasklet_init(&mv_chan
->irq_tasklet
, mv_xor_tasklet
, (unsigned long)
1109 /* clear errors before enabling interrupts */
1110 mv_xor_device_clear_err_status(mv_chan
);
1112 ret
= request_irq(mv_chan
->irq
, mv_xor_interrupt_handler
,
1113 0, dev_name(&pdev
->dev
), mv_chan
);
1117 mv_chan_unmask_interrupts(mv_chan
);
1119 mv_set_mode(mv_chan
, DMA_MEMCPY
);
1121 spin_lock_init(&mv_chan
->lock
);
1122 INIT_LIST_HEAD(&mv_chan
->chain
);
1123 INIT_LIST_HEAD(&mv_chan
->completed_slots
);
1124 INIT_LIST_HEAD(&mv_chan
->all_slots
);
1125 mv_chan
->dmachan
.device
= dma_dev
;
1126 dma_cookie_init(&mv_chan
->dmachan
);
1128 list_add_tail(&mv_chan
->dmachan
.device_node
, &dma_dev
->channels
);
1130 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
)) {
1131 ret
= mv_xor_memcpy_self_test(mv_chan
);
1132 dev_dbg(&pdev
->dev
, "memcpy self test returned %d\n", ret
);
1137 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1138 ret
= mv_xor_xor_self_test(mv_chan
);
1139 dev_dbg(&pdev
->dev
, "xor self test returned %d\n", ret
);
1144 dev_info(&pdev
->dev
, "Marvell XOR: ( %s%s%s)\n",
1145 dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
) ? "xor " : "",
1146 dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
) ? "cpy " : "",
1147 dma_has_cap(DMA_INTERRUPT
, dma_dev
->cap_mask
) ? "intr " : "");
1149 dma_async_device_register(dma_dev
);
1153 free_irq(mv_chan
->irq
, mv_chan
);
1155 dma_free_coherent(&pdev
->dev
, MV_XOR_POOL_SIZE
,
1156 mv_chan
->dma_desc_pool_virt
, mv_chan
->dma_desc_pool
);
1157 return ERR_PTR(ret
);
1161 mv_xor_conf_mbus_windows(struct mv_xor_device
*xordev
,
1162 const struct mbus_dram_target_info
*dram
)
1164 void __iomem
*base
= xordev
->xor_high_base
;
1168 for (i
= 0; i
< 8; i
++) {
1169 writel(0, base
+ WINDOW_BASE(i
));
1170 writel(0, base
+ WINDOW_SIZE(i
));
1172 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
1175 for (i
= 0; i
< dram
->num_cs
; i
++) {
1176 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
1178 writel((cs
->base
& 0xffff0000) |
1179 (cs
->mbus_attr
<< 8) |
1180 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
1181 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
1183 win_enable
|= (1 << i
);
1184 win_enable
|= 3 << (16 + (2 * i
));
1187 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(0));
1188 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(1));
1189 writel(0, base
+ WINDOW_OVERRIDE_CTRL(0));
1190 writel(0, base
+ WINDOW_OVERRIDE_CTRL(1));
1193 static int mv_xor_probe(struct platform_device
*pdev
)
1195 const struct mbus_dram_target_info
*dram
;
1196 struct mv_xor_device
*xordev
;
1197 struct mv_xor_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
1198 struct resource
*res
;
1201 dev_notice(&pdev
->dev
, "Marvell shared XOR driver\n");
1203 xordev
= devm_kzalloc(&pdev
->dev
, sizeof(*xordev
), GFP_KERNEL
);
1207 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1211 xordev
->xor_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1212 resource_size(res
));
1213 if (!xordev
->xor_base
)
1216 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1220 xordev
->xor_high_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1221 resource_size(res
));
1222 if (!xordev
->xor_high_base
)
1225 platform_set_drvdata(pdev
, xordev
);
1228 * (Re-)program MBUS remapping windows if we are asked to.
1230 dram
= mv_mbus_dram_info();
1232 mv_xor_conf_mbus_windows(xordev
, dram
);
1234 /* Not all platforms can gate the clock, so it is not
1235 * an error if the clock does not exists.
1237 xordev
->clk
= clk_get(&pdev
->dev
, NULL
);
1238 if (!IS_ERR(xordev
->clk
))
1239 clk_prepare_enable(xordev
->clk
);
1241 if (pdev
->dev
.of_node
) {
1242 struct device_node
*np
;
1245 for_each_child_of_node(pdev
->dev
.of_node
, np
) {
1246 struct mv_xor_chan
*chan
;
1247 dma_cap_mask_t cap_mask
;
1250 dma_cap_zero(cap_mask
);
1251 if (of_property_read_bool(np
, "dmacap,memcpy"))
1252 dma_cap_set(DMA_MEMCPY
, cap_mask
);
1253 if (of_property_read_bool(np
, "dmacap,xor"))
1254 dma_cap_set(DMA_XOR
, cap_mask
);
1255 if (of_property_read_bool(np
, "dmacap,interrupt"))
1256 dma_cap_set(DMA_INTERRUPT
, cap_mask
);
1258 irq
= irq_of_parse_and_map(np
, 0);
1261 goto err_channel_add
;
1264 chan
= mv_xor_channel_add(xordev
, pdev
, i
,
1267 ret
= PTR_ERR(chan
);
1268 irq_dispose_mapping(irq
);
1269 goto err_channel_add
;
1272 xordev
->channels
[i
] = chan
;
1275 } else if (pdata
&& pdata
->channels
) {
1276 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++) {
1277 struct mv_xor_channel_data
*cd
;
1278 struct mv_xor_chan
*chan
;
1281 cd
= &pdata
->channels
[i
];
1284 goto err_channel_add
;
1287 irq
= platform_get_irq(pdev
, i
);
1290 goto err_channel_add
;
1293 chan
= mv_xor_channel_add(xordev
, pdev
, i
,
1296 ret
= PTR_ERR(chan
);
1297 goto err_channel_add
;
1300 xordev
->channels
[i
] = chan
;
1307 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++)
1308 if (xordev
->channels
[i
]) {
1309 mv_xor_channel_remove(xordev
->channels
[i
]);
1310 if (pdev
->dev
.of_node
)
1311 irq_dispose_mapping(xordev
->channels
[i
]->irq
);
1314 if (!IS_ERR(xordev
->clk
)) {
1315 clk_disable_unprepare(xordev
->clk
);
1316 clk_put(xordev
->clk
);
1322 static int mv_xor_remove(struct platform_device
*pdev
)
1324 struct mv_xor_device
*xordev
= platform_get_drvdata(pdev
);
1327 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++) {
1328 if (xordev
->channels
[i
])
1329 mv_xor_channel_remove(xordev
->channels
[i
]);
1332 if (!IS_ERR(xordev
->clk
)) {
1333 clk_disable_unprepare(xordev
->clk
);
1334 clk_put(xordev
->clk
);
1341 static struct of_device_id mv_xor_dt_ids
[] = {
1342 { .compatible
= "marvell,orion-xor", },
1345 MODULE_DEVICE_TABLE(of
, mv_xor_dt_ids
);
1348 static struct platform_driver mv_xor_driver
= {
1349 .probe
= mv_xor_probe
,
1350 .remove
= mv_xor_remove
,
1352 .owner
= THIS_MODULE
,
1353 .name
= MV_XOR_NAME
,
1354 .of_match_table
= of_match_ptr(mv_xor_dt_ids
),
1359 static int __init
mv_xor_init(void)
1361 return platform_driver_register(&mv_xor_driver
);
1363 module_init(mv_xor_init
);
1365 /* it's currently unsafe to unload this module */
1367 static void __exit
mv_xor_exit(void)
1369 platform_driver_unregister(&mv_xor_driver
);
1373 module_exit(mv_xor_exit
);
1376 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1377 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1378 MODULE_LICENSE("GPL");