2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <linux/pm_runtime.h>
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
36 #define PL330_MAX_BURST 16
38 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
40 enum pl330_cachectrl
{
41 CCTRL0
, /* Noncacheable and nonbufferable */
42 CCTRL1
, /* Bufferable only */
43 CCTRL2
, /* Cacheable, but do not allocate */
44 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
45 INVALID1
, /* AWCACHE = 0x1000 */
47 CCTRL6
, /* Cacheable write-through, allocate on writes only */
48 CCTRL7
, /* Cacheable write-back, allocate on writes only */
59 /* Register and Bit field Definitions */
61 #define DS_ST_STOP 0x0
62 #define DS_ST_EXEC 0x1
63 #define DS_ST_CMISS 0x2
64 #define DS_ST_UPDTPC 0x3
66 #define DS_ST_ATBRR 0x5
67 #define DS_ST_QBUSY 0x6
69 #define DS_ST_KILL 0x8
70 #define DS_ST_CMPLT 0x9
71 #define DS_ST_FLTCMP 0xe
72 #define DS_ST_FAULT 0xf
77 #define INTSTATUS 0x28
84 #define FTC(n) (_FTC + (n)*0x4)
87 #define CS(n) (_CS + (n)*0x8)
88 #define CS_CNS (1 << 21)
91 #define CPC(n) (_CPC + (n)*0x8)
94 #define SA(n) (_SA + (n)*0x20)
97 #define DA(n) (_DA + (n)*0x20)
100 #define CC(n) (_CC + (n)*0x20)
102 #define CC_SRCINC (1 << 0)
103 #define CC_DSTINC (1 << 14)
104 #define CC_SRCPRI (1 << 8)
105 #define CC_DSTPRI (1 << 22)
106 #define CC_SRCNS (1 << 9)
107 #define CC_DSTNS (1 << 23)
108 #define CC_SRCIA (1 << 10)
109 #define CC_DSTIA (1 << 24)
110 #define CC_SRCBRSTLEN_SHFT 4
111 #define CC_DSTBRSTLEN_SHFT 18
112 #define CC_SRCBRSTSIZE_SHFT 1
113 #define CC_DSTBRSTSIZE_SHFT 15
114 #define CC_SRCCCTRL_SHFT 11
115 #define CC_SRCCCTRL_MASK 0x7
116 #define CC_DSTCCTRL_SHFT 25
117 #define CC_DRCCCTRL_MASK 0x7
118 #define CC_SWAP_SHFT 28
121 #define LC0(n) (_LC0 + (n)*0x20)
124 #define LC1(n) (_LC1 + (n)*0x20)
126 #define DBGSTATUS 0xd00
127 #define DBG_BUSY (1 << 0)
130 #define DBGINST0 0xd08
131 #define DBGINST1 0xd0c
140 #define PERIPH_ID 0xfe0
141 #define PERIPH_REV_SHIFT 20
142 #define PERIPH_REV_MASK 0xf
143 #define PERIPH_REV_R0P0 0
144 #define PERIPH_REV_R1P0 1
145 #define PERIPH_REV_R1P1 2
147 #define CR0_PERIPH_REQ_SET (1 << 0)
148 #define CR0_BOOT_EN_SET (1 << 1)
149 #define CR0_BOOT_MAN_NS (1 << 2)
150 #define CR0_NUM_CHANS_SHIFT 4
151 #define CR0_NUM_CHANS_MASK 0x7
152 #define CR0_NUM_PERIPH_SHIFT 12
153 #define CR0_NUM_PERIPH_MASK 0x1f
154 #define CR0_NUM_EVENTS_SHIFT 17
155 #define CR0_NUM_EVENTS_MASK 0x1f
157 #define CR1_ICACHE_LEN_SHIFT 0
158 #define CR1_ICACHE_LEN_MASK 0x7
159 #define CR1_NUM_ICACHELINES_SHIFT 4
160 #define CR1_NUM_ICACHELINES_MASK 0xf
162 #define CRD_DATA_WIDTH_SHIFT 0
163 #define CRD_DATA_WIDTH_MASK 0x7
164 #define CRD_WR_CAP_SHIFT 4
165 #define CRD_WR_CAP_MASK 0x7
166 #define CRD_WR_Q_DEP_SHIFT 8
167 #define CRD_WR_Q_DEP_MASK 0xf
168 #define CRD_RD_CAP_SHIFT 12
169 #define CRD_RD_CAP_MASK 0x7
170 #define CRD_RD_Q_DEP_SHIFT 16
171 #define CRD_RD_Q_DEP_MASK 0xf
172 #define CRD_DATA_BUFF_SHIFT 20
173 #define CRD_DATA_BUFF_MASK 0x3ff
176 #define DESIGNER 0x41
178 #define INTEG_CFG 0x0
179 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
181 #define PL330_STATE_STOPPED (1 << 0)
182 #define PL330_STATE_EXECUTING (1 << 1)
183 #define PL330_STATE_WFE (1 << 2)
184 #define PL330_STATE_FAULTING (1 << 3)
185 #define PL330_STATE_COMPLETING (1 << 4)
186 #define PL330_STATE_WFP (1 << 5)
187 #define PL330_STATE_KILLING (1 << 6)
188 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
189 #define PL330_STATE_CACHEMISS (1 << 8)
190 #define PL330_STATE_UPDTPC (1 << 9)
191 #define PL330_STATE_ATBARRIER (1 << 10)
192 #define PL330_STATE_QUEUEBUSY (1 << 11)
193 #define PL330_STATE_INVALID (1 << 15)
195 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
198 #define CMD_DMAADDH 0x54
199 #define CMD_DMAEND 0x00
200 #define CMD_DMAFLUSHP 0x35
201 #define CMD_DMAGO 0xa0
202 #define CMD_DMALD 0x04
203 #define CMD_DMALDP 0x25
204 #define CMD_DMALP 0x20
205 #define CMD_DMALPEND 0x28
206 #define CMD_DMAKILL 0x01
207 #define CMD_DMAMOV 0xbc
208 #define CMD_DMANOP 0x18
209 #define CMD_DMARMB 0x12
210 #define CMD_DMASEV 0x34
211 #define CMD_DMAST 0x08
212 #define CMD_DMASTP 0x29
213 #define CMD_DMASTZ 0x0c
214 #define CMD_DMAWFE 0x36
215 #define CMD_DMAWFP 0x30
216 #define CMD_DMAWMB 0x13
220 #define SZ_DMAFLUSHP 2
224 #define SZ_DMALPEND 2
238 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
241 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
250 #define MCODE_BUFF_PER_REQ 256
252 /* Use this _only_ to wait on transient states */
253 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
255 #ifdef PL330_DEBUG_MCGEN
256 static unsigned cmd_line
;
257 #define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
262 #define PL330_DBGMC_START(addr) (cmd_line = addr)
264 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265 #define PL330_DBGMC_START(addr) do {} while (0)
268 /* The number of default descriptors */
270 #define NR_DEFAULT_DESC 16
272 /* Delay for runtime PM autosuspend, ms */
273 #define PL330_AUTOSUSPEND_DELAY 20
275 /* Populated by the PL330 core driver for DMA API driver's info */
276 struct pl330_config
{
278 #define DMAC_MODE_NS (1 << 0)
280 unsigned int data_bus_width
:10; /* In number of bits */
281 unsigned int data_buf_dep
:11;
282 unsigned int num_chan
:4;
283 unsigned int num_peri
:6;
285 unsigned int num_events
:6;
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
297 struct pl330_reqcfg
{
298 /* Address Incrementing */
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
310 unsigned brst_size
:3; /* in power of 2 */
312 enum pl330_cachectrl dcctl
;
313 enum pl330_cachectrl scctl
;
314 enum pl330_byteswap swap
;
315 struct pl330_config
*pcfg
;
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
329 /* The xfer callbacks are made with one of these arguments. */
331 /* The all xfers in the request were success. */
333 /* If req aborted due to global error. */
335 /* If req failed due to problem with Channel. */
356 struct dma_pl330_desc
;
361 struct dma_pl330_desc
*desc
;
364 /* ToBeDone for tasklet */
372 struct pl330_thread
{
375 /* If the channel is not yet acquired by any client */
378 struct pl330_dmac
*dmac
;
379 /* Only two at a time */
380 struct _pl330_req req
[2];
381 /* Index of the last enqueued request */
383 /* Index of the last submitted request or -1 if the DMA is stopped */
387 enum pl330_dmac_state
{
394 /* In the DMAC pool */
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
408 * Sitting on the channel work_list but xfer done
414 struct dma_pl330_chan
{
415 /* Schedule desc completion */
416 struct tasklet_struct task
;
418 /* DMA-Engine Channel */
419 struct dma_chan chan
;
421 /* List of submitted descriptors */
422 struct list_head submitted_list
;
423 /* List of issued descriptors */
424 struct list_head work_list
;
425 /* List of completed descriptors */
426 struct list_head completed_list
;
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
433 struct pl330_dmac
*dmac
;
435 /* To protect channel manipulation */
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
442 struct pl330_thread
*thread
;
444 /* For D-to-M and M-to-D channels */
445 int burst_sz
; /* the peripheral fifo width */
446 int burst_len
; /* the number of burst */
447 dma_addr_t fifo_addr
;
449 /* for cyclic capability */
452 /* for runtime pm tracking */
457 /* DMA-Engine Device */
458 struct dma_device ddma
;
460 /* Holds info about sg limitations */
461 struct device_dma_parameters dma_parms
;
463 /* Pool of descriptors available for the DMAC's channels */
464 struct list_head desc_pool
;
465 /* To protect desc_pool manipulation */
466 spinlock_t pool_lock
;
468 /* Size of MicroCode buffers for each channel. */
470 /* ioremap'ed address of PL330 registers. */
472 /* Populated by the PL330 core driver during pl330_add */
473 struct pl330_config pcfg
;
476 /* Maximum possible events/irqs */
478 /* BUS address of MicroCode buffer */
479 dma_addr_t mcode_bus
;
480 /* CPU address of MicroCode buffer */
482 /* List of all Channel threads */
483 struct pl330_thread
*channels
;
484 /* Pointer to the MANAGER thread */
485 struct pl330_thread
*manager
;
486 /* To handle bad news in interrupt */
487 struct tasklet_struct tasks
;
488 struct _pl330_tbd dmac_tbd
;
489 /* State of DMAC operation */
490 enum pl330_dmac_state state
;
491 /* Holds list of reqs with due callbacks */
492 struct list_head req_done
;
494 /* Peripheral channels connected to this DMAC */
495 unsigned int num_peripherals
;
496 struct dma_pl330_chan
*peripherals
; /* keep at end */
500 static struct pl330_of_quirks
{
505 .quirk
= "arm,pl330-broken-no-flushp",
506 .id
= PL330_QUIRK_BROKEN_NO_FLUSHP
,
510 struct dma_pl330_desc
{
511 /* To attach to a queue as child */
512 struct list_head node
;
514 /* Descriptor for the DMA Engine API */
515 struct dma_async_tx_descriptor txd
;
517 /* Xfer for PL330 core */
518 struct pl330_xfer px
;
520 struct pl330_reqcfg rqcfg
;
522 enum desc_status status
;
527 /* The channel which currently holds this desc */
528 struct dma_pl330_chan
*pchan
;
530 enum dma_transfer_direction rqtype
;
531 /* Index of peripheral for the xfer. */
533 /* Hook to attach to DMAC's list of reqs with due callback */
534 struct list_head rqd
;
539 struct dma_pl330_desc
*desc
;
542 static inline bool _queue_empty(struct pl330_thread
*thrd
)
544 return thrd
->req
[0].desc
== NULL
&& thrd
->req
[1].desc
== NULL
;
547 static inline bool _queue_full(struct pl330_thread
*thrd
)
549 return thrd
->req
[0].desc
!= NULL
&& thrd
->req
[1].desc
!= NULL
;
552 static inline bool is_manager(struct pl330_thread
*thrd
)
554 return thrd
->dmac
->manager
== thrd
;
557 /* If manager of the thread is in Non-Secure mode */
558 static inline bool _manager_ns(struct pl330_thread
*thrd
)
560 return (thrd
->dmac
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
563 static inline u32
get_revision(u32 periph_id
)
565 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
568 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
569 enum pl330_dst da
, u16 val
)
574 buf
[0] = CMD_DMAADDH
;
579 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
580 da
== 1 ? "DA" : "SA", val
);
585 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
592 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
597 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
602 buf
[0] = CMD_DMAFLUSHP
;
608 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
613 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
621 buf
[0] |= (0 << 1) | (1 << 0);
622 else if (cond
== BURST
)
623 buf
[0] |= (1 << 1) | (1 << 0);
625 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
626 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
631 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
632 enum pl330_cond cond
, u8 peri
)
646 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
647 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
652 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
653 unsigned loop
, u8 cnt
)
663 cnt
--; /* DMAC increments by 1 internally */
666 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
672 enum pl330_cond cond
;
678 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
679 const struct _arg_LPEND
*arg
)
681 enum pl330_cond cond
= arg
->cond
;
682 bool forever
= arg
->forever
;
683 unsigned loop
= arg
->loop
;
684 u8 bjump
= arg
->bjump
;
689 buf
[0] = CMD_DMALPEND
;
698 buf
[0] |= (0 << 1) | (1 << 0);
699 else if (cond
== BURST
)
700 buf
[0] |= (1 << 1) | (1 << 0);
704 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
705 forever
? "FE" : "END",
706 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
713 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
718 buf
[0] = CMD_DMAKILL
;
723 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
724 enum dmamov_dst dst
, u32 val
)
736 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
737 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
742 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
749 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
754 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
761 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
766 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
777 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
782 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
790 buf
[0] |= (0 << 1) | (1 << 0);
791 else if (cond
== BURST
)
792 buf
[0] |= (1 << 1) | (1 << 0);
794 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
795 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
800 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
801 enum pl330_cond cond
, u8 peri
)
815 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
816 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
821 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
828 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
833 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
848 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
849 ev
>> 3, invalidate
? ", I" : "");
854 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
855 enum pl330_cond cond
, u8 peri
)
863 buf
[0] |= (0 << 1) | (0 << 0);
864 else if (cond
== BURST
)
865 buf
[0] |= (1 << 1) | (0 << 0);
867 buf
[0] |= (0 << 1) | (1 << 0);
873 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
874 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
879 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
886 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
897 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
898 const struct _arg_GO
*arg
)
901 u32 addr
= arg
->addr
;
902 unsigned ns
= arg
->ns
;
918 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
920 /* Returns Time-Out */
921 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
923 void __iomem
*regs
= thrd
->dmac
->base
;
924 unsigned long loops
= msecs_to_loops(5);
927 /* Until Manager is Idle */
928 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
940 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
941 u8 insn
[], bool as_manager
)
943 void __iomem
*regs
= thrd
->dmac
->base
;
946 val
= (insn
[0] << 16) | (insn
[1] << 24);
949 val
|= (thrd
->id
<< 8); /* Channel Number */
951 writel(val
, regs
+ DBGINST0
);
953 val
= le32_to_cpu(*((__le32
*)&insn
[2]));
954 writel(val
, regs
+ DBGINST1
);
956 /* If timed out due to halted state-machine */
957 if (_until_dmac_idle(thrd
)) {
958 dev_err(thrd
->dmac
->ddma
.dev
, "DMAC halted!\n");
963 writel(0, regs
+ DBGCMD
);
966 static inline u32
_state(struct pl330_thread
*thrd
)
968 void __iomem
*regs
= thrd
->dmac
->base
;
971 if (is_manager(thrd
))
972 val
= readl(regs
+ DS
) & 0xf;
974 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
978 return PL330_STATE_STOPPED
;
980 return PL330_STATE_EXECUTING
;
982 return PL330_STATE_CACHEMISS
;
984 return PL330_STATE_UPDTPC
;
986 return PL330_STATE_WFE
;
988 return PL330_STATE_FAULTING
;
990 if (is_manager(thrd
))
991 return PL330_STATE_INVALID
;
993 return PL330_STATE_ATBARRIER
;
995 if (is_manager(thrd
))
996 return PL330_STATE_INVALID
;
998 return PL330_STATE_QUEUEBUSY
;
1000 if (is_manager(thrd
))
1001 return PL330_STATE_INVALID
;
1003 return PL330_STATE_WFP
;
1005 if (is_manager(thrd
))
1006 return PL330_STATE_INVALID
;
1008 return PL330_STATE_KILLING
;
1010 if (is_manager(thrd
))
1011 return PL330_STATE_INVALID
;
1013 return PL330_STATE_COMPLETING
;
1015 if (is_manager(thrd
))
1016 return PL330_STATE_INVALID
;
1018 return PL330_STATE_FAULT_COMPLETING
;
1020 return PL330_STATE_INVALID
;
1024 static void _stop(struct pl330_thread
*thrd
)
1026 void __iomem
*regs
= thrd
->dmac
->base
;
1027 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1029 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1030 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1032 /* Return if nothing needs to be done */
1033 if (_state(thrd
) == PL330_STATE_COMPLETING
1034 || _state(thrd
) == PL330_STATE_KILLING
1035 || _state(thrd
) == PL330_STATE_STOPPED
)
1038 _emit_KILL(0, insn
);
1040 /* Stop generating interrupts for SEV */
1041 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1043 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1046 /* Start doing req 'idx' of thread 'thrd' */
1047 static bool _trigger(struct pl330_thread
*thrd
)
1049 void __iomem
*regs
= thrd
->dmac
->base
;
1050 struct _pl330_req
*req
;
1051 struct dma_pl330_desc
*desc
;
1054 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1057 /* Return if already ACTIVE */
1058 if (_state(thrd
) != PL330_STATE_STOPPED
)
1061 idx
= 1 - thrd
->lstenq
;
1062 if (thrd
->req
[idx
].desc
!= NULL
) {
1063 req
= &thrd
->req
[idx
];
1066 if (thrd
->req
[idx
].desc
!= NULL
)
1067 req
= &thrd
->req
[idx
];
1072 /* Return if no request */
1076 /* Return if req is running */
1077 if (idx
== thrd
->req_running
)
1082 ns
= desc
->rqcfg
.nonsecure
? 1 : 0;
1084 /* See 'Abort Sources' point-4 at Page 2-25 */
1085 if (_manager_ns(thrd
) && !ns
)
1086 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d Recipe for ABORT!\n",
1087 __func__
, __LINE__
);
1090 go
.addr
= req
->mc_bus
;
1092 _emit_GO(0, insn
, &go
);
1094 /* Set to generate interrupts for SEV */
1095 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1097 /* Only manager can execute GO */
1098 _execute_DBGINSN(thrd
, insn
, true);
1100 thrd
->req_running
= idx
;
1105 static bool _start(struct pl330_thread
*thrd
)
1107 switch (_state(thrd
)) {
1108 case PL330_STATE_FAULT_COMPLETING
:
1109 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1111 if (_state(thrd
) == PL330_STATE_KILLING
)
1112 UNTIL(thrd
, PL330_STATE_STOPPED
)
1114 case PL330_STATE_FAULTING
:
1117 case PL330_STATE_KILLING
:
1118 case PL330_STATE_COMPLETING
:
1119 UNTIL(thrd
, PL330_STATE_STOPPED
)
1121 case PL330_STATE_STOPPED
:
1122 return _trigger(thrd
);
1124 case PL330_STATE_WFP
:
1125 case PL330_STATE_QUEUEBUSY
:
1126 case PL330_STATE_ATBARRIER
:
1127 case PL330_STATE_UPDTPC
:
1128 case PL330_STATE_CACHEMISS
:
1129 case PL330_STATE_EXECUTING
:
1132 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1138 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1139 const struct _xfer_spec
*pxs
, int cyc
)
1142 struct pl330_config
*pcfg
= pxs
->desc
->rqcfg
.pcfg
;
1144 /* check lock-up free version */
1145 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1147 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1148 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1152 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1153 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1154 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1155 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1162 static inline int _ldst_devtomem(struct pl330_dmac
*pl330
, unsigned dry_run
,
1163 u8 buf
[], const struct _xfer_spec
*pxs
,
1167 enum pl330_cond cond
;
1169 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1175 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1176 off
+= _emit_LDP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1177 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1179 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1180 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1187 static inline int _ldst_memtodev(struct pl330_dmac
*pl330
,
1188 unsigned dry_run
, u8 buf
[],
1189 const struct _xfer_spec
*pxs
, int cyc
)
1192 enum pl330_cond cond
;
1194 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1200 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1201 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1202 off
+= _emit_STP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1204 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1205 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1212 static int _bursts(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1213 const struct _xfer_spec
*pxs
, int cyc
)
1217 switch (pxs
->desc
->rqtype
) {
1218 case DMA_MEM_TO_DEV
:
1219 off
+= _ldst_memtodev(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1221 case DMA_DEV_TO_MEM
:
1222 off
+= _ldst_devtomem(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1224 case DMA_MEM_TO_MEM
:
1225 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1228 off
+= 0x40000000; /* Scare off the Client */
1235 /* Returns bytes consumed and updates bursts */
1236 static inline int _loop(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1237 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1239 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1240 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1241 struct _arg_LPEND lpend
;
1244 return _bursts(pl330
, dry_run
, buf
, pxs
, 1);
1246 /* Max iterations possible in DMALP is 256 */
1247 if (*bursts
>= 256*256) {
1250 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1251 } else if (*bursts
> 256) {
1253 lcnt0
= *bursts
/ lcnt1
;
1261 szlp
= _emit_LP(1, buf
, 0, 0);
1262 szbrst
= _bursts(pl330
, 1, buf
, pxs
, 1);
1264 lpend
.cond
= ALWAYS
;
1265 lpend
.forever
= false;
1268 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1276 * Max bursts that we can unroll due to limit on the
1277 * size of backward jump that can be encoded in DMALPEND
1278 * which is 8-bits and hence 255
1280 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1282 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1287 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1291 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1294 off
+= _bursts(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1296 lpend
.cond
= ALWAYS
;
1297 lpend
.forever
= false;
1299 lpend
.bjump
= off
- ljmp1
;
1300 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1303 lpend
.cond
= ALWAYS
;
1304 lpend
.forever
= false;
1306 lpend
.bjump
= off
- ljmp0
;
1307 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1310 *bursts
= lcnt1
* cyc
;
1317 static inline int _setup_loops(struct pl330_dmac
*pl330
,
1318 unsigned dry_run
, u8 buf
[],
1319 const struct _xfer_spec
*pxs
)
1321 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1323 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1328 off
+= _loop(pl330
, dry_run
, &buf
[off
], &c
, pxs
);
1335 static inline int _setup_xfer(struct pl330_dmac
*pl330
,
1336 unsigned dry_run
, u8 buf
[],
1337 const struct _xfer_spec
*pxs
)
1339 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1342 /* DMAMOV SAR, x->src_addr */
1343 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1344 /* DMAMOV DAR, x->dst_addr */
1345 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1348 off
+= _setup_loops(pl330
, dry_run
, &buf
[off
], pxs
);
1354 * A req is a sequence of one or more xfer units.
1355 * Returns the number of bytes taken to setup the MC for the req.
1357 static int _setup_req(struct pl330_dmac
*pl330
, unsigned dry_run
,
1358 struct pl330_thread
*thrd
, unsigned index
,
1359 struct _xfer_spec
*pxs
)
1361 struct _pl330_req
*req
= &thrd
->req
[index
];
1362 struct pl330_xfer
*x
;
1363 u8
*buf
= req
->mc_cpu
;
1366 PL330_DBGMC_START(req
->mc_bus
);
1368 /* DMAMOV CCR, ccr */
1369 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1372 /* Error if xfer length is not aligned at burst size */
1373 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1376 off
+= _setup_xfer(pl330
, dry_run
, &buf
[off
], pxs
);
1378 /* DMASEV peripheral/event */
1379 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1381 off
+= _emit_END(dry_run
, &buf
[off
]);
1386 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1396 /* We set same protection levels for Src and DST for now */
1397 if (rqc
->privileged
)
1398 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1400 ccr
|= CC_SRCNS
| CC_DSTNS
;
1401 if (rqc
->insnaccess
)
1402 ccr
|= CC_SRCIA
| CC_DSTIA
;
1404 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1405 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1407 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1408 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1410 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1411 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1413 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1419 * Submit a list of xfers after which the client wants notification.
1420 * Client is not notified after each xfer unit, just once after all
1421 * xfer units are done or some error occurs.
1423 static int pl330_submit_req(struct pl330_thread
*thrd
,
1424 struct dma_pl330_desc
*desc
)
1426 struct pl330_dmac
*pl330
= thrd
->dmac
;
1427 struct _xfer_spec xs
;
1428 unsigned long flags
;
1433 if (pl330
->state
== DYING
1434 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1435 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d\n",
1436 __func__
, __LINE__
);
1440 /* If request for non-existing peripheral */
1441 if (desc
->rqtype
!= DMA_MEM_TO_MEM
&&
1442 desc
->peri
>= pl330
->pcfg
.num_peri
) {
1443 dev_info(thrd
->dmac
->ddma
.dev
,
1444 "%s:%d Invalid peripheral(%u)!\n",
1445 __func__
, __LINE__
, desc
->peri
);
1449 spin_lock_irqsave(&pl330
->lock
, flags
);
1451 if (_queue_full(thrd
)) {
1456 /* Prefer Secure Channel */
1457 if (!_manager_ns(thrd
))
1458 desc
->rqcfg
.nonsecure
= 0;
1460 desc
->rqcfg
.nonsecure
= 1;
1462 ccr
= _prepare_ccr(&desc
->rqcfg
);
1464 idx
= thrd
->req
[0].desc
== NULL
? 0 : 1;
1469 /* First dry run to check if req is acceptable */
1470 ret
= _setup_req(pl330
, 1, thrd
, idx
, &xs
);
1474 if (ret
> pl330
->mcbufsz
/ 2) {
1475 dev_info(pl330
->ddma
.dev
, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1476 __func__
, __LINE__
, ret
, pl330
->mcbufsz
/ 2);
1481 /* Hook the request */
1483 thrd
->req
[idx
].desc
= desc
;
1484 _setup_req(pl330
, 0, thrd
, idx
, &xs
);
1489 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1494 static void dma_pl330_rqcb(struct dma_pl330_desc
*desc
, enum pl330_op_err err
)
1496 struct dma_pl330_chan
*pch
;
1497 unsigned long flags
;
1504 /* If desc aborted */
1508 spin_lock_irqsave(&pch
->lock
, flags
);
1510 desc
->status
= DONE
;
1512 spin_unlock_irqrestore(&pch
->lock
, flags
);
1514 tasklet_schedule(&pch
->task
);
1517 static void pl330_dotask(unsigned long data
)
1519 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1520 unsigned long flags
;
1523 spin_lock_irqsave(&pl330
->lock
, flags
);
1525 /* The DMAC itself gone nuts */
1526 if (pl330
->dmac_tbd
.reset_dmac
) {
1527 pl330
->state
= DYING
;
1528 /* Reset the manager too */
1529 pl330
->dmac_tbd
.reset_mngr
= true;
1530 /* Clear the reset flag */
1531 pl330
->dmac_tbd
.reset_dmac
= false;
1534 if (pl330
->dmac_tbd
.reset_mngr
) {
1535 _stop(pl330
->manager
);
1536 /* Reset all channels */
1537 pl330
->dmac_tbd
.reset_chan
= (1 << pl330
->pcfg
.num_chan
) - 1;
1538 /* Clear the reset flag */
1539 pl330
->dmac_tbd
.reset_mngr
= false;
1542 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1544 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1545 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1546 void __iomem
*regs
= pl330
->base
;
1547 enum pl330_op_err err
;
1551 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1552 err
= PL330_ERR_FAIL
;
1554 err
= PL330_ERR_ABORT
;
1556 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1557 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, err
);
1558 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, err
);
1559 spin_lock_irqsave(&pl330
->lock
, flags
);
1561 thrd
->req
[0].desc
= NULL
;
1562 thrd
->req
[1].desc
= NULL
;
1563 thrd
->req_running
= -1;
1565 /* Clear the reset flag */
1566 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1570 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1575 /* Returns 1 if state was updated, 0 otherwise */
1576 static int pl330_update(struct pl330_dmac
*pl330
)
1578 struct dma_pl330_desc
*descdone
, *tmp
;
1579 unsigned long flags
;
1582 int id
, ev
, ret
= 0;
1586 spin_lock_irqsave(&pl330
->lock
, flags
);
1588 val
= readl(regs
+ FSM
) & 0x1;
1590 pl330
->dmac_tbd
.reset_mngr
= true;
1592 pl330
->dmac_tbd
.reset_mngr
= false;
1594 val
= readl(regs
+ FSC
) & ((1 << pl330
->pcfg
.num_chan
) - 1);
1595 pl330
->dmac_tbd
.reset_chan
|= val
;
1598 while (i
< pl330
->pcfg
.num_chan
) {
1599 if (val
& (1 << i
)) {
1600 dev_info(pl330
->ddma
.dev
,
1601 "Reset Channel-%d\t CS-%x FTC-%x\n",
1602 i
, readl(regs
+ CS(i
)),
1603 readl(regs
+ FTC(i
)));
1604 _stop(&pl330
->channels
[i
]);
1610 /* Check which event happened i.e, thread notified */
1611 val
= readl(regs
+ ES
);
1612 if (pl330
->pcfg
.num_events
< 32
1613 && val
& ~((1 << pl330
->pcfg
.num_events
) - 1)) {
1614 pl330
->dmac_tbd
.reset_dmac
= true;
1615 dev_err(pl330
->ddma
.dev
, "%s:%d Unexpected!\n", __func__
,
1621 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++) {
1622 if (val
& (1 << ev
)) { /* Event occurred */
1623 struct pl330_thread
*thrd
;
1624 u32 inten
= readl(regs
+ INTEN
);
1627 /* Clear the event */
1628 if (inten
& (1 << ev
))
1629 writel(1 << ev
, regs
+ INTCLR
);
1633 id
= pl330
->events
[ev
];
1635 thrd
= &pl330
->channels
[id
];
1637 active
= thrd
->req_running
;
1638 if (active
== -1) /* Aborted */
1641 /* Detach the req */
1642 descdone
= thrd
->req
[active
].desc
;
1643 thrd
->req
[active
].desc
= NULL
;
1645 thrd
->req_running
= -1;
1647 /* Get going again ASAP */
1650 /* For now, just make a list of callbacks to be done */
1651 list_add_tail(&descdone
->rqd
, &pl330
->req_done
);
1655 /* Now that we are in no hurry, do the callbacks */
1656 list_for_each_entry_safe(descdone
, tmp
, &pl330
->req_done
, rqd
) {
1657 list_del(&descdone
->rqd
);
1658 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1659 dma_pl330_rqcb(descdone
, PL330_ERR_NONE
);
1660 spin_lock_irqsave(&pl330
->lock
, flags
);
1664 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1666 if (pl330
->dmac_tbd
.reset_dmac
1667 || pl330
->dmac_tbd
.reset_mngr
1668 || pl330
->dmac_tbd
.reset_chan
) {
1670 tasklet_schedule(&pl330
->tasks
);
1676 /* Reserve an event */
1677 static inline int _alloc_event(struct pl330_thread
*thrd
)
1679 struct pl330_dmac
*pl330
= thrd
->dmac
;
1682 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++)
1683 if (pl330
->events
[ev
] == -1) {
1684 pl330
->events
[ev
] = thrd
->id
;
1691 static bool _chan_ns(const struct pl330_dmac
*pl330
, int i
)
1693 return pl330
->pcfg
.irq_ns
& (1 << i
);
1696 /* Upon success, returns IdentityToken for the
1697 * allocated channel, NULL otherwise.
1699 static struct pl330_thread
*pl330_request_channel(struct pl330_dmac
*pl330
)
1701 struct pl330_thread
*thrd
= NULL
;
1704 if (pl330
->state
== DYING
)
1707 chans
= pl330
->pcfg
.num_chan
;
1709 for (i
= 0; i
< chans
; i
++) {
1710 thrd
= &pl330
->channels
[i
];
1711 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1712 _chan_ns(pl330
, i
))) {
1713 thrd
->ev
= _alloc_event(thrd
);
1714 if (thrd
->ev
>= 0) {
1717 thrd
->req
[0].desc
= NULL
;
1718 thrd
->req
[1].desc
= NULL
;
1719 thrd
->req_running
= -1;
1729 /* Release an event */
1730 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1732 struct pl330_dmac
*pl330
= thrd
->dmac
;
1734 /* If the event is valid and was held by the thread */
1735 if (ev
>= 0 && ev
< pl330
->pcfg
.num_events
1736 && pl330
->events
[ev
] == thrd
->id
)
1737 pl330
->events
[ev
] = -1;
1740 static void pl330_release_channel(struct pl330_thread
*thrd
)
1742 struct pl330_dmac
*pl330
;
1744 if (!thrd
|| thrd
->free
)
1749 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1750 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1754 _free_event(thrd
, thrd
->ev
);
1758 /* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1761 static void read_dmac_config(struct pl330_dmac
*pl330
)
1763 void __iomem
*regs
= pl330
->base
;
1766 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1767 val
&= CRD_DATA_WIDTH_MASK
;
1768 pl330
->pcfg
.data_bus_width
= 8 * (1 << val
);
1770 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1771 val
&= CRD_DATA_BUFF_MASK
;
1772 pl330
->pcfg
.data_buf_dep
= val
+ 1;
1774 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1775 val
&= CR0_NUM_CHANS_MASK
;
1777 pl330
->pcfg
.num_chan
= val
;
1779 val
= readl(regs
+ CR0
);
1780 if (val
& CR0_PERIPH_REQ_SET
) {
1781 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1783 pl330
->pcfg
.num_peri
= val
;
1784 pl330
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1786 pl330
->pcfg
.num_peri
= 0;
1789 val
= readl(regs
+ CR0
);
1790 if (val
& CR0_BOOT_MAN_NS
)
1791 pl330
->pcfg
.mode
|= DMAC_MODE_NS
;
1793 pl330
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1795 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1796 val
&= CR0_NUM_EVENTS_MASK
;
1798 pl330
->pcfg
.num_events
= val
;
1800 pl330
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1803 static inline void _reset_thread(struct pl330_thread
*thrd
)
1805 struct pl330_dmac
*pl330
= thrd
->dmac
;
1807 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1808 + (thrd
->id
* pl330
->mcbufsz
);
1809 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1810 + (thrd
->id
* pl330
->mcbufsz
);
1811 thrd
->req
[0].desc
= NULL
;
1813 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1814 + pl330
->mcbufsz
/ 2;
1815 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1816 + pl330
->mcbufsz
/ 2;
1817 thrd
->req
[1].desc
= NULL
;
1819 thrd
->req_running
= -1;
1822 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1824 int chans
= pl330
->pcfg
.num_chan
;
1825 struct pl330_thread
*thrd
;
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1831 if (!pl330
->channels
)
1834 /* Init Channel threads */
1835 for (i
= 0; i
< chans
; i
++) {
1836 thrd
= &pl330
->channels
[i
];
1839 _reset_thread(thrd
);
1843 /* MANAGER is indexed at the end */
1844 thrd
= &pl330
->channels
[chans
];
1848 pl330
->manager
= thrd
;
1853 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1855 int chans
= pl330
->pcfg
.num_chan
;
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1862 pl330
->mcode_cpu
= dma_alloc_attrs(pl330
->ddma
.dev
,
1863 chans
* pl330
->mcbufsz
,
1864 &pl330
->mcode_bus
, GFP_KERNEL
,
1865 DMA_ATTR_PRIVILEGED
);
1866 if (!pl330
->mcode_cpu
) {
1867 dev_err(pl330
->ddma
.dev
, "%s:%d Can't allocate memory!\n",
1868 __func__
, __LINE__
);
1872 ret
= dmac_alloc_threads(pl330
);
1874 dev_err(pl330
->ddma
.dev
, "%s:%d Can't to create channels for DMAC!\n",
1875 __func__
, __LINE__
);
1876 dma_free_coherent(pl330
->ddma
.dev
,
1877 chans
* pl330
->mcbufsz
,
1878 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1885 static int pl330_add(struct pl330_dmac
*pl330
)
1889 /* Check if we can handle this DMAC */
1890 if ((pl330
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
1891 dev_err(pl330
->ddma
.dev
, "PERIPH_ID 0x%x !\n",
1892 pl330
->pcfg
.periph_id
);
1896 /* Read the configuration of the DMAC */
1897 read_dmac_config(pl330
);
1899 if (pl330
->pcfg
.num_events
== 0) {
1900 dev_err(pl330
->ddma
.dev
, "%s:%d Can't work without events!\n",
1901 __func__
, __LINE__
);
1905 spin_lock_init(&pl330
->lock
);
1907 INIT_LIST_HEAD(&pl330
->req_done
);
1909 /* Use default MC buffer size if not provided */
1910 if (!pl330
->mcbufsz
)
1911 pl330
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
1913 /* Mark all events as free */
1914 for (i
= 0; i
< pl330
->pcfg
.num_events
; i
++)
1915 pl330
->events
[i
] = -1;
1917 /* Allocate resources needed by the DMAC */
1918 ret
= dmac_alloc_resources(pl330
);
1920 dev_err(pl330
->ddma
.dev
, "Unable to create channels for DMAC\n");
1924 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
1926 pl330
->state
= INIT
;
1931 static int dmac_free_threads(struct pl330_dmac
*pl330
)
1933 struct pl330_thread
*thrd
;
1936 /* Release Channel threads */
1937 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1938 thrd
= &pl330
->channels
[i
];
1939 pl330_release_channel(thrd
);
1943 kfree(pl330
->channels
);
1948 static void pl330_del(struct pl330_dmac
*pl330
)
1950 pl330
->state
= UNINIT
;
1952 tasklet_kill(&pl330
->tasks
);
1954 /* Free DMAC resources */
1955 dmac_free_threads(pl330
);
1957 dma_free_coherent(pl330
->ddma
.dev
,
1958 pl330
->pcfg
.num_chan
* pl330
->mcbufsz
, pl330
->mcode_cpu
,
1962 /* forward declaration */
1963 static struct amba_driver pl330_driver
;
1965 static inline struct dma_pl330_chan
*
1966 to_pchan(struct dma_chan
*ch
)
1971 return container_of(ch
, struct dma_pl330_chan
, chan
);
1974 static inline struct dma_pl330_desc
*
1975 to_desc(struct dma_async_tx_descriptor
*tx
)
1977 return container_of(tx
, struct dma_pl330_desc
, txd
);
1980 static inline void fill_queue(struct dma_pl330_chan
*pch
)
1982 struct dma_pl330_desc
*desc
;
1985 list_for_each_entry(desc
, &pch
->work_list
, node
) {
1987 /* If already submitted */
1988 if (desc
->status
== BUSY
)
1991 ret
= pl330_submit_req(pch
->thread
, desc
);
1993 desc
->status
= BUSY
;
1994 } else if (ret
== -EAGAIN
) {
1995 /* QFull or DMAC Dying */
1998 /* Unacceptable request */
1999 desc
->status
= DONE
;
2000 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Bad Desc(%d)\n",
2001 __func__
, __LINE__
, desc
->txd
.cookie
);
2002 tasklet_schedule(&pch
->task
);
2007 static void pl330_tasklet(unsigned long data
)
2009 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2010 struct dma_pl330_desc
*desc
, *_dt
;
2011 unsigned long flags
;
2012 bool power_down
= false;
2014 spin_lock_irqsave(&pch
->lock
, flags
);
2016 /* Pick up ripe tomatoes */
2017 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2018 if (desc
->status
== DONE
) {
2020 dma_cookie_complete(&desc
->txd
);
2021 list_move_tail(&desc
->node
, &pch
->completed_list
);
2024 /* Try to submit a req imm. next to the last completed cookie */
2027 if (list_empty(&pch
->work_list
)) {
2028 spin_lock(&pch
->thread
->dmac
->lock
);
2030 spin_unlock(&pch
->thread
->dmac
->lock
);
2032 pch
->active
= false;
2034 /* Make sure the PL330 Channel thread is active */
2035 spin_lock(&pch
->thread
->dmac
->lock
);
2036 _start(pch
->thread
);
2037 spin_unlock(&pch
->thread
->dmac
->lock
);
2040 while (!list_empty(&pch
->completed_list
)) {
2041 struct dmaengine_desc_callback cb
;
2043 desc
= list_first_entry(&pch
->completed_list
,
2044 struct dma_pl330_desc
, node
);
2046 dmaengine_desc_get_callback(&desc
->txd
, &cb
);
2049 desc
->status
= PREP
;
2050 list_move_tail(&desc
->node
, &pch
->work_list
);
2053 spin_lock(&pch
->thread
->dmac
->lock
);
2054 _start(pch
->thread
);
2055 spin_unlock(&pch
->thread
->dmac
->lock
);
2059 desc
->status
= FREE
;
2060 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2063 dma_descriptor_unmap(&desc
->txd
);
2065 if (dmaengine_desc_callback_valid(&cb
)) {
2066 spin_unlock_irqrestore(&pch
->lock
, flags
);
2067 dmaengine_desc_callback_invoke(&cb
, NULL
);
2068 spin_lock_irqsave(&pch
->lock
, flags
);
2071 spin_unlock_irqrestore(&pch
->lock
, flags
);
2073 /* If work list empty, power down */
2075 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2076 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2080 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2084 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2087 peri_id
= chan
->private;
2088 return *peri_id
== (unsigned long)param
;
2090 EXPORT_SYMBOL(pl330_filter
);
2092 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2093 struct of_dma
*ofdma
)
2095 int count
= dma_spec
->args_count
;
2096 struct pl330_dmac
*pl330
= ofdma
->of_dma_data
;
2097 unsigned int chan_id
;
2105 chan_id
= dma_spec
->args
[0];
2106 if (chan_id
>= pl330
->num_peripherals
)
2109 return dma_get_slave_channel(&pl330
->peripherals
[chan_id
].chan
);
2112 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2114 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2115 struct pl330_dmac
*pl330
= pch
->dmac
;
2116 unsigned long flags
;
2118 spin_lock_irqsave(&pl330
->lock
, flags
);
2120 dma_cookie_init(chan
);
2121 pch
->cyclic
= false;
2123 pch
->thread
= pl330_request_channel(pl330
);
2125 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2129 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2131 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2136 static int pl330_config(struct dma_chan
*chan
,
2137 struct dma_slave_config
*slave_config
)
2139 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2141 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2142 if (slave_config
->dst_addr
)
2143 pch
->fifo_addr
= slave_config
->dst_addr
;
2144 if (slave_config
->dst_addr_width
)
2145 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2146 if (slave_config
->dst_maxburst
)
2147 pch
->burst_len
= slave_config
->dst_maxburst
;
2148 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2149 if (slave_config
->src_addr
)
2150 pch
->fifo_addr
= slave_config
->src_addr
;
2151 if (slave_config
->src_addr_width
)
2152 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2153 if (slave_config
->src_maxburst
)
2154 pch
->burst_len
= slave_config
->src_maxburst
;
2160 static int pl330_terminate_all(struct dma_chan
*chan
)
2162 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2163 struct dma_pl330_desc
*desc
;
2164 unsigned long flags
;
2165 struct pl330_dmac
*pl330
= pch
->dmac
;
2167 bool power_down
= false;
2169 pm_runtime_get_sync(pl330
->ddma
.dev
);
2170 spin_lock_irqsave(&pch
->lock
, flags
);
2171 spin_lock(&pl330
->lock
);
2173 spin_unlock(&pl330
->lock
);
2175 pch
->thread
->req
[0].desc
= NULL
;
2176 pch
->thread
->req
[1].desc
= NULL
;
2177 pch
->thread
->req_running
= -1;
2178 power_down
= pch
->active
;
2179 pch
->active
= false;
2181 /* Mark all desc done */
2182 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2183 desc
->status
= FREE
;
2184 dma_cookie_complete(&desc
->txd
);
2187 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2188 desc
->status
= FREE
;
2189 dma_cookie_complete(&desc
->txd
);
2192 list_splice_tail_init(&pch
->submitted_list
, &pl330
->desc_pool
);
2193 list_splice_tail_init(&pch
->work_list
, &pl330
->desc_pool
);
2194 list_splice_tail_init(&pch
->completed_list
, &pl330
->desc_pool
);
2195 spin_unlock_irqrestore(&pch
->lock
, flags
);
2196 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2198 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2199 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2205 * We don't support DMA_RESUME command because of hardware
2206 * limitations, so after pausing the channel we cannot restore
2207 * it to active state. We have to terminate channel and setup
2208 * DMA transfer again. This pause feature was implemented to
2209 * allow safely read residue before channel termination.
2211 static int pl330_pause(struct dma_chan
*chan
)
2213 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2214 struct pl330_dmac
*pl330
= pch
->dmac
;
2215 unsigned long flags
;
2217 pm_runtime_get_sync(pl330
->ddma
.dev
);
2218 spin_lock_irqsave(&pch
->lock
, flags
);
2220 spin_lock(&pl330
->lock
);
2222 spin_unlock(&pl330
->lock
);
2224 spin_unlock_irqrestore(&pch
->lock
, flags
);
2225 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2226 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2231 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2233 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2234 struct pl330_dmac
*pl330
= pch
->dmac
;
2235 unsigned long flags
;
2237 tasklet_kill(&pch
->task
);
2239 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2240 spin_lock_irqsave(&pl330
->lock
, flags
);
2242 pl330_release_channel(pch
->thread
);
2246 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2248 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2249 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2250 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2253 static int pl330_get_current_xferred_count(struct dma_pl330_chan
*pch
,
2254 struct dma_pl330_desc
*desc
)
2256 struct pl330_thread
*thrd
= pch
->thread
;
2257 struct pl330_dmac
*pl330
= pch
->dmac
;
2258 void __iomem
*regs
= thrd
->dmac
->base
;
2261 pm_runtime_get_sync(pl330
->ddma
.dev
);
2263 if (desc
->rqcfg
.src_inc
) {
2264 val
= readl(regs
+ SA(thrd
->id
));
2265 addr
= desc
->px
.src_addr
;
2267 val
= readl(regs
+ DA(thrd
->id
));
2268 addr
= desc
->px
.dst_addr
;
2270 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2271 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2273 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2280 static enum dma_status
2281 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2282 struct dma_tx_state
*txstate
)
2284 enum dma_status ret
;
2285 unsigned long flags
;
2286 struct dma_pl330_desc
*desc
, *running
= NULL
, *last_enq
= NULL
;
2287 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2288 unsigned int transferred
, residual
= 0;
2290 ret
= dma_cookie_status(chan
, cookie
, txstate
);
2295 if (ret
== DMA_COMPLETE
)
2298 spin_lock_irqsave(&pch
->lock
, flags
);
2299 spin_lock(&pch
->thread
->dmac
->lock
);
2301 if (pch
->thread
->req_running
!= -1)
2302 running
= pch
->thread
->req
[pch
->thread
->req_running
].desc
;
2304 last_enq
= pch
->thread
->req
[pch
->thread
->lstenq
].desc
;
2306 /* Check in pending list */
2307 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2308 if (desc
->status
== DONE
)
2309 transferred
= desc
->bytes_requested
;
2310 else if (running
&& desc
== running
)
2312 pl330_get_current_xferred_count(pch
, desc
);
2313 else if (desc
->status
== BUSY
)
2315 * Busy but not running means either just enqueued,
2316 * or finished and not yet marked done
2318 if (desc
== last_enq
)
2321 transferred
= desc
->bytes_requested
;
2324 residual
+= desc
->bytes_requested
- transferred
;
2325 if (desc
->txd
.cookie
== cookie
) {
2326 switch (desc
->status
) {
2332 ret
= DMA_IN_PROGRESS
;
2342 spin_unlock(&pch
->thread
->dmac
->lock
);
2343 spin_unlock_irqrestore(&pch
->lock
, flags
);
2346 dma_set_residue(txstate
, residual
);
2351 static void pl330_issue_pending(struct dma_chan
*chan
)
2353 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2354 unsigned long flags
;
2356 spin_lock_irqsave(&pch
->lock
, flags
);
2357 if (list_empty(&pch
->work_list
)) {
2359 * Warn on nothing pending. Empty submitted_list may
2360 * break our pm_runtime usage counter as it is
2361 * updated on work_list emptiness status.
2363 WARN_ON(list_empty(&pch
->submitted_list
));
2365 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2367 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2368 spin_unlock_irqrestore(&pch
->lock
, flags
);
2370 pl330_tasklet((unsigned long)pch
);
2374 * We returned the last one of the circular list of descriptor(s)
2375 * from prep_xxx, so the argument to submit corresponds to the last
2376 * descriptor of the list.
2378 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2380 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2381 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2382 dma_cookie_t cookie
;
2383 unsigned long flags
;
2385 spin_lock_irqsave(&pch
->lock
, flags
);
2387 /* Assign cookies to all nodes */
2388 while (!list_empty(&last
->node
)) {
2389 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2391 desc
->txd
.callback
= last
->txd
.callback
;
2392 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2396 dma_cookie_assign(&desc
->txd
);
2398 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2402 cookie
= dma_cookie_assign(&last
->txd
);
2403 list_add_tail(&last
->node
, &pch
->submitted_list
);
2404 spin_unlock_irqrestore(&pch
->lock
, flags
);
2409 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2411 desc
->rqcfg
.swap
= SWAP_NO
;
2412 desc
->rqcfg
.scctl
= CCTRL0
;
2413 desc
->rqcfg
.dcctl
= CCTRL0
;
2414 desc
->txd
.tx_submit
= pl330_tx_submit
;
2416 INIT_LIST_HEAD(&desc
->node
);
2419 /* Returns the number of descriptors added to the DMAC pool */
2420 static int add_desc(struct pl330_dmac
*pl330
, gfp_t flg
, int count
)
2422 struct dma_pl330_desc
*desc
;
2423 unsigned long flags
;
2426 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2430 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2432 for (i
= 0; i
< count
; i
++) {
2433 _init_desc(&desc
[i
]);
2434 list_add_tail(&desc
[i
].node
, &pl330
->desc_pool
);
2437 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2442 static struct dma_pl330_desc
*pluck_desc(struct pl330_dmac
*pl330
)
2444 struct dma_pl330_desc
*desc
= NULL
;
2445 unsigned long flags
;
2447 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2449 if (!list_empty(&pl330
->desc_pool
)) {
2450 desc
= list_entry(pl330
->desc_pool
.next
,
2451 struct dma_pl330_desc
, node
);
2453 list_del_init(&desc
->node
);
2455 desc
->status
= PREP
;
2456 desc
->txd
.callback
= NULL
;
2459 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2464 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2466 struct pl330_dmac
*pl330
= pch
->dmac
;
2467 u8
*peri_id
= pch
->chan
.private;
2468 struct dma_pl330_desc
*desc
;
2470 /* Pluck one desc from the pool of DMAC */
2471 desc
= pluck_desc(pl330
);
2473 /* If the DMAC pool is empty, alloc new */
2475 if (!add_desc(pl330
, GFP_ATOMIC
, 1))
2479 desc
= pluck_desc(pl330
);
2481 dev_err(pch
->dmac
->ddma
.dev
,
2482 "%s:%d ALERT!\n", __func__
, __LINE__
);
2487 /* Initialize the descriptor */
2489 desc
->txd
.cookie
= 0;
2490 async_tx_ack(&desc
->txd
);
2492 desc
->peri
= peri_id
? pch
->chan
.chan_id
: 0;
2493 desc
->rqcfg
.pcfg
= &pch
->dmac
->pcfg
;
2495 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2500 static inline void fill_px(struct pl330_xfer
*px
,
2501 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2508 static struct dma_pl330_desc
*
2509 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2510 dma_addr_t src
, size_t len
)
2512 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2515 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2516 __func__
, __LINE__
);
2521 * Ideally we should lookout for reqs bigger than
2522 * those that can be programmed with 256 bytes of
2523 * MC buffer, but considering a req size is seldom
2524 * going to be word-unaligned and more than 200MB,
2526 * Also, should the limit is reached we'd rather
2527 * have the platform increase MC buffer size than
2528 * complicating this API driver.
2530 fill_px(&desc
->px
, dst
, src
, len
);
2535 /* Call after fixing burst size */
2536 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2538 struct dma_pl330_chan
*pch
= desc
->pchan
;
2539 struct pl330_dmac
*pl330
= pch
->dmac
;
2542 burst_len
= pl330
->pcfg
.data_bus_width
/ 8;
2543 burst_len
*= pl330
->pcfg
.data_buf_dep
/ pl330
->pcfg
.num_chan
;
2544 burst_len
>>= desc
->rqcfg
.brst_size
;
2546 /* src/dst_burst_len can't be more than 16 */
2550 while (burst_len
> 1) {
2551 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2559 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2560 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2561 size_t period_len
, enum dma_transfer_direction direction
,
2562 unsigned long flags
)
2564 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2565 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2566 struct pl330_dmac
*pl330
= pch
->dmac
;
2571 if (len
% period_len
!= 0)
2574 if (!is_slave_direction(direction
)) {
2575 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Invalid dma direction\n",
2576 __func__
, __LINE__
);
2580 for (i
= 0; i
< len
/ period_len
; i
++) {
2581 desc
= pl330_get_desc(pch
);
2583 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2584 __func__
, __LINE__
);
2589 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2591 while (!list_empty(&first
->node
)) {
2592 desc
= list_entry(first
->node
.next
,
2593 struct dma_pl330_desc
, node
);
2594 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2597 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2599 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2604 switch (direction
) {
2605 case DMA_MEM_TO_DEV
:
2606 desc
->rqcfg
.src_inc
= 1;
2607 desc
->rqcfg
.dst_inc
= 0;
2609 dst
= pch
->fifo_addr
;
2611 case DMA_DEV_TO_MEM
:
2612 desc
->rqcfg
.src_inc
= 0;
2613 desc
->rqcfg
.dst_inc
= 1;
2614 src
= pch
->fifo_addr
;
2621 desc
->rqtype
= direction
;
2622 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2623 desc
->rqcfg
.brst_len
= 1;
2624 desc
->bytes_requested
= period_len
;
2625 fill_px(&desc
->px
, dst
, src
, period_len
);
2630 list_add_tail(&desc
->node
, &first
->node
);
2632 dma_addr
+= period_len
;
2639 desc
->txd
.flags
= flags
;
2644 static struct dma_async_tx_descriptor
*
2645 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2646 dma_addr_t src
, size_t len
, unsigned long flags
)
2648 struct dma_pl330_desc
*desc
;
2649 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2650 struct pl330_dmac
*pl330
;
2653 if (unlikely(!pch
|| !len
))
2658 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2662 desc
->rqcfg
.src_inc
= 1;
2663 desc
->rqcfg
.dst_inc
= 1;
2664 desc
->rqtype
= DMA_MEM_TO_MEM
;
2666 /* Select max possible burst size */
2667 burst
= pl330
->pcfg
.data_bus_width
/ 8;
2670 * Make sure we use a burst size that aligns with all the memcpy
2671 * parameters because our DMA programming algorithm doesn't cope with
2672 * transfers which straddle an entry in the DMA device's MFIFO.
2674 while ((src
| dst
| len
) & (burst
- 1))
2677 desc
->rqcfg
.brst_size
= 0;
2678 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2679 desc
->rqcfg
.brst_size
++;
2682 * If burst size is smaller than bus width then make sure we only
2683 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2685 if (desc
->rqcfg
.brst_size
* 8 < pl330
->pcfg
.data_bus_width
)
2686 desc
->rqcfg
.brst_len
= 1;
2688 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2689 desc
->bytes_requested
= len
;
2691 desc
->txd
.flags
= flags
;
2696 static void __pl330_giveback_desc(struct pl330_dmac
*pl330
,
2697 struct dma_pl330_desc
*first
)
2699 unsigned long flags
;
2700 struct dma_pl330_desc
*desc
;
2705 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2707 while (!list_empty(&first
->node
)) {
2708 desc
= list_entry(first
->node
.next
,
2709 struct dma_pl330_desc
, node
);
2710 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2713 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2715 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2718 static struct dma_async_tx_descriptor
*
2719 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2720 unsigned int sg_len
, enum dma_transfer_direction direction
,
2721 unsigned long flg
, void *context
)
2723 struct dma_pl330_desc
*first
, *desc
= NULL
;
2724 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2725 struct scatterlist
*sg
;
2729 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2732 addr
= pch
->fifo_addr
;
2736 for_each_sg(sgl
, sg
, sg_len
, i
) {
2738 desc
= pl330_get_desc(pch
);
2740 struct pl330_dmac
*pl330
= pch
->dmac
;
2742 dev_err(pch
->dmac
->ddma
.dev
,
2743 "%s:%d Unable to fetch desc\n",
2744 __func__
, __LINE__
);
2745 __pl330_giveback_desc(pl330
, first
);
2753 list_add_tail(&desc
->node
, &first
->node
);
2755 if (direction
== DMA_MEM_TO_DEV
) {
2756 desc
->rqcfg
.src_inc
= 1;
2757 desc
->rqcfg
.dst_inc
= 0;
2759 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2761 desc
->rqcfg
.src_inc
= 0;
2762 desc
->rqcfg
.dst_inc
= 1;
2764 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2767 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2768 desc
->rqcfg
.brst_len
= 1;
2769 desc
->rqtype
= direction
;
2770 desc
->bytes_requested
= sg_dma_len(sg
);
2773 /* Return the last desc in the chain */
2774 desc
->txd
.flags
= flg
;
2778 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2780 if (pl330_update(data
))
2786 #define PL330_DMA_BUSWIDTHS \
2787 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2788 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2789 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2790 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2791 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2794 * Runtime PM callbacks are provided by amba/bus.c driver.
2796 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2797 * bus driver will only disable/enable the clock in runtime PM callbacks.
2799 static int __maybe_unused
pl330_suspend(struct device
*dev
)
2801 struct amba_device
*pcdev
= to_amba_device(dev
);
2803 pm_runtime_disable(dev
);
2805 if (!pm_runtime_status_suspended(dev
)) {
2806 /* amba did not disable the clock */
2807 amba_pclk_disable(pcdev
);
2809 amba_pclk_unprepare(pcdev
);
2814 static int __maybe_unused
pl330_resume(struct device
*dev
)
2816 struct amba_device
*pcdev
= to_amba_device(dev
);
2819 ret
= amba_pclk_prepare(pcdev
);
2823 if (!pm_runtime_status_suspended(dev
))
2824 ret
= amba_pclk_enable(pcdev
);
2826 pm_runtime_enable(dev
);
2831 static SIMPLE_DEV_PM_OPS(pl330_pm
, pl330_suspend
, pl330_resume
);
2834 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2836 struct dma_pl330_platdata
*pdat
;
2837 struct pl330_config
*pcfg
;
2838 struct pl330_dmac
*pl330
;
2839 struct dma_pl330_chan
*pch
, *_p
;
2840 struct dma_device
*pd
;
2841 struct resource
*res
;
2844 struct device_node
*np
= adev
->dev
.of_node
;
2846 pdat
= dev_get_platdata(&adev
->dev
);
2848 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2852 /* Allocate a new DMAC and its Channels */
2853 pl330
= devm_kzalloc(&adev
->dev
, sizeof(*pl330
), GFP_KERNEL
);
2858 pd
->dev
= &adev
->dev
;
2860 pl330
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2863 for (i
= 0; i
< ARRAY_SIZE(of_quirks
); i
++)
2864 if (of_property_read_bool(np
, of_quirks
[i
].quirk
))
2865 pl330
->quirks
|= of_quirks
[i
].id
;
2868 pl330
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2869 if (IS_ERR(pl330
->base
))
2870 return PTR_ERR(pl330
->base
);
2872 amba_set_drvdata(adev
, pl330
);
2874 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2877 ret
= devm_request_irq(&adev
->dev
, irq
,
2878 pl330_irq_handler
, 0,
2879 dev_name(&adev
->dev
), pl330
);
2887 pcfg
= &pl330
->pcfg
;
2889 pcfg
->periph_id
= adev
->periphid
;
2890 ret
= pl330_add(pl330
);
2894 INIT_LIST_HEAD(&pl330
->desc_pool
);
2895 spin_lock_init(&pl330
->pool_lock
);
2897 /* Create a descriptor pool of default size */
2898 if (!add_desc(pl330
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2899 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2901 INIT_LIST_HEAD(&pd
->channels
);
2903 /* Initialize channel parameters */
2905 num_chan
= max_t(int, pdat
->nr_valid_peri
, pcfg
->num_chan
);
2907 num_chan
= max_t(int, pcfg
->num_peri
, pcfg
->num_chan
);
2909 pl330
->num_peripherals
= num_chan
;
2911 pl330
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2912 if (!pl330
->peripherals
) {
2917 for (i
= 0; i
< num_chan
; i
++) {
2918 pch
= &pl330
->peripherals
[i
];
2919 if (!adev
->dev
.of_node
)
2920 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2922 pch
->chan
.private = adev
->dev
.of_node
;
2924 INIT_LIST_HEAD(&pch
->submitted_list
);
2925 INIT_LIST_HEAD(&pch
->work_list
);
2926 INIT_LIST_HEAD(&pch
->completed_list
);
2927 spin_lock_init(&pch
->lock
);
2929 pch
->chan
.device
= pd
;
2932 /* Add the channel to the DMAC list */
2933 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2937 pd
->cap_mask
= pdat
->cap_mask
;
2939 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2940 if (pcfg
->num_peri
) {
2941 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2942 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2943 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2947 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2948 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2949 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2950 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2951 pd
->device_tx_status
= pl330_tx_status
;
2952 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2953 pd
->device_config
= pl330_config
;
2954 pd
->device_pause
= pl330_pause
;
2955 pd
->device_terminate_all
= pl330_terminate_all
;
2956 pd
->device_issue_pending
= pl330_issue_pending
;
2957 pd
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2958 pd
->dst_addr_widths
= PL330_DMA_BUSWIDTHS
;
2959 pd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2960 pd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_SEGMENT
;
2961 pd
->max_burst
= ((pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
) ?
2962 1 : PL330_MAX_BURST
);
2964 ret
= dma_async_device_register(pd
);
2966 dev_err(&adev
->dev
, "unable to register DMAC\n");
2970 if (adev
->dev
.of_node
) {
2971 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2972 of_dma_pl330_xlate
, pl330
);
2975 "unable to register DMA to the generic DT DMA helpers\n");
2979 adev
->dev
.dma_parms
= &pl330
->dma_parms
;
2982 * This is the limit for transfers with a buswidth of 1, larger
2983 * buswidths will have larger limits.
2985 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2987 dev_err(&adev
->dev
, "unable to set the seg size\n");
2990 dev_info(&adev
->dev
,
2991 "Loaded driver for PL330 DMAC-%x\n", adev
->periphid
);
2992 dev_info(&adev
->dev
,
2993 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2994 pcfg
->data_buf_dep
, pcfg
->data_bus_width
/ 8, pcfg
->num_chan
,
2995 pcfg
->num_peri
, pcfg
->num_events
);
2997 pm_runtime_irq_safe(&adev
->dev
);
2998 pm_runtime_use_autosuspend(&adev
->dev
);
2999 pm_runtime_set_autosuspend_delay(&adev
->dev
, PL330_AUTOSUSPEND_DELAY
);
3000 pm_runtime_mark_last_busy(&adev
->dev
);
3001 pm_runtime_put_autosuspend(&adev
->dev
);
3006 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
3009 /* Remove the channel */
3010 list_del(&pch
->chan
.device_node
);
3012 /* Flush the channel */
3014 pl330_terminate_all(&pch
->chan
);
3015 pl330_free_chan_resources(&pch
->chan
);
3024 static int pl330_remove(struct amba_device
*adev
)
3026 struct pl330_dmac
*pl330
= amba_get_drvdata(adev
);
3027 struct dma_pl330_chan
*pch
, *_p
;
3030 pm_runtime_get_noresume(pl330
->ddma
.dev
);
3032 if (adev
->dev
.of_node
)
3033 of_dma_controller_free(adev
->dev
.of_node
);
3035 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
3037 devm_free_irq(&adev
->dev
, irq
, pl330
);
3040 dma_async_device_unregister(&pl330
->ddma
);
3043 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
3046 /* Remove the channel */
3047 list_del(&pch
->chan
.device_node
);
3049 /* Flush the channel */
3051 pl330_terminate_all(&pch
->chan
);
3052 pl330_free_chan_resources(&pch
->chan
);
3061 static struct amba_id pl330_ids
[] = {
3069 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3071 static struct amba_driver pl330_driver
= {
3073 .owner
= THIS_MODULE
,
3074 .name
= "dma-pl330",
3077 .id_table
= pl330_ids
,
3078 .probe
= pl330_probe
,
3079 .remove
= pl330_remove
,
3082 module_amba_driver(pl330_driver
);
3084 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3085 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3086 MODULE_LICENSE("GPL");