2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/scatterlist.h>
27 #include <linux/of_dma.h>
28 #include <linux/err.h>
29 #include <linux/pm_runtime.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
35 #define PL330_MAX_BURST 16
37 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39 enum pl330_cachectrl
{
40 CCTRL0
, /* Noncacheable and nonbufferable */
41 CCTRL1
, /* Bufferable only */
42 CCTRL2
, /* Cacheable, but do not allocate */
43 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
44 INVALID1
, /* AWCACHE = 0x1000 */
46 CCTRL6
, /* Cacheable write-through, allocate on writes only */
47 CCTRL7
, /* Cacheable write-back, allocate on writes only */
58 /* Register and Bit field Definitions */
60 #define DS_ST_STOP 0x0
61 #define DS_ST_EXEC 0x1
62 #define DS_ST_CMISS 0x2
63 #define DS_ST_UPDTPC 0x3
65 #define DS_ST_ATBRR 0x5
66 #define DS_ST_QBUSY 0x6
68 #define DS_ST_KILL 0x8
69 #define DS_ST_CMPLT 0x9
70 #define DS_ST_FLTCMP 0xe
71 #define DS_ST_FAULT 0xf
76 #define INTSTATUS 0x28
83 #define FTC(n) (_FTC + (n)*0x4)
86 #define CS(n) (_CS + (n)*0x8)
87 #define CS_CNS (1 << 21)
90 #define CPC(n) (_CPC + (n)*0x8)
93 #define SA(n) (_SA + (n)*0x20)
96 #define DA(n) (_DA + (n)*0x20)
99 #define CC(n) (_CC + (n)*0x20)
101 #define CC_SRCINC (1 << 0)
102 #define CC_DSTINC (1 << 14)
103 #define CC_SRCPRI (1 << 8)
104 #define CC_DSTPRI (1 << 22)
105 #define CC_SRCNS (1 << 9)
106 #define CC_DSTNS (1 << 23)
107 #define CC_SRCIA (1 << 10)
108 #define CC_DSTIA (1 << 24)
109 #define CC_SRCBRSTLEN_SHFT 4
110 #define CC_DSTBRSTLEN_SHFT 18
111 #define CC_SRCBRSTSIZE_SHFT 1
112 #define CC_DSTBRSTSIZE_SHFT 15
113 #define CC_SRCCCTRL_SHFT 11
114 #define CC_SRCCCTRL_MASK 0x7
115 #define CC_DSTCCTRL_SHFT 25
116 #define CC_DRCCCTRL_MASK 0x7
117 #define CC_SWAP_SHFT 28
120 #define LC0(n) (_LC0 + (n)*0x20)
123 #define LC1(n) (_LC1 + (n)*0x20)
125 #define DBGSTATUS 0xd00
126 #define DBG_BUSY (1 << 0)
129 #define DBGINST0 0xd08
130 #define DBGINST1 0xd0c
139 #define PERIPH_ID 0xfe0
140 #define PERIPH_REV_SHIFT 20
141 #define PERIPH_REV_MASK 0xf
142 #define PERIPH_REV_R0P0 0
143 #define PERIPH_REV_R1P0 1
144 #define PERIPH_REV_R1P1 2
146 #define CR0_PERIPH_REQ_SET (1 << 0)
147 #define CR0_BOOT_EN_SET (1 << 1)
148 #define CR0_BOOT_MAN_NS (1 << 2)
149 #define CR0_NUM_CHANS_SHIFT 4
150 #define CR0_NUM_CHANS_MASK 0x7
151 #define CR0_NUM_PERIPH_SHIFT 12
152 #define CR0_NUM_PERIPH_MASK 0x1f
153 #define CR0_NUM_EVENTS_SHIFT 17
154 #define CR0_NUM_EVENTS_MASK 0x1f
156 #define CR1_ICACHE_LEN_SHIFT 0
157 #define CR1_ICACHE_LEN_MASK 0x7
158 #define CR1_NUM_ICACHELINES_SHIFT 4
159 #define CR1_NUM_ICACHELINES_MASK 0xf
161 #define CRD_DATA_WIDTH_SHIFT 0
162 #define CRD_DATA_WIDTH_MASK 0x7
163 #define CRD_WR_CAP_SHIFT 4
164 #define CRD_WR_CAP_MASK 0x7
165 #define CRD_WR_Q_DEP_SHIFT 8
166 #define CRD_WR_Q_DEP_MASK 0xf
167 #define CRD_RD_CAP_SHIFT 12
168 #define CRD_RD_CAP_MASK 0x7
169 #define CRD_RD_Q_DEP_SHIFT 16
170 #define CRD_RD_Q_DEP_MASK 0xf
171 #define CRD_DATA_BUFF_SHIFT 20
172 #define CRD_DATA_BUFF_MASK 0x3ff
175 #define DESIGNER 0x41
177 #define INTEG_CFG 0x0
178 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180 #define PL330_STATE_STOPPED (1 << 0)
181 #define PL330_STATE_EXECUTING (1 << 1)
182 #define PL330_STATE_WFE (1 << 2)
183 #define PL330_STATE_FAULTING (1 << 3)
184 #define PL330_STATE_COMPLETING (1 << 4)
185 #define PL330_STATE_WFP (1 << 5)
186 #define PL330_STATE_KILLING (1 << 6)
187 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
188 #define PL330_STATE_CACHEMISS (1 << 8)
189 #define PL330_STATE_UPDTPC (1 << 9)
190 #define PL330_STATE_ATBARRIER (1 << 10)
191 #define PL330_STATE_QUEUEBUSY (1 << 11)
192 #define PL330_STATE_INVALID (1 << 15)
194 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197 #define CMD_DMAADDH 0x54
198 #define CMD_DMAEND 0x00
199 #define CMD_DMAFLUSHP 0x35
200 #define CMD_DMAGO 0xa0
201 #define CMD_DMALD 0x04
202 #define CMD_DMALDP 0x25
203 #define CMD_DMALP 0x20
204 #define CMD_DMALPEND 0x28
205 #define CMD_DMAKILL 0x01
206 #define CMD_DMAMOV 0xbc
207 #define CMD_DMANOP 0x18
208 #define CMD_DMARMB 0x12
209 #define CMD_DMASEV 0x34
210 #define CMD_DMAST 0x08
211 #define CMD_DMASTP 0x29
212 #define CMD_DMASTZ 0x0c
213 #define CMD_DMAWFE 0x36
214 #define CMD_DMAWFP 0x30
215 #define CMD_DMAWMB 0x13
219 #define SZ_DMAFLUSHP 2
223 #define SZ_DMALPEND 2
237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
249 #define MCODE_BUFF_PER_REQ 256
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line
;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Delay for runtime PM autosuspend, ms */
272 #define PL330_AUTOSUSPEND_DELAY 20
274 /* Populated by the PL330 core driver for DMA API driver's info */
275 struct pl330_config
{
277 #define DMAC_MODE_NS (1 << 0)
279 unsigned int data_bus_width
:10; /* In number of bits */
280 unsigned int data_buf_dep
:11;
281 unsigned int num_chan
:4;
282 unsigned int num_peri
:6;
284 unsigned int num_events
:6;
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
296 struct pl330_reqcfg
{
297 /* Address Incrementing */
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
309 unsigned brst_size
:3; /* in power of 2 */
311 enum pl330_cachectrl dcctl
;
312 enum pl330_cachectrl scctl
;
313 enum pl330_byteswap swap
;
314 struct pl330_config
*pcfg
;
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
328 /* The xfer callbacks are made with one of these arguments. */
330 /* The all xfers in the request were success. */
332 /* If req aborted due to global error. */
334 /* If req failed due to problem with Channel. */
355 struct dma_pl330_desc
;
360 struct dma_pl330_desc
*desc
;
363 /* ToBeDone for tasklet */
371 struct pl330_thread
{
374 /* If the channel is not yet acquired by any client */
377 struct pl330_dmac
*dmac
;
378 /* Only two at a time */
379 struct _pl330_req req
[2];
380 /* Index of the last enqueued request */
382 /* Index of the last submitted request or -1 if the DMA is stopped */
386 enum pl330_dmac_state
{
393 /* In the DMAC pool */
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
407 * Sitting on the channel work_list but xfer done
413 struct dma_pl330_chan
{
414 /* Schedule desc completion */
415 struct tasklet_struct task
;
417 /* DMA-Engine Channel */
418 struct dma_chan chan
;
420 /* List of submitted descriptors */
421 struct list_head submitted_list
;
422 /* List of issued descriptors */
423 struct list_head work_list
;
424 /* List of completed descriptors */
425 struct list_head completed_list
;
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
432 struct pl330_dmac
*dmac
;
434 /* To protect channel manipulation */
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
441 struct pl330_thread
*thread
;
443 /* For D-to-M and M-to-D channels */
444 int burst_sz
; /* the peripheral fifo width */
445 int burst_len
; /* the number of burst */
446 dma_addr_t fifo_addr
;
448 /* for cyclic capability */
451 /* for runtime pm tracking */
456 /* DMA-Engine Device */
457 struct dma_device ddma
;
459 /* Holds info about sg limitations */
460 struct device_dma_parameters dma_parms
;
462 /* Pool of descriptors available for the DMAC's channels */
463 struct list_head desc_pool
;
464 /* To protect desc_pool manipulation */
465 spinlock_t pool_lock
;
467 /* Size of MicroCode buffers for each channel. */
469 /* ioremap'ed address of PL330 registers. */
471 /* Populated by the PL330 core driver during pl330_add */
472 struct pl330_config pcfg
;
475 /* Maximum possible events/irqs */
477 /* BUS address of MicroCode buffer */
478 dma_addr_t mcode_bus
;
479 /* CPU address of MicroCode buffer */
481 /* List of all Channel threads */
482 struct pl330_thread
*channels
;
483 /* Pointer to the MANAGER thread */
484 struct pl330_thread
*manager
;
485 /* To handle bad news in interrupt */
486 struct tasklet_struct tasks
;
487 struct _pl330_tbd dmac_tbd
;
488 /* State of DMAC operation */
489 enum pl330_dmac_state state
;
490 /* Holds list of reqs with due callbacks */
491 struct list_head req_done
;
493 /* Peripheral channels connected to this DMAC */
494 unsigned int num_peripherals
;
495 struct dma_pl330_chan
*peripherals
; /* keep at end */
499 static struct pl330_of_quirks
{
504 .quirk
= "arm,pl330-broken-no-flushp",
505 .id
= PL330_QUIRK_BROKEN_NO_FLUSHP
,
509 struct dma_pl330_desc
{
510 /* To attach to a queue as child */
511 struct list_head node
;
513 /* Descriptor for the DMA Engine API */
514 struct dma_async_tx_descriptor txd
;
516 /* Xfer for PL330 core */
517 struct pl330_xfer px
;
519 struct pl330_reqcfg rqcfg
;
521 enum desc_status status
;
526 /* The channel which currently holds this desc */
527 struct dma_pl330_chan
*pchan
;
529 enum dma_transfer_direction rqtype
;
530 /* Index of peripheral for the xfer. */
532 /* Hook to attach to DMAC's list of reqs with due callback */
533 struct list_head rqd
;
538 struct dma_pl330_desc
*desc
;
541 static inline bool _queue_empty(struct pl330_thread
*thrd
)
543 return thrd
->req
[0].desc
== NULL
&& thrd
->req
[1].desc
== NULL
;
546 static inline bool _queue_full(struct pl330_thread
*thrd
)
548 return thrd
->req
[0].desc
!= NULL
&& thrd
->req
[1].desc
!= NULL
;
551 static inline bool is_manager(struct pl330_thread
*thrd
)
553 return thrd
->dmac
->manager
== thrd
;
556 /* If manager of the thread is in Non-Secure mode */
557 static inline bool _manager_ns(struct pl330_thread
*thrd
)
559 return (thrd
->dmac
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
562 static inline u32
get_revision(u32 periph_id
)
564 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
567 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
568 enum pl330_dst da
, u16 val
)
573 buf
[0] = CMD_DMAADDH
;
578 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
579 da
== 1 ? "DA" : "SA", val
);
584 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
591 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
596 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
601 buf
[0] = CMD_DMAFLUSHP
;
607 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
612 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
620 buf
[0] |= (0 << 1) | (1 << 0);
621 else if (cond
== BURST
)
622 buf
[0] |= (1 << 1) | (1 << 0);
624 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
625 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
630 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
631 enum pl330_cond cond
, u8 peri
)
645 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
646 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
651 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
652 unsigned loop
, u8 cnt
)
662 cnt
--; /* DMAC increments by 1 internally */
665 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
671 enum pl330_cond cond
;
677 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
678 const struct _arg_LPEND
*arg
)
680 enum pl330_cond cond
= arg
->cond
;
681 bool forever
= arg
->forever
;
682 unsigned loop
= arg
->loop
;
683 u8 bjump
= arg
->bjump
;
688 buf
[0] = CMD_DMALPEND
;
697 buf
[0] |= (0 << 1) | (1 << 0);
698 else if (cond
== BURST
)
699 buf
[0] |= (1 << 1) | (1 << 0);
703 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
704 forever
? "FE" : "END",
705 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
712 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
717 buf
[0] = CMD_DMAKILL
;
722 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
723 enum dmamov_dst dst
, u32 val
)
735 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
736 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
741 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
748 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
753 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
760 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
765 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
776 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
781 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
789 buf
[0] |= (0 << 1) | (1 << 0);
790 else if (cond
== BURST
)
791 buf
[0] |= (1 << 1) | (1 << 0);
793 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
794 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
799 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
800 enum pl330_cond cond
, u8 peri
)
814 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
815 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
820 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
827 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
832 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
847 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
848 ev
>> 3, invalidate
? ", I" : "");
853 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
854 enum pl330_cond cond
, u8 peri
)
862 buf
[0] |= (0 << 1) | (0 << 0);
863 else if (cond
== BURST
)
864 buf
[0] |= (1 << 1) | (0 << 0);
866 buf
[0] |= (0 << 1) | (1 << 0);
872 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
873 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
878 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
885 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
896 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
897 const struct _arg_GO
*arg
)
900 u32 addr
= arg
->addr
;
901 unsigned ns
= arg
->ns
;
917 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
919 /* Returns Time-Out */
920 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
922 void __iomem
*regs
= thrd
->dmac
->base
;
923 unsigned long loops
= msecs_to_loops(5);
926 /* Until Manager is Idle */
927 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
939 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
940 u8 insn
[], bool as_manager
)
942 void __iomem
*regs
= thrd
->dmac
->base
;
945 val
= (insn
[0] << 16) | (insn
[1] << 24);
948 val
|= (thrd
->id
<< 8); /* Channel Number */
950 writel(val
, regs
+ DBGINST0
);
952 val
= le32_to_cpu(*((__le32
*)&insn
[2]));
953 writel(val
, regs
+ DBGINST1
);
955 /* If timed out due to halted state-machine */
956 if (_until_dmac_idle(thrd
)) {
957 dev_err(thrd
->dmac
->ddma
.dev
, "DMAC halted!\n");
962 writel(0, regs
+ DBGCMD
);
965 static inline u32
_state(struct pl330_thread
*thrd
)
967 void __iomem
*regs
= thrd
->dmac
->base
;
970 if (is_manager(thrd
))
971 val
= readl(regs
+ DS
) & 0xf;
973 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
977 return PL330_STATE_STOPPED
;
979 return PL330_STATE_EXECUTING
;
981 return PL330_STATE_CACHEMISS
;
983 return PL330_STATE_UPDTPC
;
985 return PL330_STATE_WFE
;
987 return PL330_STATE_FAULTING
;
989 if (is_manager(thrd
))
990 return PL330_STATE_INVALID
;
992 return PL330_STATE_ATBARRIER
;
994 if (is_manager(thrd
))
995 return PL330_STATE_INVALID
;
997 return PL330_STATE_QUEUEBUSY
;
999 if (is_manager(thrd
))
1000 return PL330_STATE_INVALID
;
1002 return PL330_STATE_WFP
;
1004 if (is_manager(thrd
))
1005 return PL330_STATE_INVALID
;
1007 return PL330_STATE_KILLING
;
1009 if (is_manager(thrd
))
1010 return PL330_STATE_INVALID
;
1012 return PL330_STATE_COMPLETING
;
1014 if (is_manager(thrd
))
1015 return PL330_STATE_INVALID
;
1017 return PL330_STATE_FAULT_COMPLETING
;
1019 return PL330_STATE_INVALID
;
1023 static void _stop(struct pl330_thread
*thrd
)
1025 void __iomem
*regs
= thrd
->dmac
->base
;
1026 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1028 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1029 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1031 /* Return if nothing needs to be done */
1032 if (_state(thrd
) == PL330_STATE_COMPLETING
1033 || _state(thrd
) == PL330_STATE_KILLING
1034 || _state(thrd
) == PL330_STATE_STOPPED
)
1037 _emit_KILL(0, insn
);
1039 /* Stop generating interrupts for SEV */
1040 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1042 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1045 /* Start doing req 'idx' of thread 'thrd' */
1046 static bool _trigger(struct pl330_thread
*thrd
)
1048 void __iomem
*regs
= thrd
->dmac
->base
;
1049 struct _pl330_req
*req
;
1050 struct dma_pl330_desc
*desc
;
1053 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1056 /* Return if already ACTIVE */
1057 if (_state(thrd
) != PL330_STATE_STOPPED
)
1060 idx
= 1 - thrd
->lstenq
;
1061 if (thrd
->req
[idx
].desc
!= NULL
) {
1062 req
= &thrd
->req
[idx
];
1065 if (thrd
->req
[idx
].desc
!= NULL
)
1066 req
= &thrd
->req
[idx
];
1071 /* Return if no request */
1075 /* Return if req is running */
1076 if (idx
== thrd
->req_running
)
1081 ns
= desc
->rqcfg
.nonsecure
? 1 : 0;
1083 /* See 'Abort Sources' point-4 at Page 2-25 */
1084 if (_manager_ns(thrd
) && !ns
)
1085 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d Recipe for ABORT!\n",
1086 __func__
, __LINE__
);
1089 go
.addr
= req
->mc_bus
;
1091 _emit_GO(0, insn
, &go
);
1093 /* Set to generate interrupts for SEV */
1094 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1096 /* Only manager can execute GO */
1097 _execute_DBGINSN(thrd
, insn
, true);
1099 thrd
->req_running
= idx
;
1104 static bool _start(struct pl330_thread
*thrd
)
1106 switch (_state(thrd
)) {
1107 case PL330_STATE_FAULT_COMPLETING
:
1108 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1110 if (_state(thrd
) == PL330_STATE_KILLING
)
1111 UNTIL(thrd
, PL330_STATE_STOPPED
)
1113 case PL330_STATE_FAULTING
:
1116 case PL330_STATE_KILLING
:
1117 case PL330_STATE_COMPLETING
:
1118 UNTIL(thrd
, PL330_STATE_STOPPED
)
1120 case PL330_STATE_STOPPED
:
1121 return _trigger(thrd
);
1123 case PL330_STATE_WFP
:
1124 case PL330_STATE_QUEUEBUSY
:
1125 case PL330_STATE_ATBARRIER
:
1126 case PL330_STATE_UPDTPC
:
1127 case PL330_STATE_CACHEMISS
:
1128 case PL330_STATE_EXECUTING
:
1131 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1137 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1138 const struct _xfer_spec
*pxs
, int cyc
)
1141 struct pl330_config
*pcfg
= pxs
->desc
->rqcfg
.pcfg
;
1143 /* check lock-up free version */
1144 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1146 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1147 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1151 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1152 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1153 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1154 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1161 static inline int _ldst_devtomem(struct pl330_dmac
*pl330
, unsigned dry_run
,
1162 u8 buf
[], const struct _xfer_spec
*pxs
,
1166 enum pl330_cond cond
;
1168 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1174 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1175 off
+= _emit_LDP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1176 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1178 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1179 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1186 static inline int _ldst_memtodev(struct pl330_dmac
*pl330
,
1187 unsigned dry_run
, u8 buf
[],
1188 const struct _xfer_spec
*pxs
, int cyc
)
1191 enum pl330_cond cond
;
1193 if (pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
)
1199 off
+= _emit_WFP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1200 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1201 off
+= _emit_STP(dry_run
, &buf
[off
], cond
, pxs
->desc
->peri
);
1203 if (!(pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
))
1204 off
+= _emit_FLUSHP(dry_run
, &buf
[off
],
1211 static int _bursts(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1212 const struct _xfer_spec
*pxs
, int cyc
)
1216 switch (pxs
->desc
->rqtype
) {
1217 case DMA_MEM_TO_DEV
:
1218 off
+= _ldst_memtodev(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1220 case DMA_DEV_TO_MEM
:
1221 off
+= _ldst_devtomem(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1223 case DMA_MEM_TO_MEM
:
1224 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1227 off
+= 0x40000000; /* Scare off the Client */
1234 /* Returns bytes consumed and updates bursts */
1235 static inline int _loop(struct pl330_dmac
*pl330
, unsigned dry_run
, u8 buf
[],
1236 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1238 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1239 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1240 struct _arg_LPEND lpend
;
1243 return _bursts(pl330
, dry_run
, buf
, pxs
, 1);
1245 /* Max iterations possible in DMALP is 256 */
1246 if (*bursts
>= 256*256) {
1249 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1250 } else if (*bursts
> 256) {
1252 lcnt0
= *bursts
/ lcnt1
;
1260 szlp
= _emit_LP(1, buf
, 0, 0);
1261 szbrst
= _bursts(pl330
, 1, buf
, pxs
, 1);
1263 lpend
.cond
= ALWAYS
;
1264 lpend
.forever
= false;
1267 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1275 * Max bursts that we can unroll due to limit on the
1276 * size of backward jump that can be encoded in DMALPEND
1277 * which is 8-bits and hence 255
1279 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1281 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1286 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1290 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1293 off
+= _bursts(pl330
, dry_run
, &buf
[off
], pxs
, cyc
);
1295 lpend
.cond
= ALWAYS
;
1296 lpend
.forever
= false;
1298 lpend
.bjump
= off
- ljmp1
;
1299 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1302 lpend
.cond
= ALWAYS
;
1303 lpend
.forever
= false;
1305 lpend
.bjump
= off
- ljmp0
;
1306 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1309 *bursts
= lcnt1
* cyc
;
1316 static inline int _setup_loops(struct pl330_dmac
*pl330
,
1317 unsigned dry_run
, u8 buf
[],
1318 const struct _xfer_spec
*pxs
)
1320 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1322 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1327 off
+= _loop(pl330
, dry_run
, &buf
[off
], &c
, pxs
);
1334 static inline int _setup_xfer(struct pl330_dmac
*pl330
,
1335 unsigned dry_run
, u8 buf
[],
1336 const struct _xfer_spec
*pxs
)
1338 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1341 /* DMAMOV SAR, x->src_addr */
1342 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1343 /* DMAMOV DAR, x->dst_addr */
1344 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1347 off
+= _setup_loops(pl330
, dry_run
, &buf
[off
], pxs
);
1353 * A req is a sequence of one or more xfer units.
1354 * Returns the number of bytes taken to setup the MC for the req.
1356 static int _setup_req(struct pl330_dmac
*pl330
, unsigned dry_run
,
1357 struct pl330_thread
*thrd
, unsigned index
,
1358 struct _xfer_spec
*pxs
)
1360 struct _pl330_req
*req
= &thrd
->req
[index
];
1361 struct pl330_xfer
*x
;
1362 u8
*buf
= req
->mc_cpu
;
1365 PL330_DBGMC_START(req
->mc_bus
);
1367 /* DMAMOV CCR, ccr */
1368 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1371 /* Error if xfer length is not aligned at burst size */
1372 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1375 off
+= _setup_xfer(pl330
, dry_run
, &buf
[off
], pxs
);
1377 /* DMASEV peripheral/event */
1378 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1380 off
+= _emit_END(dry_run
, &buf
[off
]);
1385 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1395 /* We set same protection levels for Src and DST for now */
1396 if (rqc
->privileged
)
1397 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1399 ccr
|= CC_SRCNS
| CC_DSTNS
;
1400 if (rqc
->insnaccess
)
1401 ccr
|= CC_SRCIA
| CC_DSTIA
;
1403 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1404 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1406 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1407 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1409 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1410 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1412 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1418 * Submit a list of xfers after which the client wants notification.
1419 * Client is not notified after each xfer unit, just once after all
1420 * xfer units are done or some error occurs.
1422 static int pl330_submit_req(struct pl330_thread
*thrd
,
1423 struct dma_pl330_desc
*desc
)
1425 struct pl330_dmac
*pl330
= thrd
->dmac
;
1426 struct _xfer_spec xs
;
1427 unsigned long flags
;
1432 if (pl330
->state
== DYING
1433 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1434 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d\n",
1435 __func__
, __LINE__
);
1439 /* If request for non-existing peripheral */
1440 if (desc
->rqtype
!= DMA_MEM_TO_MEM
&&
1441 desc
->peri
>= pl330
->pcfg
.num_peri
) {
1442 dev_info(thrd
->dmac
->ddma
.dev
,
1443 "%s:%d Invalid peripheral(%u)!\n",
1444 __func__
, __LINE__
, desc
->peri
);
1448 spin_lock_irqsave(&pl330
->lock
, flags
);
1450 if (_queue_full(thrd
)) {
1455 /* Prefer Secure Channel */
1456 if (!_manager_ns(thrd
))
1457 desc
->rqcfg
.nonsecure
= 0;
1459 desc
->rqcfg
.nonsecure
= 1;
1461 ccr
= _prepare_ccr(&desc
->rqcfg
);
1463 idx
= thrd
->req
[0].desc
== NULL
? 0 : 1;
1468 /* First dry run to check if req is acceptable */
1469 ret
= _setup_req(pl330
, 1, thrd
, idx
, &xs
);
1473 if (ret
> pl330
->mcbufsz
/ 2) {
1474 dev_info(pl330
->ddma
.dev
, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1475 __func__
, __LINE__
, ret
, pl330
->mcbufsz
/ 2);
1480 /* Hook the request */
1482 thrd
->req
[idx
].desc
= desc
;
1483 _setup_req(pl330
, 0, thrd
, idx
, &xs
);
1488 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1493 static void dma_pl330_rqcb(struct dma_pl330_desc
*desc
, enum pl330_op_err err
)
1495 struct dma_pl330_chan
*pch
;
1496 unsigned long flags
;
1503 /* If desc aborted */
1507 spin_lock_irqsave(&pch
->lock
, flags
);
1509 desc
->status
= DONE
;
1511 spin_unlock_irqrestore(&pch
->lock
, flags
);
1513 tasklet_schedule(&pch
->task
);
1516 static void pl330_dotask(unsigned long data
)
1518 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1519 unsigned long flags
;
1522 spin_lock_irqsave(&pl330
->lock
, flags
);
1524 /* The DMAC itself gone nuts */
1525 if (pl330
->dmac_tbd
.reset_dmac
) {
1526 pl330
->state
= DYING
;
1527 /* Reset the manager too */
1528 pl330
->dmac_tbd
.reset_mngr
= true;
1529 /* Clear the reset flag */
1530 pl330
->dmac_tbd
.reset_dmac
= false;
1533 if (pl330
->dmac_tbd
.reset_mngr
) {
1534 _stop(pl330
->manager
);
1535 /* Reset all channels */
1536 pl330
->dmac_tbd
.reset_chan
= (1 << pl330
->pcfg
.num_chan
) - 1;
1537 /* Clear the reset flag */
1538 pl330
->dmac_tbd
.reset_mngr
= false;
1541 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1543 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1544 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1545 void __iomem
*regs
= pl330
->base
;
1546 enum pl330_op_err err
;
1550 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1551 err
= PL330_ERR_FAIL
;
1553 err
= PL330_ERR_ABORT
;
1555 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1556 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, err
);
1557 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, err
);
1558 spin_lock_irqsave(&pl330
->lock
, flags
);
1560 thrd
->req
[0].desc
= NULL
;
1561 thrd
->req
[1].desc
= NULL
;
1562 thrd
->req_running
= -1;
1564 /* Clear the reset flag */
1565 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1569 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1574 /* Returns 1 if state was updated, 0 otherwise */
1575 static int pl330_update(struct pl330_dmac
*pl330
)
1577 struct dma_pl330_desc
*descdone
, *tmp
;
1578 unsigned long flags
;
1581 int id
, ev
, ret
= 0;
1585 spin_lock_irqsave(&pl330
->lock
, flags
);
1587 val
= readl(regs
+ FSM
) & 0x1;
1589 pl330
->dmac_tbd
.reset_mngr
= true;
1591 pl330
->dmac_tbd
.reset_mngr
= false;
1593 val
= readl(regs
+ FSC
) & ((1 << pl330
->pcfg
.num_chan
) - 1);
1594 pl330
->dmac_tbd
.reset_chan
|= val
;
1597 while (i
< pl330
->pcfg
.num_chan
) {
1598 if (val
& (1 << i
)) {
1599 dev_info(pl330
->ddma
.dev
,
1600 "Reset Channel-%d\t CS-%x FTC-%x\n",
1601 i
, readl(regs
+ CS(i
)),
1602 readl(regs
+ FTC(i
)));
1603 _stop(&pl330
->channels
[i
]);
1609 /* Check which event happened i.e, thread notified */
1610 val
= readl(regs
+ ES
);
1611 if (pl330
->pcfg
.num_events
< 32
1612 && val
& ~((1 << pl330
->pcfg
.num_events
) - 1)) {
1613 pl330
->dmac_tbd
.reset_dmac
= true;
1614 dev_err(pl330
->ddma
.dev
, "%s:%d Unexpected!\n", __func__
,
1620 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++) {
1621 if (val
& (1 << ev
)) { /* Event occurred */
1622 struct pl330_thread
*thrd
;
1623 u32 inten
= readl(regs
+ INTEN
);
1626 /* Clear the event */
1627 if (inten
& (1 << ev
))
1628 writel(1 << ev
, regs
+ INTCLR
);
1632 id
= pl330
->events
[ev
];
1634 thrd
= &pl330
->channels
[id
];
1636 active
= thrd
->req_running
;
1637 if (active
== -1) /* Aborted */
1640 /* Detach the req */
1641 descdone
= thrd
->req
[active
].desc
;
1642 thrd
->req
[active
].desc
= NULL
;
1644 thrd
->req_running
= -1;
1646 /* Get going again ASAP */
1649 /* For now, just make a list of callbacks to be done */
1650 list_add_tail(&descdone
->rqd
, &pl330
->req_done
);
1654 /* Now that we are in no hurry, do the callbacks */
1655 list_for_each_entry_safe(descdone
, tmp
, &pl330
->req_done
, rqd
) {
1656 list_del(&descdone
->rqd
);
1657 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1658 dma_pl330_rqcb(descdone
, PL330_ERR_NONE
);
1659 spin_lock_irqsave(&pl330
->lock
, flags
);
1663 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1665 if (pl330
->dmac_tbd
.reset_dmac
1666 || pl330
->dmac_tbd
.reset_mngr
1667 || pl330
->dmac_tbd
.reset_chan
) {
1669 tasklet_schedule(&pl330
->tasks
);
1675 /* Reserve an event */
1676 static inline int _alloc_event(struct pl330_thread
*thrd
)
1678 struct pl330_dmac
*pl330
= thrd
->dmac
;
1681 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++)
1682 if (pl330
->events
[ev
] == -1) {
1683 pl330
->events
[ev
] = thrd
->id
;
1690 static bool _chan_ns(const struct pl330_dmac
*pl330
, int i
)
1692 return pl330
->pcfg
.irq_ns
& (1 << i
);
1695 /* Upon success, returns IdentityToken for the
1696 * allocated channel, NULL otherwise.
1698 static struct pl330_thread
*pl330_request_channel(struct pl330_dmac
*pl330
)
1700 struct pl330_thread
*thrd
= NULL
;
1703 if (pl330
->state
== DYING
)
1706 chans
= pl330
->pcfg
.num_chan
;
1708 for (i
= 0; i
< chans
; i
++) {
1709 thrd
= &pl330
->channels
[i
];
1710 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1711 _chan_ns(pl330
, i
))) {
1712 thrd
->ev
= _alloc_event(thrd
);
1713 if (thrd
->ev
>= 0) {
1716 thrd
->req
[0].desc
= NULL
;
1717 thrd
->req
[1].desc
= NULL
;
1718 thrd
->req_running
= -1;
1728 /* Release an event */
1729 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1731 struct pl330_dmac
*pl330
= thrd
->dmac
;
1733 /* If the event is valid and was held by the thread */
1734 if (ev
>= 0 && ev
< pl330
->pcfg
.num_events
1735 && pl330
->events
[ev
] == thrd
->id
)
1736 pl330
->events
[ev
] = -1;
1739 static void pl330_release_channel(struct pl330_thread
*thrd
)
1741 struct pl330_dmac
*pl330
;
1743 if (!thrd
|| thrd
->free
)
1748 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1749 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1753 _free_event(thrd
, thrd
->ev
);
1757 /* Initialize the structure for PL330 configuration, that can be used
1758 * by the client driver the make best use of the DMAC
1760 static void read_dmac_config(struct pl330_dmac
*pl330
)
1762 void __iomem
*regs
= pl330
->base
;
1765 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1766 val
&= CRD_DATA_WIDTH_MASK
;
1767 pl330
->pcfg
.data_bus_width
= 8 * (1 << val
);
1769 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1770 val
&= CRD_DATA_BUFF_MASK
;
1771 pl330
->pcfg
.data_buf_dep
= val
+ 1;
1773 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1774 val
&= CR0_NUM_CHANS_MASK
;
1776 pl330
->pcfg
.num_chan
= val
;
1778 val
= readl(regs
+ CR0
);
1779 if (val
& CR0_PERIPH_REQ_SET
) {
1780 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1782 pl330
->pcfg
.num_peri
= val
;
1783 pl330
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1785 pl330
->pcfg
.num_peri
= 0;
1788 val
= readl(regs
+ CR0
);
1789 if (val
& CR0_BOOT_MAN_NS
)
1790 pl330
->pcfg
.mode
|= DMAC_MODE_NS
;
1792 pl330
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1794 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1795 val
&= CR0_NUM_EVENTS_MASK
;
1797 pl330
->pcfg
.num_events
= val
;
1799 pl330
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1802 static inline void _reset_thread(struct pl330_thread
*thrd
)
1804 struct pl330_dmac
*pl330
= thrd
->dmac
;
1806 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1807 + (thrd
->id
* pl330
->mcbufsz
);
1808 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1809 + (thrd
->id
* pl330
->mcbufsz
);
1810 thrd
->req
[0].desc
= NULL
;
1812 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1813 + pl330
->mcbufsz
/ 2;
1814 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1815 + pl330
->mcbufsz
/ 2;
1816 thrd
->req
[1].desc
= NULL
;
1818 thrd
->req_running
= -1;
1821 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1823 int chans
= pl330
->pcfg
.num_chan
;
1824 struct pl330_thread
*thrd
;
1827 /* Allocate 1 Manager and 'chans' Channel threads */
1828 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1830 if (!pl330
->channels
)
1833 /* Init Channel threads */
1834 for (i
= 0; i
< chans
; i
++) {
1835 thrd
= &pl330
->channels
[i
];
1838 _reset_thread(thrd
);
1842 /* MANAGER is indexed at the end */
1843 thrd
= &pl330
->channels
[chans
];
1847 pl330
->manager
= thrd
;
1852 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1854 int chans
= pl330
->pcfg
.num_chan
;
1858 * Alloc MicroCode buffer for 'chans' Channel threads.
1859 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 pl330
->mcode_cpu
= dma_alloc_attrs(pl330
->ddma
.dev
,
1862 chans
* pl330
->mcbufsz
,
1863 &pl330
->mcode_bus
, GFP_KERNEL
,
1864 DMA_ATTR_PRIVILEGED
);
1865 if (!pl330
->mcode_cpu
) {
1866 dev_err(pl330
->ddma
.dev
, "%s:%d Can't allocate memory!\n",
1867 __func__
, __LINE__
);
1871 ret
= dmac_alloc_threads(pl330
);
1873 dev_err(pl330
->ddma
.dev
, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__
, __LINE__
);
1875 dma_free_coherent(pl330
->ddma
.dev
,
1876 chans
* pl330
->mcbufsz
,
1877 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1884 static int pl330_add(struct pl330_dmac
*pl330
)
1888 /* Check if we can handle this DMAC */
1889 if ((pl330
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
1890 dev_err(pl330
->ddma
.dev
, "PERIPH_ID 0x%x !\n",
1891 pl330
->pcfg
.periph_id
);
1895 /* Read the configuration of the DMAC */
1896 read_dmac_config(pl330
);
1898 if (pl330
->pcfg
.num_events
== 0) {
1899 dev_err(pl330
->ddma
.dev
, "%s:%d Can't work without events!\n",
1900 __func__
, __LINE__
);
1904 spin_lock_init(&pl330
->lock
);
1906 INIT_LIST_HEAD(&pl330
->req_done
);
1908 /* Use default MC buffer size if not provided */
1909 if (!pl330
->mcbufsz
)
1910 pl330
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
1912 /* Mark all events as free */
1913 for (i
= 0; i
< pl330
->pcfg
.num_events
; i
++)
1914 pl330
->events
[i
] = -1;
1916 /* Allocate resources needed by the DMAC */
1917 ret
= dmac_alloc_resources(pl330
);
1919 dev_err(pl330
->ddma
.dev
, "Unable to create channels for DMAC\n");
1923 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
1925 pl330
->state
= INIT
;
1930 static int dmac_free_threads(struct pl330_dmac
*pl330
)
1932 struct pl330_thread
*thrd
;
1935 /* Release Channel threads */
1936 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1937 thrd
= &pl330
->channels
[i
];
1938 pl330_release_channel(thrd
);
1942 kfree(pl330
->channels
);
1947 static void pl330_del(struct pl330_dmac
*pl330
)
1949 pl330
->state
= UNINIT
;
1951 tasklet_kill(&pl330
->tasks
);
1953 /* Free DMAC resources */
1954 dmac_free_threads(pl330
);
1956 dma_free_coherent(pl330
->ddma
.dev
,
1957 pl330
->pcfg
.num_chan
* pl330
->mcbufsz
, pl330
->mcode_cpu
,
1961 /* forward declaration */
1962 static struct amba_driver pl330_driver
;
1964 static inline struct dma_pl330_chan
*
1965 to_pchan(struct dma_chan
*ch
)
1970 return container_of(ch
, struct dma_pl330_chan
, chan
);
1973 static inline struct dma_pl330_desc
*
1974 to_desc(struct dma_async_tx_descriptor
*tx
)
1976 return container_of(tx
, struct dma_pl330_desc
, txd
);
1979 static inline void fill_queue(struct dma_pl330_chan
*pch
)
1981 struct dma_pl330_desc
*desc
;
1984 list_for_each_entry(desc
, &pch
->work_list
, node
) {
1986 /* If already submitted */
1987 if (desc
->status
== BUSY
)
1990 ret
= pl330_submit_req(pch
->thread
, desc
);
1992 desc
->status
= BUSY
;
1993 } else if (ret
== -EAGAIN
) {
1994 /* QFull or DMAC Dying */
1997 /* Unacceptable request */
1998 desc
->status
= DONE
;
1999 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Bad Desc(%d)\n",
2000 __func__
, __LINE__
, desc
->txd
.cookie
);
2001 tasklet_schedule(&pch
->task
);
2006 static void pl330_tasklet(unsigned long data
)
2008 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2009 struct dma_pl330_desc
*desc
, *_dt
;
2010 unsigned long flags
;
2011 bool power_down
= false;
2013 spin_lock_irqsave(&pch
->lock
, flags
);
2015 /* Pick up ripe tomatoes */
2016 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2017 if (desc
->status
== DONE
) {
2019 dma_cookie_complete(&desc
->txd
);
2020 list_move_tail(&desc
->node
, &pch
->completed_list
);
2023 /* Try to submit a req imm. next to the last completed cookie */
2026 if (list_empty(&pch
->work_list
)) {
2027 spin_lock(&pch
->thread
->dmac
->lock
);
2029 spin_unlock(&pch
->thread
->dmac
->lock
);
2031 pch
->active
= false;
2033 /* Make sure the PL330 Channel thread is active */
2034 spin_lock(&pch
->thread
->dmac
->lock
);
2035 _start(pch
->thread
);
2036 spin_unlock(&pch
->thread
->dmac
->lock
);
2039 while (!list_empty(&pch
->completed_list
)) {
2040 struct dmaengine_desc_callback cb
;
2042 desc
= list_first_entry(&pch
->completed_list
,
2043 struct dma_pl330_desc
, node
);
2045 dmaengine_desc_get_callback(&desc
->txd
, &cb
);
2048 desc
->status
= PREP
;
2049 list_move_tail(&desc
->node
, &pch
->work_list
);
2052 spin_lock(&pch
->thread
->dmac
->lock
);
2053 _start(pch
->thread
);
2054 spin_unlock(&pch
->thread
->dmac
->lock
);
2058 desc
->status
= FREE
;
2059 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2062 dma_descriptor_unmap(&desc
->txd
);
2064 if (dmaengine_desc_callback_valid(&cb
)) {
2065 spin_unlock_irqrestore(&pch
->lock
, flags
);
2066 dmaengine_desc_callback_invoke(&cb
, NULL
);
2067 spin_lock_irqsave(&pch
->lock
, flags
);
2070 spin_unlock_irqrestore(&pch
->lock
, flags
);
2072 /* If work list empty, power down */
2074 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2075 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2079 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2080 struct of_dma
*ofdma
)
2082 int count
= dma_spec
->args_count
;
2083 struct pl330_dmac
*pl330
= ofdma
->of_dma_data
;
2084 unsigned int chan_id
;
2092 chan_id
= dma_spec
->args
[0];
2093 if (chan_id
>= pl330
->num_peripherals
)
2096 return dma_get_slave_channel(&pl330
->peripherals
[chan_id
].chan
);
2099 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2101 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2102 struct pl330_dmac
*pl330
= pch
->dmac
;
2103 unsigned long flags
;
2105 spin_lock_irqsave(&pl330
->lock
, flags
);
2107 dma_cookie_init(chan
);
2108 pch
->cyclic
= false;
2110 pch
->thread
= pl330_request_channel(pl330
);
2112 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2116 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2118 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2123 static int pl330_config(struct dma_chan
*chan
,
2124 struct dma_slave_config
*slave_config
)
2126 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2128 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2129 if (slave_config
->dst_addr
)
2130 pch
->fifo_addr
= slave_config
->dst_addr
;
2131 if (slave_config
->dst_addr_width
)
2132 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2133 if (slave_config
->dst_maxburst
)
2134 pch
->burst_len
= slave_config
->dst_maxburst
;
2135 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2136 if (slave_config
->src_addr
)
2137 pch
->fifo_addr
= slave_config
->src_addr
;
2138 if (slave_config
->src_addr_width
)
2139 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2140 if (slave_config
->src_maxburst
)
2141 pch
->burst_len
= slave_config
->src_maxburst
;
2147 static int pl330_terminate_all(struct dma_chan
*chan
)
2149 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2150 struct dma_pl330_desc
*desc
;
2151 unsigned long flags
;
2152 struct pl330_dmac
*pl330
= pch
->dmac
;
2154 bool power_down
= false;
2156 pm_runtime_get_sync(pl330
->ddma
.dev
);
2157 spin_lock_irqsave(&pch
->lock
, flags
);
2158 spin_lock(&pl330
->lock
);
2160 spin_unlock(&pl330
->lock
);
2162 pch
->thread
->req
[0].desc
= NULL
;
2163 pch
->thread
->req
[1].desc
= NULL
;
2164 pch
->thread
->req_running
= -1;
2165 power_down
= pch
->active
;
2166 pch
->active
= false;
2168 /* Mark all desc done */
2169 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2170 desc
->status
= FREE
;
2171 dma_cookie_complete(&desc
->txd
);
2174 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2175 desc
->status
= FREE
;
2176 dma_cookie_complete(&desc
->txd
);
2179 list_splice_tail_init(&pch
->submitted_list
, &pl330
->desc_pool
);
2180 list_splice_tail_init(&pch
->work_list
, &pl330
->desc_pool
);
2181 list_splice_tail_init(&pch
->completed_list
, &pl330
->desc_pool
);
2182 spin_unlock_irqrestore(&pch
->lock
, flags
);
2183 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2185 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2186 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2192 * We don't support DMA_RESUME command because of hardware
2193 * limitations, so after pausing the channel we cannot restore
2194 * it to active state. We have to terminate channel and setup
2195 * DMA transfer again. This pause feature was implemented to
2196 * allow safely read residue before channel termination.
2198 static int pl330_pause(struct dma_chan
*chan
)
2200 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2201 struct pl330_dmac
*pl330
= pch
->dmac
;
2202 unsigned long flags
;
2204 pm_runtime_get_sync(pl330
->ddma
.dev
);
2205 spin_lock_irqsave(&pch
->lock
, flags
);
2207 spin_lock(&pl330
->lock
);
2209 spin_unlock(&pl330
->lock
);
2211 spin_unlock_irqrestore(&pch
->lock
, flags
);
2212 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2213 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2218 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2220 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2221 struct pl330_dmac
*pl330
= pch
->dmac
;
2222 unsigned long flags
;
2224 tasklet_kill(&pch
->task
);
2226 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2227 spin_lock_irqsave(&pl330
->lock
, flags
);
2229 pl330_release_channel(pch
->thread
);
2233 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2235 spin_unlock_irqrestore(&pl330
->lock
, flags
);
2236 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2237 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2240 static int pl330_get_current_xferred_count(struct dma_pl330_chan
*pch
,
2241 struct dma_pl330_desc
*desc
)
2243 struct pl330_thread
*thrd
= pch
->thread
;
2244 struct pl330_dmac
*pl330
= pch
->dmac
;
2245 void __iomem
*regs
= thrd
->dmac
->base
;
2248 pm_runtime_get_sync(pl330
->ddma
.dev
);
2250 if (desc
->rqcfg
.src_inc
) {
2251 val
= readl(regs
+ SA(thrd
->id
));
2252 addr
= desc
->px
.src_addr
;
2254 val
= readl(regs
+ DA(thrd
->id
));
2255 addr
= desc
->px
.dst_addr
;
2257 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2258 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2260 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2267 static enum dma_status
2268 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2269 struct dma_tx_state
*txstate
)
2271 enum dma_status ret
;
2272 unsigned long flags
;
2273 struct dma_pl330_desc
*desc
, *running
= NULL
, *last_enq
= NULL
;
2274 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2275 unsigned int transferred
, residual
= 0;
2277 ret
= dma_cookie_status(chan
, cookie
, txstate
);
2282 if (ret
== DMA_COMPLETE
)
2285 spin_lock_irqsave(&pch
->lock
, flags
);
2286 spin_lock(&pch
->thread
->dmac
->lock
);
2288 if (pch
->thread
->req_running
!= -1)
2289 running
= pch
->thread
->req
[pch
->thread
->req_running
].desc
;
2291 last_enq
= pch
->thread
->req
[pch
->thread
->lstenq
].desc
;
2293 /* Check in pending list */
2294 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2295 if (desc
->status
== DONE
)
2296 transferred
= desc
->bytes_requested
;
2297 else if (running
&& desc
== running
)
2299 pl330_get_current_xferred_count(pch
, desc
);
2300 else if (desc
->status
== BUSY
)
2302 * Busy but not running means either just enqueued,
2303 * or finished and not yet marked done
2305 if (desc
== last_enq
)
2308 transferred
= desc
->bytes_requested
;
2311 residual
+= desc
->bytes_requested
- transferred
;
2312 if (desc
->txd
.cookie
== cookie
) {
2313 switch (desc
->status
) {
2319 ret
= DMA_IN_PROGRESS
;
2329 spin_unlock(&pch
->thread
->dmac
->lock
);
2330 spin_unlock_irqrestore(&pch
->lock
, flags
);
2333 dma_set_residue(txstate
, residual
);
2338 static void pl330_issue_pending(struct dma_chan
*chan
)
2340 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2341 unsigned long flags
;
2343 spin_lock_irqsave(&pch
->lock
, flags
);
2344 if (list_empty(&pch
->work_list
)) {
2346 * Warn on nothing pending. Empty submitted_list may
2347 * break our pm_runtime usage counter as it is
2348 * updated on work_list emptiness status.
2350 WARN_ON(list_empty(&pch
->submitted_list
));
2352 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2354 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2355 spin_unlock_irqrestore(&pch
->lock
, flags
);
2357 pl330_tasklet((unsigned long)pch
);
2361 * We returned the last one of the circular list of descriptor(s)
2362 * from prep_xxx, so the argument to submit corresponds to the last
2363 * descriptor of the list.
2365 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2367 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2368 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2369 dma_cookie_t cookie
;
2370 unsigned long flags
;
2372 spin_lock_irqsave(&pch
->lock
, flags
);
2374 /* Assign cookies to all nodes */
2375 while (!list_empty(&last
->node
)) {
2376 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2378 desc
->txd
.callback
= last
->txd
.callback
;
2379 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2383 dma_cookie_assign(&desc
->txd
);
2385 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2389 cookie
= dma_cookie_assign(&last
->txd
);
2390 list_add_tail(&last
->node
, &pch
->submitted_list
);
2391 spin_unlock_irqrestore(&pch
->lock
, flags
);
2396 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2398 desc
->rqcfg
.swap
= SWAP_NO
;
2399 desc
->rqcfg
.scctl
= CCTRL0
;
2400 desc
->rqcfg
.dcctl
= CCTRL0
;
2401 desc
->txd
.tx_submit
= pl330_tx_submit
;
2403 INIT_LIST_HEAD(&desc
->node
);
2406 /* Returns the number of descriptors added to the DMAC pool */
2407 static int add_desc(struct pl330_dmac
*pl330
, gfp_t flg
, int count
)
2409 struct dma_pl330_desc
*desc
;
2410 unsigned long flags
;
2413 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2417 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2419 for (i
= 0; i
< count
; i
++) {
2420 _init_desc(&desc
[i
]);
2421 list_add_tail(&desc
[i
].node
, &pl330
->desc_pool
);
2424 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2429 static struct dma_pl330_desc
*pluck_desc(struct pl330_dmac
*pl330
)
2431 struct dma_pl330_desc
*desc
= NULL
;
2432 unsigned long flags
;
2434 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2436 if (!list_empty(&pl330
->desc_pool
)) {
2437 desc
= list_entry(pl330
->desc_pool
.next
,
2438 struct dma_pl330_desc
, node
);
2440 list_del_init(&desc
->node
);
2442 desc
->status
= PREP
;
2443 desc
->txd
.callback
= NULL
;
2446 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2451 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2453 struct pl330_dmac
*pl330
= pch
->dmac
;
2454 u8
*peri_id
= pch
->chan
.private;
2455 struct dma_pl330_desc
*desc
;
2457 /* Pluck one desc from the pool of DMAC */
2458 desc
= pluck_desc(pl330
);
2460 /* If the DMAC pool is empty, alloc new */
2462 if (!add_desc(pl330
, GFP_ATOMIC
, 1))
2466 desc
= pluck_desc(pl330
);
2468 dev_err(pch
->dmac
->ddma
.dev
,
2469 "%s:%d ALERT!\n", __func__
, __LINE__
);
2474 /* Initialize the descriptor */
2476 desc
->txd
.cookie
= 0;
2477 async_tx_ack(&desc
->txd
);
2479 desc
->peri
= peri_id
? pch
->chan
.chan_id
: 0;
2480 desc
->rqcfg
.pcfg
= &pch
->dmac
->pcfg
;
2482 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2487 static inline void fill_px(struct pl330_xfer
*px
,
2488 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2495 static struct dma_pl330_desc
*
2496 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2497 dma_addr_t src
, size_t len
)
2499 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2502 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2503 __func__
, __LINE__
);
2508 * Ideally we should lookout for reqs bigger than
2509 * those that can be programmed with 256 bytes of
2510 * MC buffer, but considering a req size is seldom
2511 * going to be word-unaligned and more than 200MB,
2513 * Also, should the limit is reached we'd rather
2514 * have the platform increase MC buffer size than
2515 * complicating this API driver.
2517 fill_px(&desc
->px
, dst
, src
, len
);
2522 /* Call after fixing burst size */
2523 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2525 struct dma_pl330_chan
*pch
= desc
->pchan
;
2526 struct pl330_dmac
*pl330
= pch
->dmac
;
2529 burst_len
= pl330
->pcfg
.data_bus_width
/ 8;
2530 burst_len
*= pl330
->pcfg
.data_buf_dep
/ pl330
->pcfg
.num_chan
;
2531 burst_len
>>= desc
->rqcfg
.brst_size
;
2533 /* src/dst_burst_len can't be more than 16 */
2537 while (burst_len
> 1) {
2538 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2546 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2547 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2548 size_t period_len
, enum dma_transfer_direction direction
,
2549 unsigned long flags
)
2551 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2552 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2553 struct pl330_dmac
*pl330
= pch
->dmac
;
2558 if (len
% period_len
!= 0)
2561 if (!is_slave_direction(direction
)) {
2562 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Invalid dma direction\n",
2563 __func__
, __LINE__
);
2567 for (i
= 0; i
< len
/ period_len
; i
++) {
2568 desc
= pl330_get_desc(pch
);
2570 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2571 __func__
, __LINE__
);
2576 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2578 while (!list_empty(&first
->node
)) {
2579 desc
= list_entry(first
->node
.next
,
2580 struct dma_pl330_desc
, node
);
2581 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2584 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2586 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2591 switch (direction
) {
2592 case DMA_MEM_TO_DEV
:
2593 desc
->rqcfg
.src_inc
= 1;
2594 desc
->rqcfg
.dst_inc
= 0;
2596 dst
= pch
->fifo_addr
;
2598 case DMA_DEV_TO_MEM
:
2599 desc
->rqcfg
.src_inc
= 0;
2600 desc
->rqcfg
.dst_inc
= 1;
2601 src
= pch
->fifo_addr
;
2608 desc
->rqtype
= direction
;
2609 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2610 desc
->rqcfg
.brst_len
= 1;
2611 desc
->bytes_requested
= period_len
;
2612 fill_px(&desc
->px
, dst
, src
, period_len
);
2617 list_add_tail(&desc
->node
, &first
->node
);
2619 dma_addr
+= period_len
;
2626 desc
->txd
.flags
= flags
;
2631 static struct dma_async_tx_descriptor
*
2632 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2633 dma_addr_t src
, size_t len
, unsigned long flags
)
2635 struct dma_pl330_desc
*desc
;
2636 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2637 struct pl330_dmac
*pl330
;
2640 if (unlikely(!pch
|| !len
))
2645 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2649 desc
->rqcfg
.src_inc
= 1;
2650 desc
->rqcfg
.dst_inc
= 1;
2651 desc
->rqtype
= DMA_MEM_TO_MEM
;
2653 /* Select max possible burst size */
2654 burst
= pl330
->pcfg
.data_bus_width
/ 8;
2657 * Make sure we use a burst size that aligns with all the memcpy
2658 * parameters because our DMA programming algorithm doesn't cope with
2659 * transfers which straddle an entry in the DMA device's MFIFO.
2661 while ((src
| dst
| len
) & (burst
- 1))
2664 desc
->rqcfg
.brst_size
= 0;
2665 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2666 desc
->rqcfg
.brst_size
++;
2669 * If burst size is smaller than bus width then make sure we only
2670 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2672 if (desc
->rqcfg
.brst_size
* 8 < pl330
->pcfg
.data_bus_width
)
2673 desc
->rqcfg
.brst_len
= 1;
2675 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2676 desc
->bytes_requested
= len
;
2678 desc
->txd
.flags
= flags
;
2683 static void __pl330_giveback_desc(struct pl330_dmac
*pl330
,
2684 struct dma_pl330_desc
*first
)
2686 unsigned long flags
;
2687 struct dma_pl330_desc
*desc
;
2692 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2694 while (!list_empty(&first
->node
)) {
2695 desc
= list_entry(first
->node
.next
,
2696 struct dma_pl330_desc
, node
);
2697 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2700 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2702 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2705 static struct dma_async_tx_descriptor
*
2706 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2707 unsigned int sg_len
, enum dma_transfer_direction direction
,
2708 unsigned long flg
, void *context
)
2710 struct dma_pl330_desc
*first
, *desc
= NULL
;
2711 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2712 struct scatterlist
*sg
;
2716 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2719 addr
= pch
->fifo_addr
;
2723 for_each_sg(sgl
, sg
, sg_len
, i
) {
2725 desc
= pl330_get_desc(pch
);
2727 struct pl330_dmac
*pl330
= pch
->dmac
;
2729 dev_err(pch
->dmac
->ddma
.dev
,
2730 "%s:%d Unable to fetch desc\n",
2731 __func__
, __LINE__
);
2732 __pl330_giveback_desc(pl330
, first
);
2740 list_add_tail(&desc
->node
, &first
->node
);
2742 if (direction
== DMA_MEM_TO_DEV
) {
2743 desc
->rqcfg
.src_inc
= 1;
2744 desc
->rqcfg
.dst_inc
= 0;
2746 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2748 desc
->rqcfg
.src_inc
= 0;
2749 desc
->rqcfg
.dst_inc
= 1;
2751 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2754 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2755 desc
->rqcfg
.brst_len
= 1;
2756 desc
->rqtype
= direction
;
2757 desc
->bytes_requested
= sg_dma_len(sg
);
2760 /* Return the last desc in the chain */
2761 desc
->txd
.flags
= flg
;
2765 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2767 if (pl330_update(data
))
2773 #define PL330_DMA_BUSWIDTHS \
2774 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2775 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2776 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2777 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2778 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2781 * Runtime PM callbacks are provided by amba/bus.c driver.
2783 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2784 * bus driver will only disable/enable the clock in runtime PM callbacks.
2786 static int __maybe_unused
pl330_suspend(struct device
*dev
)
2788 struct amba_device
*pcdev
= to_amba_device(dev
);
2790 pm_runtime_disable(dev
);
2792 if (!pm_runtime_status_suspended(dev
)) {
2793 /* amba did not disable the clock */
2794 amba_pclk_disable(pcdev
);
2796 amba_pclk_unprepare(pcdev
);
2801 static int __maybe_unused
pl330_resume(struct device
*dev
)
2803 struct amba_device
*pcdev
= to_amba_device(dev
);
2806 ret
= amba_pclk_prepare(pcdev
);
2810 if (!pm_runtime_status_suspended(dev
))
2811 ret
= amba_pclk_enable(pcdev
);
2813 pm_runtime_enable(dev
);
2818 static SIMPLE_DEV_PM_OPS(pl330_pm
, pl330_suspend
, pl330_resume
);
2821 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2823 struct pl330_config
*pcfg
;
2824 struct pl330_dmac
*pl330
;
2825 struct dma_pl330_chan
*pch
, *_p
;
2826 struct dma_device
*pd
;
2827 struct resource
*res
;
2830 struct device_node
*np
= adev
->dev
.of_node
;
2832 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2836 /* Allocate a new DMAC and its Channels */
2837 pl330
= devm_kzalloc(&adev
->dev
, sizeof(*pl330
), GFP_KERNEL
);
2842 pd
->dev
= &adev
->dev
;
2847 for (i
= 0; i
< ARRAY_SIZE(of_quirks
); i
++)
2848 if (of_property_read_bool(np
, of_quirks
[i
].quirk
))
2849 pl330
->quirks
|= of_quirks
[i
].id
;
2852 pl330
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2853 if (IS_ERR(pl330
->base
))
2854 return PTR_ERR(pl330
->base
);
2856 amba_set_drvdata(adev
, pl330
);
2858 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2861 ret
= devm_request_irq(&adev
->dev
, irq
,
2862 pl330_irq_handler
, 0,
2863 dev_name(&adev
->dev
), pl330
);
2871 pcfg
= &pl330
->pcfg
;
2873 pcfg
->periph_id
= adev
->periphid
;
2874 ret
= pl330_add(pl330
);
2878 INIT_LIST_HEAD(&pl330
->desc_pool
);
2879 spin_lock_init(&pl330
->pool_lock
);
2881 /* Create a descriptor pool of default size */
2882 if (!add_desc(pl330
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2883 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2885 INIT_LIST_HEAD(&pd
->channels
);
2887 /* Initialize channel parameters */
2888 num_chan
= max_t(int, pcfg
->num_peri
, pcfg
->num_chan
);
2890 pl330
->num_peripherals
= num_chan
;
2892 pl330
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2893 if (!pl330
->peripherals
) {
2898 for (i
= 0; i
< num_chan
; i
++) {
2899 pch
= &pl330
->peripherals
[i
];
2901 pch
->chan
.private = adev
->dev
.of_node
;
2902 INIT_LIST_HEAD(&pch
->submitted_list
);
2903 INIT_LIST_HEAD(&pch
->work_list
);
2904 INIT_LIST_HEAD(&pch
->completed_list
);
2905 spin_lock_init(&pch
->lock
);
2907 pch
->chan
.device
= pd
;
2910 /* Add the channel to the DMAC list */
2911 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2914 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2915 if (pcfg
->num_peri
) {
2916 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2917 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2918 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2921 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2922 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2923 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2924 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2925 pd
->device_tx_status
= pl330_tx_status
;
2926 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2927 pd
->device_config
= pl330_config
;
2928 pd
->device_pause
= pl330_pause
;
2929 pd
->device_terminate_all
= pl330_terminate_all
;
2930 pd
->device_issue_pending
= pl330_issue_pending
;
2931 pd
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2932 pd
->dst_addr_widths
= PL330_DMA_BUSWIDTHS
;
2933 pd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2934 pd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_SEGMENT
;
2935 pd
->max_burst
= ((pl330
->quirks
& PL330_QUIRK_BROKEN_NO_FLUSHP
) ?
2936 1 : PL330_MAX_BURST
);
2938 ret
= dma_async_device_register(pd
);
2940 dev_err(&adev
->dev
, "unable to register DMAC\n");
2944 if (adev
->dev
.of_node
) {
2945 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2946 of_dma_pl330_xlate
, pl330
);
2949 "unable to register DMA to the generic DT DMA helpers\n");
2953 adev
->dev
.dma_parms
= &pl330
->dma_parms
;
2956 * This is the limit for transfers with a buswidth of 1, larger
2957 * buswidths will have larger limits.
2959 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2961 dev_err(&adev
->dev
, "unable to set the seg size\n");
2964 dev_info(&adev
->dev
,
2965 "Loaded driver for PL330 DMAC-%x\n", adev
->periphid
);
2966 dev_info(&adev
->dev
,
2967 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2968 pcfg
->data_buf_dep
, pcfg
->data_bus_width
/ 8, pcfg
->num_chan
,
2969 pcfg
->num_peri
, pcfg
->num_events
);
2971 pm_runtime_irq_safe(&adev
->dev
);
2972 pm_runtime_use_autosuspend(&adev
->dev
);
2973 pm_runtime_set_autosuspend_delay(&adev
->dev
, PL330_AUTOSUSPEND_DELAY
);
2974 pm_runtime_mark_last_busy(&adev
->dev
);
2975 pm_runtime_put_autosuspend(&adev
->dev
);
2980 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
2983 /* Remove the channel */
2984 list_del(&pch
->chan
.device_node
);
2986 /* Flush the channel */
2988 pl330_terminate_all(&pch
->chan
);
2989 pl330_free_chan_resources(&pch
->chan
);
2998 static int pl330_remove(struct amba_device
*adev
)
3000 struct pl330_dmac
*pl330
= amba_get_drvdata(adev
);
3001 struct dma_pl330_chan
*pch
, *_p
;
3004 pm_runtime_get_noresume(pl330
->ddma
.dev
);
3006 if (adev
->dev
.of_node
)
3007 of_dma_controller_free(adev
->dev
.of_node
);
3009 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
3012 devm_free_irq(&adev
->dev
, irq
, pl330
);
3015 dma_async_device_unregister(&pl330
->ddma
);
3018 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
3021 /* Remove the channel */
3022 list_del(&pch
->chan
.device_node
);
3024 /* Flush the channel */
3026 pl330_terminate_all(&pch
->chan
);
3027 pl330_free_chan_resources(&pch
->chan
);
3036 static struct amba_id pl330_ids
[] = {
3044 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3046 static struct amba_driver pl330_driver
= {
3048 .owner
= THIS_MODULE
,
3049 .name
= "dma-pl330",
3052 .id_table
= pl330_ids
,
3053 .probe
= pl330_probe
,
3054 .remove
= pl330_remove
,
3057 module_amba_driver(pl330_driver
);
3059 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3060 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3061 MODULE_LICENSE("GPL");