2 * Renesas SuperH DMA Engine support
4 * base is drivers/dma/flsdma.c
6 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
9 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * - DMA of SuperH does not have Hardware DMA chain mode.
17 * - MAX DMA size is 16MB.
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/dmaengine.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30 #include <linux/notifier.h>
31 #include <linux/kdebug.h>
32 #include <linux/spinlock.h>
33 #include <linux/rculist.h>
35 #include "../dmaengine.h"
38 #define SH_DMAE_DRV_NAME "sh-dma-engine"
40 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
41 #define LOG2_DEFAULT_XFER_SIZE 2
42 #define SH_DMA_SLAVE_NUMBER 256
43 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
46 * Used for write-side mutual exclusion for the global device list,
47 * read-side synchronization by way of RCU, and per-controller data.
49 static DEFINE_SPINLOCK(sh_dmae_lock
);
50 static LIST_HEAD(sh_dmae_devices
);
52 static void chclr_write(struct sh_dmae_chan
*sh_dc
, u32 data
)
54 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
56 __raw_writel(data
, shdev
->chan_reg
+
57 shdev
->pdata
->channel
[sh_dc
->shdma_chan
.id
].chclr_offset
);
60 static void sh_dmae_writel(struct sh_dmae_chan
*sh_dc
, u32 data
, u32 reg
)
62 __raw_writel(data
, sh_dc
->base
+ reg
/ sizeof(u32
));
65 static u32
sh_dmae_readl(struct sh_dmae_chan
*sh_dc
, u32 reg
)
67 return __raw_readl(sh_dc
->base
+ reg
/ sizeof(u32
));
70 static u16
dmaor_read(struct sh_dmae_device
*shdev
)
72 u32 __iomem
*addr
= shdev
->chan_reg
+ DMAOR
/ sizeof(u32
);
74 if (shdev
->pdata
->dmaor_is_32bit
)
75 return __raw_readl(addr
);
77 return __raw_readw(addr
);
80 static void dmaor_write(struct sh_dmae_device
*shdev
, u16 data
)
82 u32 __iomem
*addr
= shdev
->chan_reg
+ DMAOR
/ sizeof(u32
);
84 if (shdev
->pdata
->dmaor_is_32bit
)
85 __raw_writel(data
, addr
);
87 __raw_writew(data
, addr
);
90 static void chcr_write(struct sh_dmae_chan
*sh_dc
, u32 data
)
92 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
94 __raw_writel(data
, sh_dc
->base
+ shdev
->chcr_offset
/ sizeof(u32
));
97 static u32
chcr_read(struct sh_dmae_chan
*sh_dc
)
99 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
101 return __raw_readl(sh_dc
->base
+ shdev
->chcr_offset
/ sizeof(u32
));
105 * Reset DMA controller
107 * SH7780 has two DMAOR register
109 static void sh_dmae_ctl_stop(struct sh_dmae_device
*shdev
)
111 unsigned short dmaor
;
114 spin_lock_irqsave(&sh_dmae_lock
, flags
);
116 dmaor
= dmaor_read(shdev
);
117 dmaor_write(shdev
, dmaor
& ~(DMAOR_NMIF
| DMAOR_AE
| DMAOR_DME
));
119 spin_unlock_irqrestore(&sh_dmae_lock
, flags
);
122 static int sh_dmae_rst(struct sh_dmae_device
*shdev
)
124 unsigned short dmaor
;
127 spin_lock_irqsave(&sh_dmae_lock
, flags
);
129 dmaor
= dmaor_read(shdev
) & ~(DMAOR_NMIF
| DMAOR_AE
| DMAOR_DME
);
131 if (shdev
->pdata
->chclr_present
) {
133 for (i
= 0; i
< shdev
->pdata
->channel_num
; i
++) {
134 struct sh_dmae_chan
*sh_chan
= shdev
->chan
[i
];
136 chclr_write(sh_chan
, 0);
140 dmaor_write(shdev
, dmaor
| shdev
->pdata
->dmaor_init
);
142 dmaor
= dmaor_read(shdev
);
144 spin_unlock_irqrestore(&sh_dmae_lock
, flags
);
146 if (dmaor
& (DMAOR_AE
| DMAOR_NMIF
)) {
147 dev_warn(shdev
->shdma_dev
.dma_dev
.dev
, "Can't initialize DMAOR.\n");
150 if (shdev
->pdata
->dmaor_init
& ~dmaor
)
151 dev_warn(shdev
->shdma_dev
.dma_dev
.dev
,
152 "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
153 dmaor
, shdev
->pdata
->dmaor_init
);
157 static bool dmae_is_busy(struct sh_dmae_chan
*sh_chan
)
159 u32 chcr
= chcr_read(sh_chan
);
161 if ((chcr
& (CHCR_DE
| CHCR_TE
)) == CHCR_DE
)
162 return true; /* working */
164 return false; /* waiting */
167 static unsigned int calc_xmit_shift(struct sh_dmae_chan
*sh_chan
, u32 chcr
)
169 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
170 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
171 int cnt
= ((chcr
& pdata
->ts_low_mask
) >> pdata
->ts_low_shift
) |
172 ((chcr
& pdata
->ts_high_mask
) >> pdata
->ts_high_shift
);
174 if (cnt
>= pdata
->ts_shift_num
)
177 return pdata
->ts_shift
[cnt
];
180 static u32
log2size_to_chcr(struct sh_dmae_chan
*sh_chan
, int l2size
)
182 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
183 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
186 for (i
= 0; i
< pdata
->ts_shift_num
; i
++)
187 if (pdata
->ts_shift
[i
] == l2size
)
190 if (i
== pdata
->ts_shift_num
)
193 return ((i
<< pdata
->ts_low_shift
) & pdata
->ts_low_mask
) |
194 ((i
<< pdata
->ts_high_shift
) & pdata
->ts_high_mask
);
197 static void dmae_set_reg(struct sh_dmae_chan
*sh_chan
, struct sh_dmae_regs
*hw
)
199 sh_dmae_writel(sh_chan
, hw
->sar
, SAR
);
200 sh_dmae_writel(sh_chan
, hw
->dar
, DAR
);
201 sh_dmae_writel(sh_chan
, hw
->tcr
>> sh_chan
->xmit_shift
, TCR
);
204 static void dmae_start(struct sh_dmae_chan
*sh_chan
)
206 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
207 u32 chcr
= chcr_read(sh_chan
);
209 if (shdev
->pdata
->needs_tend_set
)
210 sh_dmae_writel(sh_chan
, 0xFFFFFFFF, TEND
);
212 chcr
|= CHCR_DE
| shdev
->chcr_ie_bit
;
213 chcr_write(sh_chan
, chcr
& ~CHCR_TE
);
216 static void dmae_init(struct sh_dmae_chan
*sh_chan
)
219 * Default configuration for dual address memory-memory transfer.
220 * 0x400 represents auto-request.
222 u32 chcr
= DM_INC
| SM_INC
| 0x400 | log2size_to_chcr(sh_chan
,
223 LOG2_DEFAULT_XFER_SIZE
);
224 sh_chan
->xmit_shift
= calc_xmit_shift(sh_chan
, chcr
);
225 chcr_write(sh_chan
, chcr
);
228 static int dmae_set_chcr(struct sh_dmae_chan
*sh_chan
, u32 val
)
230 /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
231 if (dmae_is_busy(sh_chan
))
234 sh_chan
->xmit_shift
= calc_xmit_shift(sh_chan
, val
);
235 chcr_write(sh_chan
, val
);
240 static int dmae_set_dmars(struct sh_dmae_chan
*sh_chan
, u16 val
)
242 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
243 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
244 const struct sh_dmae_channel
*chan_pdata
= &pdata
->channel
[sh_chan
->shdma_chan
.id
];
245 u16 __iomem
*addr
= shdev
->dmars
;
246 unsigned int shift
= chan_pdata
->dmars_bit
;
248 if (dmae_is_busy(sh_chan
))
254 /* in the case of a missing DMARS resource use first memory window */
256 addr
= (u16 __iomem
*)shdev
->chan_reg
;
257 addr
+= chan_pdata
->dmars
/ sizeof(u16
);
259 __raw_writew((__raw_readw(addr
) & (0xff00 >> shift
)) | (val
<< shift
),
265 static void sh_dmae_start_xfer(struct shdma_chan
*schan
,
266 struct shdma_desc
*sdesc
)
268 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
270 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
271 struct sh_dmae_desc
, shdma_desc
);
272 dev_dbg(sh_chan
->shdma_chan
.dev
, "Queue #%d to %d: %u@%x -> %x\n",
273 sdesc
->async_tx
.cookie
, sh_chan
->shdma_chan
.id
,
274 sh_desc
->hw
.tcr
, sh_desc
->hw
.sar
, sh_desc
->hw
.dar
);
275 /* Get the ld start address from ld_queue */
276 dmae_set_reg(sh_chan
, &sh_desc
->hw
);
280 static bool sh_dmae_channel_busy(struct shdma_chan
*schan
)
282 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
284 return dmae_is_busy(sh_chan
);
287 static void sh_dmae_setup_xfer(struct shdma_chan
*schan
,
290 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
294 const struct sh_dmae_slave_config
*cfg
=
297 dmae_set_dmars(sh_chan
, cfg
->mid_rid
);
298 dmae_set_chcr(sh_chan
, cfg
->chcr
);
305 * Find a slave channel configuration from the contoller list by either a slave
306 * ID in the non-DT case, or by a MID/RID value in the DT case
308 static const struct sh_dmae_slave_config
*dmae_find_slave(
309 struct sh_dmae_chan
*sh_chan
, int match
)
311 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
312 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
313 const struct sh_dmae_slave_config
*cfg
;
316 if (!sh_chan
->shdma_chan
.dev
->of_node
) {
317 if (match
>= SH_DMA_SLAVE_NUMBER
)
320 for (i
= 0, cfg
= pdata
->slave
; i
< pdata
->slave_num
; i
++, cfg
++)
321 if (cfg
->slave_id
== match
)
324 for (i
= 0, cfg
= pdata
->slave
; i
< pdata
->slave_num
; i
++, cfg
++)
325 if (cfg
->mid_rid
== match
) {
326 sh_chan
->shdma_chan
.slave_id
= cfg
->slave_id
;
334 static int sh_dmae_set_slave(struct shdma_chan
*schan
,
335 int slave_id
, bool try)
337 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
339 const struct sh_dmae_slave_config
*cfg
= dmae_find_slave(sh_chan
, slave_id
);
344 sh_chan
->config
= cfg
;
349 static void dmae_halt(struct sh_dmae_chan
*sh_chan
)
351 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
352 u32 chcr
= chcr_read(sh_chan
);
354 chcr
&= ~(CHCR_DE
| CHCR_TE
| shdev
->chcr_ie_bit
);
355 chcr_write(sh_chan
, chcr
);
358 static int sh_dmae_desc_setup(struct shdma_chan
*schan
,
359 struct shdma_desc
*sdesc
,
360 dma_addr_t src
, dma_addr_t dst
, size_t *len
)
362 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
363 struct sh_dmae_desc
, shdma_desc
);
365 if (*len
> schan
->max_xfer_len
)
366 *len
= schan
->max_xfer_len
;
368 sh_desc
->hw
.sar
= src
;
369 sh_desc
->hw
.dar
= dst
;
370 sh_desc
->hw
.tcr
= *len
;
375 static void sh_dmae_halt(struct shdma_chan
*schan
)
377 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
382 static bool sh_dmae_chan_irq(struct shdma_chan
*schan
, int irq
)
384 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
387 if (!(chcr_read(sh_chan
) & CHCR_TE
))
396 static size_t sh_dmae_get_partial(struct shdma_chan
*schan
,
397 struct shdma_desc
*sdesc
)
399 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
401 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
402 struct sh_dmae_desc
, shdma_desc
);
403 return sh_desc
->hw
.tcr
-
404 (sh_dmae_readl(sh_chan
, TCR
) << sh_chan
->xmit_shift
);
407 /* Called from error IRQ or NMI */
408 static bool sh_dmae_reset(struct sh_dmae_device
*shdev
)
412 /* halt the dma controller */
413 sh_dmae_ctl_stop(shdev
);
415 /* We cannot detect, which channel caused the error, have to reset all */
416 ret
= shdma_reset(&shdev
->shdma_dev
);
423 static irqreturn_t
sh_dmae_err(int irq
, void *data
)
425 struct sh_dmae_device
*shdev
= data
;
427 if (!(dmaor_read(shdev
) & DMAOR_AE
))
430 sh_dmae_reset(shdev
);
434 static bool sh_dmae_desc_completed(struct shdma_chan
*schan
,
435 struct shdma_desc
*sdesc
)
437 struct sh_dmae_chan
*sh_chan
= container_of(schan
,
438 struct sh_dmae_chan
, shdma_chan
);
439 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
440 struct sh_dmae_desc
, shdma_desc
);
441 u32 sar_buf
= sh_dmae_readl(sh_chan
, SAR
);
442 u32 dar_buf
= sh_dmae_readl(sh_chan
, DAR
);
444 return (sdesc
->direction
== DMA_DEV_TO_MEM
&&
445 (sh_desc
->hw
.dar
+ sh_desc
->hw
.tcr
) == dar_buf
) ||
446 (sdesc
->direction
!= DMA_DEV_TO_MEM
&&
447 (sh_desc
->hw
.sar
+ sh_desc
->hw
.tcr
) == sar_buf
);
450 static bool sh_dmae_nmi_notify(struct sh_dmae_device
*shdev
)
452 /* Fast path out if NMIF is not asserted for this controller */
453 if ((dmaor_read(shdev
) & DMAOR_NMIF
) == 0)
456 return sh_dmae_reset(shdev
);
459 static int sh_dmae_nmi_handler(struct notifier_block
*self
,
460 unsigned long cmd
, void *data
)
462 struct sh_dmae_device
*shdev
;
463 int ret
= NOTIFY_DONE
;
467 * Only concern ourselves with NMI events.
469 * Normally we would check the die chain value, but as this needs
470 * to be architecture independent, check for NMI context instead.
476 list_for_each_entry_rcu(shdev
, &sh_dmae_devices
, node
) {
478 * Only stop if one of the controllers has NMIF asserted,
479 * we do not want to interfere with regular address error
480 * handling or NMI events that don't concern the DMACs.
482 triggered
= sh_dmae_nmi_notify(shdev
);
483 if (triggered
== true)
491 static struct notifier_block sh_dmae_nmi_notifier __read_mostly
= {
492 .notifier_call
= sh_dmae_nmi_handler
,
494 /* Run before NMI debug handler and KGDB */
498 static int sh_dmae_chan_probe(struct sh_dmae_device
*shdev
, int id
,
499 int irq
, unsigned long flags
)
501 const struct sh_dmae_channel
*chan_pdata
= &shdev
->pdata
->channel
[id
];
502 struct shdma_dev
*sdev
= &shdev
->shdma_dev
;
503 struct platform_device
*pdev
= to_platform_device(sdev
->dma_dev
.dev
);
504 struct sh_dmae_chan
*sh_chan
;
505 struct shdma_chan
*schan
;
508 sh_chan
= kzalloc(sizeof(struct sh_dmae_chan
), GFP_KERNEL
);
510 dev_err(sdev
->dma_dev
.dev
,
511 "No free memory for allocating dma channels!\n");
515 schan
= &sh_chan
->shdma_chan
;
516 schan
->max_xfer_len
= SH_DMA_TCR_MAX
+ 1;
518 shdma_chan_probe(sdev
, schan
, id
);
520 sh_chan
->base
= shdev
->chan_reg
+ chan_pdata
->offset
/ sizeof(u32
);
522 /* set up channel irq */
524 snprintf(sh_chan
->dev_id
, sizeof(sh_chan
->dev_id
),
525 "sh-dmae%d.%d", pdev
->id
, id
);
527 snprintf(sh_chan
->dev_id
, sizeof(sh_chan
->dev_id
),
530 err
= shdma_request_irq(schan
, irq
, flags
, sh_chan
->dev_id
);
532 dev_err(sdev
->dma_dev
.dev
,
533 "DMA channel %d request_irq error %d\n",
538 shdev
->chan
[id
] = sh_chan
;
542 /* remove from dmaengine device node */
543 shdma_chan_remove(schan
);
548 static void sh_dmae_chan_remove(struct sh_dmae_device
*shdev
)
550 struct dma_device
*dma_dev
= &shdev
->shdma_dev
.dma_dev
;
551 struct shdma_chan
*schan
;
554 shdma_for_each_chan(schan
, &shdev
->shdma_dev
, i
) {
555 struct sh_dmae_chan
*sh_chan
= container_of(schan
,
556 struct sh_dmae_chan
, shdma_chan
);
559 shdma_free_irq(&sh_chan
->shdma_chan
);
561 shdma_chan_remove(schan
);
564 dma_dev
->chancnt
= 0;
567 static void sh_dmae_shutdown(struct platform_device
*pdev
)
569 struct sh_dmae_device
*shdev
= platform_get_drvdata(pdev
);
570 sh_dmae_ctl_stop(shdev
);
573 static int sh_dmae_runtime_suspend(struct device
*dev
)
578 static int sh_dmae_runtime_resume(struct device
*dev
)
580 struct sh_dmae_device
*shdev
= dev_get_drvdata(dev
);
582 return sh_dmae_rst(shdev
);
586 static int sh_dmae_suspend(struct device
*dev
)
591 static int sh_dmae_resume(struct device
*dev
)
593 struct sh_dmae_device
*shdev
= dev_get_drvdata(dev
);
596 ret
= sh_dmae_rst(shdev
);
598 dev_err(dev
, "Failed to reset!\n");
600 for (i
= 0; i
< shdev
->pdata
->channel_num
; i
++) {
601 struct sh_dmae_chan
*sh_chan
= shdev
->chan
[i
];
603 if (!sh_chan
->shdma_chan
.desc_num
)
606 if (sh_chan
->shdma_chan
.slave_id
>= 0) {
607 const struct sh_dmae_slave_config
*cfg
= sh_chan
->config
;
608 dmae_set_dmars(sh_chan
, cfg
->mid_rid
);
609 dmae_set_chcr(sh_chan
, cfg
->chcr
);
618 #define sh_dmae_suspend NULL
619 #define sh_dmae_resume NULL
622 const struct dev_pm_ops sh_dmae_pm
= {
623 .suspend
= sh_dmae_suspend
,
624 .resume
= sh_dmae_resume
,
625 .runtime_suspend
= sh_dmae_runtime_suspend
,
626 .runtime_resume
= sh_dmae_runtime_resume
,
629 static dma_addr_t
sh_dmae_slave_addr(struct shdma_chan
*schan
)
631 struct sh_dmae_chan
*sh_chan
= container_of(schan
,
632 struct sh_dmae_chan
, shdma_chan
);
635 * Implicit BUG_ON(!sh_chan->config)
636 * This is an exclusive slave DMA operation, may only be called after a
637 * successful slave configuration.
639 return sh_chan
->config
->addr
;
642 static struct shdma_desc
*sh_dmae_embedded_desc(void *buf
, int i
)
644 return &((struct sh_dmae_desc
*)buf
)[i
].shdma_desc
;
647 static const struct shdma_ops sh_dmae_shdma_ops
= {
648 .desc_completed
= sh_dmae_desc_completed
,
649 .halt_channel
= sh_dmae_halt
,
650 .channel_busy
= sh_dmae_channel_busy
,
651 .slave_addr
= sh_dmae_slave_addr
,
652 .desc_setup
= sh_dmae_desc_setup
,
653 .set_slave
= sh_dmae_set_slave
,
654 .setup_xfer
= sh_dmae_setup_xfer
,
655 .start_xfer
= sh_dmae_start_xfer
,
656 .embedded_desc
= sh_dmae_embedded_desc
,
657 .chan_irq
= sh_dmae_chan_irq
,
658 .get_partial
= sh_dmae_get_partial
,
661 static int sh_dmae_probe(struct platform_device
*pdev
)
663 struct sh_dmae_pdata
*pdata
= pdev
->dev
.platform_data
;
664 unsigned long irqflags
= IRQF_DISABLED
,
665 chan_flag
[SH_DMAE_MAX_CHANNELS
] = {};
666 int errirq
, chan_irq
[SH_DMAE_MAX_CHANNELS
];
667 int err
, i
, irq_cnt
= 0, irqres
= 0, irq_cap
= 0;
668 struct sh_dmae_device
*shdev
;
669 struct dma_device
*dma_dev
;
670 struct resource
*chan
, *dmars
, *errirq_res
, *chanirq_res
;
672 /* get platform data */
673 if (!pdata
|| !pdata
->channel_num
)
676 chan
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
677 /* DMARS area is optional */
678 dmars
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
681 * 1. there always must be at least one IRQ IO-resource. On SH4 it is
682 * the error IRQ, in which case it is the only IRQ in this resource:
683 * start == end. If it is the only IRQ resource, all channels also
685 * 2. DMA channel IRQ resources can be specified one per resource or in
686 * ranges (start != end)
687 * 3. iff all events (channels and, optionally, error) on this
688 * controller use the same IRQ, only one IRQ resource can be
689 * specified, otherwise there must be one IRQ per channel, even if
690 * some of them are equal
691 * 4. if all IRQs on this controller are equal or if some specific IRQs
692 * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
693 * requested with the IRQF_SHARED flag
695 errirq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
696 if (!chan
|| !errirq_res
)
699 if (!request_mem_region(chan
->start
, resource_size(chan
), pdev
->name
)) {
700 dev_err(&pdev
->dev
, "DMAC register region already claimed\n");
704 if (dmars
&& !request_mem_region(dmars
->start
, resource_size(dmars
), pdev
->name
)) {
705 dev_err(&pdev
->dev
, "DMAC DMARS region already claimed\n");
711 shdev
= kzalloc(sizeof(struct sh_dmae_device
), GFP_KERNEL
);
713 dev_err(&pdev
->dev
, "Not enough memory\n");
717 dma_dev
= &shdev
->shdma_dev
.dma_dev
;
719 shdev
->chan_reg
= ioremap(chan
->start
, resource_size(chan
));
720 if (!shdev
->chan_reg
)
723 shdev
->dmars
= ioremap(dmars
->start
, resource_size(dmars
));
728 if (!pdata
->slave_only
)
729 dma_cap_set(DMA_MEMCPY
, dma_dev
->cap_mask
);
730 if (pdata
->slave
&& pdata
->slave_num
)
731 dma_cap_set(DMA_SLAVE
, dma_dev
->cap_mask
);
733 /* Default transfer size of 32 bytes requires 32-byte alignment */
734 dma_dev
->copy_align
= LOG2_DEFAULT_XFER_SIZE
;
736 shdev
->shdma_dev
.ops
= &sh_dmae_shdma_ops
;
737 shdev
->shdma_dev
.desc_size
= sizeof(struct sh_dmae_desc
);
738 err
= shdma_init(&pdev
->dev
, &shdev
->shdma_dev
,
744 shdev
->pdata
= pdata
;
746 if (pdata
->chcr_offset
)
747 shdev
->chcr_offset
= pdata
->chcr_offset
;
749 shdev
->chcr_offset
= CHCR
;
751 if (pdata
->chcr_ie_bit
)
752 shdev
->chcr_ie_bit
= pdata
->chcr_ie_bit
;
754 shdev
->chcr_ie_bit
= CHCR_IE
;
756 platform_set_drvdata(pdev
, shdev
);
758 pm_runtime_enable(&pdev
->dev
);
759 err
= pm_runtime_get_sync(&pdev
->dev
);
761 dev_err(&pdev
->dev
, "%s(): GET = %d\n", __func__
, err
);
763 spin_lock_irq(&sh_dmae_lock
);
764 list_add_tail_rcu(&shdev
->node
, &sh_dmae_devices
);
765 spin_unlock_irq(&sh_dmae_lock
);
767 /* reset dma controller - only needed as a test */
768 err
= sh_dmae_rst(shdev
);
772 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
773 chanirq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 1);
776 chanirq_res
= errirq_res
;
780 if (chanirq_res
== errirq_res
||
781 (errirq_res
->flags
& IORESOURCE_BITS
) == IORESOURCE_IRQ_SHAREABLE
)
782 irqflags
= IRQF_SHARED
;
784 errirq
= errirq_res
->start
;
786 err
= request_irq(errirq
, sh_dmae_err
, irqflags
,
787 "DMAC Address Error", shdev
);
790 "DMA failed requesting irq #%d, error %d\n",
796 chanirq_res
= errirq_res
;
797 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
799 if (chanirq_res
->start
== chanirq_res
->end
&&
800 !platform_get_resource(pdev
, IORESOURCE_IRQ
, 1)) {
801 /* Special case - all multiplexed */
802 for (; irq_cnt
< pdata
->channel_num
; irq_cnt
++) {
803 if (irq_cnt
< SH_DMAE_MAX_CHANNELS
) {
804 chan_irq
[irq_cnt
] = chanirq_res
->start
;
805 chan_flag
[irq_cnt
] = IRQF_SHARED
;
813 for (i
= chanirq_res
->start
; i
<= chanirq_res
->end
; i
++) {
814 if (irq_cnt
>= SH_DMAE_MAX_CHANNELS
) {
819 if ((errirq_res
->flags
& IORESOURCE_BITS
) ==
820 IORESOURCE_IRQ_SHAREABLE
)
821 chan_flag
[irq_cnt
] = IRQF_SHARED
;
823 chan_flag
[irq_cnt
] = IRQF_DISABLED
;
825 "Found IRQ %d for channel %d\n",
827 chan_irq
[irq_cnt
++] = i
;
830 if (irq_cnt
>= SH_DMAE_MAX_CHANNELS
)
833 chanirq_res
= platform_get_resource(pdev
,
834 IORESOURCE_IRQ
, ++irqres
);
835 } while (irq_cnt
< pdata
->channel_num
&& chanirq_res
);
838 /* Create DMA Channel */
839 for (i
= 0; i
< irq_cnt
; i
++) {
840 err
= sh_dmae_chan_probe(shdev
, i
, chan_irq
[i
], chan_flag
[i
]);
846 dev_notice(&pdev
->dev
, "Attempting to register %d DMA "
847 "channels when a maximum of %d are supported.\n",
848 pdata
->channel_num
, SH_DMAE_MAX_CHANNELS
);
850 pm_runtime_put(&pdev
->dev
);
852 err
= dma_async_device_register(&shdev
->shdma_dev
.dma_dev
);
859 pm_runtime_get(&pdev
->dev
);
862 sh_dmae_chan_remove(shdev
);
864 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
865 free_irq(errirq
, shdev
);
869 spin_lock_irq(&sh_dmae_lock
);
870 list_del_rcu(&shdev
->node
);
871 spin_unlock_irq(&sh_dmae_lock
);
873 pm_runtime_put(&pdev
->dev
);
874 pm_runtime_disable(&pdev
->dev
);
876 platform_set_drvdata(pdev
, NULL
);
877 shdma_cleanup(&shdev
->shdma_dev
);
880 iounmap(shdev
->dmars
);
882 iounmap(shdev
->chan_reg
);
888 release_mem_region(dmars
->start
, resource_size(dmars
));
890 release_mem_region(chan
->start
, resource_size(chan
));
895 static int sh_dmae_remove(struct platform_device
*pdev
)
897 struct sh_dmae_device
*shdev
= platform_get_drvdata(pdev
);
898 struct dma_device
*dma_dev
= &shdev
->shdma_dev
.dma_dev
;
899 struct resource
*res
;
900 int errirq
= platform_get_irq(pdev
, 0);
902 dma_async_device_unregister(dma_dev
);
905 free_irq(errirq
, shdev
);
907 spin_lock_irq(&sh_dmae_lock
);
908 list_del_rcu(&shdev
->node
);
909 spin_unlock_irq(&sh_dmae_lock
);
911 pm_runtime_disable(&pdev
->dev
);
913 sh_dmae_chan_remove(shdev
);
914 shdma_cleanup(&shdev
->shdma_dev
);
917 iounmap(shdev
->dmars
);
918 iounmap(shdev
->chan_reg
);
920 platform_set_drvdata(pdev
, NULL
);
925 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
927 release_mem_region(res
->start
, resource_size(res
));
928 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
930 release_mem_region(res
->start
, resource_size(res
));
935 static const struct of_device_id sh_dmae_of_match
[] = {
936 { .compatible
= "renesas,shdma", },
939 MODULE_DEVICE_TABLE(of
, sh_dmae_of_match
);
941 static struct platform_driver sh_dmae_driver
= {
943 .owner
= THIS_MODULE
,
945 .name
= SH_DMAE_DRV_NAME
,
946 .of_match_table
= sh_dmae_of_match
,
948 .remove
= sh_dmae_remove
,
949 .shutdown
= sh_dmae_shutdown
,
952 static int __init
sh_dmae_init(void)
954 /* Wire up NMI handling */
955 int err
= register_die_notifier(&sh_dmae_nmi_notifier
);
959 return platform_driver_probe(&sh_dmae_driver
, sh_dmae_probe
);
961 module_init(sh_dmae_init
);
963 static void __exit
sh_dmae_exit(void)
965 platform_driver_unregister(&sh_dmae_driver
);
967 unregister_die_notifier(&sh_dmae_nmi_notifier
);
969 module_exit(sh_dmae_exit
);
971 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
972 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
973 MODULE_LICENSE("GPL");
974 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME
);