2 * driver/dma/ste_dma40.c
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <plat/ste_dma40.h>
20 #include "ste_dma40_ll.h"
22 #define D40_NAME "dma40"
24 #define D40_PHY_CHAN -1
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan) (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
33 /* Hardware requirement on LCLA alignment */
34 #define LCLA_ALIGNMENT 0x40000
35 /* Attempts before giving up to trying to get pages that are aligned */
36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
38 /* Bit markings for allocation map */
39 #define D40_ALLOC_FREE (1 << 31)
40 #define D40_ALLOC_PHY (1 << 30)
41 #define D40_ALLOC_LOG_FREE 0
43 /* Hardware designer of the block */
44 #define D40_PERIPHID2_DESIGNER 0x8
47 * enum 40_command - The different commands and/or statuses.
49 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
50 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
51 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
52 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 D40_DMA_SUSPEND_REQ
= 2,
62 * struct d40_lli_pool - Structure for keeping LLIs in memory
64 * @base: Pointer to memory area when the pre_alloc_lli's are not large
65 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
66 * pre_alloc_lli is used.
67 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
68 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
69 * one buffer to one buffer.
74 /* Space for dst and src, plus an extra for padding */
75 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
79 * struct d40_desc - A descriptor is one DMA job.
81 * @lli_phy: LLI settings for physical channel. Both src and dst=
82 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
84 * @lli_log: Same as above but for logical channels.
85 * @lli_pool: The pool with two entries pre-allocated.
86 * @lli_len: Number of llis of current descriptor.
87 * @lli_count: Number of transfered llis.
88 * @lli_tx_len: Max number of LLIs per transfer, there can be
89 * many transfer for one descriptor.
90 * @txd: DMA engine struct. Used for among other things for communication
93 * @dir: The transfer direction of this job.
94 * @is_in_client_list: true if the client owns this descriptor.
96 * This descriptor is used for both logical and physical transfers.
101 struct d40_phy_lli_bidir lli_phy
;
103 struct d40_log_lli_bidir lli_log
;
105 struct d40_lli_pool lli_pool
;
110 struct dma_async_tx_descriptor txd
;
111 struct list_head node
;
113 enum dma_data_direction dir
;
114 bool is_in_client_list
;
118 * struct d40_lcla_pool - LCLA pool settings and data.
120 * @base: The virtual address of LCLA. 18 bit aligned.
121 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
122 * This pointer is only there for clean-up on error.
123 * @pages: The number of pages needed for all physical channels.
124 * Only used later for clean-up on error
125 * @lock: Lock to protect the content in this struct.
126 * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
127 * @num_blocks: The number of entries of alloc_map. Equals to the
128 * number of physical channels.
130 struct d40_lcla_pool
{
132 void *base_unaligned
;
140 * struct d40_phy_res - struct for handling eventlines mapped to physical
143 * @lock: A lock protection this entity.
144 * @num: The physical channel number of this entity.
145 * @allocated_src: Bit mapped to show which src event line's are mapped to
146 * this physical channel. Can also be free or physically allocated.
147 * @allocated_dst: Same as for src but is dst.
148 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
149 * event line number. Both allocated_src and allocated_dst can not be
150 * allocated to a physical channel, since the interrupt handler has then
151 * no way of figure out which one the interrupt belongs to.
163 * struct d40_chan - Struct that describes a channel.
165 * @lock: A spinlock to protect this struct.
166 * @log_num: The logical number, if any of this channel.
167 * @completed: Starts with 1, after first interrupt it is set to dma engine's
169 * @pending_tx: The number of pending transfers. Used between interrupt handler
171 * @busy: Set to true when transfer is ongoing on this channel.
172 * @phy_chan: Pointer to physical channel which this instance runs on. If this
173 * point is NULL, then the channel is not allocated.
174 * @chan: DMA engine handle.
175 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176 * transfer and call client callback.
177 * @client: Cliented owned descriptor list.
178 * @active: Active descriptor.
179 * @queue: Queued jobs.
180 * @dma_cfg: The client configuration of this dma channel.
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res
*phy_chan
;
198 struct dma_chan chan
;
199 struct tasklet_struct tasklet
;
200 struct list_head client
;
201 struct list_head active
;
202 struct list_head queue
;
203 struct stedma40_chan_cfg dma_cfg
;
204 struct d40_base
*base
;
205 /* Default register configurations */
208 struct d40_def_lcsp log_def
;
209 struct d40_lcla_elem lcla
;
210 struct d40_log_lli_full
*lcpa
;
211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr
;
213 enum dma_data_direction runtime_direction
;
217 * struct d40_base - The big global struct, one for each probe'd instance.
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
224 * @rev: silicon revision detected.
225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237 * @phy_chans: Room for all possible physical channels in system.
238 * @log_chans: Room for all possible logical channels in system.
239 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
240 * to log_chans entries.
241 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
242 * to phy_chans entries.
243 * @plat_data: Pointer to provided platform_data which is the driver
245 * @phy_res: Vector containing all physical channels.
246 * @lcla_pool: lcla pool settings and data.
247 * @lcpa_base: The virtual mapped address of LCPA.
248 * @phy_lcpa: The physical address of the LCPA.
249 * @lcpa_size: The size of the LCPA area.
250 * @desc_slab: cache for descriptors.
253 spinlock_t interrupt_lock
;
254 spinlock_t execmd_lock
;
256 void __iomem
*virtbase
;
259 phys_addr_t phy_start
;
260 resource_size_t phy_size
;
264 struct dma_device dma_both
;
265 struct dma_device dma_slave
;
266 struct dma_device dma_memcpy
;
267 struct d40_chan
*phy_chans
;
268 struct d40_chan
*log_chans
;
269 struct d40_chan
**lookup_log_chans
;
270 struct d40_chan
**lookup_phy_chans
;
271 struct stedma40_platform_data
*plat_data
;
272 /* Physical half channels */
273 struct d40_phy_res
*phy_res
;
274 struct d40_lcla_pool lcla_pool
;
277 resource_size_t lcpa_size
;
278 struct kmem_cache
*desc_slab
;
282 * struct d40_interrupt_lookup - lookup table for interrupt handler
284 * @src: Interrupt mask register.
285 * @clr: Interrupt clear register.
286 * @is_error: true if this is an error interrupt.
287 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
288 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
290 struct d40_interrupt_lookup
{
298 * struct d40_reg_val - simple lookup struct
300 * @reg: The register.
301 * @val: The value that belongs to the register in reg.
308 static int d40_pool_lli_alloc(struct d40_desc
*d40d
,
309 int lli_len
, bool is_log
)
315 align
= sizeof(struct d40_log_lli
);
317 align
= sizeof(struct d40_phy_lli
);
320 base
= d40d
->lli_pool
.pre_alloc_lli
;
321 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
322 d40d
->lli_pool
.base
= NULL
;
324 d40d
->lli_pool
.size
= ALIGN(lli_len
* 2 * align
, align
);
326 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
327 d40d
->lli_pool
.base
= base
;
329 if (d40d
->lli_pool
.base
== NULL
)
334 d40d
->lli_log
.src
= PTR_ALIGN((struct d40_log_lli
*) base
,
336 d40d
->lli_log
.dst
= PTR_ALIGN(d40d
->lli_log
.src
+ lli_len
,
339 d40d
->lli_phy
.src
= PTR_ALIGN((struct d40_phy_lli
*)base
,
341 d40d
->lli_phy
.dst
= PTR_ALIGN(d40d
->lli_phy
.src
+ lli_len
,
344 d40d
->lli_phy
.src_addr
= virt_to_phys(d40d
->lli_phy
.src
);
345 d40d
->lli_phy
.dst_addr
= virt_to_phys(d40d
->lli_phy
.dst
);
351 static void d40_pool_lli_free(struct d40_desc
*d40d
)
353 kfree(d40d
->lli_pool
.base
);
354 d40d
->lli_pool
.base
= NULL
;
355 d40d
->lli_pool
.size
= 0;
356 d40d
->lli_log
.src
= NULL
;
357 d40d
->lli_log
.dst
= NULL
;
358 d40d
->lli_phy
.src
= NULL
;
359 d40d
->lli_phy
.dst
= NULL
;
360 d40d
->lli_phy
.src_addr
= 0;
361 d40d
->lli_phy
.dst_addr
= 0;
364 static dma_cookie_t
d40_assign_cookie(struct d40_chan
*d40c
,
365 struct d40_desc
*desc
)
367 dma_cookie_t cookie
= d40c
->chan
.cookie
;
372 d40c
->chan
.cookie
= cookie
;
373 desc
->txd
.cookie
= cookie
;
378 static void d40_desc_remove(struct d40_desc
*d40d
)
380 list_del(&d40d
->node
);
383 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
388 if (!list_empty(&d40c
->client
)) {
389 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
390 if (async_tx_test_ack(&d
->txd
)) {
391 d40_pool_lli_free(d
);
396 d
= kmem_cache_alloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
398 memset(d
, 0, sizeof(struct d40_desc
));
399 INIT_LIST_HEAD(&d
->node
);
405 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
407 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
410 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
412 list_add_tail(&desc
->node
, &d40c
->active
);
415 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
419 if (list_empty(&d40c
->active
))
422 d
= list_first_entry(&d40c
->active
,
428 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
430 list_add_tail(&desc
->node
, &d40c
->queue
);
433 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
437 if (list_empty(&d40c
->queue
))
440 d
= list_first_entry(&d40c
->queue
,
446 /* Support functions for logical channels */
448 static int d40_lcla_id_get(struct d40_chan
*d40c
)
452 struct d40_log_lli
*lcla_lidx_base
=
453 d40c
->base
->lcla_pool
.base
+ d40c
->phy_chan
->num
* 1024;
455 int lli_per_log
= d40c
->base
->plat_data
->llis_per_log
;
458 if (d40c
->lcla
.src_id
>= 0 && d40c
->lcla
.dst_id
>= 0)
461 if (d40c
->base
->lcla_pool
.num_blocks
> 32)
464 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
466 for (i
= 0; i
< d40c
->base
->lcla_pool
.num_blocks
; i
++) {
467 if (!(d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &
469 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] |=
475 if (src_id
>= d40c
->base
->lcla_pool
.num_blocks
)
478 for (; i
< d40c
->base
->lcla_pool
.num_blocks
; i
++) {
479 if (!(d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &
481 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] |=
488 if (dst_id
== src_id
)
491 d40c
->lcla
.src_id
= src_id
;
492 d40c
->lcla
.dst_id
= dst_id
;
493 d40c
->lcla
.dst
= lcla_lidx_base
+ dst_id
* lli_per_log
+ 1;
494 d40c
->lcla
.src
= lcla_lidx_base
+ src_id
* lli_per_log
+ 1;
496 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
499 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
504 static int d40_channel_execute_command(struct d40_chan
*d40c
,
505 enum d40_command command
)
508 void __iomem
*active_reg
;
513 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
515 if (d40c
->phy_chan
->num
% 2 == 0)
516 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
518 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
520 if (command
== D40_DMA_SUSPEND_REQ
) {
521 status
= (readl(active_reg
) &
522 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
523 D40_CHAN_POS(d40c
->phy_chan
->num
);
525 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
529 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
530 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
533 if (command
== D40_DMA_SUSPEND_REQ
) {
535 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
536 status
= (readl(active_reg
) &
537 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
538 D40_CHAN_POS(d40c
->phy_chan
->num
);
542 * Reduce the number of bus accesses while
543 * waiting for the DMA to suspend.
547 if (status
== D40_DMA_STOP
||
548 status
== D40_DMA_SUSPENDED
)
552 if (i
== D40_SUSPEND_MAX_IT
) {
553 dev_err(&d40c
->chan
.dev
->device
,
554 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
555 __func__
, d40c
->phy_chan
->num
, d40c
->log_num
,
563 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
567 static void d40_term_all(struct d40_chan
*d40c
)
569 struct d40_desc
*d40d
;
572 /* Release active descriptors */
573 while ((d40d
= d40_first_active_get(d40c
))) {
574 d40_desc_remove(d40d
);
576 /* Return desc to free-list */
577 d40_desc_free(d40c
, d40d
);
580 /* Release queued descriptors waiting for transfer */
581 while ((d40d
= d40_first_queued(d40c
))) {
582 d40_desc_remove(d40d
);
584 /* Return desc to free-list */
585 d40_desc_free(d40c
, d40d
);
588 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
590 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &=
591 (~(0x1 << d40c
->lcla
.dst_id
));
592 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &=
593 (~(0x1 << d40c
->lcla
.src_id
));
595 d40c
->lcla
.src_id
= -1;
596 d40c
->lcla
.dst_id
= -1;
598 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
600 d40c
->pending_tx
= 0;
604 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
609 /* Notice, that disable requires the physical channel to be stopped */
611 val
= D40_ACTIVATE_EVENTLINE
;
613 val
= D40_DEACTIVATE_EVENTLINE
;
615 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
617 /* Enable event line connected to device (or memcpy) */
618 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
619 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
620 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
622 writel((val
<< D40_EVENTLINE_POS(event
)) |
623 ~D40_EVENTLINE_MASK(event
),
624 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
625 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
628 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
629 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
631 writel((val
<< D40_EVENTLINE_POS(event
)) |
632 ~D40_EVENTLINE_MASK(event
),
633 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
634 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
638 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
641 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
645 val
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
646 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
649 val
|= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
650 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
655 static void d40_config_write(struct d40_chan
*d40c
)
660 /* Odd addresses are even addresses + 4 */
661 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
662 /* Setup channel mode to logical or physical */
663 var
= ((u32
)(d40c
->log_num
!= D40_PHY_CHAN
) + 1) <<
664 D40_CHAN_POS(d40c
->phy_chan
->num
);
665 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
667 /* Setup operational mode option register */
668 var
= ((d40c
->dma_cfg
.channel_type
>> STEDMA40_INFO_CH_MODE_OPT_POS
) &
669 0x3) << D40_CHAN_POS(d40c
->phy_chan
->num
);
671 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
673 if (d40c
->log_num
!= D40_PHY_CHAN
) {
674 /* Set default config for CFG reg */
675 writel(d40c
->src_def_cfg
,
676 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
677 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
679 writel(d40c
->dst_def_cfg
,
680 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
681 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
684 /* Set LIDX for lcla */
685 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
686 D40_SREG_ELEM_LOG_LIDX_MASK
,
687 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
688 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
691 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
692 D40_SREG_ELEM_LOG_LIDX_MASK
,
693 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
694 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
700 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
702 if (d40d
->lli_phy
.dst
&& d40d
->lli_phy
.src
) {
703 d40_phy_lli_write(d40c
->base
->virtbase
,
707 } else if (d40d
->lli_log
.dst
&& d40d
->lli_log
.src
) {
708 struct d40_log_lli
*src
= d40d
->lli_log
.src
;
709 struct d40_log_lli
*dst
= d40d
->lli_log
.dst
;
712 src
+= d40d
->lli_count
;
713 dst
+= d40d
->lli_count
;
714 s
= d40_log_lli_write(d40c
->lcpa
,
715 d40c
->lcla
.src
, d40c
->lcla
.dst
,
717 d40c
->base
->plat_data
->llis_per_log
);
719 /* If s equals to zero, the job is not linked */
721 (void) dma_map_single(d40c
->base
->dev
, d40c
->lcla
.src
,
722 s
* sizeof(struct d40_log_lli
),
724 (void) dma_map_single(d40c
->base
->dev
, d40c
->lcla
.dst
,
725 s
* sizeof(struct d40_log_lli
),
729 d40d
->lli_count
+= d40d
->lli_tx_len
;
732 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
734 struct d40_chan
*d40c
= container_of(tx
->chan
,
737 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
740 spin_lock_irqsave(&d40c
->lock
, flags
);
742 tx
->cookie
= d40_assign_cookie(d40c
, d40d
);
744 d40_desc_queue(d40c
, d40d
);
746 spin_unlock_irqrestore(&d40c
->lock
, flags
);
751 static int d40_start(struct d40_chan
*d40c
)
753 if (d40c
->base
->rev
== 0) {
756 if (d40c
->log_num
!= D40_PHY_CHAN
) {
757 err
= d40_channel_execute_command(d40c
,
758 D40_DMA_SUSPEND_REQ
);
764 if (d40c
->log_num
!= D40_PHY_CHAN
)
765 d40_config_set_event(d40c
, true);
767 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
770 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
772 struct d40_desc
*d40d
;
775 /* Start queued jobs, if any */
776 d40d
= d40_first_queued(d40c
);
781 /* Remove from queue */
782 d40_desc_remove(d40d
);
784 /* Add to active queue */
785 d40_desc_submit(d40c
, d40d
);
787 /* Initiate DMA job */
788 d40_desc_load(d40c
, d40d
);
791 err
= d40_start(d40c
);
800 /* called from interrupt context */
801 static void dma_tc_handle(struct d40_chan
*d40c
)
803 struct d40_desc
*d40d
;
808 /* Get first active entry from list */
809 d40d
= d40_first_active_get(d40c
);
814 if (d40d
->lli_count
< d40d
->lli_len
) {
816 d40_desc_load(d40c
, d40d
);
818 (void) d40_start(d40c
);
822 if (d40_queue_start(d40c
) == NULL
)
826 tasklet_schedule(&d40c
->tasklet
);
830 static void dma_tasklet(unsigned long data
)
832 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
833 struct d40_desc
*d40d_fin
;
835 dma_async_tx_callback callback
;
836 void *callback_param
;
838 spin_lock_irqsave(&d40c
->lock
, flags
);
840 /* Get first active entry from list */
841 d40d_fin
= d40_first_active_get(d40c
);
843 if (d40d_fin
== NULL
)
846 d40c
->completed
= d40d_fin
->txd
.cookie
;
849 * If terminating a channel pending_tx is set to zero.
850 * This prevents any finished active jobs to return to the client.
852 if (d40c
->pending_tx
== 0) {
853 spin_unlock_irqrestore(&d40c
->lock
, flags
);
857 /* Callback to client */
858 callback
= d40d_fin
->txd
.callback
;
859 callback_param
= d40d_fin
->txd
.callback_param
;
861 if (async_tx_test_ack(&d40d_fin
->txd
)) {
862 d40_pool_lli_free(d40d_fin
);
863 d40_desc_remove(d40d_fin
);
864 /* Return desc to free-list */
865 d40_desc_free(d40c
, d40d_fin
);
867 if (!d40d_fin
->is_in_client_list
) {
868 d40_desc_remove(d40d_fin
);
869 list_add_tail(&d40d_fin
->node
, &d40c
->client
);
870 d40d_fin
->is_in_client_list
= true;
876 if (d40c
->pending_tx
)
877 tasklet_schedule(&d40c
->tasklet
);
879 spin_unlock_irqrestore(&d40c
->lock
, flags
);
881 if (callback
&& (d40d_fin
->txd
.flags
& DMA_PREP_INTERRUPT
))
882 callback(callback_param
);
887 /* Rescue manouver if receiving double interrupts */
888 if (d40c
->pending_tx
> 0)
890 spin_unlock_irqrestore(&d40c
->lock
, flags
);
893 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
895 static const struct d40_interrupt_lookup il
[] = {
896 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
897 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
898 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
899 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
900 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
901 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
902 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
903 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
904 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
905 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
909 u32 regs
[ARRAY_SIZE(il
)];
913 struct d40_chan
*d40c
;
915 struct d40_base
*base
= data
;
917 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
919 /* Read interrupt status of both logical and physical channels */
920 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
921 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
925 chan
= find_next_bit((unsigned long *)regs
,
926 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
928 /* No more set bits found? */
929 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
932 row
= chan
/ BITS_PER_LONG
;
933 idx
= chan
& (BITS_PER_LONG
- 1);
936 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
938 if (il
[row
].offset
== D40_PHY_CHAN
)
939 d40c
= base
->lookup_phy_chans
[idx
];
941 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
942 spin_lock(&d40c
->lock
);
944 if (!il
[row
].is_error
)
948 "[%s] IRQ chan: %ld offset %d idx %d\n",
949 __func__
, chan
, il
[row
].offset
, idx
);
951 spin_unlock(&d40c
->lock
);
954 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
960 static int d40_validate_conf(struct d40_chan
*d40c
,
961 struct stedma40_chan_cfg
*conf
)
964 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
965 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
966 bool is_log
= (conf
->channel_type
& STEDMA40_CHANNEL_IN_OPER_MODE
)
967 == STEDMA40_CHANNEL_IN_LOG_MODE
;
970 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid direction.\n",
975 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
976 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
977 d40c
->runtime_addr
== 0) {
979 dev_err(&d40c
->chan
.dev
->device
,
980 "[%s] Invalid TX channel address (%d)\n",
981 __func__
, conf
->dst_dev_type
);
985 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
986 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
987 d40c
->runtime_addr
== 0) {
988 dev_err(&d40c
->chan
.dev
->device
,
989 "[%s] Invalid RX channel address (%d)\n",
990 __func__
, conf
->src_dev_type
);
994 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
995 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
996 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid dst\n",
1001 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1002 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1003 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid src\n",
1008 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1009 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1010 dev_err(&d40c
->chan
.dev
->device
,
1011 "[%s] No event line\n", __func__
);
1015 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1016 (src_event_group
!= dst_event_group
)) {
1017 dev_err(&d40c
->chan
.dev
->device
,
1018 "[%s] Invalid event group\n", __func__
);
1022 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1024 * DMAC HW supports it. Will be added to this driver,
1025 * in case any dma client requires it.
1027 dev_err(&d40c
->chan
.dev
->device
,
1028 "[%s] periph to periph not supported\n",
1036 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1037 int log_event_line
, bool is_log
)
1039 unsigned long flags
;
1040 spin_lock_irqsave(&phy
->lock
, flags
);
1042 /* Physical interrupts are masked per physical full channel */
1043 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1044 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1045 phy
->allocated_dst
= D40_ALLOC_PHY
;
1046 phy
->allocated_src
= D40_ALLOC_PHY
;
1052 /* Logical channel */
1054 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1057 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1058 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1060 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1061 phy
->allocated_src
|= 1 << log_event_line
;
1066 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1069 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1070 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1072 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1073 phy
->allocated_dst
|= 1 << log_event_line
;
1080 spin_unlock_irqrestore(&phy
->lock
, flags
);
1083 spin_unlock_irqrestore(&phy
->lock
, flags
);
1087 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1090 unsigned long flags
;
1091 bool is_free
= false;
1093 spin_lock_irqsave(&phy
->lock
, flags
);
1094 if (!log_event_line
) {
1095 /* Physical interrupts are masked per physical full channel */
1096 phy
->allocated_dst
= D40_ALLOC_FREE
;
1097 phy
->allocated_src
= D40_ALLOC_FREE
;
1102 /* Logical channel */
1104 phy
->allocated_src
&= ~(1 << log_event_line
);
1105 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1106 phy
->allocated_src
= D40_ALLOC_FREE
;
1108 phy
->allocated_dst
&= ~(1 << log_event_line
);
1109 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1110 phy
->allocated_dst
= D40_ALLOC_FREE
;
1113 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1117 spin_unlock_irqrestore(&phy
->lock
, flags
);
1122 static int d40_allocate_channel(struct d40_chan
*d40c
)
1127 struct d40_phy_res
*phys
;
1132 bool is_log
= (d40c
->dma_cfg
.channel_type
&
1133 STEDMA40_CHANNEL_IN_OPER_MODE
)
1134 == STEDMA40_CHANNEL_IN_LOG_MODE
;
1137 phys
= d40c
->base
->phy_res
;
1139 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1140 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1141 log_num
= 2 * dev_type
;
1143 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1144 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1145 /* dst event lines are used for logical memcpy */
1146 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1147 log_num
= 2 * dev_type
+ 1;
1152 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1153 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1156 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1157 /* Find physical half channel */
1158 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1160 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1165 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1166 int phy_num
= j
+ event_group
* 2;
1167 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1168 if (d40_alloc_mask_set(&phys
[i
],
1177 d40c
->phy_chan
= &phys
[i
];
1178 d40c
->log_num
= D40_PHY_CHAN
;
1184 /* Find logical channel */
1185 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1186 int phy_num
= j
+ event_group
* 2;
1188 * Spread logical channels across all available physical rather
1189 * than pack every logical channel at the first available phy
1193 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1194 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1195 event_line
, is_log
))
1199 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1200 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1201 event_line
, is_log
))
1209 d40c
->phy_chan
= &phys
[i
];
1210 d40c
->log_num
= log_num
;
1214 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1216 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1222 static int d40_config_memcpy(struct d40_chan
*d40c
)
1224 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1226 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1227 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1228 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1229 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1230 memcpy
[d40c
->chan
.chan_id
];
1232 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1233 dma_has_cap(DMA_SLAVE
, cap
)) {
1234 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1236 dev_err(&d40c
->chan
.dev
->device
, "[%s] No memcpy\n",
1245 static int d40_free_dma(struct d40_chan
*d40c
)
1250 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1253 struct d40_desc
*_d
;
1256 /* Terminate all queued and active transfers */
1259 /* Release client owned descriptors */
1260 if (!list_empty(&d40c
->client
))
1261 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1262 d40_pool_lli_free(d
);
1264 /* Return desc to free-list */
1265 d40_desc_free(d40c
, d
);
1269 dev_err(&d40c
->chan
.dev
->device
, "[%s] phy == null\n",
1274 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1275 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1276 dev_err(&d40c
->chan
.dev
->device
, "[%s] channel already free\n",
1281 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1282 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1283 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1285 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1286 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1289 dev_err(&d40c
->chan
.dev
->device
,
1290 "[%s] Unknown direction\n", __func__
);
1294 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1296 dev_err(&d40c
->chan
.dev
->device
, "[%s] suspend failed\n",
1301 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1302 /* Release logical channel, deactivate the event line */
1304 d40_config_set_event(d40c
, false);
1305 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1308 * Check if there are more logical allocation
1309 * on this phy channel.
1311 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1312 /* Resume the other logical channels if any */
1313 if (d40_chan_has_events(d40c
)) {
1314 res
= d40_channel_execute_command(d40c
,
1317 dev_err(&d40c
->chan
.dev
->device
,
1318 "[%s] Executing RUN command\n",
1326 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1329 /* Release physical channel */
1330 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1332 dev_err(&d40c
->chan
.dev
->device
,
1333 "[%s] Failed to stop channel\n", __func__
);
1336 d40c
->phy_chan
= NULL
;
1337 /* Invalidate channel type */
1338 d40c
->dma_cfg
.channel_type
= 0;
1339 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1344 static int d40_pause(struct dma_chan
*chan
)
1346 struct d40_chan
*d40c
=
1347 container_of(chan
, struct d40_chan
, chan
);
1349 unsigned long flags
;
1351 spin_lock_irqsave(&d40c
->lock
, flags
);
1353 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1355 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1356 d40_config_set_event(d40c
, false);
1357 /* Resume the other logical channels if any */
1358 if (d40_chan_has_events(d40c
))
1359 res
= d40_channel_execute_command(d40c
,
1364 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1368 static bool d40_is_paused(struct d40_chan
*d40c
)
1370 bool is_paused
= false;
1371 unsigned long flags
;
1372 void __iomem
*active_reg
;
1376 spin_lock_irqsave(&d40c
->lock
, flags
);
1378 if (d40c
->log_num
== D40_PHY_CHAN
) {
1379 if (d40c
->phy_chan
->num
% 2 == 0)
1380 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1382 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1384 status
= (readl(active_reg
) &
1385 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1386 D40_CHAN_POS(d40c
->phy_chan
->num
);
1387 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1393 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1394 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
)
1395 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1396 else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1397 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1399 dev_err(&d40c
->chan
.dev
->device
,
1400 "[%s] Unknown direction\n", __func__
);
1403 status
= d40_chan_has_events(d40c
);
1404 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1405 D40_EVENTLINE_POS(event
);
1407 if (status
!= D40_DMA_RUN
)
1410 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1416 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
1420 if (d40c
->log_num
!= D40_PHY_CHAN
)
1421 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
1423 is_link
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1424 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1425 D40_CHAN_REG_SDLNK
) &
1426 D40_SREG_LNK_PHYS_LNK_MASK
;
1430 static u32
d40_residue(struct d40_chan
*d40c
)
1434 if (d40c
->log_num
!= D40_PHY_CHAN
)
1435 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
1436 >> D40_MEM_LCSP2_ECNT_POS
;
1438 num_elt
= (readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1439 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1440 D40_CHAN_REG_SDELT
) &
1441 D40_SREG_ELEM_PHY_ECNT_MASK
) >>
1442 D40_SREG_ELEM_PHY_ECNT_POS
;
1443 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
1446 static int d40_resume(struct dma_chan
*chan
)
1448 struct d40_chan
*d40c
=
1449 container_of(chan
, struct d40_chan
, chan
);
1451 unsigned long flags
;
1453 spin_lock_irqsave(&d40c
->lock
, flags
);
1455 if (d40c
->base
->rev
== 0)
1456 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1457 res
= d40_channel_execute_command(d40c
,
1458 D40_DMA_SUSPEND_REQ
);
1462 /* If bytes left to transfer or linked tx resume job */
1463 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
1464 if (d40c
->log_num
!= D40_PHY_CHAN
)
1465 d40_config_set_event(d40c
, true);
1466 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1470 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1474 static u32
stedma40_residue(struct dma_chan
*chan
)
1476 struct d40_chan
*d40c
=
1477 container_of(chan
, struct d40_chan
, chan
);
1479 unsigned long flags
;
1481 spin_lock_irqsave(&d40c
->lock
, flags
);
1482 bytes_left
= d40_residue(d40c
);
1483 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1488 /* Public DMA functions in addition to the DMA engine framework */
1490 int stedma40_set_psize(struct dma_chan
*chan
,
1494 struct d40_chan
*d40c
=
1495 container_of(chan
, struct d40_chan
, chan
);
1496 unsigned long flags
;
1498 spin_lock_irqsave(&d40c
->lock
, flags
);
1500 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1501 d40c
->log_def
.lcsp1
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1502 d40c
->log_def
.lcsp3
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1503 d40c
->log_def
.lcsp1
|= src_psize
<<
1504 D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1505 d40c
->log_def
.lcsp3
|= dst_psize
<<
1506 D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1510 if (src_psize
== STEDMA40_PSIZE_PHY_1
)
1511 d40c
->src_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1513 d40c
->src_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1514 d40c
->src_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1515 D40_SREG_CFG_PSIZE_POS
);
1516 d40c
->src_def_cfg
|= src_psize
<< D40_SREG_CFG_PSIZE_POS
;
1519 if (dst_psize
== STEDMA40_PSIZE_PHY_1
)
1520 d40c
->dst_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1522 d40c
->dst_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1523 d40c
->dst_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1524 D40_SREG_CFG_PSIZE_POS
);
1525 d40c
->dst_def_cfg
|= dst_psize
<< D40_SREG_CFG_PSIZE_POS
;
1528 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1531 EXPORT_SYMBOL(stedma40_set_psize
);
1533 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1534 struct scatterlist
*sgl_dst
,
1535 struct scatterlist
*sgl_src
,
1536 unsigned int sgl_len
,
1537 unsigned long dma_flags
)
1540 struct d40_desc
*d40d
;
1541 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1543 unsigned long flags
;
1545 if (d40c
->phy_chan
== NULL
) {
1546 dev_err(&d40c
->chan
.dev
->device
,
1547 "[%s] Unallocated channel.\n", __func__
);
1548 return ERR_PTR(-EINVAL
);
1551 spin_lock_irqsave(&d40c
->lock
, flags
);
1552 d40d
= d40_desc_get(d40c
);
1557 d40d
->lli_len
= sgl_len
;
1558 d40d
->lli_tx_len
= d40d
->lli_len
;
1559 d40d
->txd
.flags
= dma_flags
;
1561 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1562 if (d40d
->lli_len
> d40c
->base
->plat_data
->llis_per_log
)
1563 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1567 * Check if there is space available in lcla. If not,
1568 * split list into 1-length and run only in lcpa
1571 if (d40_lcla_id_get(d40c
) != 0)
1572 d40d
->lli_tx_len
= 1;
1574 if (d40_pool_lli_alloc(d40d
, sgl_len
, true) < 0) {
1575 dev_err(&d40c
->chan
.dev
->device
,
1576 "[%s] Out of memory\n", __func__
);
1580 (void) d40_log_sg_to_lli(d40c
->lcla
.src_id
,
1584 d40c
->log_def
.lcsp1
,
1585 d40c
->dma_cfg
.src_info
.data_width
,
1587 d40c
->base
->plat_data
->llis_per_log
);
1589 (void) d40_log_sg_to_lli(d40c
->lcla
.dst_id
,
1593 d40c
->log_def
.lcsp3
,
1594 d40c
->dma_cfg
.dst_info
.data_width
,
1596 d40c
->base
->plat_data
->llis_per_log
);
1600 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1601 dev_err(&d40c
->chan
.dev
->device
,
1602 "[%s] Out of memory\n", __func__
);
1606 res
= d40_phy_sg_to_lli(sgl_src
,
1610 d40d
->lli_phy
.src_addr
,
1612 d40c
->dma_cfg
.src_info
.data_width
,
1613 d40c
->dma_cfg
.src_info
.psize
);
1618 res
= d40_phy_sg_to_lli(sgl_dst
,
1622 d40d
->lli_phy
.dst_addr
,
1624 d40c
->dma_cfg
.dst_info
.data_width
,
1625 d40c
->dma_cfg
.dst_info
.psize
);
1630 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1631 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1634 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1636 d40d
->txd
.tx_submit
= d40_tx_submit
;
1638 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1642 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1645 EXPORT_SYMBOL(stedma40_memcpy_sg
);
1647 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1649 struct stedma40_chan_cfg
*info
= data
;
1650 struct d40_chan
*d40c
=
1651 container_of(chan
, struct d40_chan
, chan
);
1655 err
= d40_validate_conf(d40c
, info
);
1657 d40c
->dma_cfg
= *info
;
1659 err
= d40_config_memcpy(d40c
);
1663 EXPORT_SYMBOL(stedma40_filter
);
1665 /* DMA ENGINE functions */
1666 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1669 unsigned long flags
;
1670 struct d40_chan
*d40c
=
1671 container_of(chan
, struct d40_chan
, chan
);
1673 spin_lock_irqsave(&d40c
->lock
, flags
);
1675 d40c
->completed
= chan
->cookie
= 1;
1678 * If no dma configuration is set (channel_type == 0)
1679 * use default configuration (memcpy)
1681 if (d40c
->dma_cfg
.channel_type
== 0) {
1682 err
= d40_config_memcpy(d40c
);
1684 dev_err(&d40c
->chan
.dev
->device
,
1685 "[%s] Failed to configure memcpy channel\n",
1690 is_free_phy
= (d40c
->phy_chan
== NULL
);
1692 err
= d40_allocate_channel(d40c
);
1694 dev_err(&d40c
->chan
.dev
->device
,
1695 "[%s] Failed to allocate channel\n", __func__
);
1699 /* Fill in basic CFG register values */
1700 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1701 &d40c
->dst_def_cfg
, d40c
->log_num
!= D40_PHY_CHAN
);
1703 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1704 d40_log_cfg(&d40c
->dma_cfg
,
1705 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1707 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1708 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1709 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1711 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1712 d40c
->dma_cfg
.dst_dev_type
*
1713 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1717 * Only write channel configuration to the DMA if the physical
1718 * resource is free. In case of multiple logical channels
1719 * on the same physical resource, only the first write is necessary.
1722 d40_config_write(d40c
);
1724 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1728 static void d40_free_chan_resources(struct dma_chan
*chan
)
1730 struct d40_chan
*d40c
=
1731 container_of(chan
, struct d40_chan
, chan
);
1733 unsigned long flags
;
1735 if (d40c
->phy_chan
== NULL
) {
1736 dev_err(&d40c
->chan
.dev
->device
,
1737 "[%s] Cannot free unallocated channel\n", __func__
);
1742 spin_lock_irqsave(&d40c
->lock
, flags
);
1744 err
= d40_free_dma(d40c
);
1747 dev_err(&d40c
->chan
.dev
->device
,
1748 "[%s] Failed to free channel\n", __func__
);
1749 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1752 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1756 unsigned long dma_flags
)
1758 struct d40_desc
*d40d
;
1759 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1761 unsigned long flags
;
1764 if (d40c
->phy_chan
== NULL
) {
1765 dev_err(&d40c
->chan
.dev
->device
,
1766 "[%s] Channel is not allocated.\n", __func__
);
1767 return ERR_PTR(-EINVAL
);
1770 spin_lock_irqsave(&d40c
->lock
, flags
);
1771 d40d
= d40_desc_get(d40c
);
1774 dev_err(&d40c
->chan
.dev
->device
,
1775 "[%s] Descriptor is NULL\n", __func__
);
1779 d40d
->txd
.flags
= dma_flags
;
1781 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1783 d40d
->txd
.tx_submit
= d40_tx_submit
;
1785 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1787 if (d40_pool_lli_alloc(d40d
, 1, true) < 0) {
1788 dev_err(&d40c
->chan
.dev
->device
,
1789 "[%s] Out of memory\n", __func__
);
1793 d40d
->lli_tx_len
= 1;
1795 d40_log_fill_lli(d40d
->lli_log
.src
,
1799 d40c
->log_def
.lcsp1
,
1800 d40c
->dma_cfg
.src_info
.data_width
,
1803 d40_log_fill_lli(d40d
->lli_log
.dst
,
1807 d40c
->log_def
.lcsp3
,
1808 d40c
->dma_cfg
.dst_info
.data_width
,
1813 if (d40_pool_lli_alloc(d40d
, 1, false) < 0) {
1814 dev_err(&d40c
->chan
.dev
->device
,
1815 "[%s] Out of memory\n", __func__
);
1819 err
= d40_phy_fill_lli(d40d
->lli_phy
.src
,
1822 d40c
->dma_cfg
.src_info
.psize
,
1826 d40c
->dma_cfg
.src_info
.data_width
,
1831 err
= d40_phy_fill_lli(d40d
->lli_phy
.dst
,
1834 d40c
->dma_cfg
.dst_info
.psize
,
1838 d40c
->dma_cfg
.dst_info
.data_width
,
1844 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1845 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1848 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1852 dev_err(&d40c
->chan
.dev
->device
,
1853 "[%s] Failed filling in PHY LLI\n", __func__
);
1854 d40_pool_lli_free(d40d
);
1856 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1860 static int d40_prep_slave_sg_log(struct d40_desc
*d40d
,
1861 struct d40_chan
*d40c
,
1862 struct scatterlist
*sgl
,
1863 unsigned int sg_len
,
1864 enum dma_data_direction direction
,
1865 unsigned long dma_flags
)
1867 dma_addr_t dev_addr
= 0;
1870 if (d40_pool_lli_alloc(d40d
, sg_len
, true) < 0) {
1871 dev_err(&d40c
->chan
.dev
->device
,
1872 "[%s] Out of memory\n", __func__
);
1876 d40d
->lli_len
= sg_len
;
1877 if (d40d
->lli_len
<= d40c
->base
->plat_data
->llis_per_log
)
1878 d40d
->lli_tx_len
= d40d
->lli_len
;
1880 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1884 * Check if there is space available in lcla.
1885 * If not, split list into 1-length and run only
1888 if (d40_lcla_id_get(d40c
) != 0)
1889 d40d
->lli_tx_len
= 1;
1891 if (direction
== DMA_FROM_DEVICE
)
1892 if (d40c
->runtime_addr
)
1893 dev_addr
= d40c
->runtime_addr
;
1895 dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1896 else if (direction
== DMA_TO_DEVICE
)
1897 if (d40c
->runtime_addr
)
1898 dev_addr
= d40c
->runtime_addr
;
1900 dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1905 total_size
= d40_log_sg_to_dev(&d40c
->lcla
,
1909 d40c
->dma_cfg
.src_info
.data_width
,
1910 d40c
->dma_cfg
.dst_info
.data_width
,
1912 dev_addr
, d40d
->lli_tx_len
,
1913 d40c
->base
->plat_data
->llis_per_log
);
1921 static int d40_prep_slave_sg_phy(struct d40_desc
*d40d
,
1922 struct d40_chan
*d40c
,
1923 struct scatterlist
*sgl
,
1924 unsigned int sgl_len
,
1925 enum dma_data_direction direction
,
1926 unsigned long dma_flags
)
1928 dma_addr_t src_dev_addr
;
1929 dma_addr_t dst_dev_addr
;
1932 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1933 dev_err(&d40c
->chan
.dev
->device
,
1934 "[%s] Out of memory\n", __func__
);
1938 d40d
->lli_len
= sgl_len
;
1939 d40d
->lli_tx_len
= sgl_len
;
1941 if (direction
== DMA_FROM_DEVICE
) {
1943 if (d40c
->runtime_addr
)
1944 src_dev_addr
= d40c
->runtime_addr
;
1946 src_dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1947 } else if (direction
== DMA_TO_DEVICE
) {
1948 if (d40c
->runtime_addr
)
1949 dst_dev_addr
= d40c
->runtime_addr
;
1951 dst_dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1956 res
= d40_phy_sg_to_lli(sgl
,
1960 d40d
->lli_phy
.src_addr
,
1962 d40c
->dma_cfg
.src_info
.data_width
,
1963 d40c
->dma_cfg
.src_info
.psize
);
1967 res
= d40_phy_sg_to_lli(sgl
,
1971 d40d
->lli_phy
.dst_addr
,
1973 d40c
->dma_cfg
.dst_info
.data_width
,
1974 d40c
->dma_cfg
.dst_info
.psize
);
1978 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1979 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1983 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
1984 struct scatterlist
*sgl
,
1985 unsigned int sg_len
,
1986 enum dma_data_direction direction
,
1987 unsigned long dma_flags
)
1989 struct d40_desc
*d40d
;
1990 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1992 unsigned long flags
;
1995 if (d40c
->phy_chan
== NULL
) {
1996 dev_err(&d40c
->chan
.dev
->device
,
1997 "[%s] Cannot prepare unallocated channel\n", __func__
);
1998 return ERR_PTR(-EINVAL
);
2001 if (d40c
->dma_cfg
.pre_transfer
)
2002 d40c
->dma_cfg
.pre_transfer(chan
,
2003 d40c
->dma_cfg
.pre_transfer_data
,
2006 spin_lock_irqsave(&d40c
->lock
, flags
);
2007 d40d
= d40_desc_get(d40c
);
2008 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2013 if (d40c
->log_num
!= D40_PHY_CHAN
)
2014 err
= d40_prep_slave_sg_log(d40d
, d40c
, sgl
, sg_len
,
2015 direction
, dma_flags
);
2017 err
= d40_prep_slave_sg_phy(d40d
, d40c
, sgl
, sg_len
,
2018 direction
, dma_flags
);
2020 dev_err(&d40c
->chan
.dev
->device
,
2021 "[%s] Failed to prepare %s slave sg job: %d\n",
2023 d40c
->log_num
!= D40_PHY_CHAN
? "log" : "phy", err
);
2027 d40d
->txd
.flags
= dma_flags
;
2029 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
2031 d40d
->txd
.tx_submit
= d40_tx_submit
;
2036 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2037 dma_cookie_t cookie
,
2038 struct dma_tx_state
*txstate
)
2040 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2041 dma_cookie_t last_used
;
2042 dma_cookie_t last_complete
;
2045 if (d40c
->phy_chan
== NULL
) {
2046 dev_err(&d40c
->chan
.dev
->device
,
2047 "[%s] Cannot read status of unallocated channel\n",
2052 last_complete
= d40c
->completed
;
2053 last_used
= chan
->cookie
;
2055 if (d40_is_paused(d40c
))
2058 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2060 dma_set_tx_state(txstate
, last_complete
, last_used
,
2061 stedma40_residue(chan
));
2066 static void d40_issue_pending(struct dma_chan
*chan
)
2068 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2069 unsigned long flags
;
2071 if (d40c
->phy_chan
== NULL
) {
2072 dev_err(&d40c
->chan
.dev
->device
,
2073 "[%s] Channel is not allocated!\n", __func__
);
2077 spin_lock_irqsave(&d40c
->lock
, flags
);
2079 /* Busy means that pending jobs are already being processed */
2081 (void) d40_queue_start(d40c
);
2083 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2086 /* Runtime reconfiguration extension */
2087 static void d40_set_runtime_config(struct dma_chan
*chan
,
2088 struct dma_slave_config
*config
)
2090 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2091 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2092 enum dma_slave_buswidth config_addr_width
;
2093 dma_addr_t config_addr
;
2094 u32 config_maxburst
;
2095 enum stedma40_periph_data_width addr_width
;
2098 if (config
->direction
== DMA_FROM_DEVICE
) {
2099 dma_addr_t dev_addr_rx
=
2100 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2102 config_addr
= config
->src_addr
;
2104 dev_dbg(d40c
->base
->dev
,
2105 "channel has a pre-wired RX address %08x "
2106 "overriding with %08x\n",
2107 dev_addr_rx
, config_addr
);
2108 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2109 dev_dbg(d40c
->base
->dev
,
2110 "channel was not configured for peripheral "
2111 "to memory transfer (%d) overriding\n",
2113 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2115 config_addr_width
= config
->src_addr_width
;
2116 config_maxburst
= config
->src_maxburst
;
2118 } else if (config
->direction
== DMA_TO_DEVICE
) {
2119 dma_addr_t dev_addr_tx
=
2120 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2122 config_addr
= config
->dst_addr
;
2124 dev_dbg(d40c
->base
->dev
,
2125 "channel has a pre-wired TX address %08x "
2126 "overriding with %08x\n",
2127 dev_addr_tx
, config_addr
);
2128 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2129 dev_dbg(d40c
->base
->dev
,
2130 "channel was not configured for memory "
2131 "to peripheral transfer (%d) overriding\n",
2133 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2135 config_addr_width
= config
->dst_addr_width
;
2136 config_maxburst
= config
->dst_maxburst
;
2139 dev_err(d40c
->base
->dev
,
2140 "unrecognized channel direction %d\n",
2145 switch (config_addr_width
) {
2146 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2147 addr_width
= STEDMA40_BYTE_WIDTH
;
2149 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2150 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2152 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2153 addr_width
= STEDMA40_WORD_WIDTH
;
2155 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2156 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2159 dev_err(d40c
->base
->dev
,
2160 "illegal peripheral address width "
2162 config
->src_addr_width
);
2166 if (config_maxburst
>= 16)
2167 psize
= STEDMA40_PSIZE_LOG_16
;
2168 else if (config_maxburst
>= 8)
2169 psize
= STEDMA40_PSIZE_LOG_8
;
2170 else if (config_maxburst
>= 4)
2171 psize
= STEDMA40_PSIZE_LOG_4
;
2173 psize
= STEDMA40_PSIZE_LOG_1
;
2175 /* Set up all the endpoint configs */
2176 cfg
->src_info
.data_width
= addr_width
;
2177 cfg
->src_info
.psize
= psize
;
2178 cfg
->src_info
.endianess
= STEDMA40_LITTLE_ENDIAN
;
2179 cfg
->src_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2180 cfg
->dst_info
.data_width
= addr_width
;
2181 cfg
->dst_info
.psize
= psize
;
2182 cfg
->dst_info
.endianess
= STEDMA40_LITTLE_ENDIAN
;
2183 cfg
->dst_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2185 /* These settings will take precedence later */
2186 d40c
->runtime_addr
= config_addr
;
2187 d40c
->runtime_direction
= config
->direction
;
2188 dev_dbg(d40c
->base
->dev
,
2189 "configured channel %s for %s, data width %d, "
2190 "maxburst %d bytes, LE, no flow control\n",
2191 dma_chan_name(chan
),
2192 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
2197 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2200 unsigned long flags
;
2201 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2203 if (d40c
->phy_chan
== NULL
) {
2204 dev_err(&d40c
->chan
.dev
->device
,
2205 "[%s] Channel is not allocated!\n", __func__
);
2210 case DMA_TERMINATE_ALL
:
2211 spin_lock_irqsave(&d40c
->lock
, flags
);
2213 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2216 return d40_pause(chan
);
2218 return d40_resume(chan
);
2219 case DMA_SLAVE_CONFIG
:
2220 d40_set_runtime_config(chan
,
2221 (struct dma_slave_config
*) arg
);
2227 /* Other commands are unimplemented */
2231 /* Initialization functions */
2233 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2234 struct d40_chan
*chans
, int offset
,
2238 struct d40_chan
*d40c
;
2240 INIT_LIST_HEAD(&dma
->channels
);
2242 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2245 d40c
->chan
.device
= dma
;
2247 /* Invalidate lcla element */
2248 d40c
->lcla
.src_id
= -1;
2249 d40c
->lcla
.dst_id
= -1;
2251 spin_lock_init(&d40c
->lock
);
2253 d40c
->log_num
= D40_PHY_CHAN
;
2255 INIT_LIST_HEAD(&d40c
->active
);
2256 INIT_LIST_HEAD(&d40c
->queue
);
2257 INIT_LIST_HEAD(&d40c
->client
);
2259 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2260 (unsigned long) d40c
);
2262 list_add_tail(&d40c
->chan
.device_node
,
2267 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2268 int num_reserved_chans
)
2272 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2273 0, base
->num_log_chans
);
2275 dma_cap_zero(base
->dma_slave
.cap_mask
);
2276 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2278 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2279 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2280 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2281 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2282 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2283 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2284 base
->dma_slave
.device_control
= d40_control
;
2285 base
->dma_slave
.dev
= base
->dev
;
2287 err
= dma_async_device_register(&base
->dma_slave
);
2291 "[%s] Failed to register slave channels\n",
2296 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2297 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2299 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2300 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2302 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2303 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2304 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2305 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2306 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2307 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2308 base
->dma_memcpy
.device_control
= d40_control
;
2309 base
->dma_memcpy
.dev
= base
->dev
;
2311 * This controller can only access address at even
2312 * 32bit boundaries, i.e. 2^2
2314 base
->dma_memcpy
.copy_align
= 2;
2316 err
= dma_async_device_register(&base
->dma_memcpy
);
2320 "[%s] Failed to regsiter memcpy only channels\n",
2325 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2326 0, num_reserved_chans
);
2328 dma_cap_zero(base
->dma_both
.cap_mask
);
2329 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2330 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2332 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2333 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2334 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2335 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2336 base
->dma_both
.device_tx_status
= d40_tx_status
;
2337 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2338 base
->dma_both
.device_control
= d40_control
;
2339 base
->dma_both
.dev
= base
->dev
;
2340 base
->dma_both
.copy_align
= 2;
2341 err
= dma_async_device_register(&base
->dma_both
);
2345 "[%s] Failed to register logical and physical capable channels\n",
2351 dma_async_device_unregister(&base
->dma_memcpy
);
2353 dma_async_device_unregister(&base
->dma_slave
);
2358 /* Initialization functions. */
2360 static int __init
d40_phy_res_init(struct d40_base
*base
)
2363 int num_phy_chans_avail
= 0;
2365 int odd_even_bit
= -2;
2367 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2368 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2370 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2371 base
->phy_res
[i
].num
= i
;
2372 odd_even_bit
+= 2 * ((i
% 2) == 0);
2373 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2374 /* Mark security only channels as occupied */
2375 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2376 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2378 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2379 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2380 num_phy_chans_avail
++;
2382 spin_lock_init(&base
->phy_res
[i
].lock
);
2385 /* Mark disabled channels as occupied */
2386 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2387 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2388 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2389 num_phy_chans_avail
--;
2392 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2393 num_phy_chans_avail
, base
->num_phy_chans
);
2395 /* Verify settings extended vs standard */
2396 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2398 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2400 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2401 (val
[0] & 0x3) != 1)
2403 "[%s] INFO: channel %d is misconfigured (%d)\n",
2404 __func__
, i
, val
[0] & 0x3);
2406 val
[0] = val
[0] >> 2;
2409 return num_phy_chans_avail
;
2412 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2414 static const struct d40_reg_val dma_id_regs
[] = {
2416 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2417 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2419 * D40_DREG_PERIPHID2 Depends on HW revision:
2420 * MOP500/HREF ED has 0x0008,
2422 * HREF V1 has 0x0028
2424 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2427 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2428 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2429 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2430 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2432 struct stedma40_platform_data
*plat_data
;
2433 struct clk
*clk
= NULL
;
2434 void __iomem
*virtbase
= NULL
;
2435 struct resource
*res
= NULL
;
2436 struct d40_base
*base
= NULL
;
2437 int num_log_chans
= 0;
2442 clk
= clk_get(&pdev
->dev
, NULL
);
2445 dev_err(&pdev
->dev
, "[%s] No matching clock found\n",
2452 /* Get IO for DMAC base address */
2453 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2457 if (request_mem_region(res
->start
, resource_size(res
),
2458 D40_NAME
" I/O base") == NULL
)
2461 virtbase
= ioremap(res
->start
, resource_size(res
));
2465 /* HW version check */
2466 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2467 if (dma_id_regs
[i
].val
!=
2468 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2470 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2474 readl(virtbase
+ dma_id_regs
[i
].reg
));
2479 /* Get silicon revision */
2480 val
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2482 if ((val
& 0xf) != D40_PERIPHID2_DESIGNER
) {
2484 "[%s] Unknown designer! Got %x wanted %x\n",
2485 __func__
, val
& 0xf, D40_PERIPHID2_DESIGNER
);
2489 /* The number of physical channels on this HW */
2490 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2492 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2493 (val
>> 4) & 0xf, res
->start
);
2495 plat_data
= pdev
->dev
.platform_data
;
2497 /* Count the number of logical channels in use */
2498 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2499 if (plat_data
->dev_rx
[i
] != 0)
2502 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2503 if (plat_data
->dev_tx
[i
] != 0)
2506 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2507 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2508 sizeof(struct d40_chan
), GFP_KERNEL
);
2511 dev_err(&pdev
->dev
, "[%s] Out of memory\n", __func__
);
2515 base
->rev
= (val
>> 4) & 0xf;
2517 base
->num_phy_chans
= num_phy_chans
;
2518 base
->num_log_chans
= num_log_chans
;
2519 base
->phy_start
= res
->start
;
2520 base
->phy_size
= resource_size(res
);
2521 base
->virtbase
= virtbase
;
2522 base
->plat_data
= plat_data
;
2523 base
->dev
= &pdev
->dev
;
2524 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2525 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2527 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2532 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2533 sizeof(struct d40_chan
*),
2535 if (!base
->lookup_phy_chans
)
2538 if (num_log_chans
+ plat_data
->memcpy_len
) {
2540 * The max number of logical channels are event lines for all
2541 * src devices and dst devices
2543 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2544 sizeof(struct d40_chan
*),
2546 if (!base
->lookup_log_chans
)
2549 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
* sizeof(u32
),
2551 if (!base
->lcla_pool
.alloc_map
)
2554 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2555 0, SLAB_HWCACHE_ALIGN
,
2557 if (base
->desc_slab
== NULL
)
2570 release_mem_region(res
->start
,
2571 resource_size(res
));
2576 kfree(base
->lcla_pool
.alloc_map
);
2577 kfree(base
->lookup_log_chans
);
2578 kfree(base
->lookup_phy_chans
);
2579 kfree(base
->phy_res
);
2586 static void __init
d40_hw_init(struct d40_base
*base
)
2589 static const struct d40_reg_val dma_init_reg
[] = {
2590 /* Clock every part of the DMA block from start */
2591 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2593 /* Interrupts on all logical channels */
2594 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2595 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2596 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2597 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2598 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2599 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2600 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2601 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2602 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2603 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2604 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2605 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2608 u32 prmseo
[2] = {0, 0};
2609 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2613 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2614 writel(dma_init_reg
[i
].val
,
2615 base
->virtbase
+ dma_init_reg
[i
].reg
);
2617 /* Configure all our dma channels to default settings */
2618 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2620 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2622 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2624 activeo
[i
% 2] |= 3;
2628 /* Enable interrupt # */
2629 pcmis
= (pcmis
<< 1) | 1;
2631 /* Clear interrupt # */
2632 pcicr
= (pcicr
<< 1) | 1;
2634 /* Set channel to physical mode */
2635 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2640 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2641 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2642 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2643 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2645 /* Write which interrupt to enable */
2646 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2648 /* Write which interrupt to clear */
2649 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2653 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2655 unsigned long *page_list
;
2660 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2661 * To full fill this hardware requirement without wasting 256 kb
2662 * we allocate pages until we get an aligned one.
2664 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2672 /* Calculating how many pages that are required */
2673 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2675 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2676 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2677 base
->lcla_pool
.pages
);
2678 if (!page_list
[i
]) {
2681 "[%s] Failed to allocate %d pages.\n",
2682 __func__
, base
->lcla_pool
.pages
);
2684 for (j
= 0; j
< i
; j
++)
2685 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2689 if ((virt_to_phys((void *)page_list
[i
]) &
2690 (LCLA_ALIGNMENT
- 1)) == 0)
2694 for (j
= 0; j
< i
; j
++)
2695 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2697 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2698 base
->lcla_pool
.base
= (void *)page_list
[i
];
2700 /* After many attempts, no succees with finding the correct
2701 * alignment try with allocating a big buffer */
2703 "[%s] Failed to get %d pages @ 18 bit align.\n",
2704 __func__
, base
->lcla_pool
.pages
);
2705 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2706 base
->num_phy_chans
+
2709 if (!base
->lcla_pool
.base_unaligned
) {
2714 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2718 writel(virt_to_phys(base
->lcla_pool
.base
),
2719 base
->virtbase
+ D40_DREG_LCLA
);
2725 static int __init
d40_probe(struct platform_device
*pdev
)
2729 struct d40_base
*base
;
2730 struct resource
*res
= NULL
;
2731 int num_reserved_chans
;
2734 base
= d40_hw_detect_init(pdev
);
2739 num_reserved_chans
= d40_phy_res_init(base
);
2741 platform_set_drvdata(pdev
, base
);
2743 spin_lock_init(&base
->interrupt_lock
);
2744 spin_lock_init(&base
->execmd_lock
);
2746 /* Get IO for logical channel parameter address */
2747 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2751 "[%s] No \"lcpa\" memory resource\n",
2755 base
->lcpa_size
= resource_size(res
);
2756 base
->phy_lcpa
= res
->start
;
2758 if (request_mem_region(res
->start
, resource_size(res
),
2759 D40_NAME
" I/O lcpa") == NULL
) {
2762 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2763 __func__
, res
->start
, res
->end
);
2767 /* We make use of ESRAM memory for this. */
2768 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2769 if (res
->start
!= val
&& val
!= 0) {
2770 dev_warn(&pdev
->dev
,
2771 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2772 __func__
, val
, res
->start
);
2774 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2776 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2777 if (!base
->lcpa_base
) {
2780 "[%s] Failed to ioremap LCPA region\n",
2785 ret
= d40_lcla_allocate(base
);
2787 dev_err(&pdev
->dev
, "[%s] Failed to allocate LCLA area\n",
2792 spin_lock_init(&base
->lcla_pool
.lock
);
2794 base
->lcla_pool
.num_blocks
= base
->num_phy_chans
;
2796 base
->irq
= platform_get_irq(pdev
, 0);
2798 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2801 dev_err(&pdev
->dev
, "[%s] No IRQ defined\n", __func__
);
2805 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2811 dev_info(base
->dev
, "initialized\n");
2816 if (base
->desc_slab
)
2817 kmem_cache_destroy(base
->desc_slab
);
2819 iounmap(base
->virtbase
);
2820 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2821 free_pages((unsigned long)base
->lcla_pool
.base
,
2822 base
->lcla_pool
.pages
);
2823 if (base
->lcla_pool
.base_unaligned
)
2824 kfree(base
->lcla_pool
.base_unaligned
);
2826 release_mem_region(base
->phy_lcpa
,
2828 if (base
->phy_start
)
2829 release_mem_region(base
->phy_start
,
2832 clk_disable(base
->clk
);
2836 kfree(base
->lcla_pool
.alloc_map
);
2837 kfree(base
->lookup_log_chans
);
2838 kfree(base
->lookup_phy_chans
);
2839 kfree(base
->phy_res
);
2843 dev_err(&pdev
->dev
, "[%s] probe failed\n", __func__
);
2847 static struct platform_driver d40_driver
= {
2849 .owner
= THIS_MODULE
,
2854 int __init
stedma40_init(void)
2856 return platform_driver_probe(&d40_driver
, d40_probe
);
2858 arch_initcall(stedma40_init
);