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ste_dma40: Rename a jump label in d40_log_lli_to_lcxa()
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / ste_dma40.c
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/log2.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_dma.h>
23 #include <linux/amba/bus.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/platform_data/dma-ste-dma40.h>
26
27 #include "dmaengine.h"
28 #include "ste_dma40_ll.h"
29
30 #define D40_NAME "dma40"
31
32 #define D40_PHY_CHAN -1
33
34 /* For masking out/in 2 bit channel positions */
35 #define D40_CHAN_POS(chan) (2 * (chan / 2))
36 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
37
38 /* Maximum iterations taken before giving up suspending a channel */
39 #define D40_SUSPEND_MAX_IT 500
40
41 /* Milliseconds */
42 #define DMA40_AUTOSUSPEND_DELAY 100
43
44 /* Hardware requirement on LCLA alignment */
45 #define LCLA_ALIGNMENT 0x40000
46
47 /* Max number of links per event group */
48 #define D40_LCLA_LINK_PER_EVENT_GRP 128
49 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
50
51 /* Max number of logical channels per physical channel */
52 #define D40_MAX_LOG_CHAN_PER_PHY 32
53
54 /* Attempts before giving up to trying to get pages that are aligned */
55 #define MAX_LCLA_ALLOC_ATTEMPTS 256
56
57 /* Bit markings for allocation map */
58 #define D40_ALLOC_FREE BIT(31)
59 #define D40_ALLOC_PHY BIT(30)
60 #define D40_ALLOC_LOG_FREE 0
61
62 #define D40_MEMCPY_MAX_CHANS 8
63
64 /* Reserved event lines for memcpy only. */
65 #define DB8500_DMA_MEMCPY_EV_0 51
66 #define DB8500_DMA_MEMCPY_EV_1 56
67 #define DB8500_DMA_MEMCPY_EV_2 57
68 #define DB8500_DMA_MEMCPY_EV_3 58
69 #define DB8500_DMA_MEMCPY_EV_4 59
70 #define DB8500_DMA_MEMCPY_EV_5 60
71
72 static int dma40_memcpy_channels[] = {
73 DB8500_DMA_MEMCPY_EV_0,
74 DB8500_DMA_MEMCPY_EV_1,
75 DB8500_DMA_MEMCPY_EV_2,
76 DB8500_DMA_MEMCPY_EV_3,
77 DB8500_DMA_MEMCPY_EV_4,
78 DB8500_DMA_MEMCPY_EV_5,
79 };
80
81 /* Default configuration for physcial memcpy */
82 static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
83 .mode = STEDMA40_MODE_PHYSICAL,
84 .dir = DMA_MEM_TO_MEM,
85
86 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
87 .src_info.psize = STEDMA40_PSIZE_PHY_1,
88 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
89
90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
93 };
94
95 /* Default configuration for logical memcpy */
96 static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
97 .mode = STEDMA40_MODE_LOGICAL,
98 .dir = DMA_MEM_TO_MEM,
99
100 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
101 .src_info.psize = STEDMA40_PSIZE_LOG_1,
102 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
103
104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
107 };
108
109 /**
110 * enum 40_command - The different commands and/or statuses.
111 *
112 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
113 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
114 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
115 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
116 */
117 enum d40_command {
118 D40_DMA_STOP = 0,
119 D40_DMA_RUN = 1,
120 D40_DMA_SUSPEND_REQ = 2,
121 D40_DMA_SUSPENDED = 3
122 };
123
124 /*
125 * enum d40_events - The different Event Enables for the event lines.
126 *
127 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
128 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
129 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
130 * @D40_ROUND_EVENTLINE: Status check for event line.
131 */
132
133 enum d40_events {
134 D40_DEACTIVATE_EVENTLINE = 0,
135 D40_ACTIVATE_EVENTLINE = 1,
136 D40_SUSPEND_REQ_EVENTLINE = 2,
137 D40_ROUND_EVENTLINE = 3
138 };
139
140 /*
141 * These are the registers that has to be saved and later restored
142 * when the DMA hw is powered off.
143 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
144 */
145 static u32 d40_backup_regs[] = {
146 D40_DREG_LCPA,
147 D40_DREG_LCLA,
148 D40_DREG_PRMSE,
149 D40_DREG_PRMSO,
150 D40_DREG_PRMOE,
151 D40_DREG_PRMOO,
152 };
153
154 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
155
156 /*
157 * since 9540 and 8540 has the same HW revision
158 * use v4a for 9540 or ealier
159 * use v4b for 8540 or later
160 * HW revision:
161 * DB8500ed has revision 0
162 * DB8500v1 has revision 2
163 * DB8500v2 has revision 3
164 * AP9540v1 has revision 4
165 * DB8540v1 has revision 4
166 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
167 */
168 static u32 d40_backup_regs_v4a[] = {
169 D40_DREG_PSEG1,
170 D40_DREG_PSEG2,
171 D40_DREG_PSEG3,
172 D40_DREG_PSEG4,
173 D40_DREG_PCEG1,
174 D40_DREG_PCEG2,
175 D40_DREG_PCEG3,
176 D40_DREG_PCEG4,
177 D40_DREG_RSEG1,
178 D40_DREG_RSEG2,
179 D40_DREG_RSEG3,
180 D40_DREG_RSEG4,
181 D40_DREG_RCEG1,
182 D40_DREG_RCEG2,
183 D40_DREG_RCEG3,
184 D40_DREG_RCEG4,
185 };
186
187 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
188
189 static u32 d40_backup_regs_v4b[] = {
190 D40_DREG_CPSEG1,
191 D40_DREG_CPSEG2,
192 D40_DREG_CPSEG3,
193 D40_DREG_CPSEG4,
194 D40_DREG_CPSEG5,
195 D40_DREG_CPCEG1,
196 D40_DREG_CPCEG2,
197 D40_DREG_CPCEG3,
198 D40_DREG_CPCEG4,
199 D40_DREG_CPCEG5,
200 D40_DREG_CRSEG1,
201 D40_DREG_CRSEG2,
202 D40_DREG_CRSEG3,
203 D40_DREG_CRSEG4,
204 D40_DREG_CRSEG5,
205 D40_DREG_CRCEG1,
206 D40_DREG_CRCEG2,
207 D40_DREG_CRCEG3,
208 D40_DREG_CRCEG4,
209 D40_DREG_CRCEG5,
210 };
211
212 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
213
214 static u32 d40_backup_regs_chan[] = {
215 D40_CHAN_REG_SSCFG,
216 D40_CHAN_REG_SSELT,
217 D40_CHAN_REG_SSPTR,
218 D40_CHAN_REG_SSLNK,
219 D40_CHAN_REG_SDCFG,
220 D40_CHAN_REG_SDELT,
221 D40_CHAN_REG_SDPTR,
222 D40_CHAN_REG_SDLNK,
223 };
224
225 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
226 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
227
228 /**
229 * struct d40_interrupt_lookup - lookup table for interrupt handler
230 *
231 * @src: Interrupt mask register.
232 * @clr: Interrupt clear register.
233 * @is_error: true if this is an error interrupt.
234 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
235 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
236 */
237 struct d40_interrupt_lookup {
238 u32 src;
239 u32 clr;
240 bool is_error;
241 int offset;
242 };
243
244
245 static struct d40_interrupt_lookup il_v4a[] = {
246 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
247 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
248 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
249 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
250 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
251 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
252 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
253 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
254 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
255 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
256 };
257
258 static struct d40_interrupt_lookup il_v4b[] = {
259 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
260 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
261 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
262 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
263 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
264 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
265 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
266 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
267 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
268 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
269 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
270 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
271 };
272
273 /**
274 * struct d40_reg_val - simple lookup struct
275 *
276 * @reg: The register.
277 * @val: The value that belongs to the register in reg.
278 */
279 struct d40_reg_val {
280 unsigned int reg;
281 unsigned int val;
282 };
283
284 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
285 /* Clock every part of the DMA block from start */
286 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
287
288 /* Interrupts on all logical channels */
289 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
290 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
291 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
292 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
293 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
294 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
295 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
296 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
297 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
298 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
299 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
300 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
301 };
302 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
303 /* Clock every part of the DMA block from start */
304 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
305
306 /* Interrupts on all logical channels */
307 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
308 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
309 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
310 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
311 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
312 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
313 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
314 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
315 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
316 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
317 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
318 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
319 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
320 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
321 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
322 };
323
324 /**
325 * struct d40_lli_pool - Structure for keeping LLIs in memory
326 *
327 * @base: Pointer to memory area when the pre_alloc_lli's are not large
328 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
329 * pre_alloc_lli is used.
330 * @dma_addr: DMA address, if mapped
331 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
332 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
333 * one buffer to one buffer.
334 */
335 struct d40_lli_pool {
336 void *base;
337 int size;
338 dma_addr_t dma_addr;
339 /* Space for dst and src, plus an extra for padding */
340 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
341 };
342
343 /**
344 * struct d40_desc - A descriptor is one DMA job.
345 *
346 * @lli_phy: LLI settings for physical channel. Both src and dst=
347 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
348 * lli_len equals one.
349 * @lli_log: Same as above but for logical channels.
350 * @lli_pool: The pool with two entries pre-allocated.
351 * @lli_len: Number of llis of current descriptor.
352 * @lli_current: Number of transferred llis.
353 * @lcla_alloc: Number of LCLA entries allocated.
354 * @txd: DMA engine struct. Used for among other things for communication
355 * during a transfer.
356 * @node: List entry.
357 * @is_in_client_list: true if the client owns this descriptor.
358 * @cyclic: true if this is a cyclic job
359 *
360 * This descriptor is used for both logical and physical transfers.
361 */
362 struct d40_desc {
363 /* LLI physical */
364 struct d40_phy_lli_bidir lli_phy;
365 /* LLI logical */
366 struct d40_log_lli_bidir lli_log;
367
368 struct d40_lli_pool lli_pool;
369 int lli_len;
370 int lli_current;
371 int lcla_alloc;
372
373 struct dma_async_tx_descriptor txd;
374 struct list_head node;
375
376 bool is_in_client_list;
377 bool cyclic;
378 };
379
380 /**
381 * struct d40_lcla_pool - LCLA pool settings and data.
382 *
383 * @base: The virtual address of LCLA. 18 bit aligned.
384 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385 * This pointer is only there for clean-up on error.
386 * @pages: The number of pages needed for all physical channels.
387 * Only used later for clean-up on error
388 * @lock: Lock to protect the content in this struct.
389 * @alloc_map: big map over which LCLA entry is own by which job.
390 */
391 struct d40_lcla_pool {
392 void *base;
393 dma_addr_t dma_addr;
394 void *base_unaligned;
395 int pages;
396 spinlock_t lock;
397 struct d40_desc **alloc_map;
398 };
399
400 /**
401 * struct d40_phy_res - struct for handling eventlines mapped to physical
402 * channels.
403 *
404 * @lock: A lock protection this entity.
405 * @reserved: True if used by secure world or otherwise.
406 * @num: The physical channel number of this entity.
407 * @allocated_src: Bit mapped to show which src event line's are mapped to
408 * this physical channel. Can also be free or physically allocated.
409 * @allocated_dst: Same as for src but is dst.
410 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
411 * event line number.
412 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
413 */
414 struct d40_phy_res {
415 spinlock_t lock;
416 bool reserved;
417 int num;
418 u32 allocated_src;
419 u32 allocated_dst;
420 bool use_soft_lli;
421 };
422
423 struct d40_base;
424
425 /**
426 * struct d40_chan - Struct that describes a channel.
427 *
428 * @lock: A spinlock to protect this struct.
429 * @log_num: The logical number, if any of this channel.
430 * @pending_tx: The number of pending transfers. Used between interrupt handler
431 * and tasklet.
432 * @busy: Set to true when transfer is ongoing on this channel.
433 * @phy_chan: Pointer to physical channel which this instance runs on. If this
434 * point is NULL, then the channel is not allocated.
435 * @chan: DMA engine handle.
436 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
437 * transfer and call client callback.
438 * @client: Cliented owned descriptor list.
439 * @pending_queue: Submitted jobs, to be issued by issue_pending()
440 * @active: Active descriptor.
441 * @done: Completed jobs
442 * @queue: Queued jobs.
443 * @prepare_queue: Prepared jobs.
444 * @dma_cfg: The client configuration of this dma channel.
445 * @configured: whether the dma_cfg configuration is valid
446 * @base: Pointer to the device instance struct.
447 * @src_def_cfg: Default cfg register setting for src.
448 * @dst_def_cfg: Default cfg register setting for dst.
449 * @log_def: Default logical channel settings.
450 * @lcpa: Pointer to dst and src lcpa settings.
451 * @runtime_addr: runtime configured address.
452 * @runtime_direction: runtime configured direction.
453 *
454 * This struct can either "be" a logical or a physical channel.
455 */
456 struct d40_chan {
457 spinlock_t lock;
458 int log_num;
459 int pending_tx;
460 bool busy;
461 struct d40_phy_res *phy_chan;
462 struct dma_chan chan;
463 struct tasklet_struct tasklet;
464 struct list_head client;
465 struct list_head pending_queue;
466 struct list_head active;
467 struct list_head done;
468 struct list_head queue;
469 struct list_head prepare_queue;
470 struct stedma40_chan_cfg dma_cfg;
471 bool configured;
472 struct d40_base *base;
473 /* Default register configurations */
474 u32 src_def_cfg;
475 u32 dst_def_cfg;
476 struct d40_def_lcsp log_def;
477 struct d40_log_lli_full *lcpa;
478 /* Runtime reconfiguration */
479 dma_addr_t runtime_addr;
480 enum dma_transfer_direction runtime_direction;
481 };
482
483 /**
484 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
485 * controller
486 *
487 * @backup: the pointer to the registers address array for backup
488 * @backup_size: the size of the registers address array for backup
489 * @realtime_en: the realtime enable register
490 * @realtime_clear: the realtime clear register
491 * @high_prio_en: the high priority enable register
492 * @high_prio_clear: the high priority clear register
493 * @interrupt_en: the interrupt enable register
494 * @interrupt_clear: the interrupt clear register
495 * @il: the pointer to struct d40_interrupt_lookup
496 * @il_size: the size of d40_interrupt_lookup array
497 * @init_reg: the pointer to the struct d40_reg_val
498 * @init_reg_size: the size of d40_reg_val array
499 */
500 struct d40_gen_dmac {
501 u32 *backup;
502 u32 backup_size;
503 u32 realtime_en;
504 u32 realtime_clear;
505 u32 high_prio_en;
506 u32 high_prio_clear;
507 u32 interrupt_en;
508 u32 interrupt_clear;
509 struct d40_interrupt_lookup *il;
510 u32 il_size;
511 struct d40_reg_val *init_reg;
512 u32 init_reg_size;
513 };
514
515 /**
516 * struct d40_base - The big global struct, one for each probe'd instance.
517 *
518 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
519 * @execmd_lock: Lock for execute command usage since several channels share
520 * the same physical register.
521 * @dev: The device structure.
522 * @virtbase: The virtual base address of the DMA's register.
523 * @rev: silicon revision detected.
524 * @clk: Pointer to the DMA clock structure.
525 * @phy_start: Physical memory start of the DMA registers.
526 * @phy_size: Size of the DMA register map.
527 * @irq: The IRQ number.
528 * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
529 * transfers).
530 * @num_phy_chans: The number of physical channels. Read from HW. This
531 * is the number of available channels for this driver, not counting "Secure
532 * mode" allocated physical channels.
533 * @num_log_chans: The number of logical channels. Calculated from
534 * num_phy_chans.
535 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
536 * @dma_slave: dma_device channels that can do only do slave transfers.
537 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
538 * @phy_chans: Room for all possible physical channels in system.
539 * @log_chans: Room for all possible logical channels in system.
540 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
541 * to log_chans entries.
542 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
543 * to phy_chans entries.
544 * @plat_data: Pointer to provided platform_data which is the driver
545 * configuration.
546 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
547 * @phy_res: Vector containing all physical channels.
548 * @lcla_pool: lcla pool settings and data.
549 * @lcpa_base: The virtual mapped address of LCPA.
550 * @phy_lcpa: The physical address of the LCPA.
551 * @lcpa_size: The size of the LCPA area.
552 * @desc_slab: cache for descriptors.
553 * @reg_val_backup: Here the values of some hardware registers are stored
554 * before the DMA is powered off. They are restored when the power is back on.
555 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
556 * later
557 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
558 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
559 * @gen_dmac: the struct for generic registers values to represent u8500/8540
560 * DMA controller
561 */
562 struct d40_base {
563 spinlock_t interrupt_lock;
564 spinlock_t execmd_lock;
565 struct device *dev;
566 void __iomem *virtbase;
567 u8 rev:4;
568 struct clk *clk;
569 phys_addr_t phy_start;
570 resource_size_t phy_size;
571 int irq;
572 int num_memcpy_chans;
573 int num_phy_chans;
574 int num_log_chans;
575 struct device_dma_parameters dma_parms;
576 struct dma_device dma_both;
577 struct dma_device dma_slave;
578 struct dma_device dma_memcpy;
579 struct d40_chan *phy_chans;
580 struct d40_chan *log_chans;
581 struct d40_chan **lookup_log_chans;
582 struct d40_chan **lookup_phy_chans;
583 struct stedma40_platform_data *plat_data;
584 struct regulator *lcpa_regulator;
585 /* Physical half channels */
586 struct d40_phy_res *phy_res;
587 struct d40_lcla_pool lcla_pool;
588 void *lcpa_base;
589 dma_addr_t phy_lcpa;
590 resource_size_t lcpa_size;
591 struct kmem_cache *desc_slab;
592 u32 reg_val_backup[BACKUP_REGS_SZ];
593 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
594 u32 *reg_val_backup_chan;
595 u16 gcc_pwr_off_mask;
596 struct d40_gen_dmac gen_dmac;
597 };
598
599 static struct device *chan2dev(struct d40_chan *d40c)
600 {
601 return &d40c->chan.dev->device;
602 }
603
604 static bool chan_is_physical(struct d40_chan *chan)
605 {
606 return chan->log_num == D40_PHY_CHAN;
607 }
608
609 static bool chan_is_logical(struct d40_chan *chan)
610 {
611 return !chan_is_physical(chan);
612 }
613
614 static void __iomem *chan_base(struct d40_chan *chan)
615 {
616 return chan->base->virtbase + D40_DREG_PCBASE +
617 chan->phy_chan->num * D40_DREG_PCDELTA;
618 }
619
620 #define d40_err(dev, format, arg...) \
621 dev_err(dev, "[%s] " format, __func__, ## arg)
622
623 #define chan_err(d40c, format, arg...) \
624 d40_err(chan2dev(d40c), format, ## arg)
625
626 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
627 int lli_len)
628 {
629 bool is_log = chan_is_logical(d40c);
630 u32 align;
631 void *base;
632
633 if (is_log)
634 align = sizeof(struct d40_log_lli);
635 else
636 align = sizeof(struct d40_phy_lli);
637
638 if (lli_len == 1) {
639 base = d40d->lli_pool.pre_alloc_lli;
640 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
641 d40d->lli_pool.base = NULL;
642 } else {
643 d40d->lli_pool.size = lli_len * 2 * align;
644
645 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
646 d40d->lli_pool.base = base;
647
648 if (d40d->lli_pool.base == NULL)
649 return -ENOMEM;
650 }
651
652 if (is_log) {
653 d40d->lli_log.src = PTR_ALIGN(base, align);
654 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
655
656 d40d->lli_pool.dma_addr = 0;
657 } else {
658 d40d->lli_phy.src = PTR_ALIGN(base, align);
659 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
660
661 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
662 d40d->lli_phy.src,
663 d40d->lli_pool.size,
664 DMA_TO_DEVICE);
665
666 if (dma_mapping_error(d40c->base->dev,
667 d40d->lli_pool.dma_addr)) {
668 kfree(d40d->lli_pool.base);
669 d40d->lli_pool.base = NULL;
670 d40d->lli_pool.dma_addr = 0;
671 return -ENOMEM;
672 }
673 }
674
675 return 0;
676 }
677
678 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
679 {
680 if (d40d->lli_pool.dma_addr)
681 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
682 d40d->lli_pool.size, DMA_TO_DEVICE);
683
684 kfree(d40d->lli_pool.base);
685 d40d->lli_pool.base = NULL;
686 d40d->lli_pool.size = 0;
687 d40d->lli_log.src = NULL;
688 d40d->lli_log.dst = NULL;
689 d40d->lli_phy.src = NULL;
690 d40d->lli_phy.dst = NULL;
691 }
692
693 static int d40_lcla_alloc_one(struct d40_chan *d40c,
694 struct d40_desc *d40d)
695 {
696 unsigned long flags;
697 int i;
698 int ret = -EINVAL;
699
700 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
701
702 /*
703 * Allocate both src and dst at the same time, therefore the half
704 * start on 1 since 0 can't be used since zero is used as end marker.
705 */
706 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
707 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
708
709 if (!d40c->base->lcla_pool.alloc_map[idx]) {
710 d40c->base->lcla_pool.alloc_map[idx] = d40d;
711 d40d->lcla_alloc++;
712 ret = i;
713 break;
714 }
715 }
716
717 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
718
719 return ret;
720 }
721
722 static int d40_lcla_free_all(struct d40_chan *d40c,
723 struct d40_desc *d40d)
724 {
725 unsigned long flags;
726 int i;
727 int ret = -EINVAL;
728
729 if (chan_is_physical(d40c))
730 return 0;
731
732 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
733
734 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
735 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
736
737 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
738 d40c->base->lcla_pool.alloc_map[idx] = NULL;
739 d40d->lcla_alloc--;
740 if (d40d->lcla_alloc == 0) {
741 ret = 0;
742 break;
743 }
744 }
745 }
746
747 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
748
749 return ret;
750
751 }
752
753 static void d40_desc_remove(struct d40_desc *d40d)
754 {
755 list_del(&d40d->node);
756 }
757
758 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
759 {
760 struct d40_desc *desc = NULL;
761
762 if (!list_empty(&d40c->client)) {
763 struct d40_desc *d;
764 struct d40_desc *_d;
765
766 list_for_each_entry_safe(d, _d, &d40c->client, node) {
767 if (async_tx_test_ack(&d->txd)) {
768 d40_desc_remove(d);
769 desc = d;
770 memset(desc, 0, sizeof(*desc));
771 break;
772 }
773 }
774 }
775
776 if (!desc)
777 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
778
779 if (desc)
780 INIT_LIST_HEAD(&desc->node);
781
782 return desc;
783 }
784
785 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
786 {
787
788 d40_pool_lli_free(d40c, d40d);
789 d40_lcla_free_all(d40c, d40d);
790 kmem_cache_free(d40c->base->desc_slab, d40d);
791 }
792
793 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
794 {
795 list_add_tail(&desc->node, &d40c->active);
796 }
797
798 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
799 {
800 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
801 struct d40_phy_lli *lli_src = desc->lli_phy.src;
802 void __iomem *base = chan_base(chan);
803
804 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
805 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
806 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
807 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
808
809 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
810 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
811 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
812 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
813 }
814
815 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
816 {
817 list_add_tail(&desc->node, &d40c->done);
818 }
819
820 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
821 {
822 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
823 struct d40_log_lli_bidir *lli = &desc->lli_log;
824 int lli_current = desc->lli_current;
825 int lli_len = desc->lli_len;
826 bool cyclic = desc->cyclic;
827 int curr_lcla = -EINVAL;
828 int first_lcla = 0;
829 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
830 bool linkback;
831
832 /*
833 * We may have partially running cyclic transfers, in case we did't get
834 * enough LCLA entries.
835 */
836 linkback = cyclic && lli_current == 0;
837
838 /*
839 * For linkback, we need one LCLA even with only one link, because we
840 * can't link back to the one in LCPA space
841 */
842 if (linkback || (lli_len - lli_current > 1)) {
843 /*
844 * If the channel is expected to use only soft_lli don't
845 * allocate a lcla. This is to avoid a HW issue that exists
846 * in some controller during a peripheral to memory transfer
847 * that uses linked lists.
848 */
849 if (!(chan->phy_chan->use_soft_lli &&
850 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
851 curr_lcla = d40_lcla_alloc_one(chan, desc);
852
853 first_lcla = curr_lcla;
854 }
855
856 /*
857 * For linkback, we normally load the LCPA in the loop since we need to
858 * link it to the second LCLA and not the first. However, if we
859 * couldn't even get a first LCLA, then we have to run in LCPA and
860 * reload manually.
861 */
862 if (!linkback || curr_lcla == -EINVAL) {
863 unsigned int flags = 0;
864
865 if (curr_lcla == -EINVAL)
866 flags |= LLI_TERM_INT;
867
868 d40_log_lli_lcpa_write(chan->lcpa,
869 &lli->dst[lli_current],
870 &lli->src[lli_current],
871 curr_lcla,
872 flags);
873 lli_current++;
874 }
875
876 if (curr_lcla < 0)
877 goto set_current;
878
879 for (; lli_current < lli_len; lli_current++) {
880 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
881 8 * curr_lcla * 2;
882 struct d40_log_lli *lcla = pool->base + lcla_offset;
883 unsigned int flags = 0;
884 int next_lcla;
885
886 if (lli_current + 1 < lli_len)
887 next_lcla = d40_lcla_alloc_one(chan, desc);
888 else
889 next_lcla = linkback ? first_lcla : -EINVAL;
890
891 if (cyclic || next_lcla == -EINVAL)
892 flags |= LLI_TERM_INT;
893
894 if (linkback && curr_lcla == first_lcla) {
895 /* First link goes in both LCPA and LCLA */
896 d40_log_lli_lcpa_write(chan->lcpa,
897 &lli->dst[lli_current],
898 &lli->src[lli_current],
899 next_lcla, flags);
900 }
901
902 /*
903 * One unused LCLA in the cyclic case if the very first
904 * next_lcla fails...
905 */
906 d40_log_lli_lcla_write(lcla,
907 &lli->dst[lli_current],
908 &lli->src[lli_current],
909 next_lcla, flags);
910
911 /*
912 * Cache maintenance is not needed if lcla is
913 * mapped in esram
914 */
915 if (!use_esram_lcla) {
916 dma_sync_single_range_for_device(chan->base->dev,
917 pool->dma_addr, lcla_offset,
918 2 * sizeof(struct d40_log_lli),
919 DMA_TO_DEVICE);
920 }
921 curr_lcla = next_lcla;
922
923 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
924 lli_current++;
925 break;
926 }
927 }
928 set_current:
929 desc->lli_current = lli_current;
930 }
931
932 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
933 {
934 if (chan_is_physical(d40c)) {
935 d40_phy_lli_load(d40c, d40d);
936 d40d->lli_current = d40d->lli_len;
937 } else
938 d40_log_lli_to_lcxa(d40c, d40d);
939 }
940
941 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
942 {
943 struct d40_desc *d;
944
945 if (list_empty(&d40c->active))
946 return NULL;
947
948 d = list_first_entry(&d40c->active,
949 struct d40_desc,
950 node);
951 return d;
952 }
953
954 /* remove desc from current queue and add it to the pending_queue */
955 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
956 {
957 d40_desc_remove(desc);
958 desc->is_in_client_list = false;
959 list_add_tail(&desc->node, &d40c->pending_queue);
960 }
961
962 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
963 {
964 struct d40_desc *d;
965
966 if (list_empty(&d40c->pending_queue))
967 return NULL;
968
969 d = list_first_entry(&d40c->pending_queue,
970 struct d40_desc,
971 node);
972 return d;
973 }
974
975 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
976 {
977 struct d40_desc *d;
978
979 if (list_empty(&d40c->queue))
980 return NULL;
981
982 d = list_first_entry(&d40c->queue,
983 struct d40_desc,
984 node);
985 return d;
986 }
987
988 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
989 {
990 if (list_empty(&d40c->done))
991 return NULL;
992
993 return list_first_entry(&d40c->done, struct d40_desc, node);
994 }
995
996 static int d40_psize_2_burst_size(bool is_log, int psize)
997 {
998 if (is_log) {
999 if (psize == STEDMA40_PSIZE_LOG_1)
1000 return 1;
1001 } else {
1002 if (psize == STEDMA40_PSIZE_PHY_1)
1003 return 1;
1004 }
1005
1006 return 2 << psize;
1007 }
1008
1009 /*
1010 * The dma only supports transmitting packages up to
1011 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1012 *
1013 * Calculate the total number of dma elements required to send the entire sg list.
1014 */
1015 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1016 {
1017 int dmalen;
1018 u32 max_w = max(data_width1, data_width2);
1019 u32 min_w = min(data_width1, data_width2);
1020 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
1021
1022 if (seg_max > STEDMA40_MAX_SEG_SIZE)
1023 seg_max -= max_w;
1024
1025 if (!IS_ALIGNED(size, max_w))
1026 return -EINVAL;
1027
1028 if (size <= seg_max)
1029 dmalen = 1;
1030 else {
1031 dmalen = size / seg_max;
1032 if (dmalen * seg_max < size)
1033 dmalen++;
1034 }
1035 return dmalen;
1036 }
1037
1038 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1039 u32 data_width1, u32 data_width2)
1040 {
1041 struct scatterlist *sg;
1042 int i;
1043 int len = 0;
1044 int ret;
1045
1046 for_each_sg(sgl, sg, sg_len, i) {
1047 ret = d40_size_2_dmalen(sg_dma_len(sg),
1048 data_width1, data_width2);
1049 if (ret < 0)
1050 return ret;
1051 len += ret;
1052 }
1053 return len;
1054 }
1055
1056 static int __d40_execute_command_phy(struct d40_chan *d40c,
1057 enum d40_command command)
1058 {
1059 u32 status;
1060 int i;
1061 void __iomem *active_reg;
1062 int ret = 0;
1063 unsigned long flags;
1064 u32 wmask;
1065
1066 if (command == D40_DMA_STOP) {
1067 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1068 if (ret)
1069 return ret;
1070 }
1071
1072 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1073
1074 if (d40c->phy_chan->num % 2 == 0)
1075 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1076 else
1077 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1078
1079 if (command == D40_DMA_SUSPEND_REQ) {
1080 status = (readl(active_reg) &
1081 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1082 D40_CHAN_POS(d40c->phy_chan->num);
1083
1084 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1085 goto unlock;
1086 }
1087
1088 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1089 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1090 active_reg);
1091
1092 if (command == D40_DMA_SUSPEND_REQ) {
1093
1094 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1095 status = (readl(active_reg) &
1096 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1097 D40_CHAN_POS(d40c->phy_chan->num);
1098
1099 cpu_relax();
1100 /*
1101 * Reduce the number of bus accesses while
1102 * waiting for the DMA to suspend.
1103 */
1104 udelay(3);
1105
1106 if (status == D40_DMA_STOP ||
1107 status == D40_DMA_SUSPENDED)
1108 break;
1109 }
1110
1111 if (i == D40_SUSPEND_MAX_IT) {
1112 chan_err(d40c,
1113 "unable to suspend the chl %d (log: %d) status %x\n",
1114 d40c->phy_chan->num, d40c->log_num,
1115 status);
1116 dump_stack();
1117 ret = -EBUSY;
1118 }
1119
1120 }
1121 unlock:
1122 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1123 return ret;
1124 }
1125
1126 static void d40_term_all(struct d40_chan *d40c)
1127 {
1128 struct d40_desc *d40d;
1129 struct d40_desc *_d;
1130
1131 /* Release completed descriptors */
1132 while ((d40d = d40_first_done(d40c))) {
1133 d40_desc_remove(d40d);
1134 d40_desc_free(d40c, d40d);
1135 }
1136
1137 /* Release active descriptors */
1138 while ((d40d = d40_first_active_get(d40c))) {
1139 d40_desc_remove(d40d);
1140 d40_desc_free(d40c, d40d);
1141 }
1142
1143 /* Release queued descriptors waiting for transfer */
1144 while ((d40d = d40_first_queued(d40c))) {
1145 d40_desc_remove(d40d);
1146 d40_desc_free(d40c, d40d);
1147 }
1148
1149 /* Release pending descriptors */
1150 while ((d40d = d40_first_pending(d40c))) {
1151 d40_desc_remove(d40d);
1152 d40_desc_free(d40c, d40d);
1153 }
1154
1155 /* Release client owned descriptors */
1156 if (!list_empty(&d40c->client))
1157 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1158 d40_desc_remove(d40d);
1159 d40_desc_free(d40c, d40d);
1160 }
1161
1162 /* Release descriptors in prepare queue */
1163 if (!list_empty(&d40c->prepare_queue))
1164 list_for_each_entry_safe(d40d, _d,
1165 &d40c->prepare_queue, node) {
1166 d40_desc_remove(d40d);
1167 d40_desc_free(d40c, d40d);
1168 }
1169
1170 d40c->pending_tx = 0;
1171 }
1172
1173 static void __d40_config_set_event(struct d40_chan *d40c,
1174 enum d40_events event_type, u32 event,
1175 int reg)
1176 {
1177 void __iomem *addr = chan_base(d40c) + reg;
1178 int tries;
1179 u32 status;
1180
1181 switch (event_type) {
1182
1183 case D40_DEACTIVATE_EVENTLINE:
1184
1185 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1186 | ~D40_EVENTLINE_MASK(event), addr);
1187 break;
1188
1189 case D40_SUSPEND_REQ_EVENTLINE:
1190 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1191 D40_EVENTLINE_POS(event);
1192
1193 if (status == D40_DEACTIVATE_EVENTLINE ||
1194 status == D40_SUSPEND_REQ_EVENTLINE)
1195 break;
1196
1197 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1198 | ~D40_EVENTLINE_MASK(event), addr);
1199
1200 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1201
1202 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1203 D40_EVENTLINE_POS(event);
1204
1205 cpu_relax();
1206 /*
1207 * Reduce the number of bus accesses while
1208 * waiting for the DMA to suspend.
1209 */
1210 udelay(3);
1211
1212 if (status == D40_DEACTIVATE_EVENTLINE)
1213 break;
1214 }
1215
1216 if (tries == D40_SUSPEND_MAX_IT) {
1217 chan_err(d40c,
1218 "unable to stop the event_line chl %d (log: %d)"
1219 "status %x\n", d40c->phy_chan->num,
1220 d40c->log_num, status);
1221 }
1222 break;
1223
1224 case D40_ACTIVATE_EVENTLINE:
1225 /*
1226 * The hardware sometimes doesn't register the enable when src and dst
1227 * event lines are active on the same logical channel. Retry to ensure
1228 * it does. Usually only one retry is sufficient.
1229 */
1230 tries = 100;
1231 while (--tries) {
1232 writel((D40_ACTIVATE_EVENTLINE <<
1233 D40_EVENTLINE_POS(event)) |
1234 ~D40_EVENTLINE_MASK(event), addr);
1235
1236 if (readl(addr) & D40_EVENTLINE_MASK(event))
1237 break;
1238 }
1239
1240 if (tries != 99)
1241 dev_dbg(chan2dev(d40c),
1242 "[%s] workaround enable S%cLNK (%d tries)\n",
1243 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1244 100 - tries);
1245
1246 WARN_ON(!tries);
1247 break;
1248
1249 case D40_ROUND_EVENTLINE:
1250 BUG();
1251 break;
1252
1253 }
1254 }
1255
1256 static void d40_config_set_event(struct d40_chan *d40c,
1257 enum d40_events event_type)
1258 {
1259 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1260
1261 /* Enable event line connected to device (or memcpy) */
1262 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1263 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1264 __d40_config_set_event(d40c, event_type, event,
1265 D40_CHAN_REG_SSLNK);
1266
1267 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1268 __d40_config_set_event(d40c, event_type, event,
1269 D40_CHAN_REG_SDLNK);
1270 }
1271
1272 static u32 d40_chan_has_events(struct d40_chan *d40c)
1273 {
1274 void __iomem *chanbase = chan_base(d40c);
1275 u32 val;
1276
1277 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1278 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1279
1280 return val;
1281 }
1282
1283 static int
1284 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1285 {
1286 unsigned long flags;
1287 int ret = 0;
1288 u32 active_status;
1289 void __iomem *active_reg;
1290
1291 if (d40c->phy_chan->num % 2 == 0)
1292 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1293 else
1294 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1295
1296
1297 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1298
1299 switch (command) {
1300 case D40_DMA_STOP:
1301 case D40_DMA_SUSPEND_REQ:
1302
1303 active_status = (readl(active_reg) &
1304 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1305 D40_CHAN_POS(d40c->phy_chan->num);
1306
1307 if (active_status == D40_DMA_RUN)
1308 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1309 else
1310 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1311
1312 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1313 ret = __d40_execute_command_phy(d40c, command);
1314
1315 break;
1316
1317 case D40_DMA_RUN:
1318
1319 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1320 ret = __d40_execute_command_phy(d40c, command);
1321 break;
1322
1323 case D40_DMA_SUSPENDED:
1324 BUG();
1325 break;
1326 }
1327
1328 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1329 return ret;
1330 }
1331
1332 static int d40_channel_execute_command(struct d40_chan *d40c,
1333 enum d40_command command)
1334 {
1335 if (chan_is_logical(d40c))
1336 return __d40_execute_command_log(d40c, command);
1337 else
1338 return __d40_execute_command_phy(d40c, command);
1339 }
1340
1341 static u32 d40_get_prmo(struct d40_chan *d40c)
1342 {
1343 static const unsigned int phy_map[] = {
1344 [STEDMA40_PCHAN_BASIC_MODE]
1345 = D40_DREG_PRMO_PCHAN_BASIC,
1346 [STEDMA40_PCHAN_MODULO_MODE]
1347 = D40_DREG_PRMO_PCHAN_MODULO,
1348 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1349 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1350 };
1351 static const unsigned int log_map[] = {
1352 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1353 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1354 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1355 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1356 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1357 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1358 };
1359
1360 if (chan_is_physical(d40c))
1361 return phy_map[d40c->dma_cfg.mode_opt];
1362 else
1363 return log_map[d40c->dma_cfg.mode_opt];
1364 }
1365
1366 static void d40_config_write(struct d40_chan *d40c)
1367 {
1368 u32 addr_base;
1369 u32 var;
1370
1371 /* Odd addresses are even addresses + 4 */
1372 addr_base = (d40c->phy_chan->num % 2) * 4;
1373 /* Setup channel mode to logical or physical */
1374 var = ((u32)(chan_is_logical(d40c)) + 1) <<
1375 D40_CHAN_POS(d40c->phy_chan->num);
1376 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1377
1378 /* Setup operational mode option register */
1379 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1380
1381 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1382
1383 if (chan_is_logical(d40c)) {
1384 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1385 & D40_SREG_ELEM_LOG_LIDX_MASK;
1386 void __iomem *chanbase = chan_base(d40c);
1387
1388 /* Set default config for CFG reg */
1389 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1390 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1391
1392 /* Set LIDX for lcla */
1393 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1394 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1395
1396 /* Clear LNK which will be used by d40_chan_has_events() */
1397 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1398 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1399 }
1400 }
1401
1402 static u32 d40_residue(struct d40_chan *d40c)
1403 {
1404 u32 num_elt;
1405
1406 if (chan_is_logical(d40c))
1407 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1408 >> D40_MEM_LCSP2_ECNT_POS;
1409 else {
1410 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1411 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1412 >> D40_SREG_ELEM_PHY_ECNT_POS;
1413 }
1414
1415 return num_elt * d40c->dma_cfg.dst_info.data_width;
1416 }
1417
1418 static bool d40_tx_is_linked(struct d40_chan *d40c)
1419 {
1420 bool is_link;
1421
1422 if (chan_is_logical(d40c))
1423 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1424 else
1425 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1426 & D40_SREG_LNK_PHYS_LNK_MASK;
1427
1428 return is_link;
1429 }
1430
1431 static int d40_pause(struct dma_chan *chan)
1432 {
1433 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1434 int res = 0;
1435 unsigned long flags;
1436
1437 if (d40c->phy_chan == NULL) {
1438 chan_err(d40c, "Channel is not allocated!\n");
1439 return -EINVAL;
1440 }
1441
1442 if (!d40c->busy)
1443 return 0;
1444
1445 spin_lock_irqsave(&d40c->lock, flags);
1446 pm_runtime_get_sync(d40c->base->dev);
1447
1448 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1449
1450 pm_runtime_mark_last_busy(d40c->base->dev);
1451 pm_runtime_put_autosuspend(d40c->base->dev);
1452 spin_unlock_irqrestore(&d40c->lock, flags);
1453 return res;
1454 }
1455
1456 static int d40_resume(struct dma_chan *chan)
1457 {
1458 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1459 int res = 0;
1460 unsigned long flags;
1461
1462 if (d40c->phy_chan == NULL) {
1463 chan_err(d40c, "Channel is not allocated!\n");
1464 return -EINVAL;
1465 }
1466
1467 if (!d40c->busy)
1468 return 0;
1469
1470 spin_lock_irqsave(&d40c->lock, flags);
1471 pm_runtime_get_sync(d40c->base->dev);
1472
1473 /* If bytes left to transfer or linked tx resume job */
1474 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1475 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1476
1477 pm_runtime_mark_last_busy(d40c->base->dev);
1478 pm_runtime_put_autosuspend(d40c->base->dev);
1479 spin_unlock_irqrestore(&d40c->lock, flags);
1480 return res;
1481 }
1482
1483 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1484 {
1485 struct d40_chan *d40c = container_of(tx->chan,
1486 struct d40_chan,
1487 chan);
1488 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1489 unsigned long flags;
1490 dma_cookie_t cookie;
1491
1492 spin_lock_irqsave(&d40c->lock, flags);
1493 cookie = dma_cookie_assign(tx);
1494 d40_desc_queue(d40c, d40d);
1495 spin_unlock_irqrestore(&d40c->lock, flags);
1496
1497 return cookie;
1498 }
1499
1500 static int d40_start(struct d40_chan *d40c)
1501 {
1502 return d40_channel_execute_command(d40c, D40_DMA_RUN);
1503 }
1504
1505 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1506 {
1507 struct d40_desc *d40d;
1508 int err;
1509
1510 /* Start queued jobs, if any */
1511 d40d = d40_first_queued(d40c);
1512
1513 if (d40d != NULL) {
1514 if (!d40c->busy) {
1515 d40c->busy = true;
1516 pm_runtime_get_sync(d40c->base->dev);
1517 }
1518
1519 /* Remove from queue */
1520 d40_desc_remove(d40d);
1521
1522 /* Add to active queue */
1523 d40_desc_submit(d40c, d40d);
1524
1525 /* Initiate DMA job */
1526 d40_desc_load(d40c, d40d);
1527
1528 /* Start dma job */
1529 err = d40_start(d40c);
1530
1531 if (err)
1532 return NULL;
1533 }
1534
1535 return d40d;
1536 }
1537
1538 /* called from interrupt context */
1539 static void dma_tc_handle(struct d40_chan *d40c)
1540 {
1541 struct d40_desc *d40d;
1542
1543 /* Get first active entry from list */
1544 d40d = d40_first_active_get(d40c);
1545
1546 if (d40d == NULL)
1547 return;
1548
1549 if (d40d->cyclic) {
1550 /*
1551 * If this was a paritially loaded list, we need to reloaded
1552 * it, and only when the list is completed. We need to check
1553 * for done because the interrupt will hit for every link, and
1554 * not just the last one.
1555 */
1556 if (d40d->lli_current < d40d->lli_len
1557 && !d40_tx_is_linked(d40c)
1558 && !d40_residue(d40c)) {
1559 d40_lcla_free_all(d40c, d40d);
1560 d40_desc_load(d40c, d40d);
1561 (void) d40_start(d40c);
1562
1563 if (d40d->lli_current == d40d->lli_len)
1564 d40d->lli_current = 0;
1565 }
1566 } else {
1567 d40_lcla_free_all(d40c, d40d);
1568
1569 if (d40d->lli_current < d40d->lli_len) {
1570 d40_desc_load(d40c, d40d);
1571 /* Start dma job */
1572 (void) d40_start(d40c);
1573 return;
1574 }
1575
1576 if (d40_queue_start(d40c) == NULL) {
1577 d40c->busy = false;
1578
1579 pm_runtime_mark_last_busy(d40c->base->dev);
1580 pm_runtime_put_autosuspend(d40c->base->dev);
1581 }
1582
1583 d40_desc_remove(d40d);
1584 d40_desc_done(d40c, d40d);
1585 }
1586
1587 d40c->pending_tx++;
1588 tasklet_schedule(&d40c->tasklet);
1589
1590 }
1591
1592 static void dma_tasklet(unsigned long data)
1593 {
1594 struct d40_chan *d40c = (struct d40_chan *) data;
1595 struct d40_desc *d40d;
1596 unsigned long flags;
1597 bool callback_active;
1598 dma_async_tx_callback callback;
1599 void *callback_param;
1600
1601 spin_lock_irqsave(&d40c->lock, flags);
1602
1603 /* Get first entry from the done list */
1604 d40d = d40_first_done(d40c);
1605 if (d40d == NULL) {
1606 /* Check if we have reached here for cyclic job */
1607 d40d = d40_first_active_get(d40c);
1608 if (d40d == NULL || !d40d->cyclic)
1609 goto check_pending_tx;
1610 }
1611
1612 if (!d40d->cyclic)
1613 dma_cookie_complete(&d40d->txd);
1614
1615 /*
1616 * If terminating a channel pending_tx is set to zero.
1617 * This prevents any finished active jobs to return to the client.
1618 */
1619 if (d40c->pending_tx == 0) {
1620 spin_unlock_irqrestore(&d40c->lock, flags);
1621 return;
1622 }
1623
1624 /* Callback to client */
1625 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
1626 callback = d40d->txd.callback;
1627 callback_param = d40d->txd.callback_param;
1628
1629 if (!d40d->cyclic) {
1630 if (async_tx_test_ack(&d40d->txd)) {
1631 d40_desc_remove(d40d);
1632 d40_desc_free(d40c, d40d);
1633 } else if (!d40d->is_in_client_list) {
1634 d40_desc_remove(d40d);
1635 d40_lcla_free_all(d40c, d40d);
1636 list_add_tail(&d40d->node, &d40c->client);
1637 d40d->is_in_client_list = true;
1638 }
1639 }
1640
1641 d40c->pending_tx--;
1642
1643 if (d40c->pending_tx)
1644 tasklet_schedule(&d40c->tasklet);
1645
1646 spin_unlock_irqrestore(&d40c->lock, flags);
1647
1648 if (callback_active && callback)
1649 callback(callback_param);
1650
1651 return;
1652 check_pending_tx:
1653 /* Rescue manouver if receiving double interrupts */
1654 if (d40c->pending_tx > 0)
1655 d40c->pending_tx--;
1656 spin_unlock_irqrestore(&d40c->lock, flags);
1657 }
1658
1659 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1660 {
1661 int i;
1662 u32 idx;
1663 u32 row;
1664 long chan = -1;
1665 struct d40_chan *d40c;
1666 unsigned long flags;
1667 struct d40_base *base = data;
1668 u32 regs[base->gen_dmac.il_size];
1669 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1670 u32 il_size = base->gen_dmac.il_size;
1671
1672 spin_lock_irqsave(&base->interrupt_lock, flags);
1673
1674 /* Read interrupt status of both logical and physical channels */
1675 for (i = 0; i < il_size; i++)
1676 regs[i] = readl(base->virtbase + il[i].src);
1677
1678 for (;;) {
1679
1680 chan = find_next_bit((unsigned long *)regs,
1681 BITS_PER_LONG * il_size, chan + 1);
1682
1683 /* No more set bits found? */
1684 if (chan == BITS_PER_LONG * il_size)
1685 break;
1686
1687 row = chan / BITS_PER_LONG;
1688 idx = chan & (BITS_PER_LONG - 1);
1689
1690 if (il[row].offset == D40_PHY_CHAN)
1691 d40c = base->lookup_phy_chans[idx];
1692 else
1693 d40c = base->lookup_log_chans[il[row].offset + idx];
1694
1695 if (!d40c) {
1696 /*
1697 * No error because this can happen if something else
1698 * in the system is using the channel.
1699 */
1700 continue;
1701 }
1702
1703 /* ACK interrupt */
1704 writel(BIT(idx), base->virtbase + il[row].clr);
1705
1706 spin_lock(&d40c->lock);
1707
1708 if (!il[row].is_error)
1709 dma_tc_handle(d40c);
1710 else
1711 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1712 chan, il[row].offset, idx);
1713
1714 spin_unlock(&d40c->lock);
1715 }
1716
1717 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1718
1719 return IRQ_HANDLED;
1720 }
1721
1722 static int d40_validate_conf(struct d40_chan *d40c,
1723 struct stedma40_chan_cfg *conf)
1724 {
1725 int res = 0;
1726 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1727
1728 if (!conf->dir) {
1729 chan_err(d40c, "Invalid direction.\n");
1730 res = -EINVAL;
1731 }
1732
1733 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1734 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1735 (conf->dev_type < 0)) {
1736 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1737 res = -EINVAL;
1738 }
1739
1740 if (conf->dir == DMA_DEV_TO_DEV) {
1741 /*
1742 * DMAC HW supports it. Will be added to this driver,
1743 * in case any dma client requires it.
1744 */
1745 chan_err(d40c, "periph to periph not supported\n");
1746 res = -EINVAL;
1747 }
1748
1749 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1750 conf->src_info.data_width !=
1751 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1752 conf->dst_info.data_width) {
1753 /*
1754 * The DMAC hardware only supports
1755 * src (burst x width) == dst (burst x width)
1756 */
1757
1758 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1759 res = -EINVAL;
1760 }
1761
1762 return res;
1763 }
1764
1765 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1766 bool is_src, int log_event_line, bool is_log,
1767 bool *first_user)
1768 {
1769 unsigned long flags;
1770 spin_lock_irqsave(&phy->lock, flags);
1771
1772 *first_user = ((phy->allocated_src | phy->allocated_dst)
1773 == D40_ALLOC_FREE);
1774
1775 if (!is_log) {
1776 /* Physical interrupts are masked per physical full channel */
1777 if (phy->allocated_src == D40_ALLOC_FREE &&
1778 phy->allocated_dst == D40_ALLOC_FREE) {
1779 phy->allocated_dst = D40_ALLOC_PHY;
1780 phy->allocated_src = D40_ALLOC_PHY;
1781 goto found_unlock;
1782 } else
1783 goto not_found_unlock;
1784 }
1785
1786 /* Logical channel */
1787 if (is_src) {
1788 if (phy->allocated_src == D40_ALLOC_PHY)
1789 goto not_found_unlock;
1790
1791 if (phy->allocated_src == D40_ALLOC_FREE)
1792 phy->allocated_src = D40_ALLOC_LOG_FREE;
1793
1794 if (!(phy->allocated_src & BIT(log_event_line))) {
1795 phy->allocated_src |= BIT(log_event_line);
1796 goto found_unlock;
1797 } else
1798 goto not_found_unlock;
1799 } else {
1800 if (phy->allocated_dst == D40_ALLOC_PHY)
1801 goto not_found_unlock;
1802
1803 if (phy->allocated_dst == D40_ALLOC_FREE)
1804 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1805
1806 if (!(phy->allocated_dst & BIT(log_event_line))) {
1807 phy->allocated_dst |= BIT(log_event_line);
1808 goto found_unlock;
1809 }
1810 }
1811 not_found_unlock:
1812 spin_unlock_irqrestore(&phy->lock, flags);
1813 return false;
1814 found_unlock:
1815 spin_unlock_irqrestore(&phy->lock, flags);
1816 return true;
1817 }
1818
1819 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1820 int log_event_line)
1821 {
1822 unsigned long flags;
1823 bool is_free = false;
1824
1825 spin_lock_irqsave(&phy->lock, flags);
1826 if (!log_event_line) {
1827 phy->allocated_dst = D40_ALLOC_FREE;
1828 phy->allocated_src = D40_ALLOC_FREE;
1829 is_free = true;
1830 goto unlock;
1831 }
1832
1833 /* Logical channel */
1834 if (is_src) {
1835 phy->allocated_src &= ~BIT(log_event_line);
1836 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1837 phy->allocated_src = D40_ALLOC_FREE;
1838 } else {
1839 phy->allocated_dst &= ~BIT(log_event_line);
1840 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1841 phy->allocated_dst = D40_ALLOC_FREE;
1842 }
1843
1844 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1845 D40_ALLOC_FREE);
1846 unlock:
1847 spin_unlock_irqrestore(&phy->lock, flags);
1848
1849 return is_free;
1850 }
1851
1852 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1853 {
1854 int dev_type = d40c->dma_cfg.dev_type;
1855 int event_group;
1856 int event_line;
1857 struct d40_phy_res *phys;
1858 int i;
1859 int j;
1860 int log_num;
1861 int num_phy_chans;
1862 bool is_src;
1863 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1864
1865 phys = d40c->base->phy_res;
1866 num_phy_chans = d40c->base->num_phy_chans;
1867
1868 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1869 log_num = 2 * dev_type;
1870 is_src = true;
1871 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1872 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1873 /* dst event lines are used for logical memcpy */
1874 log_num = 2 * dev_type + 1;
1875 is_src = false;
1876 } else
1877 return -EINVAL;
1878
1879 event_group = D40_TYPE_TO_GROUP(dev_type);
1880 event_line = D40_TYPE_TO_EVENT(dev_type);
1881
1882 if (!is_log) {
1883 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1884 /* Find physical half channel */
1885 if (d40c->dma_cfg.use_fixed_channel) {
1886 i = d40c->dma_cfg.phy_channel;
1887 if (d40_alloc_mask_set(&phys[i], is_src,
1888 0, is_log,
1889 first_phy_user))
1890 goto found_phy;
1891 } else {
1892 for (i = 0; i < num_phy_chans; i++) {
1893 if (d40_alloc_mask_set(&phys[i], is_src,
1894 0, is_log,
1895 first_phy_user))
1896 goto found_phy;
1897 }
1898 }
1899 } else
1900 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1901 int phy_num = j + event_group * 2;
1902 for (i = phy_num; i < phy_num + 2; i++) {
1903 if (d40_alloc_mask_set(&phys[i],
1904 is_src,
1905 0,
1906 is_log,
1907 first_phy_user))
1908 goto found_phy;
1909 }
1910 }
1911 return -EINVAL;
1912 found_phy:
1913 d40c->phy_chan = &phys[i];
1914 d40c->log_num = D40_PHY_CHAN;
1915 goto out;
1916 }
1917 if (dev_type == -1)
1918 return -EINVAL;
1919
1920 /* Find logical channel */
1921 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1922 int phy_num = j + event_group * 2;
1923
1924 if (d40c->dma_cfg.use_fixed_channel) {
1925 i = d40c->dma_cfg.phy_channel;
1926
1927 if ((i != phy_num) && (i != phy_num + 1)) {
1928 dev_err(chan2dev(d40c),
1929 "invalid fixed phy channel %d\n", i);
1930 return -EINVAL;
1931 }
1932
1933 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1934 is_log, first_phy_user))
1935 goto found_log;
1936
1937 dev_err(chan2dev(d40c),
1938 "could not allocate fixed phy channel %d\n", i);
1939 return -EINVAL;
1940 }
1941
1942 /*
1943 * Spread logical channels across all available physical rather
1944 * than pack every logical channel at the first available phy
1945 * channels.
1946 */
1947 if (is_src) {
1948 for (i = phy_num; i < phy_num + 2; i++) {
1949 if (d40_alloc_mask_set(&phys[i], is_src,
1950 event_line, is_log,
1951 first_phy_user))
1952 goto found_log;
1953 }
1954 } else {
1955 for (i = phy_num + 1; i >= phy_num; i--) {
1956 if (d40_alloc_mask_set(&phys[i], is_src,
1957 event_line, is_log,
1958 first_phy_user))
1959 goto found_log;
1960 }
1961 }
1962 }
1963 return -EINVAL;
1964
1965 found_log:
1966 d40c->phy_chan = &phys[i];
1967 d40c->log_num = log_num;
1968 out:
1969
1970 if (is_log)
1971 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1972 else
1973 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1974
1975 return 0;
1976
1977 }
1978
1979 static int d40_config_memcpy(struct d40_chan *d40c)
1980 {
1981 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1982
1983 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1984 d40c->dma_cfg = dma40_memcpy_conf_log;
1985 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
1986
1987 d40_log_cfg(&d40c->dma_cfg,
1988 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1989
1990 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1991 dma_has_cap(DMA_SLAVE, cap)) {
1992 d40c->dma_cfg = dma40_memcpy_conf_phy;
1993
1994 /* Generate interrrupt at end of transfer or relink. */
1995 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
1996
1997 /* Generate interrupt on error. */
1998 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
1999 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2000
2001 } else {
2002 chan_err(d40c, "No memcpy\n");
2003 return -EINVAL;
2004 }
2005
2006 return 0;
2007 }
2008
2009 static int d40_free_dma(struct d40_chan *d40c)
2010 {
2011
2012 int res = 0;
2013 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2014 struct d40_phy_res *phy = d40c->phy_chan;
2015 bool is_src;
2016
2017 /* Terminate all queued and active transfers */
2018 d40_term_all(d40c);
2019
2020 if (phy == NULL) {
2021 chan_err(d40c, "phy == null\n");
2022 return -EINVAL;
2023 }
2024
2025 if (phy->allocated_src == D40_ALLOC_FREE &&
2026 phy->allocated_dst == D40_ALLOC_FREE) {
2027 chan_err(d40c, "channel already free\n");
2028 return -EINVAL;
2029 }
2030
2031 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2032 d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2033 is_src = false;
2034 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2035 is_src = true;
2036 else {
2037 chan_err(d40c, "Unknown direction\n");
2038 return -EINVAL;
2039 }
2040
2041 pm_runtime_get_sync(d40c->base->dev);
2042 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2043 if (res) {
2044 chan_err(d40c, "stop failed\n");
2045 goto mark_last_busy;
2046 }
2047
2048 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2049
2050 if (chan_is_logical(d40c))
2051 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2052 else
2053 d40c->base->lookup_phy_chans[phy->num] = NULL;
2054
2055 if (d40c->busy) {
2056 pm_runtime_mark_last_busy(d40c->base->dev);
2057 pm_runtime_put_autosuspend(d40c->base->dev);
2058 }
2059
2060 d40c->busy = false;
2061 d40c->phy_chan = NULL;
2062 d40c->configured = false;
2063 mark_last_busy:
2064 pm_runtime_mark_last_busy(d40c->base->dev);
2065 pm_runtime_put_autosuspend(d40c->base->dev);
2066 return res;
2067 }
2068
2069 static bool d40_is_paused(struct d40_chan *d40c)
2070 {
2071 void __iomem *chanbase = chan_base(d40c);
2072 bool is_paused = false;
2073 unsigned long flags;
2074 void __iomem *active_reg;
2075 u32 status;
2076 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2077
2078 spin_lock_irqsave(&d40c->lock, flags);
2079
2080 if (chan_is_physical(d40c)) {
2081 if (d40c->phy_chan->num % 2 == 0)
2082 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2083 else
2084 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2085
2086 status = (readl(active_reg) &
2087 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2088 D40_CHAN_POS(d40c->phy_chan->num);
2089 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2090 is_paused = true;
2091 goto unlock;
2092 }
2093
2094 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2095 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2096 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2097 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2098 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2099 } else {
2100 chan_err(d40c, "Unknown direction\n");
2101 goto unlock;
2102 }
2103
2104 status = (status & D40_EVENTLINE_MASK(event)) >>
2105 D40_EVENTLINE_POS(event);
2106
2107 if (status != D40_DMA_RUN)
2108 is_paused = true;
2109 unlock:
2110 spin_unlock_irqrestore(&d40c->lock, flags);
2111 return is_paused;
2112
2113 }
2114
2115 static u32 stedma40_residue(struct dma_chan *chan)
2116 {
2117 struct d40_chan *d40c =
2118 container_of(chan, struct d40_chan, chan);
2119 u32 bytes_left;
2120 unsigned long flags;
2121
2122 spin_lock_irqsave(&d40c->lock, flags);
2123 bytes_left = d40_residue(d40c);
2124 spin_unlock_irqrestore(&d40c->lock, flags);
2125
2126 return bytes_left;
2127 }
2128
2129 static int
2130 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2131 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2132 unsigned int sg_len, dma_addr_t src_dev_addr,
2133 dma_addr_t dst_dev_addr)
2134 {
2135 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2136 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2137 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2138 int ret;
2139
2140 ret = d40_log_sg_to_lli(sg_src, sg_len,
2141 src_dev_addr,
2142 desc->lli_log.src,
2143 chan->log_def.lcsp1,
2144 src_info->data_width,
2145 dst_info->data_width);
2146
2147 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2148 dst_dev_addr,
2149 desc->lli_log.dst,
2150 chan->log_def.lcsp3,
2151 dst_info->data_width,
2152 src_info->data_width);
2153
2154 return ret < 0 ? ret : 0;
2155 }
2156
2157 static int
2158 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2159 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2160 unsigned int sg_len, dma_addr_t src_dev_addr,
2161 dma_addr_t dst_dev_addr)
2162 {
2163 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2164 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2165 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2166 unsigned long flags = 0;
2167 int ret;
2168
2169 if (desc->cyclic)
2170 flags |= LLI_CYCLIC | LLI_TERM_INT;
2171
2172 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2173 desc->lli_phy.src,
2174 virt_to_phys(desc->lli_phy.src),
2175 chan->src_def_cfg,
2176 src_info, dst_info, flags);
2177
2178 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2179 desc->lli_phy.dst,
2180 virt_to_phys(desc->lli_phy.dst),
2181 chan->dst_def_cfg,
2182 dst_info, src_info, flags);
2183
2184 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2185 desc->lli_pool.size, DMA_TO_DEVICE);
2186
2187 return ret < 0 ? ret : 0;
2188 }
2189
2190 static struct d40_desc *
2191 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2192 unsigned int sg_len, unsigned long dma_flags)
2193 {
2194 struct stedma40_chan_cfg *cfg;
2195 struct d40_desc *desc;
2196 int ret;
2197
2198 desc = d40_desc_get(chan);
2199 if (!desc)
2200 return NULL;
2201
2202 cfg = &chan->dma_cfg;
2203 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2204 cfg->dst_info.data_width);
2205 if (desc->lli_len < 0) {
2206 chan_err(chan, "Unaligned size\n");
2207 goto free_desc;
2208 }
2209
2210 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2211 if (ret < 0) {
2212 chan_err(chan, "Could not allocate lli\n");
2213 goto free_desc;
2214 }
2215
2216 desc->lli_current = 0;
2217 desc->txd.flags = dma_flags;
2218 desc->txd.tx_submit = d40_tx_submit;
2219
2220 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2221
2222 return desc;
2223 free_desc:
2224 d40_desc_free(chan, desc);
2225 return NULL;
2226 }
2227
2228 static struct dma_async_tx_descriptor *
2229 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2230 struct scatterlist *sg_dst, unsigned int sg_len,
2231 enum dma_transfer_direction direction, unsigned long dma_flags)
2232 {
2233 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2234 dma_addr_t src_dev_addr;
2235 dma_addr_t dst_dev_addr;
2236 struct d40_desc *desc;
2237 unsigned long flags;
2238 int ret;
2239
2240 if (!chan->phy_chan) {
2241 chan_err(chan, "Cannot prepare unallocated channel\n");
2242 return NULL;
2243 }
2244
2245 spin_lock_irqsave(&chan->lock, flags);
2246
2247 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2248 if (desc == NULL)
2249 goto unlock;
2250
2251 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2252 desc->cyclic = true;
2253
2254 src_dev_addr = 0;
2255 dst_dev_addr = 0;
2256 if (direction == DMA_DEV_TO_MEM)
2257 src_dev_addr = chan->runtime_addr;
2258 else if (direction == DMA_MEM_TO_DEV)
2259 dst_dev_addr = chan->runtime_addr;
2260
2261 if (chan_is_logical(chan))
2262 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2263 sg_len, src_dev_addr, dst_dev_addr);
2264 else
2265 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2266 sg_len, src_dev_addr, dst_dev_addr);
2267
2268 if (ret) {
2269 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2270 chan_is_logical(chan) ? "log" : "phy", ret);
2271 goto free_desc;
2272 }
2273
2274 /*
2275 * add descriptor to the prepare queue in order to be able
2276 * to free them later in terminate_all
2277 */
2278 list_add_tail(&desc->node, &chan->prepare_queue);
2279
2280 spin_unlock_irqrestore(&chan->lock, flags);
2281
2282 return &desc->txd;
2283 free_desc:
2284 d40_desc_free(chan, desc);
2285 unlock:
2286 spin_unlock_irqrestore(&chan->lock, flags);
2287 return NULL;
2288 }
2289
2290 bool stedma40_filter(struct dma_chan *chan, void *data)
2291 {
2292 struct stedma40_chan_cfg *info = data;
2293 struct d40_chan *d40c =
2294 container_of(chan, struct d40_chan, chan);
2295 int err;
2296
2297 if (data) {
2298 err = d40_validate_conf(d40c, info);
2299 if (!err)
2300 d40c->dma_cfg = *info;
2301 } else
2302 err = d40_config_memcpy(d40c);
2303
2304 if (!err)
2305 d40c->configured = true;
2306
2307 return err == 0;
2308 }
2309 EXPORT_SYMBOL(stedma40_filter);
2310
2311 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2312 {
2313 bool realtime = d40c->dma_cfg.realtime;
2314 bool highprio = d40c->dma_cfg.high_priority;
2315 u32 rtreg;
2316 u32 event = D40_TYPE_TO_EVENT(dev_type);
2317 u32 group = D40_TYPE_TO_GROUP(dev_type);
2318 u32 bit = BIT(event);
2319 u32 prioreg;
2320 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2321
2322 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2323 /*
2324 * Due to a hardware bug, in some cases a logical channel triggered by
2325 * a high priority destination event line can generate extra packet
2326 * transactions.
2327 *
2328 * The workaround is to not set the high priority level for the
2329 * destination event lines that trigger logical channels.
2330 */
2331 if (!src && chan_is_logical(d40c))
2332 highprio = false;
2333
2334 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2335
2336 /* Destination event lines are stored in the upper halfword */
2337 if (!src)
2338 bit <<= 16;
2339
2340 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2341 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2342 }
2343
2344 static void d40_set_prio_realtime(struct d40_chan *d40c)
2345 {
2346 if (d40c->base->rev < 3)
2347 return;
2348
2349 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
2350 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2351 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2352
2353 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
2354 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2355 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2356 }
2357
2358 #define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2359 #define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2360 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2361 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2362 #define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
2363
2364 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2365 struct of_dma *ofdma)
2366 {
2367 struct stedma40_chan_cfg cfg;
2368 dma_cap_mask_t cap;
2369 u32 flags;
2370
2371 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2372
2373 dma_cap_zero(cap);
2374 dma_cap_set(DMA_SLAVE, cap);
2375
2376 cfg.dev_type = dma_spec->args[0];
2377 flags = dma_spec->args[2];
2378
2379 switch (D40_DT_FLAGS_MODE(flags)) {
2380 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2381 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2382 }
2383
2384 switch (D40_DT_FLAGS_DIR(flags)) {
2385 case 0:
2386 cfg.dir = DMA_MEM_TO_DEV;
2387 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2388 break;
2389 case 1:
2390 cfg.dir = DMA_DEV_TO_MEM;
2391 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2392 break;
2393 }
2394
2395 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2396 cfg.phy_channel = dma_spec->args[1];
2397 cfg.use_fixed_channel = true;
2398 }
2399
2400 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2401 cfg.high_priority = true;
2402
2403 return dma_request_channel(cap, stedma40_filter, &cfg);
2404 }
2405
2406 /* DMA ENGINE functions */
2407 static int d40_alloc_chan_resources(struct dma_chan *chan)
2408 {
2409 int err;
2410 unsigned long flags;
2411 struct d40_chan *d40c =
2412 container_of(chan, struct d40_chan, chan);
2413 bool is_free_phy;
2414 spin_lock_irqsave(&d40c->lock, flags);
2415
2416 dma_cookie_init(chan);
2417
2418 /* If no dma configuration is set use default configuration (memcpy) */
2419 if (!d40c->configured) {
2420 err = d40_config_memcpy(d40c);
2421 if (err) {
2422 chan_err(d40c, "Failed to configure memcpy channel\n");
2423 goto mark_last_busy;
2424 }
2425 }
2426
2427 err = d40_allocate_channel(d40c, &is_free_phy);
2428 if (err) {
2429 chan_err(d40c, "Failed to allocate channel\n");
2430 d40c->configured = false;
2431 goto mark_last_busy;
2432 }
2433
2434 pm_runtime_get_sync(d40c->base->dev);
2435
2436 d40_set_prio_realtime(d40c);
2437
2438 if (chan_is_logical(d40c)) {
2439 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2440 d40c->lcpa = d40c->base->lcpa_base +
2441 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2442 else
2443 d40c->lcpa = d40c->base->lcpa_base +
2444 d40c->dma_cfg.dev_type *
2445 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2446
2447 /* Unmask the Global Interrupt Mask. */
2448 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2449 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2450 }
2451
2452 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2453 chan_is_logical(d40c) ? "logical" : "physical",
2454 d40c->phy_chan->num,
2455 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2456
2457
2458 /*
2459 * Only write channel configuration to the DMA if the physical
2460 * resource is free. In case of multiple logical channels
2461 * on the same physical resource, only the first write is necessary.
2462 */
2463 if (is_free_phy)
2464 d40_config_write(d40c);
2465 mark_last_busy:
2466 pm_runtime_mark_last_busy(d40c->base->dev);
2467 pm_runtime_put_autosuspend(d40c->base->dev);
2468 spin_unlock_irqrestore(&d40c->lock, flags);
2469 return err;
2470 }
2471
2472 static void d40_free_chan_resources(struct dma_chan *chan)
2473 {
2474 struct d40_chan *d40c =
2475 container_of(chan, struct d40_chan, chan);
2476 int err;
2477 unsigned long flags;
2478
2479 if (d40c->phy_chan == NULL) {
2480 chan_err(d40c, "Cannot free unallocated channel\n");
2481 return;
2482 }
2483
2484 spin_lock_irqsave(&d40c->lock, flags);
2485
2486 err = d40_free_dma(d40c);
2487
2488 if (err)
2489 chan_err(d40c, "Failed to free channel\n");
2490 spin_unlock_irqrestore(&d40c->lock, flags);
2491 }
2492
2493 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2494 dma_addr_t dst,
2495 dma_addr_t src,
2496 size_t size,
2497 unsigned long dma_flags)
2498 {
2499 struct scatterlist dst_sg;
2500 struct scatterlist src_sg;
2501
2502 sg_init_table(&dst_sg, 1);
2503 sg_init_table(&src_sg, 1);
2504
2505 sg_dma_address(&dst_sg) = dst;
2506 sg_dma_address(&src_sg) = src;
2507
2508 sg_dma_len(&dst_sg) = size;
2509 sg_dma_len(&src_sg) = size;
2510
2511 return d40_prep_sg(chan, &src_sg, &dst_sg, 1,
2512 DMA_MEM_TO_MEM, dma_flags);
2513 }
2514
2515 static struct dma_async_tx_descriptor *
2516 d40_prep_memcpy_sg(struct dma_chan *chan,
2517 struct scatterlist *dst_sg, unsigned int dst_nents,
2518 struct scatterlist *src_sg, unsigned int src_nents,
2519 unsigned long dma_flags)
2520 {
2521 if (dst_nents != src_nents)
2522 return NULL;
2523
2524 return d40_prep_sg(chan, src_sg, dst_sg, src_nents,
2525 DMA_MEM_TO_MEM, dma_flags);
2526 }
2527
2528 static struct dma_async_tx_descriptor *
2529 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2530 unsigned int sg_len, enum dma_transfer_direction direction,
2531 unsigned long dma_flags, void *context)
2532 {
2533 if (!is_slave_direction(direction))
2534 return NULL;
2535
2536 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2537 }
2538
2539 static struct dma_async_tx_descriptor *
2540 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2541 size_t buf_len, size_t period_len,
2542 enum dma_transfer_direction direction, unsigned long flags)
2543 {
2544 unsigned int periods = buf_len / period_len;
2545 struct dma_async_tx_descriptor *txd;
2546 struct scatterlist *sg;
2547 int i;
2548
2549 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2550 if (!sg)
2551 return NULL;
2552
2553 for (i = 0; i < periods; i++) {
2554 sg_dma_address(&sg[i]) = dma_addr;
2555 sg_dma_len(&sg[i]) = period_len;
2556 dma_addr += period_len;
2557 }
2558
2559 sg[periods].offset = 0;
2560 sg_dma_len(&sg[periods]) = 0;
2561 sg[periods].page_link =
2562 ((unsigned long)sg | 0x01) & ~0x02;
2563
2564 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2565 DMA_PREP_INTERRUPT);
2566
2567 kfree(sg);
2568
2569 return txd;
2570 }
2571
2572 static enum dma_status d40_tx_status(struct dma_chan *chan,
2573 dma_cookie_t cookie,
2574 struct dma_tx_state *txstate)
2575 {
2576 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2577 enum dma_status ret;
2578
2579 if (d40c->phy_chan == NULL) {
2580 chan_err(d40c, "Cannot read status of unallocated channel\n");
2581 return -EINVAL;
2582 }
2583
2584 ret = dma_cookie_status(chan, cookie, txstate);
2585 if (ret != DMA_COMPLETE && txstate)
2586 dma_set_residue(txstate, stedma40_residue(chan));
2587
2588 if (d40_is_paused(d40c))
2589 ret = DMA_PAUSED;
2590
2591 return ret;
2592 }
2593
2594 static void d40_issue_pending(struct dma_chan *chan)
2595 {
2596 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2597 unsigned long flags;
2598
2599 if (d40c->phy_chan == NULL) {
2600 chan_err(d40c, "Channel is not allocated!\n");
2601 return;
2602 }
2603
2604 spin_lock_irqsave(&d40c->lock, flags);
2605
2606 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2607
2608 /* Busy means that queued jobs are already being processed */
2609 if (!d40c->busy)
2610 (void) d40_queue_start(d40c);
2611
2612 spin_unlock_irqrestore(&d40c->lock, flags);
2613 }
2614
2615 static int d40_terminate_all(struct dma_chan *chan)
2616 {
2617 unsigned long flags;
2618 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2619 int ret;
2620
2621 if (d40c->phy_chan == NULL) {
2622 chan_err(d40c, "Channel is not allocated!\n");
2623 return -EINVAL;
2624 }
2625
2626 spin_lock_irqsave(&d40c->lock, flags);
2627
2628 pm_runtime_get_sync(d40c->base->dev);
2629 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2630 if (ret)
2631 chan_err(d40c, "Failed to stop channel\n");
2632
2633 d40_term_all(d40c);
2634 pm_runtime_mark_last_busy(d40c->base->dev);
2635 pm_runtime_put_autosuspend(d40c->base->dev);
2636 if (d40c->busy) {
2637 pm_runtime_mark_last_busy(d40c->base->dev);
2638 pm_runtime_put_autosuspend(d40c->base->dev);
2639 }
2640 d40c->busy = false;
2641
2642 spin_unlock_irqrestore(&d40c->lock, flags);
2643 return 0;
2644 }
2645
2646 static int
2647 dma40_config_to_halfchannel(struct d40_chan *d40c,
2648 struct stedma40_half_channel_info *info,
2649 u32 maxburst)
2650 {
2651 int psize;
2652
2653 if (chan_is_logical(d40c)) {
2654 if (maxburst >= 16)
2655 psize = STEDMA40_PSIZE_LOG_16;
2656 else if (maxburst >= 8)
2657 psize = STEDMA40_PSIZE_LOG_8;
2658 else if (maxburst >= 4)
2659 psize = STEDMA40_PSIZE_LOG_4;
2660 else
2661 psize = STEDMA40_PSIZE_LOG_1;
2662 } else {
2663 if (maxburst >= 16)
2664 psize = STEDMA40_PSIZE_PHY_16;
2665 else if (maxburst >= 8)
2666 psize = STEDMA40_PSIZE_PHY_8;
2667 else if (maxburst >= 4)
2668 psize = STEDMA40_PSIZE_PHY_4;
2669 else
2670 psize = STEDMA40_PSIZE_PHY_1;
2671 }
2672
2673 info->psize = psize;
2674 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2675
2676 return 0;
2677 }
2678
2679 /* Runtime reconfiguration extension */
2680 static int d40_set_runtime_config(struct dma_chan *chan,
2681 struct dma_slave_config *config)
2682 {
2683 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2684 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2685 enum dma_slave_buswidth src_addr_width, dst_addr_width;
2686 dma_addr_t config_addr;
2687 u32 src_maxburst, dst_maxburst;
2688 int ret;
2689
2690 if (d40c->phy_chan == NULL) {
2691 chan_err(d40c, "Channel is not allocated!\n");
2692 return -EINVAL;
2693 }
2694
2695 src_addr_width = config->src_addr_width;
2696 src_maxburst = config->src_maxburst;
2697 dst_addr_width = config->dst_addr_width;
2698 dst_maxburst = config->dst_maxburst;
2699
2700 if (config->direction == DMA_DEV_TO_MEM) {
2701 config_addr = config->src_addr;
2702
2703 if (cfg->dir != DMA_DEV_TO_MEM)
2704 dev_dbg(d40c->base->dev,
2705 "channel was not configured for peripheral "
2706 "to memory transfer (%d) overriding\n",
2707 cfg->dir);
2708 cfg->dir = DMA_DEV_TO_MEM;
2709
2710 /* Configure the memory side */
2711 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2712 dst_addr_width = src_addr_width;
2713 if (dst_maxburst == 0)
2714 dst_maxburst = src_maxburst;
2715
2716 } else if (config->direction == DMA_MEM_TO_DEV) {
2717 config_addr = config->dst_addr;
2718
2719 if (cfg->dir != DMA_MEM_TO_DEV)
2720 dev_dbg(d40c->base->dev,
2721 "channel was not configured for memory "
2722 "to peripheral transfer (%d) overriding\n",
2723 cfg->dir);
2724 cfg->dir = DMA_MEM_TO_DEV;
2725
2726 /* Configure the memory side */
2727 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2728 src_addr_width = dst_addr_width;
2729 if (src_maxburst == 0)
2730 src_maxburst = dst_maxburst;
2731 } else {
2732 dev_err(d40c->base->dev,
2733 "unrecognized channel direction %d\n",
2734 config->direction);
2735 return -EINVAL;
2736 }
2737
2738 if (config_addr <= 0) {
2739 dev_err(d40c->base->dev, "no address supplied\n");
2740 return -EINVAL;
2741 }
2742
2743 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2744 dev_err(d40c->base->dev,
2745 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2746 src_maxburst,
2747 src_addr_width,
2748 dst_maxburst,
2749 dst_addr_width);
2750 return -EINVAL;
2751 }
2752
2753 if (src_maxburst > 16) {
2754 src_maxburst = 16;
2755 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2756 } else if (dst_maxburst > 16) {
2757 dst_maxburst = 16;
2758 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2759 }
2760
2761 /* Only valid widths are; 1, 2, 4 and 8. */
2762 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2763 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2764 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2765 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2766 !is_power_of_2(src_addr_width) ||
2767 !is_power_of_2(dst_addr_width))
2768 return -EINVAL;
2769
2770 cfg->src_info.data_width = src_addr_width;
2771 cfg->dst_info.data_width = dst_addr_width;
2772
2773 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2774 src_maxburst);
2775 if (ret)
2776 return ret;
2777
2778 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2779 dst_maxburst);
2780 if (ret)
2781 return ret;
2782
2783 /* Fill in register values */
2784 if (chan_is_logical(d40c))
2785 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2786 else
2787 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2788
2789 /* These settings will take precedence later */
2790 d40c->runtime_addr = config_addr;
2791 d40c->runtime_direction = config->direction;
2792 dev_dbg(d40c->base->dev,
2793 "configured channel %s for %s, data width %d/%d, "
2794 "maxburst %d/%d elements, LE, no flow control\n",
2795 dma_chan_name(chan),
2796 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2797 src_addr_width, dst_addr_width,
2798 src_maxburst, dst_maxburst);
2799
2800 return 0;
2801 }
2802
2803 /* Initialization functions */
2804
2805 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2806 struct d40_chan *chans, int offset,
2807 int num_chans)
2808 {
2809 int i = 0;
2810 struct d40_chan *d40c;
2811
2812 INIT_LIST_HEAD(&dma->channels);
2813
2814 for (i = offset; i < offset + num_chans; i++) {
2815 d40c = &chans[i];
2816 d40c->base = base;
2817 d40c->chan.device = dma;
2818
2819 spin_lock_init(&d40c->lock);
2820
2821 d40c->log_num = D40_PHY_CHAN;
2822
2823 INIT_LIST_HEAD(&d40c->done);
2824 INIT_LIST_HEAD(&d40c->active);
2825 INIT_LIST_HEAD(&d40c->queue);
2826 INIT_LIST_HEAD(&d40c->pending_queue);
2827 INIT_LIST_HEAD(&d40c->client);
2828 INIT_LIST_HEAD(&d40c->prepare_queue);
2829
2830 tasklet_init(&d40c->tasklet, dma_tasklet,
2831 (unsigned long) d40c);
2832
2833 list_add_tail(&d40c->chan.device_node,
2834 &dma->channels);
2835 }
2836 }
2837
2838 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2839 {
2840 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2841 dev->device_prep_slave_sg = d40_prep_slave_sg;
2842
2843 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2844 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2845
2846 /*
2847 * This controller can only access address at even
2848 * 32bit boundaries, i.e. 2^2
2849 */
2850 dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
2851 }
2852
2853 if (dma_has_cap(DMA_SG, dev->cap_mask))
2854 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2855
2856 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2857 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2858
2859 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2860 dev->device_free_chan_resources = d40_free_chan_resources;
2861 dev->device_issue_pending = d40_issue_pending;
2862 dev->device_tx_status = d40_tx_status;
2863 dev->device_config = d40_set_runtime_config;
2864 dev->device_pause = d40_pause;
2865 dev->device_resume = d40_resume;
2866 dev->device_terminate_all = d40_terminate_all;
2867 dev->dev = base->dev;
2868 }
2869
2870 static int __init d40_dmaengine_init(struct d40_base *base,
2871 int num_reserved_chans)
2872 {
2873 int err ;
2874
2875 d40_chan_init(base, &base->dma_slave, base->log_chans,
2876 0, base->num_log_chans);
2877
2878 dma_cap_zero(base->dma_slave.cap_mask);
2879 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2880 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2881
2882 d40_ops_init(base, &base->dma_slave);
2883
2884 err = dma_async_device_register(&base->dma_slave);
2885
2886 if (err) {
2887 d40_err(base->dev, "Failed to register slave channels\n");
2888 goto exit;
2889 }
2890
2891 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2892 base->num_log_chans, base->num_memcpy_chans);
2893
2894 dma_cap_zero(base->dma_memcpy.cap_mask);
2895 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2896 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2897
2898 d40_ops_init(base, &base->dma_memcpy);
2899
2900 err = dma_async_device_register(&base->dma_memcpy);
2901
2902 if (err) {
2903 d40_err(base->dev,
2904 "Failed to register memcpy only channels\n");
2905 goto unregister_slave;
2906 }
2907
2908 d40_chan_init(base, &base->dma_both, base->phy_chans,
2909 0, num_reserved_chans);
2910
2911 dma_cap_zero(base->dma_both.cap_mask);
2912 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2913 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2914 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2915 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2916
2917 d40_ops_init(base, &base->dma_both);
2918 err = dma_async_device_register(&base->dma_both);
2919
2920 if (err) {
2921 d40_err(base->dev,
2922 "Failed to register logical and physical capable channels\n");
2923 goto unregister_memcpy;
2924 }
2925 return 0;
2926 unregister_memcpy:
2927 dma_async_device_unregister(&base->dma_memcpy);
2928 unregister_slave:
2929 dma_async_device_unregister(&base->dma_slave);
2930 exit:
2931 return err;
2932 }
2933
2934 /* Suspend resume functionality */
2935 #ifdef CONFIG_PM_SLEEP
2936 static int dma40_suspend(struct device *dev)
2937 {
2938 struct platform_device *pdev = to_platform_device(dev);
2939 struct d40_base *base = platform_get_drvdata(pdev);
2940 int ret;
2941
2942 ret = pm_runtime_force_suspend(dev);
2943 if (ret)
2944 return ret;
2945
2946 if (base->lcpa_regulator)
2947 ret = regulator_disable(base->lcpa_regulator);
2948 return ret;
2949 }
2950
2951 static int dma40_resume(struct device *dev)
2952 {
2953 struct platform_device *pdev = to_platform_device(dev);
2954 struct d40_base *base = platform_get_drvdata(pdev);
2955 int ret = 0;
2956
2957 if (base->lcpa_regulator) {
2958 ret = regulator_enable(base->lcpa_regulator);
2959 if (ret)
2960 return ret;
2961 }
2962
2963 return pm_runtime_force_resume(dev);
2964 }
2965 #endif
2966
2967 #ifdef CONFIG_PM
2968 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
2969 u32 *regaddr, int num, bool save)
2970 {
2971 int i;
2972
2973 for (i = 0; i < num; i++) {
2974 void __iomem *addr = baseaddr + regaddr[i];
2975
2976 if (save)
2977 backup[i] = readl_relaxed(addr);
2978 else
2979 writel_relaxed(backup[i], addr);
2980 }
2981 }
2982
2983 static void d40_save_restore_registers(struct d40_base *base, bool save)
2984 {
2985 int i;
2986
2987 /* Save/Restore channel specific registers */
2988 for (i = 0; i < base->num_phy_chans; i++) {
2989 void __iomem *addr;
2990 int idx;
2991
2992 if (base->phy_res[i].reserved)
2993 continue;
2994
2995 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2996 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
2997
2998 dma40_backup(addr, &base->reg_val_backup_chan[idx],
2999 d40_backup_regs_chan,
3000 ARRAY_SIZE(d40_backup_regs_chan),
3001 save);
3002 }
3003
3004 /* Save/Restore global registers */
3005 dma40_backup(base->virtbase, base->reg_val_backup,
3006 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
3007 save);
3008
3009 /* Save/Restore registers only existing on dma40 v3 and later */
3010 if (base->gen_dmac.backup)
3011 dma40_backup(base->virtbase, base->reg_val_backup_v4,
3012 base->gen_dmac.backup,
3013 base->gen_dmac.backup_size,
3014 save);
3015 }
3016
3017 static int dma40_runtime_suspend(struct device *dev)
3018 {
3019 struct platform_device *pdev = to_platform_device(dev);
3020 struct d40_base *base = platform_get_drvdata(pdev);
3021
3022 d40_save_restore_registers(base, true);
3023
3024 /* Don't disable/enable clocks for v1 due to HW bugs */
3025 if (base->rev != 1)
3026 writel_relaxed(base->gcc_pwr_off_mask,
3027 base->virtbase + D40_DREG_GCC);
3028
3029 return 0;
3030 }
3031
3032 static int dma40_runtime_resume(struct device *dev)
3033 {
3034 struct platform_device *pdev = to_platform_device(dev);
3035 struct d40_base *base = platform_get_drvdata(pdev);
3036
3037 d40_save_restore_registers(base, false);
3038
3039 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3040 base->virtbase + D40_DREG_GCC);
3041 return 0;
3042 }
3043 #endif
3044
3045 static const struct dev_pm_ops dma40_pm_ops = {
3046 SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume)
3047 SET_RUNTIME_PM_OPS(dma40_runtime_suspend,
3048 dma40_runtime_resume,
3049 NULL)
3050 };
3051
3052 /* Initialization functions. */
3053
3054 static int __init d40_phy_res_init(struct d40_base *base)
3055 {
3056 int i;
3057 int num_phy_chans_avail = 0;
3058 u32 val[2];
3059 int odd_even_bit = -2;
3060 int gcc = D40_DREG_GCC_ENA;
3061
3062 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3063 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3064
3065 for (i = 0; i < base->num_phy_chans; i++) {
3066 base->phy_res[i].num = i;
3067 odd_even_bit += 2 * ((i % 2) == 0);
3068 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3069 /* Mark security only channels as occupied */
3070 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3071 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3072 base->phy_res[i].reserved = true;
3073 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3074 D40_DREG_GCC_SRC);
3075 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3076 D40_DREG_GCC_DST);
3077
3078
3079 } else {
3080 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3081 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3082 base->phy_res[i].reserved = false;
3083 num_phy_chans_avail++;
3084 }
3085 spin_lock_init(&base->phy_res[i].lock);
3086 }
3087
3088 /* Mark disabled channels as occupied */
3089 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3090 int chan = base->plat_data->disabled_channels[i];
3091
3092 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3093 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3094 base->phy_res[chan].reserved = true;
3095 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3096 D40_DREG_GCC_SRC);
3097 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3098 D40_DREG_GCC_DST);
3099 num_phy_chans_avail--;
3100 }
3101
3102 /* Mark soft_lli channels */
3103 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3104 int chan = base->plat_data->soft_lli_chans[i];
3105
3106 base->phy_res[chan].use_soft_lli = true;
3107 }
3108
3109 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3110 num_phy_chans_avail, base->num_phy_chans);
3111
3112 /* Verify settings extended vs standard */
3113 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3114
3115 for (i = 0; i < base->num_phy_chans; i++) {
3116
3117 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3118 (val[0] & 0x3) != 1)
3119 dev_info(base->dev,
3120 "[%s] INFO: channel %d is misconfigured (%d)\n",
3121 __func__, i, val[0] & 0x3);
3122
3123 val[0] = val[0] >> 2;
3124 }
3125
3126 /*
3127 * To keep things simple, Enable all clocks initially.
3128 * The clocks will get managed later post channel allocation.
3129 * The clocks for the event lines on which reserved channels exists
3130 * are not managed here.
3131 */
3132 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3133 base->gcc_pwr_off_mask = gcc;
3134
3135 return num_phy_chans_avail;
3136 }
3137
3138 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3139 {
3140 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3141 struct clk *clk;
3142 void __iomem *virtbase;
3143 struct resource *res;
3144 struct d40_base *base;
3145 int num_log_chans;
3146 int num_phy_chans;
3147 int num_memcpy_chans;
3148 int clk_ret = -EINVAL;
3149 int i;
3150 u32 pid;
3151 u32 cid;
3152 u8 rev;
3153
3154 clk = clk_get(&pdev->dev, NULL);
3155 if (IS_ERR(clk)) {
3156 d40_err(&pdev->dev, "No matching clock found\n");
3157 goto check_prepare_enabled;
3158 }
3159
3160 clk_ret = clk_prepare_enable(clk);
3161 if (clk_ret) {
3162 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3163 goto disable_unprepare;
3164 }
3165
3166 /* Get IO for DMAC base address */
3167 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3168 if (!res)
3169 goto disable_unprepare;
3170
3171 if (request_mem_region(res->start, resource_size(res),
3172 D40_NAME " I/O base") == NULL)
3173 goto release_region;
3174
3175 virtbase = ioremap(res->start, resource_size(res));
3176 if (!virtbase)
3177 goto release_region;
3178
3179 /* This is just a regular AMBA PrimeCell ID actually */
3180 for (pid = 0, i = 0; i < 4; i++)
3181 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3182 & 255) << (i * 8);
3183 for (cid = 0, i = 0; i < 4; i++)
3184 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3185 & 255) << (i * 8);
3186
3187 if (cid != AMBA_CID) {
3188 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3189 goto unmap_io;
3190 }
3191 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3192 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3193 AMBA_MANF_BITS(pid),
3194 AMBA_VENDOR_ST);
3195 goto unmap_io;
3196 }
3197 /*
3198 * HW revision:
3199 * DB8500ed has revision 0
3200 * ? has revision 1
3201 * DB8500v1 has revision 2
3202 * DB8500v2 has revision 3
3203 * AP9540v1 has revision 4
3204 * DB8540v1 has revision 4
3205 */
3206 rev = AMBA_REV_BITS(pid);
3207 if (rev < 2) {
3208 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3209 goto unmap_io;
3210 }
3211
3212 /* The number of physical channels on this HW */
3213 if (plat_data->num_of_phy_chans)
3214 num_phy_chans = plat_data->num_of_phy_chans;
3215 else
3216 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3217
3218 /* The number of channels used for memcpy */
3219 if (plat_data->num_of_memcpy_chans)
3220 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3221 else
3222 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3223
3224 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3225
3226 dev_info(&pdev->dev,
3227 "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3228 rev, &res->start, num_phy_chans, num_log_chans);
3229
3230 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3231 (num_phy_chans + num_log_chans + num_memcpy_chans) *
3232 sizeof(struct d40_chan), GFP_KERNEL);
3233
3234 if (base == NULL)
3235 goto unmap_io;
3236
3237 base->rev = rev;
3238 base->clk = clk;
3239 base->num_memcpy_chans = num_memcpy_chans;
3240 base->num_phy_chans = num_phy_chans;
3241 base->num_log_chans = num_log_chans;
3242 base->phy_start = res->start;
3243 base->phy_size = resource_size(res);
3244 base->virtbase = virtbase;
3245 base->plat_data = plat_data;
3246 base->dev = &pdev->dev;
3247 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3248 base->log_chans = &base->phy_chans[num_phy_chans];
3249
3250 if (base->plat_data->num_of_phy_chans == 14) {
3251 base->gen_dmac.backup = d40_backup_regs_v4b;
3252 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3253 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3254 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3255 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3256 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3257 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3258 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3259 base->gen_dmac.il = il_v4b;
3260 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3261 base->gen_dmac.init_reg = dma_init_reg_v4b;
3262 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3263 } else {
3264 if (base->rev >= 3) {
3265 base->gen_dmac.backup = d40_backup_regs_v4a;
3266 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3267 }
3268 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3269 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3270 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3271 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3272 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3273 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3274 base->gen_dmac.il = il_v4a;
3275 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3276 base->gen_dmac.init_reg = dma_init_reg_v4a;
3277 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3278 }
3279
3280 base->phy_res = kcalloc(num_phy_chans,
3281 sizeof(*base->phy_res),
3282 GFP_KERNEL);
3283 if (!base->phy_res)
3284 goto free_base;
3285
3286 base->lookup_phy_chans = kcalloc(num_phy_chans,
3287 sizeof(*base->lookup_phy_chans),
3288 GFP_KERNEL);
3289 if (!base->lookup_phy_chans)
3290 goto free_phy_res;
3291
3292 base->lookup_log_chans = kcalloc(num_log_chans,
3293 sizeof(*base->lookup_log_chans),
3294 GFP_KERNEL);
3295 if (!base->lookup_log_chans)
3296 goto free_phy_chans;
3297
3298 base->reg_val_backup_chan = kmalloc_array(base->num_phy_chans,
3299 sizeof(d40_backup_regs_chan),
3300 GFP_KERNEL);
3301 if (!base->reg_val_backup_chan)
3302 goto free_log_chans;
3303
3304 base->lcla_pool.alloc_map = kcalloc(num_phy_chans
3305 * D40_LCLA_LINK_PER_EVENT_GRP,
3306 sizeof(*base->lcla_pool.alloc_map),
3307 GFP_KERNEL);
3308 if (!base->lcla_pool.alloc_map)
3309 goto free_backup_chan;
3310
3311 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3312 0, SLAB_HWCACHE_ALIGN,
3313 NULL);
3314 if (base->desc_slab == NULL)
3315 goto free_map;
3316
3317 return base;
3318 free_map:
3319 kfree(base->lcla_pool.alloc_map);
3320 free_backup_chan:
3321 kfree(base->reg_val_backup_chan);
3322 free_log_chans:
3323 kfree(base->lookup_log_chans);
3324 free_phy_chans:
3325 kfree(base->lookup_phy_chans);
3326 free_phy_res:
3327 kfree(base->phy_res);
3328 free_base:
3329 kfree(base);
3330 unmap_io:
3331 iounmap(virtbase);
3332 release_region:
3333 release_mem_region(res->start, resource_size(res));
3334 check_prepare_enabled:
3335 if (!clk_ret)
3336 disable_unprepare:
3337 clk_disable_unprepare(clk);
3338 if (!IS_ERR(clk))
3339 clk_put(clk);
3340 return NULL;
3341 }
3342
3343 static void __init d40_hw_init(struct d40_base *base)
3344 {
3345
3346 int i;
3347 u32 prmseo[2] = {0, 0};
3348 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3349 u32 pcmis = 0;
3350 u32 pcicr = 0;
3351 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3352 u32 reg_size = base->gen_dmac.init_reg_size;
3353
3354 for (i = 0; i < reg_size; i++)
3355 writel(dma_init_reg[i].val,
3356 base->virtbase + dma_init_reg[i].reg);
3357
3358 /* Configure all our dma channels to default settings */
3359 for (i = 0; i < base->num_phy_chans; i++) {
3360
3361 activeo[i % 2] = activeo[i % 2] << 2;
3362
3363 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3364 == D40_ALLOC_PHY) {
3365 activeo[i % 2] |= 3;
3366 continue;
3367 }
3368
3369 /* Enable interrupt # */
3370 pcmis = (pcmis << 1) | 1;
3371
3372 /* Clear interrupt # */
3373 pcicr = (pcicr << 1) | 1;
3374
3375 /* Set channel to physical mode */
3376 prmseo[i % 2] = prmseo[i % 2] << 2;
3377 prmseo[i % 2] |= 1;
3378
3379 }
3380
3381 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3382 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3383 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3384 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3385
3386 /* Write which interrupt to enable */
3387 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3388
3389 /* Write which interrupt to clear */
3390 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3391
3392 /* These are __initdata and cannot be accessed after init */
3393 base->gen_dmac.init_reg = NULL;
3394 base->gen_dmac.init_reg_size = 0;
3395 }
3396
3397 static int __init d40_lcla_allocate(struct d40_base *base)
3398 {
3399 struct d40_lcla_pool *pool = &base->lcla_pool;
3400 unsigned long *page_list;
3401 int i, j;
3402 int ret;
3403
3404 /*
3405 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3406 * To full fill this hardware requirement without wasting 256 kb
3407 * we allocate pages until we get an aligned one.
3408 */
3409 page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS,
3410 sizeof(*page_list),
3411 GFP_KERNEL);
3412 if (!page_list)
3413 return -ENOMEM;
3414
3415 /* Calculating how many pages that are required */
3416 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3417
3418 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3419 page_list[i] = __get_free_pages(GFP_KERNEL,
3420 base->lcla_pool.pages);
3421 if (!page_list[i]) {
3422
3423 d40_err(base->dev, "Failed to allocate %d pages.\n",
3424 base->lcla_pool.pages);
3425 ret = -ENOMEM;
3426
3427 for (j = 0; j < i; j++)
3428 free_pages(page_list[j], base->lcla_pool.pages);
3429 goto free_page_list;
3430 }
3431
3432 if ((virt_to_phys((void *)page_list[i]) &
3433 (LCLA_ALIGNMENT - 1)) == 0)
3434 break;
3435 }
3436
3437 for (j = 0; j < i; j++)
3438 free_pages(page_list[j], base->lcla_pool.pages);
3439
3440 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3441 base->lcla_pool.base = (void *)page_list[i];
3442 } else {
3443 /*
3444 * After many attempts and no succees with finding the correct
3445 * alignment, try with allocating a big buffer.
3446 */
3447 dev_warn(base->dev,
3448 "[%s] Failed to get %d pages @ 18 bit align.\n",
3449 __func__, base->lcla_pool.pages);
3450 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3451 base->num_phy_chans +
3452 LCLA_ALIGNMENT,
3453 GFP_KERNEL);
3454 if (!base->lcla_pool.base_unaligned) {
3455 ret = -ENOMEM;
3456 goto free_page_list;
3457 }
3458
3459 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3460 LCLA_ALIGNMENT);
3461 }
3462
3463 pool->dma_addr = dma_map_single(base->dev, pool->base,
3464 SZ_1K * base->num_phy_chans,
3465 DMA_TO_DEVICE);
3466 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3467 pool->dma_addr = 0;
3468 ret = -ENOMEM;
3469 goto free_page_list;
3470 }
3471
3472 writel(virt_to_phys(base->lcla_pool.base),
3473 base->virtbase + D40_DREG_LCLA);
3474 ret = 0;
3475 free_page_list:
3476 kfree(page_list);
3477 return ret;
3478 }
3479
3480 static int __init d40_of_probe(struct platform_device *pdev,
3481 struct device_node *np)
3482 {
3483 struct stedma40_platform_data *pdata;
3484 int num_phy = 0, num_memcpy = 0, num_disabled = 0;
3485 const __be32 *list;
3486
3487 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
3488 if (!pdata)
3489 return -ENOMEM;
3490
3491 /* If absent this value will be obtained from h/w. */
3492 of_property_read_u32(np, "dma-channels", &num_phy);
3493 if (num_phy > 0)
3494 pdata->num_of_phy_chans = num_phy;
3495
3496 list = of_get_property(np, "memcpy-channels", &num_memcpy);
3497 num_memcpy /= sizeof(*list);
3498
3499 if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3500 d40_err(&pdev->dev,
3501 "Invalid number of memcpy channels specified (%d)\n",
3502 num_memcpy);
3503 return -EINVAL;
3504 }
3505 pdata->num_of_memcpy_chans = num_memcpy;
3506
3507 of_property_read_u32_array(np, "memcpy-channels",
3508 dma40_memcpy_channels,
3509 num_memcpy);
3510
3511 list = of_get_property(np, "disabled-channels", &num_disabled);
3512 num_disabled /= sizeof(*list);
3513
3514 if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
3515 d40_err(&pdev->dev,
3516 "Invalid number of disabled channels specified (%d)\n",
3517 num_disabled);
3518 return -EINVAL;
3519 }
3520
3521 of_property_read_u32_array(np, "disabled-channels",
3522 pdata->disabled_channels,
3523 num_disabled);
3524 pdata->disabled_channels[num_disabled] = -1;
3525
3526 pdev->dev.platform_data = pdata;
3527
3528 return 0;
3529 }
3530
3531 static int __init d40_probe(struct platform_device *pdev)
3532 {
3533 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3534 struct device_node *np = pdev->dev.of_node;
3535 int ret = -ENOENT;
3536 struct d40_base *base;
3537 struct resource *res;
3538 int num_reserved_chans;
3539 u32 val;
3540
3541 if (!plat_data) {
3542 if (np) {
3543 if (d40_of_probe(pdev, np)) {
3544 ret = -ENOMEM;
3545 goto report_failure;
3546 }
3547 } else {
3548 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3549 goto report_failure;
3550 }
3551 }
3552
3553 base = d40_hw_detect_init(pdev);
3554 if (!base)
3555 goto report_failure;
3556
3557 num_reserved_chans = d40_phy_res_init(base);
3558
3559 platform_set_drvdata(pdev, base);
3560
3561 spin_lock_init(&base->interrupt_lock);
3562 spin_lock_init(&base->execmd_lock);
3563
3564 /* Get IO for logical channel parameter address */
3565 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3566 if (!res) {
3567 ret = -ENOENT;
3568 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3569 goto destroy_cache;
3570 }
3571 base->lcpa_size = resource_size(res);
3572 base->phy_lcpa = res->start;
3573
3574 if (request_mem_region(res->start, resource_size(res),
3575 D40_NAME " I/O lcpa") == NULL) {
3576 ret = -EBUSY;
3577 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
3578 goto destroy_cache;
3579 }
3580
3581 /* We make use of ESRAM memory for this. */
3582 val = readl(base->virtbase + D40_DREG_LCPA);
3583 if (res->start != val && val != 0) {
3584 dev_warn(&pdev->dev,
3585 "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3586 __func__, val, &res->start);
3587 } else
3588 writel(res->start, base->virtbase + D40_DREG_LCPA);
3589
3590 base->lcpa_base = ioremap(res->start, resource_size(res));
3591 if (!base->lcpa_base) {
3592 ret = -ENOMEM;
3593 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3594 goto destroy_cache;
3595 }
3596 /* If lcla has to be located in ESRAM we don't need to allocate */
3597 if (base->plat_data->use_esram_lcla) {
3598 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3599 "lcla_esram");
3600 if (!res) {
3601 ret = -ENOENT;
3602 d40_err(&pdev->dev,
3603 "No \"lcla_esram\" memory resource\n");
3604 goto destroy_cache;
3605 }
3606 base->lcla_pool.base = ioremap(res->start,
3607 resource_size(res));
3608 if (!base->lcla_pool.base) {
3609 ret = -ENOMEM;
3610 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3611 goto destroy_cache;
3612 }
3613 writel(res->start, base->virtbase + D40_DREG_LCLA);
3614
3615 } else {
3616 ret = d40_lcla_allocate(base);
3617 if (ret) {
3618 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3619 goto destroy_cache;
3620 }
3621 }
3622
3623 spin_lock_init(&base->lcla_pool.lock);
3624
3625 base->irq = platform_get_irq(pdev, 0);
3626
3627 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3628 if (ret) {
3629 d40_err(&pdev->dev, "No IRQ defined\n");
3630 goto destroy_cache;
3631 }
3632
3633 if (base->plat_data->use_esram_lcla) {
3634
3635 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3636 if (IS_ERR(base->lcpa_regulator)) {
3637 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3638 ret = PTR_ERR(base->lcpa_regulator);
3639 base->lcpa_regulator = NULL;
3640 goto destroy_cache;
3641 }
3642
3643 ret = regulator_enable(base->lcpa_regulator);
3644 if (ret) {
3645 d40_err(&pdev->dev,
3646 "Failed to enable lcpa_regulator\n");
3647 regulator_put(base->lcpa_regulator);
3648 base->lcpa_regulator = NULL;
3649 goto destroy_cache;
3650 }
3651 }
3652
3653 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3654
3655 pm_runtime_irq_safe(base->dev);
3656 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3657 pm_runtime_use_autosuspend(base->dev);
3658 pm_runtime_mark_last_busy(base->dev);
3659 pm_runtime_set_active(base->dev);
3660 pm_runtime_enable(base->dev);
3661
3662 ret = d40_dmaengine_init(base, num_reserved_chans);
3663 if (ret)
3664 goto destroy_cache;
3665
3666 base->dev->dma_parms = &base->dma_parms;
3667 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3668 if (ret) {
3669 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3670 goto destroy_cache;
3671 }
3672
3673 d40_hw_init(base);
3674
3675 if (np) {
3676 ret = of_dma_controller_register(np, d40_xlate, NULL);
3677 if (ret)
3678 dev_err(&pdev->dev,
3679 "could not register of_dma_controller\n");
3680 }
3681
3682 dev_info(base->dev, "initialized\n");
3683 return 0;
3684 destroy_cache:
3685 kmem_cache_destroy(base->desc_slab);
3686 if (base->virtbase)
3687 iounmap(base->virtbase);
3688
3689 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3690 iounmap(base->lcla_pool.base);
3691 base->lcla_pool.base = NULL;
3692 }
3693
3694 if (base->lcla_pool.dma_addr)
3695 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3696 SZ_1K * base->num_phy_chans,
3697 DMA_TO_DEVICE);
3698
3699 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3700 free_pages((unsigned long)base->lcla_pool.base,
3701 base->lcla_pool.pages);
3702
3703 kfree(base->lcla_pool.base_unaligned);
3704
3705 if (base->phy_lcpa)
3706 release_mem_region(base->phy_lcpa,
3707 base->lcpa_size);
3708 if (base->phy_start)
3709 release_mem_region(base->phy_start,
3710 base->phy_size);
3711 if (base->clk) {
3712 clk_disable_unprepare(base->clk);
3713 clk_put(base->clk);
3714 }
3715
3716 if (base->lcpa_regulator) {
3717 regulator_disable(base->lcpa_regulator);
3718 regulator_put(base->lcpa_regulator);
3719 }
3720
3721 kfree(base->lcla_pool.alloc_map);
3722 kfree(base->lookup_log_chans);
3723 kfree(base->lookup_phy_chans);
3724 kfree(base->phy_res);
3725 kfree(base);
3726 report_failure:
3727 d40_err(&pdev->dev, "probe failed\n");
3728 return ret;
3729 }
3730
3731 static const struct of_device_id d40_match[] = {
3732 { .compatible = "stericsson,dma40", },
3733 {}
3734 };
3735
3736 static struct platform_driver d40_driver = {
3737 .driver = {
3738 .name = D40_NAME,
3739 .pm = &dma40_pm_ops,
3740 .of_match_table = d40_match,
3741 },
3742 };
3743
3744 static int __init stedma40_init(void)
3745 {
3746 return platform_driver_probe(&d40_driver, d40_probe);
3747 }
3748 subsys_initcall(stedma40_init);
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