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Merge branch 'topic/hsu' into for-linus
[mirror_ubuntu-bionic-kernel.git] / drivers / dma / ste_dma40.c
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/log2.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_dma.h>
23 #include <linux/amba/bus.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/platform_data/dma-ste-dma40.h>
26
27 #include "dmaengine.h"
28 #include "ste_dma40_ll.h"
29
30 #define D40_NAME "dma40"
31
32 #define D40_PHY_CHAN -1
33
34 /* For masking out/in 2 bit channel positions */
35 #define D40_CHAN_POS(chan) (2 * (chan / 2))
36 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
37
38 /* Maximum iterations taken before giving up suspending a channel */
39 #define D40_SUSPEND_MAX_IT 500
40
41 /* Milliseconds */
42 #define DMA40_AUTOSUSPEND_DELAY 100
43
44 /* Hardware requirement on LCLA alignment */
45 #define LCLA_ALIGNMENT 0x40000
46
47 /* Max number of links per event group */
48 #define D40_LCLA_LINK_PER_EVENT_GRP 128
49 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
50
51 /* Max number of logical channels per physical channel */
52 #define D40_MAX_LOG_CHAN_PER_PHY 32
53
54 /* Attempts before giving up to trying to get pages that are aligned */
55 #define MAX_LCLA_ALLOC_ATTEMPTS 256
56
57 /* Bit markings for allocation map */
58 #define D40_ALLOC_FREE BIT(31)
59 #define D40_ALLOC_PHY BIT(30)
60 #define D40_ALLOC_LOG_FREE 0
61
62 #define D40_MEMCPY_MAX_CHANS 8
63
64 /* Reserved event lines for memcpy only. */
65 #define DB8500_DMA_MEMCPY_EV_0 51
66 #define DB8500_DMA_MEMCPY_EV_1 56
67 #define DB8500_DMA_MEMCPY_EV_2 57
68 #define DB8500_DMA_MEMCPY_EV_3 58
69 #define DB8500_DMA_MEMCPY_EV_4 59
70 #define DB8500_DMA_MEMCPY_EV_5 60
71
72 static int dma40_memcpy_channels[] = {
73 DB8500_DMA_MEMCPY_EV_0,
74 DB8500_DMA_MEMCPY_EV_1,
75 DB8500_DMA_MEMCPY_EV_2,
76 DB8500_DMA_MEMCPY_EV_3,
77 DB8500_DMA_MEMCPY_EV_4,
78 DB8500_DMA_MEMCPY_EV_5,
79 };
80
81 /* Default configuration for physcial memcpy */
82 static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
83 .mode = STEDMA40_MODE_PHYSICAL,
84 .dir = DMA_MEM_TO_MEM,
85
86 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
87 .src_info.psize = STEDMA40_PSIZE_PHY_1,
88 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
89
90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
93 };
94
95 /* Default configuration for logical memcpy */
96 static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
97 .mode = STEDMA40_MODE_LOGICAL,
98 .dir = DMA_MEM_TO_MEM,
99
100 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
101 .src_info.psize = STEDMA40_PSIZE_LOG_1,
102 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
103
104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
107 };
108
109 /**
110 * enum 40_command - The different commands and/or statuses.
111 *
112 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
113 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
114 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
115 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
116 */
117 enum d40_command {
118 D40_DMA_STOP = 0,
119 D40_DMA_RUN = 1,
120 D40_DMA_SUSPEND_REQ = 2,
121 D40_DMA_SUSPENDED = 3
122 };
123
124 /*
125 * enum d40_events - The different Event Enables for the event lines.
126 *
127 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
128 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
129 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
130 * @D40_ROUND_EVENTLINE: Status check for event line.
131 */
132
133 enum d40_events {
134 D40_DEACTIVATE_EVENTLINE = 0,
135 D40_ACTIVATE_EVENTLINE = 1,
136 D40_SUSPEND_REQ_EVENTLINE = 2,
137 D40_ROUND_EVENTLINE = 3
138 };
139
140 /*
141 * These are the registers that has to be saved and later restored
142 * when the DMA hw is powered off.
143 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
144 */
145 static u32 d40_backup_regs[] = {
146 D40_DREG_LCPA,
147 D40_DREG_LCLA,
148 D40_DREG_PRMSE,
149 D40_DREG_PRMSO,
150 D40_DREG_PRMOE,
151 D40_DREG_PRMOO,
152 };
153
154 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
155
156 /*
157 * since 9540 and 8540 has the same HW revision
158 * use v4a for 9540 or ealier
159 * use v4b for 8540 or later
160 * HW revision:
161 * DB8500ed has revision 0
162 * DB8500v1 has revision 2
163 * DB8500v2 has revision 3
164 * AP9540v1 has revision 4
165 * DB8540v1 has revision 4
166 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
167 */
168 static u32 d40_backup_regs_v4a[] = {
169 D40_DREG_PSEG1,
170 D40_DREG_PSEG2,
171 D40_DREG_PSEG3,
172 D40_DREG_PSEG4,
173 D40_DREG_PCEG1,
174 D40_DREG_PCEG2,
175 D40_DREG_PCEG3,
176 D40_DREG_PCEG4,
177 D40_DREG_RSEG1,
178 D40_DREG_RSEG2,
179 D40_DREG_RSEG3,
180 D40_DREG_RSEG4,
181 D40_DREG_RCEG1,
182 D40_DREG_RCEG2,
183 D40_DREG_RCEG3,
184 D40_DREG_RCEG4,
185 };
186
187 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
188
189 static u32 d40_backup_regs_v4b[] = {
190 D40_DREG_CPSEG1,
191 D40_DREG_CPSEG2,
192 D40_DREG_CPSEG3,
193 D40_DREG_CPSEG4,
194 D40_DREG_CPSEG5,
195 D40_DREG_CPCEG1,
196 D40_DREG_CPCEG2,
197 D40_DREG_CPCEG3,
198 D40_DREG_CPCEG4,
199 D40_DREG_CPCEG5,
200 D40_DREG_CRSEG1,
201 D40_DREG_CRSEG2,
202 D40_DREG_CRSEG3,
203 D40_DREG_CRSEG4,
204 D40_DREG_CRSEG5,
205 D40_DREG_CRCEG1,
206 D40_DREG_CRCEG2,
207 D40_DREG_CRCEG3,
208 D40_DREG_CRCEG4,
209 D40_DREG_CRCEG5,
210 };
211
212 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
213
214 static u32 d40_backup_regs_chan[] = {
215 D40_CHAN_REG_SSCFG,
216 D40_CHAN_REG_SSELT,
217 D40_CHAN_REG_SSPTR,
218 D40_CHAN_REG_SSLNK,
219 D40_CHAN_REG_SDCFG,
220 D40_CHAN_REG_SDELT,
221 D40_CHAN_REG_SDPTR,
222 D40_CHAN_REG_SDLNK,
223 };
224
225 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
226 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
227
228 /**
229 * struct d40_interrupt_lookup - lookup table for interrupt handler
230 *
231 * @src: Interrupt mask register.
232 * @clr: Interrupt clear register.
233 * @is_error: true if this is an error interrupt.
234 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
235 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
236 */
237 struct d40_interrupt_lookup {
238 u32 src;
239 u32 clr;
240 bool is_error;
241 int offset;
242 };
243
244
245 static struct d40_interrupt_lookup il_v4a[] = {
246 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
247 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
248 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
249 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
250 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
251 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
252 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
253 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
254 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
255 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
256 };
257
258 static struct d40_interrupt_lookup il_v4b[] = {
259 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
260 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
261 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
262 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
263 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
264 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
265 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
266 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
267 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
268 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
269 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
270 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
271 };
272
273 /**
274 * struct d40_reg_val - simple lookup struct
275 *
276 * @reg: The register.
277 * @val: The value that belongs to the register in reg.
278 */
279 struct d40_reg_val {
280 unsigned int reg;
281 unsigned int val;
282 };
283
284 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
285 /* Clock every part of the DMA block from start */
286 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
287
288 /* Interrupts on all logical channels */
289 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
290 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
291 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
292 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
293 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
294 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
295 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
296 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
297 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
298 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
299 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
300 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
301 };
302 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
303 /* Clock every part of the DMA block from start */
304 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
305
306 /* Interrupts on all logical channels */
307 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
308 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
309 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
310 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
311 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
312 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
313 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
314 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
315 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
316 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
317 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
318 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
319 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
320 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
321 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
322 };
323
324 /**
325 * struct d40_lli_pool - Structure for keeping LLIs in memory
326 *
327 * @base: Pointer to memory area when the pre_alloc_lli's are not large
328 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
329 * pre_alloc_lli is used.
330 * @dma_addr: DMA address, if mapped
331 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
332 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
333 * one buffer to one buffer.
334 */
335 struct d40_lli_pool {
336 void *base;
337 int size;
338 dma_addr_t dma_addr;
339 /* Space for dst and src, plus an extra for padding */
340 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
341 };
342
343 /**
344 * struct d40_desc - A descriptor is one DMA job.
345 *
346 * @lli_phy: LLI settings for physical channel. Both src and dst=
347 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
348 * lli_len equals one.
349 * @lli_log: Same as above but for logical channels.
350 * @lli_pool: The pool with two entries pre-allocated.
351 * @lli_len: Number of llis of current descriptor.
352 * @lli_current: Number of transferred llis.
353 * @lcla_alloc: Number of LCLA entries allocated.
354 * @txd: DMA engine struct. Used for among other things for communication
355 * during a transfer.
356 * @node: List entry.
357 * @is_in_client_list: true if the client owns this descriptor.
358 * @cyclic: true if this is a cyclic job
359 *
360 * This descriptor is used for both logical and physical transfers.
361 */
362 struct d40_desc {
363 /* LLI physical */
364 struct d40_phy_lli_bidir lli_phy;
365 /* LLI logical */
366 struct d40_log_lli_bidir lli_log;
367
368 struct d40_lli_pool lli_pool;
369 int lli_len;
370 int lli_current;
371 int lcla_alloc;
372
373 struct dma_async_tx_descriptor txd;
374 struct list_head node;
375
376 bool is_in_client_list;
377 bool cyclic;
378 };
379
380 /**
381 * struct d40_lcla_pool - LCLA pool settings and data.
382 *
383 * @base: The virtual address of LCLA. 18 bit aligned.
384 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385 * This pointer is only there for clean-up on error.
386 * @pages: The number of pages needed for all physical channels.
387 * Only used later for clean-up on error
388 * @lock: Lock to protect the content in this struct.
389 * @alloc_map: big map over which LCLA entry is own by which job.
390 */
391 struct d40_lcla_pool {
392 void *base;
393 dma_addr_t dma_addr;
394 void *base_unaligned;
395 int pages;
396 spinlock_t lock;
397 struct d40_desc **alloc_map;
398 };
399
400 /**
401 * struct d40_phy_res - struct for handling eventlines mapped to physical
402 * channels.
403 *
404 * @lock: A lock protection this entity.
405 * @reserved: True if used by secure world or otherwise.
406 * @num: The physical channel number of this entity.
407 * @allocated_src: Bit mapped to show which src event line's are mapped to
408 * this physical channel. Can also be free or physically allocated.
409 * @allocated_dst: Same as for src but is dst.
410 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
411 * event line number.
412 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
413 */
414 struct d40_phy_res {
415 spinlock_t lock;
416 bool reserved;
417 int num;
418 u32 allocated_src;
419 u32 allocated_dst;
420 bool use_soft_lli;
421 };
422
423 struct d40_base;
424
425 /**
426 * struct d40_chan - Struct that describes a channel.
427 *
428 * @lock: A spinlock to protect this struct.
429 * @log_num: The logical number, if any of this channel.
430 * @pending_tx: The number of pending transfers. Used between interrupt handler
431 * and tasklet.
432 * @busy: Set to true when transfer is ongoing on this channel.
433 * @phy_chan: Pointer to physical channel which this instance runs on. If this
434 * point is NULL, then the channel is not allocated.
435 * @chan: DMA engine handle.
436 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
437 * transfer and call client callback.
438 * @client: Cliented owned descriptor list.
439 * @pending_queue: Submitted jobs, to be issued by issue_pending()
440 * @active: Active descriptor.
441 * @done: Completed jobs
442 * @queue: Queued jobs.
443 * @prepare_queue: Prepared jobs.
444 * @dma_cfg: The client configuration of this dma channel.
445 * @configured: whether the dma_cfg configuration is valid
446 * @base: Pointer to the device instance struct.
447 * @src_def_cfg: Default cfg register setting for src.
448 * @dst_def_cfg: Default cfg register setting for dst.
449 * @log_def: Default logical channel settings.
450 * @lcpa: Pointer to dst and src lcpa settings.
451 * @runtime_addr: runtime configured address.
452 * @runtime_direction: runtime configured direction.
453 *
454 * This struct can either "be" a logical or a physical channel.
455 */
456 struct d40_chan {
457 spinlock_t lock;
458 int log_num;
459 int pending_tx;
460 bool busy;
461 struct d40_phy_res *phy_chan;
462 struct dma_chan chan;
463 struct tasklet_struct tasklet;
464 struct list_head client;
465 struct list_head pending_queue;
466 struct list_head active;
467 struct list_head done;
468 struct list_head queue;
469 struct list_head prepare_queue;
470 struct stedma40_chan_cfg dma_cfg;
471 bool configured;
472 struct d40_base *base;
473 /* Default register configurations */
474 u32 src_def_cfg;
475 u32 dst_def_cfg;
476 struct d40_def_lcsp log_def;
477 struct d40_log_lli_full *lcpa;
478 /* Runtime reconfiguration */
479 dma_addr_t runtime_addr;
480 enum dma_transfer_direction runtime_direction;
481 };
482
483 /**
484 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
485 * controller
486 *
487 * @backup: the pointer to the registers address array for backup
488 * @backup_size: the size of the registers address array for backup
489 * @realtime_en: the realtime enable register
490 * @realtime_clear: the realtime clear register
491 * @high_prio_en: the high priority enable register
492 * @high_prio_clear: the high priority clear register
493 * @interrupt_en: the interrupt enable register
494 * @interrupt_clear: the interrupt clear register
495 * @il: the pointer to struct d40_interrupt_lookup
496 * @il_size: the size of d40_interrupt_lookup array
497 * @init_reg: the pointer to the struct d40_reg_val
498 * @init_reg_size: the size of d40_reg_val array
499 */
500 struct d40_gen_dmac {
501 u32 *backup;
502 u32 backup_size;
503 u32 realtime_en;
504 u32 realtime_clear;
505 u32 high_prio_en;
506 u32 high_prio_clear;
507 u32 interrupt_en;
508 u32 interrupt_clear;
509 struct d40_interrupt_lookup *il;
510 u32 il_size;
511 struct d40_reg_val *init_reg;
512 u32 init_reg_size;
513 };
514
515 /**
516 * struct d40_base - The big global struct, one for each probe'd instance.
517 *
518 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
519 * @execmd_lock: Lock for execute command usage since several channels share
520 * the same physical register.
521 * @dev: The device structure.
522 * @virtbase: The virtual base address of the DMA's register.
523 * @rev: silicon revision detected.
524 * @clk: Pointer to the DMA clock structure.
525 * @phy_start: Physical memory start of the DMA registers.
526 * @phy_size: Size of the DMA register map.
527 * @irq: The IRQ number.
528 * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
529 * transfers).
530 * @num_phy_chans: The number of physical channels. Read from HW. This
531 * is the number of available channels for this driver, not counting "Secure
532 * mode" allocated physical channels.
533 * @num_log_chans: The number of logical channels. Calculated from
534 * num_phy_chans.
535 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
536 * @dma_slave: dma_device channels that can do only do slave transfers.
537 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
538 * @phy_chans: Room for all possible physical channels in system.
539 * @log_chans: Room for all possible logical channels in system.
540 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
541 * to log_chans entries.
542 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
543 * to phy_chans entries.
544 * @plat_data: Pointer to provided platform_data which is the driver
545 * configuration.
546 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
547 * @phy_res: Vector containing all physical channels.
548 * @lcla_pool: lcla pool settings and data.
549 * @lcpa_base: The virtual mapped address of LCPA.
550 * @phy_lcpa: The physical address of the LCPA.
551 * @lcpa_size: The size of the LCPA area.
552 * @desc_slab: cache for descriptors.
553 * @reg_val_backup: Here the values of some hardware registers are stored
554 * before the DMA is powered off. They are restored when the power is back on.
555 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
556 * later
557 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
558 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
559 * @gen_dmac: the struct for generic registers values to represent u8500/8540
560 * DMA controller
561 */
562 struct d40_base {
563 spinlock_t interrupt_lock;
564 spinlock_t execmd_lock;
565 struct device *dev;
566 void __iomem *virtbase;
567 u8 rev:4;
568 struct clk *clk;
569 phys_addr_t phy_start;
570 resource_size_t phy_size;
571 int irq;
572 int num_memcpy_chans;
573 int num_phy_chans;
574 int num_log_chans;
575 struct device_dma_parameters dma_parms;
576 struct dma_device dma_both;
577 struct dma_device dma_slave;
578 struct dma_device dma_memcpy;
579 struct d40_chan *phy_chans;
580 struct d40_chan *log_chans;
581 struct d40_chan **lookup_log_chans;
582 struct d40_chan **lookup_phy_chans;
583 struct stedma40_platform_data *plat_data;
584 struct regulator *lcpa_regulator;
585 /* Physical half channels */
586 struct d40_phy_res *phy_res;
587 struct d40_lcla_pool lcla_pool;
588 void *lcpa_base;
589 dma_addr_t phy_lcpa;
590 resource_size_t lcpa_size;
591 struct kmem_cache *desc_slab;
592 u32 reg_val_backup[BACKUP_REGS_SZ];
593 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
594 u32 *reg_val_backup_chan;
595 u16 gcc_pwr_off_mask;
596 struct d40_gen_dmac gen_dmac;
597 };
598
599 static struct device *chan2dev(struct d40_chan *d40c)
600 {
601 return &d40c->chan.dev->device;
602 }
603
604 static bool chan_is_physical(struct d40_chan *chan)
605 {
606 return chan->log_num == D40_PHY_CHAN;
607 }
608
609 static bool chan_is_logical(struct d40_chan *chan)
610 {
611 return !chan_is_physical(chan);
612 }
613
614 static void __iomem *chan_base(struct d40_chan *chan)
615 {
616 return chan->base->virtbase + D40_DREG_PCBASE +
617 chan->phy_chan->num * D40_DREG_PCDELTA;
618 }
619
620 #define d40_err(dev, format, arg...) \
621 dev_err(dev, "[%s] " format, __func__, ## arg)
622
623 #define chan_err(d40c, format, arg...) \
624 d40_err(chan2dev(d40c), format, ## arg)
625
626 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
627 int lli_len)
628 {
629 bool is_log = chan_is_logical(d40c);
630 u32 align;
631 void *base;
632
633 if (is_log)
634 align = sizeof(struct d40_log_lli);
635 else
636 align = sizeof(struct d40_phy_lli);
637
638 if (lli_len == 1) {
639 base = d40d->lli_pool.pre_alloc_lli;
640 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
641 d40d->lli_pool.base = NULL;
642 } else {
643 d40d->lli_pool.size = lli_len * 2 * align;
644
645 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
646 d40d->lli_pool.base = base;
647
648 if (d40d->lli_pool.base == NULL)
649 return -ENOMEM;
650 }
651
652 if (is_log) {
653 d40d->lli_log.src = PTR_ALIGN(base, align);
654 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
655
656 d40d->lli_pool.dma_addr = 0;
657 } else {
658 d40d->lli_phy.src = PTR_ALIGN(base, align);
659 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
660
661 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
662 d40d->lli_phy.src,
663 d40d->lli_pool.size,
664 DMA_TO_DEVICE);
665
666 if (dma_mapping_error(d40c->base->dev,
667 d40d->lli_pool.dma_addr)) {
668 kfree(d40d->lli_pool.base);
669 d40d->lli_pool.base = NULL;
670 d40d->lli_pool.dma_addr = 0;
671 return -ENOMEM;
672 }
673 }
674
675 return 0;
676 }
677
678 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
679 {
680 if (d40d->lli_pool.dma_addr)
681 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
682 d40d->lli_pool.size, DMA_TO_DEVICE);
683
684 kfree(d40d->lli_pool.base);
685 d40d->lli_pool.base = NULL;
686 d40d->lli_pool.size = 0;
687 d40d->lli_log.src = NULL;
688 d40d->lli_log.dst = NULL;
689 d40d->lli_phy.src = NULL;
690 d40d->lli_phy.dst = NULL;
691 }
692
693 static int d40_lcla_alloc_one(struct d40_chan *d40c,
694 struct d40_desc *d40d)
695 {
696 unsigned long flags;
697 int i;
698 int ret = -EINVAL;
699
700 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
701
702 /*
703 * Allocate both src and dst at the same time, therefore the half
704 * start on 1 since 0 can't be used since zero is used as end marker.
705 */
706 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
707 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
708
709 if (!d40c->base->lcla_pool.alloc_map[idx]) {
710 d40c->base->lcla_pool.alloc_map[idx] = d40d;
711 d40d->lcla_alloc++;
712 ret = i;
713 break;
714 }
715 }
716
717 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
718
719 return ret;
720 }
721
722 static int d40_lcla_free_all(struct d40_chan *d40c,
723 struct d40_desc *d40d)
724 {
725 unsigned long flags;
726 int i;
727 int ret = -EINVAL;
728
729 if (chan_is_physical(d40c))
730 return 0;
731
732 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
733
734 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
735 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
736
737 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
738 d40c->base->lcla_pool.alloc_map[idx] = NULL;
739 d40d->lcla_alloc--;
740 if (d40d->lcla_alloc == 0) {
741 ret = 0;
742 break;
743 }
744 }
745 }
746
747 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
748
749 return ret;
750
751 }
752
753 static void d40_desc_remove(struct d40_desc *d40d)
754 {
755 list_del(&d40d->node);
756 }
757
758 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
759 {
760 struct d40_desc *desc = NULL;
761
762 if (!list_empty(&d40c->client)) {
763 struct d40_desc *d;
764 struct d40_desc *_d;
765
766 list_for_each_entry_safe(d, _d, &d40c->client, node) {
767 if (async_tx_test_ack(&d->txd)) {
768 d40_desc_remove(d);
769 desc = d;
770 memset(desc, 0, sizeof(*desc));
771 break;
772 }
773 }
774 }
775
776 if (!desc)
777 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
778
779 if (desc)
780 INIT_LIST_HEAD(&desc->node);
781
782 return desc;
783 }
784
785 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
786 {
787
788 d40_pool_lli_free(d40c, d40d);
789 d40_lcla_free_all(d40c, d40d);
790 kmem_cache_free(d40c->base->desc_slab, d40d);
791 }
792
793 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
794 {
795 list_add_tail(&desc->node, &d40c->active);
796 }
797
798 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
799 {
800 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
801 struct d40_phy_lli *lli_src = desc->lli_phy.src;
802 void __iomem *base = chan_base(chan);
803
804 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
805 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
806 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
807 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
808
809 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
810 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
811 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
812 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
813 }
814
815 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
816 {
817 list_add_tail(&desc->node, &d40c->done);
818 }
819
820 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
821 {
822 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
823 struct d40_log_lli_bidir *lli = &desc->lli_log;
824 int lli_current = desc->lli_current;
825 int lli_len = desc->lli_len;
826 bool cyclic = desc->cyclic;
827 int curr_lcla = -EINVAL;
828 int first_lcla = 0;
829 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
830 bool linkback;
831
832 /*
833 * We may have partially running cyclic transfers, in case we did't get
834 * enough LCLA entries.
835 */
836 linkback = cyclic && lli_current == 0;
837
838 /*
839 * For linkback, we need one LCLA even with only one link, because we
840 * can't link back to the one in LCPA space
841 */
842 if (linkback || (lli_len - lli_current > 1)) {
843 /*
844 * If the channel is expected to use only soft_lli don't
845 * allocate a lcla. This is to avoid a HW issue that exists
846 * in some controller during a peripheral to memory transfer
847 * that uses linked lists.
848 */
849 if (!(chan->phy_chan->use_soft_lli &&
850 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
851 curr_lcla = d40_lcla_alloc_one(chan, desc);
852
853 first_lcla = curr_lcla;
854 }
855
856 /*
857 * For linkback, we normally load the LCPA in the loop since we need to
858 * link it to the second LCLA and not the first. However, if we
859 * couldn't even get a first LCLA, then we have to run in LCPA and
860 * reload manually.
861 */
862 if (!linkback || curr_lcla == -EINVAL) {
863 unsigned int flags = 0;
864
865 if (curr_lcla == -EINVAL)
866 flags |= LLI_TERM_INT;
867
868 d40_log_lli_lcpa_write(chan->lcpa,
869 &lli->dst[lli_current],
870 &lli->src[lli_current],
871 curr_lcla,
872 flags);
873 lli_current++;
874 }
875
876 if (curr_lcla < 0)
877 goto out;
878
879 for (; lli_current < lli_len; lli_current++) {
880 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
881 8 * curr_lcla * 2;
882 struct d40_log_lli *lcla = pool->base + lcla_offset;
883 unsigned int flags = 0;
884 int next_lcla;
885
886 if (lli_current + 1 < lli_len)
887 next_lcla = d40_lcla_alloc_one(chan, desc);
888 else
889 next_lcla = linkback ? first_lcla : -EINVAL;
890
891 if (cyclic || next_lcla == -EINVAL)
892 flags |= LLI_TERM_INT;
893
894 if (linkback && curr_lcla == first_lcla) {
895 /* First link goes in both LCPA and LCLA */
896 d40_log_lli_lcpa_write(chan->lcpa,
897 &lli->dst[lli_current],
898 &lli->src[lli_current],
899 next_lcla, flags);
900 }
901
902 /*
903 * One unused LCLA in the cyclic case if the very first
904 * next_lcla fails...
905 */
906 d40_log_lli_lcla_write(lcla,
907 &lli->dst[lli_current],
908 &lli->src[lli_current],
909 next_lcla, flags);
910
911 /*
912 * Cache maintenance is not needed if lcla is
913 * mapped in esram
914 */
915 if (!use_esram_lcla) {
916 dma_sync_single_range_for_device(chan->base->dev,
917 pool->dma_addr, lcla_offset,
918 2 * sizeof(struct d40_log_lli),
919 DMA_TO_DEVICE);
920 }
921 curr_lcla = next_lcla;
922
923 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
924 lli_current++;
925 break;
926 }
927 }
928
929 out:
930 desc->lli_current = lli_current;
931 }
932
933 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
934 {
935 if (chan_is_physical(d40c)) {
936 d40_phy_lli_load(d40c, d40d);
937 d40d->lli_current = d40d->lli_len;
938 } else
939 d40_log_lli_to_lcxa(d40c, d40d);
940 }
941
942 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
943 {
944 return list_first_entry_or_null(&d40c->active, struct d40_desc, node);
945 }
946
947 /* remove desc from current queue and add it to the pending_queue */
948 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
949 {
950 d40_desc_remove(desc);
951 desc->is_in_client_list = false;
952 list_add_tail(&desc->node, &d40c->pending_queue);
953 }
954
955 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
956 {
957 return list_first_entry_or_null(&d40c->pending_queue, struct d40_desc,
958 node);
959 }
960
961 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
962 {
963 return list_first_entry_or_null(&d40c->queue, struct d40_desc, node);
964 }
965
966 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
967 {
968 return list_first_entry_or_null(&d40c->done, struct d40_desc, node);
969 }
970
971 static int d40_psize_2_burst_size(bool is_log, int psize)
972 {
973 if (is_log) {
974 if (psize == STEDMA40_PSIZE_LOG_1)
975 return 1;
976 } else {
977 if (psize == STEDMA40_PSIZE_PHY_1)
978 return 1;
979 }
980
981 return 2 << psize;
982 }
983
984 /*
985 * The dma only supports transmitting packages up to
986 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
987 *
988 * Calculate the total number of dma elements required to send the entire sg list.
989 */
990 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
991 {
992 int dmalen;
993 u32 max_w = max(data_width1, data_width2);
994 u32 min_w = min(data_width1, data_width2);
995 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
996
997 if (seg_max > STEDMA40_MAX_SEG_SIZE)
998 seg_max -= max_w;
999
1000 if (!IS_ALIGNED(size, max_w))
1001 return -EINVAL;
1002
1003 if (size <= seg_max)
1004 dmalen = 1;
1005 else {
1006 dmalen = size / seg_max;
1007 if (dmalen * seg_max < size)
1008 dmalen++;
1009 }
1010 return dmalen;
1011 }
1012
1013 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1014 u32 data_width1, u32 data_width2)
1015 {
1016 struct scatterlist *sg;
1017 int i;
1018 int len = 0;
1019 int ret;
1020
1021 for_each_sg(sgl, sg, sg_len, i) {
1022 ret = d40_size_2_dmalen(sg_dma_len(sg),
1023 data_width1, data_width2);
1024 if (ret < 0)
1025 return ret;
1026 len += ret;
1027 }
1028 return len;
1029 }
1030
1031 static int __d40_execute_command_phy(struct d40_chan *d40c,
1032 enum d40_command command)
1033 {
1034 u32 status;
1035 int i;
1036 void __iomem *active_reg;
1037 int ret = 0;
1038 unsigned long flags;
1039 u32 wmask;
1040
1041 if (command == D40_DMA_STOP) {
1042 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1043 if (ret)
1044 return ret;
1045 }
1046
1047 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1048
1049 if (d40c->phy_chan->num % 2 == 0)
1050 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1051 else
1052 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1053
1054 if (command == D40_DMA_SUSPEND_REQ) {
1055 status = (readl(active_reg) &
1056 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1057 D40_CHAN_POS(d40c->phy_chan->num);
1058
1059 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1060 goto done;
1061 }
1062
1063 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1064 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1065 active_reg);
1066
1067 if (command == D40_DMA_SUSPEND_REQ) {
1068
1069 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1070 status = (readl(active_reg) &
1071 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1072 D40_CHAN_POS(d40c->phy_chan->num);
1073
1074 cpu_relax();
1075 /*
1076 * Reduce the number of bus accesses while
1077 * waiting for the DMA to suspend.
1078 */
1079 udelay(3);
1080
1081 if (status == D40_DMA_STOP ||
1082 status == D40_DMA_SUSPENDED)
1083 break;
1084 }
1085
1086 if (i == D40_SUSPEND_MAX_IT) {
1087 chan_err(d40c,
1088 "unable to suspend the chl %d (log: %d) status %x\n",
1089 d40c->phy_chan->num, d40c->log_num,
1090 status);
1091 dump_stack();
1092 ret = -EBUSY;
1093 }
1094
1095 }
1096 done:
1097 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1098 return ret;
1099 }
1100
1101 static void d40_term_all(struct d40_chan *d40c)
1102 {
1103 struct d40_desc *d40d;
1104 struct d40_desc *_d;
1105
1106 /* Release completed descriptors */
1107 while ((d40d = d40_first_done(d40c))) {
1108 d40_desc_remove(d40d);
1109 d40_desc_free(d40c, d40d);
1110 }
1111
1112 /* Release active descriptors */
1113 while ((d40d = d40_first_active_get(d40c))) {
1114 d40_desc_remove(d40d);
1115 d40_desc_free(d40c, d40d);
1116 }
1117
1118 /* Release queued descriptors waiting for transfer */
1119 while ((d40d = d40_first_queued(d40c))) {
1120 d40_desc_remove(d40d);
1121 d40_desc_free(d40c, d40d);
1122 }
1123
1124 /* Release pending descriptors */
1125 while ((d40d = d40_first_pending(d40c))) {
1126 d40_desc_remove(d40d);
1127 d40_desc_free(d40c, d40d);
1128 }
1129
1130 /* Release client owned descriptors */
1131 if (!list_empty(&d40c->client))
1132 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1133 d40_desc_remove(d40d);
1134 d40_desc_free(d40c, d40d);
1135 }
1136
1137 /* Release descriptors in prepare queue */
1138 if (!list_empty(&d40c->prepare_queue))
1139 list_for_each_entry_safe(d40d, _d,
1140 &d40c->prepare_queue, node) {
1141 d40_desc_remove(d40d);
1142 d40_desc_free(d40c, d40d);
1143 }
1144
1145 d40c->pending_tx = 0;
1146 }
1147
1148 static void __d40_config_set_event(struct d40_chan *d40c,
1149 enum d40_events event_type, u32 event,
1150 int reg)
1151 {
1152 void __iomem *addr = chan_base(d40c) + reg;
1153 int tries;
1154 u32 status;
1155
1156 switch (event_type) {
1157
1158 case D40_DEACTIVATE_EVENTLINE:
1159
1160 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1161 | ~D40_EVENTLINE_MASK(event), addr);
1162 break;
1163
1164 case D40_SUSPEND_REQ_EVENTLINE:
1165 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1166 D40_EVENTLINE_POS(event);
1167
1168 if (status == D40_DEACTIVATE_EVENTLINE ||
1169 status == D40_SUSPEND_REQ_EVENTLINE)
1170 break;
1171
1172 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1173 | ~D40_EVENTLINE_MASK(event), addr);
1174
1175 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1176
1177 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1178 D40_EVENTLINE_POS(event);
1179
1180 cpu_relax();
1181 /*
1182 * Reduce the number of bus accesses while
1183 * waiting for the DMA to suspend.
1184 */
1185 udelay(3);
1186
1187 if (status == D40_DEACTIVATE_EVENTLINE)
1188 break;
1189 }
1190
1191 if (tries == D40_SUSPEND_MAX_IT) {
1192 chan_err(d40c,
1193 "unable to stop the event_line chl %d (log: %d)"
1194 "status %x\n", d40c->phy_chan->num,
1195 d40c->log_num, status);
1196 }
1197 break;
1198
1199 case D40_ACTIVATE_EVENTLINE:
1200 /*
1201 * The hardware sometimes doesn't register the enable when src and dst
1202 * event lines are active on the same logical channel. Retry to ensure
1203 * it does. Usually only one retry is sufficient.
1204 */
1205 tries = 100;
1206 while (--tries) {
1207 writel((D40_ACTIVATE_EVENTLINE <<
1208 D40_EVENTLINE_POS(event)) |
1209 ~D40_EVENTLINE_MASK(event), addr);
1210
1211 if (readl(addr) & D40_EVENTLINE_MASK(event))
1212 break;
1213 }
1214
1215 if (tries != 99)
1216 dev_dbg(chan2dev(d40c),
1217 "[%s] workaround enable S%cLNK (%d tries)\n",
1218 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1219 100 - tries);
1220
1221 WARN_ON(!tries);
1222 break;
1223
1224 case D40_ROUND_EVENTLINE:
1225 BUG();
1226 break;
1227
1228 }
1229 }
1230
1231 static void d40_config_set_event(struct d40_chan *d40c,
1232 enum d40_events event_type)
1233 {
1234 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1235
1236 /* Enable event line connected to device (or memcpy) */
1237 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1238 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1239 __d40_config_set_event(d40c, event_type, event,
1240 D40_CHAN_REG_SSLNK);
1241
1242 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1243 __d40_config_set_event(d40c, event_type, event,
1244 D40_CHAN_REG_SDLNK);
1245 }
1246
1247 static u32 d40_chan_has_events(struct d40_chan *d40c)
1248 {
1249 void __iomem *chanbase = chan_base(d40c);
1250 u32 val;
1251
1252 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1253 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1254
1255 return val;
1256 }
1257
1258 static int
1259 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1260 {
1261 unsigned long flags;
1262 int ret = 0;
1263 u32 active_status;
1264 void __iomem *active_reg;
1265
1266 if (d40c->phy_chan->num % 2 == 0)
1267 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1268 else
1269 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1270
1271
1272 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1273
1274 switch (command) {
1275 case D40_DMA_STOP:
1276 case D40_DMA_SUSPEND_REQ:
1277
1278 active_status = (readl(active_reg) &
1279 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1280 D40_CHAN_POS(d40c->phy_chan->num);
1281
1282 if (active_status == D40_DMA_RUN)
1283 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1284 else
1285 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1286
1287 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1288 ret = __d40_execute_command_phy(d40c, command);
1289
1290 break;
1291
1292 case D40_DMA_RUN:
1293
1294 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1295 ret = __d40_execute_command_phy(d40c, command);
1296 break;
1297
1298 case D40_DMA_SUSPENDED:
1299 BUG();
1300 break;
1301 }
1302
1303 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1304 return ret;
1305 }
1306
1307 static int d40_channel_execute_command(struct d40_chan *d40c,
1308 enum d40_command command)
1309 {
1310 if (chan_is_logical(d40c))
1311 return __d40_execute_command_log(d40c, command);
1312 else
1313 return __d40_execute_command_phy(d40c, command);
1314 }
1315
1316 static u32 d40_get_prmo(struct d40_chan *d40c)
1317 {
1318 static const unsigned int phy_map[] = {
1319 [STEDMA40_PCHAN_BASIC_MODE]
1320 = D40_DREG_PRMO_PCHAN_BASIC,
1321 [STEDMA40_PCHAN_MODULO_MODE]
1322 = D40_DREG_PRMO_PCHAN_MODULO,
1323 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1324 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1325 };
1326 static const unsigned int log_map[] = {
1327 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1328 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1329 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1330 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1331 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1332 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1333 };
1334
1335 if (chan_is_physical(d40c))
1336 return phy_map[d40c->dma_cfg.mode_opt];
1337 else
1338 return log_map[d40c->dma_cfg.mode_opt];
1339 }
1340
1341 static void d40_config_write(struct d40_chan *d40c)
1342 {
1343 u32 addr_base;
1344 u32 var;
1345
1346 /* Odd addresses are even addresses + 4 */
1347 addr_base = (d40c->phy_chan->num % 2) * 4;
1348 /* Setup channel mode to logical or physical */
1349 var = ((u32)(chan_is_logical(d40c)) + 1) <<
1350 D40_CHAN_POS(d40c->phy_chan->num);
1351 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1352
1353 /* Setup operational mode option register */
1354 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1355
1356 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1357
1358 if (chan_is_logical(d40c)) {
1359 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1360 & D40_SREG_ELEM_LOG_LIDX_MASK;
1361 void __iomem *chanbase = chan_base(d40c);
1362
1363 /* Set default config for CFG reg */
1364 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1365 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1366
1367 /* Set LIDX for lcla */
1368 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1369 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1370
1371 /* Clear LNK which will be used by d40_chan_has_events() */
1372 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1373 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1374 }
1375 }
1376
1377 static u32 d40_residue(struct d40_chan *d40c)
1378 {
1379 u32 num_elt;
1380
1381 if (chan_is_logical(d40c))
1382 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1383 >> D40_MEM_LCSP2_ECNT_POS;
1384 else {
1385 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1386 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1387 >> D40_SREG_ELEM_PHY_ECNT_POS;
1388 }
1389
1390 return num_elt * d40c->dma_cfg.dst_info.data_width;
1391 }
1392
1393 static bool d40_tx_is_linked(struct d40_chan *d40c)
1394 {
1395 bool is_link;
1396
1397 if (chan_is_logical(d40c))
1398 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1399 else
1400 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1401 & D40_SREG_LNK_PHYS_LNK_MASK;
1402
1403 return is_link;
1404 }
1405
1406 static int d40_pause(struct dma_chan *chan)
1407 {
1408 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1409 int res = 0;
1410 unsigned long flags;
1411
1412 if (d40c->phy_chan == NULL) {
1413 chan_err(d40c, "Channel is not allocated!\n");
1414 return -EINVAL;
1415 }
1416
1417 if (!d40c->busy)
1418 return 0;
1419
1420 spin_lock_irqsave(&d40c->lock, flags);
1421 pm_runtime_get_sync(d40c->base->dev);
1422
1423 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1424
1425 pm_runtime_mark_last_busy(d40c->base->dev);
1426 pm_runtime_put_autosuspend(d40c->base->dev);
1427 spin_unlock_irqrestore(&d40c->lock, flags);
1428 return res;
1429 }
1430
1431 static int d40_resume(struct dma_chan *chan)
1432 {
1433 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1434 int res = 0;
1435 unsigned long flags;
1436
1437 if (d40c->phy_chan == NULL) {
1438 chan_err(d40c, "Channel is not allocated!\n");
1439 return -EINVAL;
1440 }
1441
1442 if (!d40c->busy)
1443 return 0;
1444
1445 spin_lock_irqsave(&d40c->lock, flags);
1446 pm_runtime_get_sync(d40c->base->dev);
1447
1448 /* If bytes left to transfer or linked tx resume job */
1449 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1450 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1451
1452 pm_runtime_mark_last_busy(d40c->base->dev);
1453 pm_runtime_put_autosuspend(d40c->base->dev);
1454 spin_unlock_irqrestore(&d40c->lock, flags);
1455 return res;
1456 }
1457
1458 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1459 {
1460 struct d40_chan *d40c = container_of(tx->chan,
1461 struct d40_chan,
1462 chan);
1463 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1464 unsigned long flags;
1465 dma_cookie_t cookie;
1466
1467 spin_lock_irqsave(&d40c->lock, flags);
1468 cookie = dma_cookie_assign(tx);
1469 d40_desc_queue(d40c, d40d);
1470 spin_unlock_irqrestore(&d40c->lock, flags);
1471
1472 return cookie;
1473 }
1474
1475 static int d40_start(struct d40_chan *d40c)
1476 {
1477 return d40_channel_execute_command(d40c, D40_DMA_RUN);
1478 }
1479
1480 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1481 {
1482 struct d40_desc *d40d;
1483 int err;
1484
1485 /* Start queued jobs, if any */
1486 d40d = d40_first_queued(d40c);
1487
1488 if (d40d != NULL) {
1489 if (!d40c->busy) {
1490 d40c->busy = true;
1491 pm_runtime_get_sync(d40c->base->dev);
1492 }
1493
1494 /* Remove from queue */
1495 d40_desc_remove(d40d);
1496
1497 /* Add to active queue */
1498 d40_desc_submit(d40c, d40d);
1499
1500 /* Initiate DMA job */
1501 d40_desc_load(d40c, d40d);
1502
1503 /* Start dma job */
1504 err = d40_start(d40c);
1505
1506 if (err)
1507 return NULL;
1508 }
1509
1510 return d40d;
1511 }
1512
1513 /* called from interrupt context */
1514 static void dma_tc_handle(struct d40_chan *d40c)
1515 {
1516 struct d40_desc *d40d;
1517
1518 /* Get first active entry from list */
1519 d40d = d40_first_active_get(d40c);
1520
1521 if (d40d == NULL)
1522 return;
1523
1524 if (d40d->cyclic) {
1525 /*
1526 * If this was a paritially loaded list, we need to reloaded
1527 * it, and only when the list is completed. We need to check
1528 * for done because the interrupt will hit for every link, and
1529 * not just the last one.
1530 */
1531 if (d40d->lli_current < d40d->lli_len
1532 && !d40_tx_is_linked(d40c)
1533 && !d40_residue(d40c)) {
1534 d40_lcla_free_all(d40c, d40d);
1535 d40_desc_load(d40c, d40d);
1536 (void) d40_start(d40c);
1537
1538 if (d40d->lli_current == d40d->lli_len)
1539 d40d->lli_current = 0;
1540 }
1541 } else {
1542 d40_lcla_free_all(d40c, d40d);
1543
1544 if (d40d->lli_current < d40d->lli_len) {
1545 d40_desc_load(d40c, d40d);
1546 /* Start dma job */
1547 (void) d40_start(d40c);
1548 return;
1549 }
1550
1551 if (d40_queue_start(d40c) == NULL) {
1552 d40c->busy = false;
1553
1554 pm_runtime_mark_last_busy(d40c->base->dev);
1555 pm_runtime_put_autosuspend(d40c->base->dev);
1556 }
1557
1558 d40_desc_remove(d40d);
1559 d40_desc_done(d40c, d40d);
1560 }
1561
1562 d40c->pending_tx++;
1563 tasklet_schedule(&d40c->tasklet);
1564
1565 }
1566
1567 static void dma_tasklet(unsigned long data)
1568 {
1569 struct d40_chan *d40c = (struct d40_chan *) data;
1570 struct d40_desc *d40d;
1571 unsigned long flags;
1572 bool callback_active;
1573 struct dmaengine_desc_callback cb;
1574
1575 spin_lock_irqsave(&d40c->lock, flags);
1576
1577 /* Get first entry from the done list */
1578 d40d = d40_first_done(d40c);
1579 if (d40d == NULL) {
1580 /* Check if we have reached here for cyclic job */
1581 d40d = d40_first_active_get(d40c);
1582 if (d40d == NULL || !d40d->cyclic)
1583 goto err;
1584 }
1585
1586 if (!d40d->cyclic)
1587 dma_cookie_complete(&d40d->txd);
1588
1589 /*
1590 * If terminating a channel pending_tx is set to zero.
1591 * This prevents any finished active jobs to return to the client.
1592 */
1593 if (d40c->pending_tx == 0) {
1594 spin_unlock_irqrestore(&d40c->lock, flags);
1595 return;
1596 }
1597
1598 /* Callback to client */
1599 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
1600 dmaengine_desc_get_callback(&d40d->txd, &cb);
1601
1602 if (!d40d->cyclic) {
1603 if (async_tx_test_ack(&d40d->txd)) {
1604 d40_desc_remove(d40d);
1605 d40_desc_free(d40c, d40d);
1606 } else if (!d40d->is_in_client_list) {
1607 d40_desc_remove(d40d);
1608 d40_lcla_free_all(d40c, d40d);
1609 list_add_tail(&d40d->node, &d40c->client);
1610 d40d->is_in_client_list = true;
1611 }
1612 }
1613
1614 d40c->pending_tx--;
1615
1616 if (d40c->pending_tx)
1617 tasklet_schedule(&d40c->tasklet);
1618
1619 spin_unlock_irqrestore(&d40c->lock, flags);
1620
1621 if (callback_active)
1622 dmaengine_desc_callback_invoke(&cb, NULL);
1623
1624 return;
1625
1626 err:
1627 /* Rescue manouver if receiving double interrupts */
1628 if (d40c->pending_tx > 0)
1629 d40c->pending_tx--;
1630 spin_unlock_irqrestore(&d40c->lock, flags);
1631 }
1632
1633 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1634 {
1635 int i;
1636 u32 idx;
1637 u32 row;
1638 long chan = -1;
1639 struct d40_chan *d40c;
1640 unsigned long flags;
1641 struct d40_base *base = data;
1642 u32 regs[base->gen_dmac.il_size];
1643 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1644 u32 il_size = base->gen_dmac.il_size;
1645
1646 spin_lock_irqsave(&base->interrupt_lock, flags);
1647
1648 /* Read interrupt status of both logical and physical channels */
1649 for (i = 0; i < il_size; i++)
1650 regs[i] = readl(base->virtbase + il[i].src);
1651
1652 for (;;) {
1653
1654 chan = find_next_bit((unsigned long *)regs,
1655 BITS_PER_LONG * il_size, chan + 1);
1656
1657 /* No more set bits found? */
1658 if (chan == BITS_PER_LONG * il_size)
1659 break;
1660
1661 row = chan / BITS_PER_LONG;
1662 idx = chan & (BITS_PER_LONG - 1);
1663
1664 if (il[row].offset == D40_PHY_CHAN)
1665 d40c = base->lookup_phy_chans[idx];
1666 else
1667 d40c = base->lookup_log_chans[il[row].offset + idx];
1668
1669 if (!d40c) {
1670 /*
1671 * No error because this can happen if something else
1672 * in the system is using the channel.
1673 */
1674 continue;
1675 }
1676
1677 /* ACK interrupt */
1678 writel(BIT(idx), base->virtbase + il[row].clr);
1679
1680 spin_lock(&d40c->lock);
1681
1682 if (!il[row].is_error)
1683 dma_tc_handle(d40c);
1684 else
1685 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1686 chan, il[row].offset, idx);
1687
1688 spin_unlock(&d40c->lock);
1689 }
1690
1691 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1692
1693 return IRQ_HANDLED;
1694 }
1695
1696 static int d40_validate_conf(struct d40_chan *d40c,
1697 struct stedma40_chan_cfg *conf)
1698 {
1699 int res = 0;
1700 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1701
1702 if (!conf->dir) {
1703 chan_err(d40c, "Invalid direction.\n");
1704 res = -EINVAL;
1705 }
1706
1707 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1708 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1709 (conf->dev_type < 0)) {
1710 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1711 res = -EINVAL;
1712 }
1713
1714 if (conf->dir == DMA_DEV_TO_DEV) {
1715 /*
1716 * DMAC HW supports it. Will be added to this driver,
1717 * in case any dma client requires it.
1718 */
1719 chan_err(d40c, "periph to periph not supported\n");
1720 res = -EINVAL;
1721 }
1722
1723 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1724 conf->src_info.data_width !=
1725 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1726 conf->dst_info.data_width) {
1727 /*
1728 * The DMAC hardware only supports
1729 * src (burst x width) == dst (burst x width)
1730 */
1731
1732 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1733 res = -EINVAL;
1734 }
1735
1736 return res;
1737 }
1738
1739 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1740 bool is_src, int log_event_line, bool is_log,
1741 bool *first_user)
1742 {
1743 unsigned long flags;
1744 spin_lock_irqsave(&phy->lock, flags);
1745
1746 *first_user = ((phy->allocated_src | phy->allocated_dst)
1747 == D40_ALLOC_FREE);
1748
1749 if (!is_log) {
1750 /* Physical interrupts are masked per physical full channel */
1751 if (phy->allocated_src == D40_ALLOC_FREE &&
1752 phy->allocated_dst == D40_ALLOC_FREE) {
1753 phy->allocated_dst = D40_ALLOC_PHY;
1754 phy->allocated_src = D40_ALLOC_PHY;
1755 goto found;
1756 } else
1757 goto not_found;
1758 }
1759
1760 /* Logical channel */
1761 if (is_src) {
1762 if (phy->allocated_src == D40_ALLOC_PHY)
1763 goto not_found;
1764
1765 if (phy->allocated_src == D40_ALLOC_FREE)
1766 phy->allocated_src = D40_ALLOC_LOG_FREE;
1767
1768 if (!(phy->allocated_src & BIT(log_event_line))) {
1769 phy->allocated_src |= BIT(log_event_line);
1770 goto found;
1771 } else
1772 goto not_found;
1773 } else {
1774 if (phy->allocated_dst == D40_ALLOC_PHY)
1775 goto not_found;
1776
1777 if (phy->allocated_dst == D40_ALLOC_FREE)
1778 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1779
1780 if (!(phy->allocated_dst & BIT(log_event_line))) {
1781 phy->allocated_dst |= BIT(log_event_line);
1782 goto found;
1783 } else
1784 goto not_found;
1785 }
1786
1787 not_found:
1788 spin_unlock_irqrestore(&phy->lock, flags);
1789 return false;
1790 found:
1791 spin_unlock_irqrestore(&phy->lock, flags);
1792 return true;
1793 }
1794
1795 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1796 int log_event_line)
1797 {
1798 unsigned long flags;
1799 bool is_free = false;
1800
1801 spin_lock_irqsave(&phy->lock, flags);
1802 if (!log_event_line) {
1803 phy->allocated_dst = D40_ALLOC_FREE;
1804 phy->allocated_src = D40_ALLOC_FREE;
1805 is_free = true;
1806 goto out;
1807 }
1808
1809 /* Logical channel */
1810 if (is_src) {
1811 phy->allocated_src &= ~BIT(log_event_line);
1812 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1813 phy->allocated_src = D40_ALLOC_FREE;
1814 } else {
1815 phy->allocated_dst &= ~BIT(log_event_line);
1816 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1817 phy->allocated_dst = D40_ALLOC_FREE;
1818 }
1819
1820 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1821 D40_ALLOC_FREE);
1822
1823 out:
1824 spin_unlock_irqrestore(&phy->lock, flags);
1825
1826 return is_free;
1827 }
1828
1829 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1830 {
1831 int dev_type = d40c->dma_cfg.dev_type;
1832 int event_group;
1833 int event_line;
1834 struct d40_phy_res *phys;
1835 int i;
1836 int j;
1837 int log_num;
1838 int num_phy_chans;
1839 bool is_src;
1840 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1841
1842 phys = d40c->base->phy_res;
1843 num_phy_chans = d40c->base->num_phy_chans;
1844
1845 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1846 log_num = 2 * dev_type;
1847 is_src = true;
1848 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1849 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1850 /* dst event lines are used for logical memcpy */
1851 log_num = 2 * dev_type + 1;
1852 is_src = false;
1853 } else
1854 return -EINVAL;
1855
1856 event_group = D40_TYPE_TO_GROUP(dev_type);
1857 event_line = D40_TYPE_TO_EVENT(dev_type);
1858
1859 if (!is_log) {
1860 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1861 /* Find physical half channel */
1862 if (d40c->dma_cfg.use_fixed_channel) {
1863 i = d40c->dma_cfg.phy_channel;
1864 if (d40_alloc_mask_set(&phys[i], is_src,
1865 0, is_log,
1866 first_phy_user))
1867 goto found_phy;
1868 } else {
1869 for (i = 0; i < num_phy_chans; i++) {
1870 if (d40_alloc_mask_set(&phys[i], is_src,
1871 0, is_log,
1872 first_phy_user))
1873 goto found_phy;
1874 }
1875 }
1876 } else
1877 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1878 int phy_num = j + event_group * 2;
1879 for (i = phy_num; i < phy_num + 2; i++) {
1880 if (d40_alloc_mask_set(&phys[i],
1881 is_src,
1882 0,
1883 is_log,
1884 first_phy_user))
1885 goto found_phy;
1886 }
1887 }
1888 return -EINVAL;
1889 found_phy:
1890 d40c->phy_chan = &phys[i];
1891 d40c->log_num = D40_PHY_CHAN;
1892 goto out;
1893 }
1894 if (dev_type == -1)
1895 return -EINVAL;
1896
1897 /* Find logical channel */
1898 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1899 int phy_num = j + event_group * 2;
1900
1901 if (d40c->dma_cfg.use_fixed_channel) {
1902 i = d40c->dma_cfg.phy_channel;
1903
1904 if ((i != phy_num) && (i != phy_num + 1)) {
1905 dev_err(chan2dev(d40c),
1906 "invalid fixed phy channel %d\n", i);
1907 return -EINVAL;
1908 }
1909
1910 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1911 is_log, first_phy_user))
1912 goto found_log;
1913
1914 dev_err(chan2dev(d40c),
1915 "could not allocate fixed phy channel %d\n", i);
1916 return -EINVAL;
1917 }
1918
1919 /*
1920 * Spread logical channels across all available physical rather
1921 * than pack every logical channel at the first available phy
1922 * channels.
1923 */
1924 if (is_src) {
1925 for (i = phy_num; i < phy_num + 2; i++) {
1926 if (d40_alloc_mask_set(&phys[i], is_src,
1927 event_line, is_log,
1928 first_phy_user))
1929 goto found_log;
1930 }
1931 } else {
1932 for (i = phy_num + 1; i >= phy_num; i--) {
1933 if (d40_alloc_mask_set(&phys[i], is_src,
1934 event_line, is_log,
1935 first_phy_user))
1936 goto found_log;
1937 }
1938 }
1939 }
1940 return -EINVAL;
1941
1942 found_log:
1943 d40c->phy_chan = &phys[i];
1944 d40c->log_num = log_num;
1945 out:
1946
1947 if (is_log)
1948 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1949 else
1950 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1951
1952 return 0;
1953
1954 }
1955
1956 static int d40_config_memcpy(struct d40_chan *d40c)
1957 {
1958 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1959
1960 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1961 d40c->dma_cfg = dma40_memcpy_conf_log;
1962 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
1963
1964 d40_log_cfg(&d40c->dma_cfg,
1965 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1966
1967 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1968 dma_has_cap(DMA_SLAVE, cap)) {
1969 d40c->dma_cfg = dma40_memcpy_conf_phy;
1970
1971 /* Generate interrrupt at end of transfer or relink. */
1972 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
1973
1974 /* Generate interrupt on error. */
1975 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
1976 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
1977
1978 } else {
1979 chan_err(d40c, "No memcpy\n");
1980 return -EINVAL;
1981 }
1982
1983 return 0;
1984 }
1985
1986 static int d40_free_dma(struct d40_chan *d40c)
1987 {
1988
1989 int res = 0;
1990 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1991 struct d40_phy_res *phy = d40c->phy_chan;
1992 bool is_src;
1993
1994 /* Terminate all queued and active transfers */
1995 d40_term_all(d40c);
1996
1997 if (phy == NULL) {
1998 chan_err(d40c, "phy == null\n");
1999 return -EINVAL;
2000 }
2001
2002 if (phy->allocated_src == D40_ALLOC_FREE &&
2003 phy->allocated_dst == D40_ALLOC_FREE) {
2004 chan_err(d40c, "channel already free\n");
2005 return -EINVAL;
2006 }
2007
2008 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2009 d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2010 is_src = false;
2011 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2012 is_src = true;
2013 else {
2014 chan_err(d40c, "Unknown direction\n");
2015 return -EINVAL;
2016 }
2017
2018 pm_runtime_get_sync(d40c->base->dev);
2019 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2020 if (res) {
2021 chan_err(d40c, "stop failed\n");
2022 goto out;
2023 }
2024
2025 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2026
2027 if (chan_is_logical(d40c))
2028 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2029 else
2030 d40c->base->lookup_phy_chans[phy->num] = NULL;
2031
2032 if (d40c->busy) {
2033 pm_runtime_mark_last_busy(d40c->base->dev);
2034 pm_runtime_put_autosuspend(d40c->base->dev);
2035 }
2036
2037 d40c->busy = false;
2038 d40c->phy_chan = NULL;
2039 d40c->configured = false;
2040 out:
2041
2042 pm_runtime_mark_last_busy(d40c->base->dev);
2043 pm_runtime_put_autosuspend(d40c->base->dev);
2044 return res;
2045 }
2046
2047 static bool d40_is_paused(struct d40_chan *d40c)
2048 {
2049 void __iomem *chanbase = chan_base(d40c);
2050 bool is_paused = false;
2051 unsigned long flags;
2052 void __iomem *active_reg;
2053 u32 status;
2054 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2055
2056 spin_lock_irqsave(&d40c->lock, flags);
2057
2058 if (chan_is_physical(d40c)) {
2059 if (d40c->phy_chan->num % 2 == 0)
2060 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2061 else
2062 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2063
2064 status = (readl(active_reg) &
2065 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2066 D40_CHAN_POS(d40c->phy_chan->num);
2067 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2068 is_paused = true;
2069
2070 goto _exit;
2071 }
2072
2073 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2074 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2075 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2076 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2077 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2078 } else {
2079 chan_err(d40c, "Unknown direction\n");
2080 goto _exit;
2081 }
2082
2083 status = (status & D40_EVENTLINE_MASK(event)) >>
2084 D40_EVENTLINE_POS(event);
2085
2086 if (status != D40_DMA_RUN)
2087 is_paused = true;
2088 _exit:
2089 spin_unlock_irqrestore(&d40c->lock, flags);
2090 return is_paused;
2091
2092 }
2093
2094 static u32 stedma40_residue(struct dma_chan *chan)
2095 {
2096 struct d40_chan *d40c =
2097 container_of(chan, struct d40_chan, chan);
2098 u32 bytes_left;
2099 unsigned long flags;
2100
2101 spin_lock_irqsave(&d40c->lock, flags);
2102 bytes_left = d40_residue(d40c);
2103 spin_unlock_irqrestore(&d40c->lock, flags);
2104
2105 return bytes_left;
2106 }
2107
2108 static int
2109 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2110 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2111 unsigned int sg_len, dma_addr_t src_dev_addr,
2112 dma_addr_t dst_dev_addr)
2113 {
2114 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2115 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2116 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2117 int ret;
2118
2119 ret = d40_log_sg_to_lli(sg_src, sg_len,
2120 src_dev_addr,
2121 desc->lli_log.src,
2122 chan->log_def.lcsp1,
2123 src_info->data_width,
2124 dst_info->data_width);
2125
2126 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2127 dst_dev_addr,
2128 desc->lli_log.dst,
2129 chan->log_def.lcsp3,
2130 dst_info->data_width,
2131 src_info->data_width);
2132
2133 return ret < 0 ? ret : 0;
2134 }
2135
2136 static int
2137 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2138 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2139 unsigned int sg_len, dma_addr_t src_dev_addr,
2140 dma_addr_t dst_dev_addr)
2141 {
2142 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2143 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2144 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2145 unsigned long flags = 0;
2146 int ret;
2147
2148 if (desc->cyclic)
2149 flags |= LLI_CYCLIC | LLI_TERM_INT;
2150
2151 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2152 desc->lli_phy.src,
2153 virt_to_phys(desc->lli_phy.src),
2154 chan->src_def_cfg,
2155 src_info, dst_info, flags);
2156
2157 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2158 desc->lli_phy.dst,
2159 virt_to_phys(desc->lli_phy.dst),
2160 chan->dst_def_cfg,
2161 dst_info, src_info, flags);
2162
2163 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2164 desc->lli_pool.size, DMA_TO_DEVICE);
2165
2166 return ret < 0 ? ret : 0;
2167 }
2168
2169 static struct d40_desc *
2170 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2171 unsigned int sg_len, unsigned long dma_flags)
2172 {
2173 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2174 struct d40_desc *desc;
2175 int ret;
2176
2177 desc = d40_desc_get(chan);
2178 if (!desc)
2179 return NULL;
2180
2181 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2182 cfg->dst_info.data_width);
2183 if (desc->lli_len < 0) {
2184 chan_err(chan, "Unaligned size\n");
2185 goto err;
2186 }
2187
2188 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2189 if (ret < 0) {
2190 chan_err(chan, "Could not allocate lli\n");
2191 goto err;
2192 }
2193
2194 desc->lli_current = 0;
2195 desc->txd.flags = dma_flags;
2196 desc->txd.tx_submit = d40_tx_submit;
2197
2198 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2199
2200 return desc;
2201
2202 err:
2203 d40_desc_free(chan, desc);
2204 return NULL;
2205 }
2206
2207 static struct dma_async_tx_descriptor *
2208 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2209 struct scatterlist *sg_dst, unsigned int sg_len,
2210 enum dma_transfer_direction direction, unsigned long dma_flags)
2211 {
2212 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2213 dma_addr_t src_dev_addr = 0;
2214 dma_addr_t dst_dev_addr = 0;
2215 struct d40_desc *desc;
2216 unsigned long flags;
2217 int ret;
2218
2219 if (!chan->phy_chan) {
2220 chan_err(chan, "Cannot prepare unallocated channel\n");
2221 return NULL;
2222 }
2223
2224 spin_lock_irqsave(&chan->lock, flags);
2225
2226 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2227 if (desc == NULL)
2228 goto err;
2229
2230 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2231 desc->cyclic = true;
2232
2233 if (direction == DMA_DEV_TO_MEM)
2234 src_dev_addr = chan->runtime_addr;
2235 else if (direction == DMA_MEM_TO_DEV)
2236 dst_dev_addr = chan->runtime_addr;
2237
2238 if (chan_is_logical(chan))
2239 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2240 sg_len, src_dev_addr, dst_dev_addr);
2241 else
2242 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2243 sg_len, src_dev_addr, dst_dev_addr);
2244
2245 if (ret) {
2246 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2247 chan_is_logical(chan) ? "log" : "phy", ret);
2248 goto err;
2249 }
2250
2251 /*
2252 * add descriptor to the prepare queue in order to be able
2253 * to free them later in terminate_all
2254 */
2255 list_add_tail(&desc->node, &chan->prepare_queue);
2256
2257 spin_unlock_irqrestore(&chan->lock, flags);
2258
2259 return &desc->txd;
2260
2261 err:
2262 if (desc)
2263 d40_desc_free(chan, desc);
2264 spin_unlock_irqrestore(&chan->lock, flags);
2265 return NULL;
2266 }
2267
2268 bool stedma40_filter(struct dma_chan *chan, void *data)
2269 {
2270 struct stedma40_chan_cfg *info = data;
2271 struct d40_chan *d40c =
2272 container_of(chan, struct d40_chan, chan);
2273 int err;
2274
2275 if (data) {
2276 err = d40_validate_conf(d40c, info);
2277 if (!err)
2278 d40c->dma_cfg = *info;
2279 } else
2280 err = d40_config_memcpy(d40c);
2281
2282 if (!err)
2283 d40c->configured = true;
2284
2285 return err == 0;
2286 }
2287 EXPORT_SYMBOL(stedma40_filter);
2288
2289 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2290 {
2291 bool realtime = d40c->dma_cfg.realtime;
2292 bool highprio = d40c->dma_cfg.high_priority;
2293 u32 rtreg;
2294 u32 event = D40_TYPE_TO_EVENT(dev_type);
2295 u32 group = D40_TYPE_TO_GROUP(dev_type);
2296 u32 bit = BIT(event);
2297 u32 prioreg;
2298 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2299
2300 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2301 /*
2302 * Due to a hardware bug, in some cases a logical channel triggered by
2303 * a high priority destination event line can generate extra packet
2304 * transactions.
2305 *
2306 * The workaround is to not set the high priority level for the
2307 * destination event lines that trigger logical channels.
2308 */
2309 if (!src && chan_is_logical(d40c))
2310 highprio = false;
2311
2312 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2313
2314 /* Destination event lines are stored in the upper halfword */
2315 if (!src)
2316 bit <<= 16;
2317
2318 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2319 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2320 }
2321
2322 static void d40_set_prio_realtime(struct d40_chan *d40c)
2323 {
2324 if (d40c->base->rev < 3)
2325 return;
2326
2327 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
2328 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2329 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2330
2331 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
2332 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2333 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2334 }
2335
2336 #define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2337 #define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2338 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2339 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2340 #define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
2341
2342 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2343 struct of_dma *ofdma)
2344 {
2345 struct stedma40_chan_cfg cfg;
2346 dma_cap_mask_t cap;
2347 u32 flags;
2348
2349 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2350
2351 dma_cap_zero(cap);
2352 dma_cap_set(DMA_SLAVE, cap);
2353
2354 cfg.dev_type = dma_spec->args[0];
2355 flags = dma_spec->args[2];
2356
2357 switch (D40_DT_FLAGS_MODE(flags)) {
2358 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2359 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2360 }
2361
2362 switch (D40_DT_FLAGS_DIR(flags)) {
2363 case 0:
2364 cfg.dir = DMA_MEM_TO_DEV;
2365 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2366 break;
2367 case 1:
2368 cfg.dir = DMA_DEV_TO_MEM;
2369 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2370 break;
2371 }
2372
2373 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2374 cfg.phy_channel = dma_spec->args[1];
2375 cfg.use_fixed_channel = true;
2376 }
2377
2378 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2379 cfg.high_priority = true;
2380
2381 return dma_request_channel(cap, stedma40_filter, &cfg);
2382 }
2383
2384 /* DMA ENGINE functions */
2385 static int d40_alloc_chan_resources(struct dma_chan *chan)
2386 {
2387 int err;
2388 unsigned long flags;
2389 struct d40_chan *d40c =
2390 container_of(chan, struct d40_chan, chan);
2391 bool is_free_phy;
2392 spin_lock_irqsave(&d40c->lock, flags);
2393
2394 dma_cookie_init(chan);
2395
2396 /* If no dma configuration is set use default configuration (memcpy) */
2397 if (!d40c->configured) {
2398 err = d40_config_memcpy(d40c);
2399 if (err) {
2400 chan_err(d40c, "Failed to configure memcpy channel\n");
2401 goto fail;
2402 }
2403 }
2404
2405 err = d40_allocate_channel(d40c, &is_free_phy);
2406 if (err) {
2407 chan_err(d40c, "Failed to allocate channel\n");
2408 d40c->configured = false;
2409 goto fail;
2410 }
2411
2412 pm_runtime_get_sync(d40c->base->dev);
2413
2414 d40_set_prio_realtime(d40c);
2415
2416 if (chan_is_logical(d40c)) {
2417 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2418 d40c->lcpa = d40c->base->lcpa_base +
2419 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2420 else
2421 d40c->lcpa = d40c->base->lcpa_base +
2422 d40c->dma_cfg.dev_type *
2423 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2424
2425 /* Unmask the Global Interrupt Mask. */
2426 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2427 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2428 }
2429
2430 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2431 chan_is_logical(d40c) ? "logical" : "physical",
2432 d40c->phy_chan->num,
2433 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2434
2435
2436 /*
2437 * Only write channel configuration to the DMA if the physical
2438 * resource is free. In case of multiple logical channels
2439 * on the same physical resource, only the first write is necessary.
2440 */
2441 if (is_free_phy)
2442 d40_config_write(d40c);
2443 fail:
2444 pm_runtime_mark_last_busy(d40c->base->dev);
2445 pm_runtime_put_autosuspend(d40c->base->dev);
2446 spin_unlock_irqrestore(&d40c->lock, flags);
2447 return err;
2448 }
2449
2450 static void d40_free_chan_resources(struct dma_chan *chan)
2451 {
2452 struct d40_chan *d40c =
2453 container_of(chan, struct d40_chan, chan);
2454 int err;
2455 unsigned long flags;
2456
2457 if (d40c->phy_chan == NULL) {
2458 chan_err(d40c, "Cannot free unallocated channel\n");
2459 return;
2460 }
2461
2462 spin_lock_irqsave(&d40c->lock, flags);
2463
2464 err = d40_free_dma(d40c);
2465
2466 if (err)
2467 chan_err(d40c, "Failed to free channel\n");
2468 spin_unlock_irqrestore(&d40c->lock, flags);
2469 }
2470
2471 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2472 dma_addr_t dst,
2473 dma_addr_t src,
2474 size_t size,
2475 unsigned long dma_flags)
2476 {
2477 struct scatterlist dst_sg;
2478 struct scatterlist src_sg;
2479
2480 sg_init_table(&dst_sg, 1);
2481 sg_init_table(&src_sg, 1);
2482
2483 sg_dma_address(&dst_sg) = dst;
2484 sg_dma_address(&src_sg) = src;
2485
2486 sg_dma_len(&dst_sg) = size;
2487 sg_dma_len(&src_sg) = size;
2488
2489 return d40_prep_sg(chan, &src_sg, &dst_sg, 1,
2490 DMA_MEM_TO_MEM, dma_flags);
2491 }
2492
2493 static struct dma_async_tx_descriptor *
2494 d40_prep_memcpy_sg(struct dma_chan *chan,
2495 struct scatterlist *dst_sg, unsigned int dst_nents,
2496 struct scatterlist *src_sg, unsigned int src_nents,
2497 unsigned long dma_flags)
2498 {
2499 if (dst_nents != src_nents)
2500 return NULL;
2501
2502 return d40_prep_sg(chan, src_sg, dst_sg, src_nents,
2503 DMA_MEM_TO_MEM, dma_flags);
2504 }
2505
2506 static struct dma_async_tx_descriptor *
2507 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2508 unsigned int sg_len, enum dma_transfer_direction direction,
2509 unsigned long dma_flags, void *context)
2510 {
2511 if (!is_slave_direction(direction))
2512 return NULL;
2513
2514 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2515 }
2516
2517 static struct dma_async_tx_descriptor *
2518 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2519 size_t buf_len, size_t period_len,
2520 enum dma_transfer_direction direction, unsigned long flags)
2521 {
2522 unsigned int periods = buf_len / period_len;
2523 struct dma_async_tx_descriptor *txd;
2524 struct scatterlist *sg;
2525 int i;
2526
2527 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2528 if (!sg)
2529 return NULL;
2530
2531 for (i = 0; i < periods; i++) {
2532 sg_dma_address(&sg[i]) = dma_addr;
2533 sg_dma_len(&sg[i]) = period_len;
2534 dma_addr += period_len;
2535 }
2536
2537 sg[periods].offset = 0;
2538 sg_dma_len(&sg[periods]) = 0;
2539 sg[periods].page_link =
2540 ((unsigned long)sg | 0x01) & ~0x02;
2541
2542 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2543 DMA_PREP_INTERRUPT);
2544
2545 kfree(sg);
2546
2547 return txd;
2548 }
2549
2550 static enum dma_status d40_tx_status(struct dma_chan *chan,
2551 dma_cookie_t cookie,
2552 struct dma_tx_state *txstate)
2553 {
2554 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2555 enum dma_status ret;
2556
2557 if (d40c->phy_chan == NULL) {
2558 chan_err(d40c, "Cannot read status of unallocated channel\n");
2559 return -EINVAL;
2560 }
2561
2562 ret = dma_cookie_status(chan, cookie, txstate);
2563 if (ret != DMA_COMPLETE && txstate)
2564 dma_set_residue(txstate, stedma40_residue(chan));
2565
2566 if (d40_is_paused(d40c))
2567 ret = DMA_PAUSED;
2568
2569 return ret;
2570 }
2571
2572 static void d40_issue_pending(struct dma_chan *chan)
2573 {
2574 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2575 unsigned long flags;
2576
2577 if (d40c->phy_chan == NULL) {
2578 chan_err(d40c, "Channel is not allocated!\n");
2579 return;
2580 }
2581
2582 spin_lock_irqsave(&d40c->lock, flags);
2583
2584 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2585
2586 /* Busy means that queued jobs are already being processed */
2587 if (!d40c->busy)
2588 (void) d40_queue_start(d40c);
2589
2590 spin_unlock_irqrestore(&d40c->lock, flags);
2591 }
2592
2593 static int d40_terminate_all(struct dma_chan *chan)
2594 {
2595 unsigned long flags;
2596 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2597 int ret;
2598
2599 if (d40c->phy_chan == NULL) {
2600 chan_err(d40c, "Channel is not allocated!\n");
2601 return -EINVAL;
2602 }
2603
2604 spin_lock_irqsave(&d40c->lock, flags);
2605
2606 pm_runtime_get_sync(d40c->base->dev);
2607 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2608 if (ret)
2609 chan_err(d40c, "Failed to stop channel\n");
2610
2611 d40_term_all(d40c);
2612 pm_runtime_mark_last_busy(d40c->base->dev);
2613 pm_runtime_put_autosuspend(d40c->base->dev);
2614 if (d40c->busy) {
2615 pm_runtime_mark_last_busy(d40c->base->dev);
2616 pm_runtime_put_autosuspend(d40c->base->dev);
2617 }
2618 d40c->busy = false;
2619
2620 spin_unlock_irqrestore(&d40c->lock, flags);
2621 return 0;
2622 }
2623
2624 static int
2625 dma40_config_to_halfchannel(struct d40_chan *d40c,
2626 struct stedma40_half_channel_info *info,
2627 u32 maxburst)
2628 {
2629 int psize;
2630
2631 if (chan_is_logical(d40c)) {
2632 if (maxburst >= 16)
2633 psize = STEDMA40_PSIZE_LOG_16;
2634 else if (maxburst >= 8)
2635 psize = STEDMA40_PSIZE_LOG_8;
2636 else if (maxburst >= 4)
2637 psize = STEDMA40_PSIZE_LOG_4;
2638 else
2639 psize = STEDMA40_PSIZE_LOG_1;
2640 } else {
2641 if (maxburst >= 16)
2642 psize = STEDMA40_PSIZE_PHY_16;
2643 else if (maxburst >= 8)
2644 psize = STEDMA40_PSIZE_PHY_8;
2645 else if (maxburst >= 4)
2646 psize = STEDMA40_PSIZE_PHY_4;
2647 else
2648 psize = STEDMA40_PSIZE_PHY_1;
2649 }
2650
2651 info->psize = psize;
2652 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2653
2654 return 0;
2655 }
2656
2657 /* Runtime reconfiguration extension */
2658 static int d40_set_runtime_config(struct dma_chan *chan,
2659 struct dma_slave_config *config)
2660 {
2661 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2662 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2663 enum dma_slave_buswidth src_addr_width, dst_addr_width;
2664 dma_addr_t config_addr;
2665 u32 src_maxburst, dst_maxburst;
2666 int ret;
2667
2668 if (d40c->phy_chan == NULL) {
2669 chan_err(d40c, "Channel is not allocated!\n");
2670 return -EINVAL;
2671 }
2672
2673 src_addr_width = config->src_addr_width;
2674 src_maxburst = config->src_maxburst;
2675 dst_addr_width = config->dst_addr_width;
2676 dst_maxburst = config->dst_maxburst;
2677
2678 if (config->direction == DMA_DEV_TO_MEM) {
2679 config_addr = config->src_addr;
2680
2681 if (cfg->dir != DMA_DEV_TO_MEM)
2682 dev_dbg(d40c->base->dev,
2683 "channel was not configured for peripheral "
2684 "to memory transfer (%d) overriding\n",
2685 cfg->dir);
2686 cfg->dir = DMA_DEV_TO_MEM;
2687
2688 /* Configure the memory side */
2689 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2690 dst_addr_width = src_addr_width;
2691 if (dst_maxburst == 0)
2692 dst_maxburst = src_maxburst;
2693
2694 } else if (config->direction == DMA_MEM_TO_DEV) {
2695 config_addr = config->dst_addr;
2696
2697 if (cfg->dir != DMA_MEM_TO_DEV)
2698 dev_dbg(d40c->base->dev,
2699 "channel was not configured for memory "
2700 "to peripheral transfer (%d) overriding\n",
2701 cfg->dir);
2702 cfg->dir = DMA_MEM_TO_DEV;
2703
2704 /* Configure the memory side */
2705 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2706 src_addr_width = dst_addr_width;
2707 if (src_maxburst == 0)
2708 src_maxburst = dst_maxburst;
2709 } else {
2710 dev_err(d40c->base->dev,
2711 "unrecognized channel direction %d\n",
2712 config->direction);
2713 return -EINVAL;
2714 }
2715
2716 if (config_addr <= 0) {
2717 dev_err(d40c->base->dev, "no address supplied\n");
2718 return -EINVAL;
2719 }
2720
2721 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2722 dev_err(d40c->base->dev,
2723 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2724 src_maxburst,
2725 src_addr_width,
2726 dst_maxburst,
2727 dst_addr_width);
2728 return -EINVAL;
2729 }
2730
2731 if (src_maxburst > 16) {
2732 src_maxburst = 16;
2733 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2734 } else if (dst_maxburst > 16) {
2735 dst_maxburst = 16;
2736 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2737 }
2738
2739 /* Only valid widths are; 1, 2, 4 and 8. */
2740 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2741 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2742 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2743 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2744 !is_power_of_2(src_addr_width) ||
2745 !is_power_of_2(dst_addr_width))
2746 return -EINVAL;
2747
2748 cfg->src_info.data_width = src_addr_width;
2749 cfg->dst_info.data_width = dst_addr_width;
2750
2751 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2752 src_maxburst);
2753 if (ret)
2754 return ret;
2755
2756 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2757 dst_maxburst);
2758 if (ret)
2759 return ret;
2760
2761 /* Fill in register values */
2762 if (chan_is_logical(d40c))
2763 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2764 else
2765 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2766
2767 /* These settings will take precedence later */
2768 d40c->runtime_addr = config_addr;
2769 d40c->runtime_direction = config->direction;
2770 dev_dbg(d40c->base->dev,
2771 "configured channel %s for %s, data width %d/%d, "
2772 "maxburst %d/%d elements, LE, no flow control\n",
2773 dma_chan_name(chan),
2774 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2775 src_addr_width, dst_addr_width,
2776 src_maxburst, dst_maxburst);
2777
2778 return 0;
2779 }
2780
2781 /* Initialization functions */
2782
2783 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2784 struct d40_chan *chans, int offset,
2785 int num_chans)
2786 {
2787 int i = 0;
2788 struct d40_chan *d40c;
2789
2790 INIT_LIST_HEAD(&dma->channels);
2791
2792 for (i = offset; i < offset + num_chans; i++) {
2793 d40c = &chans[i];
2794 d40c->base = base;
2795 d40c->chan.device = dma;
2796
2797 spin_lock_init(&d40c->lock);
2798
2799 d40c->log_num = D40_PHY_CHAN;
2800
2801 INIT_LIST_HEAD(&d40c->done);
2802 INIT_LIST_HEAD(&d40c->active);
2803 INIT_LIST_HEAD(&d40c->queue);
2804 INIT_LIST_HEAD(&d40c->pending_queue);
2805 INIT_LIST_HEAD(&d40c->client);
2806 INIT_LIST_HEAD(&d40c->prepare_queue);
2807
2808 tasklet_init(&d40c->tasklet, dma_tasklet,
2809 (unsigned long) d40c);
2810
2811 list_add_tail(&d40c->chan.device_node,
2812 &dma->channels);
2813 }
2814 }
2815
2816 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2817 {
2818 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2819 dev->device_prep_slave_sg = d40_prep_slave_sg;
2820
2821 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2822 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2823
2824 /*
2825 * This controller can only access address at even
2826 * 32bit boundaries, i.e. 2^2
2827 */
2828 dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
2829 }
2830
2831 if (dma_has_cap(DMA_SG, dev->cap_mask))
2832 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2833
2834 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2835 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2836
2837 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2838 dev->device_free_chan_resources = d40_free_chan_resources;
2839 dev->device_issue_pending = d40_issue_pending;
2840 dev->device_tx_status = d40_tx_status;
2841 dev->device_config = d40_set_runtime_config;
2842 dev->device_pause = d40_pause;
2843 dev->device_resume = d40_resume;
2844 dev->device_terminate_all = d40_terminate_all;
2845 dev->dev = base->dev;
2846 }
2847
2848 static int __init d40_dmaengine_init(struct d40_base *base,
2849 int num_reserved_chans)
2850 {
2851 int err ;
2852
2853 d40_chan_init(base, &base->dma_slave, base->log_chans,
2854 0, base->num_log_chans);
2855
2856 dma_cap_zero(base->dma_slave.cap_mask);
2857 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2858 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2859
2860 d40_ops_init(base, &base->dma_slave);
2861
2862 err = dma_async_device_register(&base->dma_slave);
2863
2864 if (err) {
2865 d40_err(base->dev, "Failed to register slave channels\n");
2866 goto failure1;
2867 }
2868
2869 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2870 base->num_log_chans, base->num_memcpy_chans);
2871
2872 dma_cap_zero(base->dma_memcpy.cap_mask);
2873 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2874 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2875
2876 d40_ops_init(base, &base->dma_memcpy);
2877
2878 err = dma_async_device_register(&base->dma_memcpy);
2879
2880 if (err) {
2881 d40_err(base->dev,
2882 "Failed to register memcpy only channels\n");
2883 goto failure2;
2884 }
2885
2886 d40_chan_init(base, &base->dma_both, base->phy_chans,
2887 0, num_reserved_chans);
2888
2889 dma_cap_zero(base->dma_both.cap_mask);
2890 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2891 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2892 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2893 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2894
2895 d40_ops_init(base, &base->dma_both);
2896 err = dma_async_device_register(&base->dma_both);
2897
2898 if (err) {
2899 d40_err(base->dev,
2900 "Failed to register logical and physical capable channels\n");
2901 goto failure3;
2902 }
2903 return 0;
2904 failure3:
2905 dma_async_device_unregister(&base->dma_memcpy);
2906 failure2:
2907 dma_async_device_unregister(&base->dma_slave);
2908 failure1:
2909 return err;
2910 }
2911
2912 /* Suspend resume functionality */
2913 #ifdef CONFIG_PM_SLEEP
2914 static int dma40_suspend(struct device *dev)
2915 {
2916 struct platform_device *pdev = to_platform_device(dev);
2917 struct d40_base *base = platform_get_drvdata(pdev);
2918 int ret;
2919
2920 ret = pm_runtime_force_suspend(dev);
2921 if (ret)
2922 return ret;
2923
2924 if (base->lcpa_regulator)
2925 ret = regulator_disable(base->lcpa_regulator);
2926 return ret;
2927 }
2928
2929 static int dma40_resume(struct device *dev)
2930 {
2931 struct platform_device *pdev = to_platform_device(dev);
2932 struct d40_base *base = platform_get_drvdata(pdev);
2933 int ret = 0;
2934
2935 if (base->lcpa_regulator) {
2936 ret = regulator_enable(base->lcpa_regulator);
2937 if (ret)
2938 return ret;
2939 }
2940
2941 return pm_runtime_force_resume(dev);
2942 }
2943 #endif
2944
2945 #ifdef CONFIG_PM
2946 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
2947 u32 *regaddr, int num, bool save)
2948 {
2949 int i;
2950
2951 for (i = 0; i < num; i++) {
2952 void __iomem *addr = baseaddr + regaddr[i];
2953
2954 if (save)
2955 backup[i] = readl_relaxed(addr);
2956 else
2957 writel_relaxed(backup[i], addr);
2958 }
2959 }
2960
2961 static void d40_save_restore_registers(struct d40_base *base, bool save)
2962 {
2963 int i;
2964
2965 /* Save/Restore channel specific registers */
2966 for (i = 0; i < base->num_phy_chans; i++) {
2967 void __iomem *addr;
2968 int idx;
2969
2970 if (base->phy_res[i].reserved)
2971 continue;
2972
2973 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2974 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
2975
2976 dma40_backup(addr, &base->reg_val_backup_chan[idx],
2977 d40_backup_regs_chan,
2978 ARRAY_SIZE(d40_backup_regs_chan),
2979 save);
2980 }
2981
2982 /* Save/Restore global registers */
2983 dma40_backup(base->virtbase, base->reg_val_backup,
2984 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
2985 save);
2986
2987 /* Save/Restore registers only existing on dma40 v3 and later */
2988 if (base->gen_dmac.backup)
2989 dma40_backup(base->virtbase, base->reg_val_backup_v4,
2990 base->gen_dmac.backup,
2991 base->gen_dmac.backup_size,
2992 save);
2993 }
2994
2995 static int dma40_runtime_suspend(struct device *dev)
2996 {
2997 struct platform_device *pdev = to_platform_device(dev);
2998 struct d40_base *base = platform_get_drvdata(pdev);
2999
3000 d40_save_restore_registers(base, true);
3001
3002 /* Don't disable/enable clocks for v1 due to HW bugs */
3003 if (base->rev != 1)
3004 writel_relaxed(base->gcc_pwr_off_mask,
3005 base->virtbase + D40_DREG_GCC);
3006
3007 return 0;
3008 }
3009
3010 static int dma40_runtime_resume(struct device *dev)
3011 {
3012 struct platform_device *pdev = to_platform_device(dev);
3013 struct d40_base *base = platform_get_drvdata(pdev);
3014
3015 d40_save_restore_registers(base, false);
3016
3017 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3018 base->virtbase + D40_DREG_GCC);
3019 return 0;
3020 }
3021 #endif
3022
3023 static const struct dev_pm_ops dma40_pm_ops = {
3024 SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume)
3025 SET_RUNTIME_PM_OPS(dma40_runtime_suspend,
3026 dma40_runtime_resume,
3027 NULL)
3028 };
3029
3030 /* Initialization functions. */
3031
3032 static int __init d40_phy_res_init(struct d40_base *base)
3033 {
3034 int i;
3035 int num_phy_chans_avail = 0;
3036 u32 val[2];
3037 int odd_even_bit = -2;
3038 int gcc = D40_DREG_GCC_ENA;
3039
3040 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3041 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3042
3043 for (i = 0; i < base->num_phy_chans; i++) {
3044 base->phy_res[i].num = i;
3045 odd_even_bit += 2 * ((i % 2) == 0);
3046 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3047 /* Mark security only channels as occupied */
3048 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3049 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3050 base->phy_res[i].reserved = true;
3051 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3052 D40_DREG_GCC_SRC);
3053 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3054 D40_DREG_GCC_DST);
3055
3056
3057 } else {
3058 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3059 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3060 base->phy_res[i].reserved = false;
3061 num_phy_chans_avail++;
3062 }
3063 spin_lock_init(&base->phy_res[i].lock);
3064 }
3065
3066 /* Mark disabled channels as occupied */
3067 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3068 int chan = base->plat_data->disabled_channels[i];
3069
3070 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3071 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3072 base->phy_res[chan].reserved = true;
3073 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3074 D40_DREG_GCC_SRC);
3075 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3076 D40_DREG_GCC_DST);
3077 num_phy_chans_avail--;
3078 }
3079
3080 /* Mark soft_lli channels */
3081 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3082 int chan = base->plat_data->soft_lli_chans[i];
3083
3084 base->phy_res[chan].use_soft_lli = true;
3085 }
3086
3087 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3088 num_phy_chans_avail, base->num_phy_chans);
3089
3090 /* Verify settings extended vs standard */
3091 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3092
3093 for (i = 0; i < base->num_phy_chans; i++) {
3094
3095 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3096 (val[0] & 0x3) != 1)
3097 dev_info(base->dev,
3098 "[%s] INFO: channel %d is misconfigured (%d)\n",
3099 __func__, i, val[0] & 0x3);
3100
3101 val[0] = val[0] >> 2;
3102 }
3103
3104 /*
3105 * To keep things simple, Enable all clocks initially.
3106 * The clocks will get managed later post channel allocation.
3107 * The clocks for the event lines on which reserved channels exists
3108 * are not managed here.
3109 */
3110 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3111 base->gcc_pwr_off_mask = gcc;
3112
3113 return num_phy_chans_avail;
3114 }
3115
3116 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3117 {
3118 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3119 struct clk *clk = NULL;
3120 void __iomem *virtbase = NULL;
3121 struct resource *res = NULL;
3122 struct d40_base *base = NULL;
3123 int num_log_chans = 0;
3124 int num_phy_chans;
3125 int num_memcpy_chans;
3126 int clk_ret = -EINVAL;
3127 int i;
3128 u32 pid;
3129 u32 cid;
3130 u8 rev;
3131
3132 clk = clk_get(&pdev->dev, NULL);
3133 if (IS_ERR(clk)) {
3134 d40_err(&pdev->dev, "No matching clock found\n");
3135 goto failure;
3136 }
3137
3138 clk_ret = clk_prepare_enable(clk);
3139 if (clk_ret) {
3140 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3141 goto failure;
3142 }
3143
3144 /* Get IO for DMAC base address */
3145 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3146 if (!res)
3147 goto failure;
3148
3149 if (request_mem_region(res->start, resource_size(res),
3150 D40_NAME " I/O base") == NULL)
3151 goto failure;
3152
3153 virtbase = ioremap(res->start, resource_size(res));
3154 if (!virtbase)
3155 goto failure;
3156
3157 /* This is just a regular AMBA PrimeCell ID actually */
3158 for (pid = 0, i = 0; i < 4; i++)
3159 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3160 & 255) << (i * 8);
3161 for (cid = 0, i = 0; i < 4; i++)
3162 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3163 & 255) << (i * 8);
3164
3165 if (cid != AMBA_CID) {
3166 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3167 goto failure;
3168 }
3169 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3170 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3171 AMBA_MANF_BITS(pid),
3172 AMBA_VENDOR_ST);
3173 goto failure;
3174 }
3175 /*
3176 * HW revision:
3177 * DB8500ed has revision 0
3178 * ? has revision 1
3179 * DB8500v1 has revision 2
3180 * DB8500v2 has revision 3
3181 * AP9540v1 has revision 4
3182 * DB8540v1 has revision 4
3183 */
3184 rev = AMBA_REV_BITS(pid);
3185 if (rev < 2) {
3186 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3187 goto failure;
3188 }
3189
3190 /* The number of physical channels on this HW */
3191 if (plat_data->num_of_phy_chans)
3192 num_phy_chans = plat_data->num_of_phy_chans;
3193 else
3194 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3195
3196 /* The number of channels used for memcpy */
3197 if (plat_data->num_of_memcpy_chans)
3198 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3199 else
3200 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3201
3202 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3203
3204 dev_info(&pdev->dev,
3205 "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3206 rev, &res->start, num_phy_chans, num_log_chans);
3207
3208 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3209 (num_phy_chans + num_log_chans + num_memcpy_chans) *
3210 sizeof(struct d40_chan), GFP_KERNEL);
3211
3212 if (base == NULL)
3213 goto failure;
3214
3215 base->rev = rev;
3216 base->clk = clk;
3217 base->num_memcpy_chans = num_memcpy_chans;
3218 base->num_phy_chans = num_phy_chans;
3219 base->num_log_chans = num_log_chans;
3220 base->phy_start = res->start;
3221 base->phy_size = resource_size(res);
3222 base->virtbase = virtbase;
3223 base->plat_data = plat_data;
3224 base->dev = &pdev->dev;
3225 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3226 base->log_chans = &base->phy_chans[num_phy_chans];
3227
3228 if (base->plat_data->num_of_phy_chans == 14) {
3229 base->gen_dmac.backup = d40_backup_regs_v4b;
3230 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3231 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3232 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3233 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3234 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3235 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3236 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3237 base->gen_dmac.il = il_v4b;
3238 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3239 base->gen_dmac.init_reg = dma_init_reg_v4b;
3240 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3241 } else {
3242 if (base->rev >= 3) {
3243 base->gen_dmac.backup = d40_backup_regs_v4a;
3244 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3245 }
3246 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3247 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3248 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3249 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3250 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3251 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3252 base->gen_dmac.il = il_v4a;
3253 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3254 base->gen_dmac.init_reg = dma_init_reg_v4a;
3255 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3256 }
3257
3258 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3259 GFP_KERNEL);
3260 if (!base->phy_res)
3261 goto failure;
3262
3263 base->lookup_phy_chans = kzalloc(num_phy_chans *
3264 sizeof(struct d40_chan *),
3265 GFP_KERNEL);
3266 if (!base->lookup_phy_chans)
3267 goto failure;
3268
3269 base->lookup_log_chans = kzalloc(num_log_chans *
3270 sizeof(struct d40_chan *),
3271 GFP_KERNEL);
3272 if (!base->lookup_log_chans)
3273 goto failure;
3274
3275 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3276 sizeof(d40_backup_regs_chan),
3277 GFP_KERNEL);
3278 if (!base->reg_val_backup_chan)
3279 goto failure;
3280
3281 base->lcla_pool.alloc_map =
3282 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3283 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
3284 if (!base->lcla_pool.alloc_map)
3285 goto failure;
3286
3287 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3288 0, SLAB_HWCACHE_ALIGN,
3289 NULL);
3290 if (base->desc_slab == NULL)
3291 goto failure;
3292
3293 return base;
3294
3295 failure:
3296 if (!clk_ret)
3297 clk_disable_unprepare(clk);
3298 if (!IS_ERR(clk))
3299 clk_put(clk);
3300 if (virtbase)
3301 iounmap(virtbase);
3302 if (res)
3303 release_mem_region(res->start,
3304 resource_size(res));
3305 if (virtbase)
3306 iounmap(virtbase);
3307
3308 if (base) {
3309 kfree(base->lcla_pool.alloc_map);
3310 kfree(base->reg_val_backup_chan);
3311 kfree(base->lookup_log_chans);
3312 kfree(base->lookup_phy_chans);
3313 kfree(base->phy_res);
3314 kfree(base);
3315 }
3316
3317 return NULL;
3318 }
3319
3320 static void __init d40_hw_init(struct d40_base *base)
3321 {
3322
3323 int i;
3324 u32 prmseo[2] = {0, 0};
3325 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3326 u32 pcmis = 0;
3327 u32 pcicr = 0;
3328 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3329 u32 reg_size = base->gen_dmac.init_reg_size;
3330
3331 for (i = 0; i < reg_size; i++)
3332 writel(dma_init_reg[i].val,
3333 base->virtbase + dma_init_reg[i].reg);
3334
3335 /* Configure all our dma channels to default settings */
3336 for (i = 0; i < base->num_phy_chans; i++) {
3337
3338 activeo[i % 2] = activeo[i % 2] << 2;
3339
3340 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3341 == D40_ALLOC_PHY) {
3342 activeo[i % 2] |= 3;
3343 continue;
3344 }
3345
3346 /* Enable interrupt # */
3347 pcmis = (pcmis << 1) | 1;
3348
3349 /* Clear interrupt # */
3350 pcicr = (pcicr << 1) | 1;
3351
3352 /* Set channel to physical mode */
3353 prmseo[i % 2] = prmseo[i % 2] << 2;
3354 prmseo[i % 2] |= 1;
3355
3356 }
3357
3358 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3359 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3360 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3361 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3362
3363 /* Write which interrupt to enable */
3364 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3365
3366 /* Write which interrupt to clear */
3367 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3368
3369 /* These are __initdata and cannot be accessed after init */
3370 base->gen_dmac.init_reg = NULL;
3371 base->gen_dmac.init_reg_size = 0;
3372 }
3373
3374 static int __init d40_lcla_allocate(struct d40_base *base)
3375 {
3376 struct d40_lcla_pool *pool = &base->lcla_pool;
3377 unsigned long *page_list;
3378 int i, j;
3379 int ret = 0;
3380
3381 /*
3382 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3383 * To full fill this hardware requirement without wasting 256 kb
3384 * we allocate pages until we get an aligned one.
3385 */
3386 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3387 GFP_KERNEL);
3388
3389 if (!page_list) {
3390 ret = -ENOMEM;
3391 goto failure;
3392 }
3393
3394 /* Calculating how many pages that are required */
3395 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3396
3397 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3398 page_list[i] = __get_free_pages(GFP_KERNEL,
3399 base->lcla_pool.pages);
3400 if (!page_list[i]) {
3401
3402 d40_err(base->dev, "Failed to allocate %d pages.\n",
3403 base->lcla_pool.pages);
3404 ret = -ENOMEM;
3405
3406 for (j = 0; j < i; j++)
3407 free_pages(page_list[j], base->lcla_pool.pages);
3408 goto failure;
3409 }
3410
3411 if ((virt_to_phys((void *)page_list[i]) &
3412 (LCLA_ALIGNMENT - 1)) == 0)
3413 break;
3414 }
3415
3416 for (j = 0; j < i; j++)
3417 free_pages(page_list[j], base->lcla_pool.pages);
3418
3419 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3420 base->lcla_pool.base = (void *)page_list[i];
3421 } else {
3422 /*
3423 * After many attempts and no succees with finding the correct
3424 * alignment, try with allocating a big buffer.
3425 */
3426 dev_warn(base->dev,
3427 "[%s] Failed to get %d pages @ 18 bit align.\n",
3428 __func__, base->lcla_pool.pages);
3429 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3430 base->num_phy_chans +
3431 LCLA_ALIGNMENT,
3432 GFP_KERNEL);
3433 if (!base->lcla_pool.base_unaligned) {
3434 ret = -ENOMEM;
3435 goto failure;
3436 }
3437
3438 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3439 LCLA_ALIGNMENT);
3440 }
3441
3442 pool->dma_addr = dma_map_single(base->dev, pool->base,
3443 SZ_1K * base->num_phy_chans,
3444 DMA_TO_DEVICE);
3445 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3446 pool->dma_addr = 0;
3447 ret = -ENOMEM;
3448 goto failure;
3449 }
3450
3451 writel(virt_to_phys(base->lcla_pool.base),
3452 base->virtbase + D40_DREG_LCLA);
3453 failure:
3454 kfree(page_list);
3455 return ret;
3456 }
3457
3458 static int __init d40_of_probe(struct platform_device *pdev,
3459 struct device_node *np)
3460 {
3461 struct stedma40_platform_data *pdata;
3462 int num_phy = 0, num_memcpy = 0, num_disabled = 0;
3463 const __be32 *list;
3464
3465 pdata = devm_kzalloc(&pdev->dev,
3466 sizeof(struct stedma40_platform_data),
3467 GFP_KERNEL);
3468 if (!pdata)
3469 return -ENOMEM;
3470
3471 /* If absent this value will be obtained from h/w. */
3472 of_property_read_u32(np, "dma-channels", &num_phy);
3473 if (num_phy > 0)
3474 pdata->num_of_phy_chans = num_phy;
3475
3476 list = of_get_property(np, "memcpy-channels", &num_memcpy);
3477 num_memcpy /= sizeof(*list);
3478
3479 if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3480 d40_err(&pdev->dev,
3481 "Invalid number of memcpy channels specified (%d)\n",
3482 num_memcpy);
3483 return -EINVAL;
3484 }
3485 pdata->num_of_memcpy_chans = num_memcpy;
3486
3487 of_property_read_u32_array(np, "memcpy-channels",
3488 dma40_memcpy_channels,
3489 num_memcpy);
3490
3491 list = of_get_property(np, "disabled-channels", &num_disabled);
3492 num_disabled /= sizeof(*list);
3493
3494 if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
3495 d40_err(&pdev->dev,
3496 "Invalid number of disabled channels specified (%d)\n",
3497 num_disabled);
3498 return -EINVAL;
3499 }
3500
3501 of_property_read_u32_array(np, "disabled-channels",
3502 pdata->disabled_channels,
3503 num_disabled);
3504 pdata->disabled_channels[num_disabled] = -1;
3505
3506 pdev->dev.platform_data = pdata;
3507
3508 return 0;
3509 }
3510
3511 static int __init d40_probe(struct platform_device *pdev)
3512 {
3513 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3514 struct device_node *np = pdev->dev.of_node;
3515 int ret = -ENOENT;
3516 struct d40_base *base;
3517 struct resource *res;
3518 int num_reserved_chans;
3519 u32 val;
3520
3521 if (!plat_data) {
3522 if (np) {
3523 if (d40_of_probe(pdev, np)) {
3524 ret = -ENOMEM;
3525 goto report_failure;
3526 }
3527 } else {
3528 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3529 goto report_failure;
3530 }
3531 }
3532
3533 base = d40_hw_detect_init(pdev);
3534 if (!base)
3535 goto report_failure;
3536
3537 num_reserved_chans = d40_phy_res_init(base);
3538
3539 platform_set_drvdata(pdev, base);
3540
3541 spin_lock_init(&base->interrupt_lock);
3542 spin_lock_init(&base->execmd_lock);
3543
3544 /* Get IO for logical channel parameter address */
3545 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3546 if (!res) {
3547 ret = -ENOENT;
3548 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3549 goto failure;
3550 }
3551 base->lcpa_size = resource_size(res);
3552 base->phy_lcpa = res->start;
3553
3554 if (request_mem_region(res->start, resource_size(res),
3555 D40_NAME " I/O lcpa") == NULL) {
3556 ret = -EBUSY;
3557 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
3558 goto failure;
3559 }
3560
3561 /* We make use of ESRAM memory for this. */
3562 val = readl(base->virtbase + D40_DREG_LCPA);
3563 if (res->start != val && val != 0) {
3564 dev_warn(&pdev->dev,
3565 "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3566 __func__, val, &res->start);
3567 } else
3568 writel(res->start, base->virtbase + D40_DREG_LCPA);
3569
3570 base->lcpa_base = ioremap(res->start, resource_size(res));
3571 if (!base->lcpa_base) {
3572 ret = -ENOMEM;
3573 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3574 goto failure;
3575 }
3576 /* If lcla has to be located in ESRAM we don't need to allocate */
3577 if (base->plat_data->use_esram_lcla) {
3578 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3579 "lcla_esram");
3580 if (!res) {
3581 ret = -ENOENT;
3582 d40_err(&pdev->dev,
3583 "No \"lcla_esram\" memory resource\n");
3584 goto failure;
3585 }
3586 base->lcla_pool.base = ioremap(res->start,
3587 resource_size(res));
3588 if (!base->lcla_pool.base) {
3589 ret = -ENOMEM;
3590 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3591 goto failure;
3592 }
3593 writel(res->start, base->virtbase + D40_DREG_LCLA);
3594
3595 } else {
3596 ret = d40_lcla_allocate(base);
3597 if (ret) {
3598 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3599 goto failure;
3600 }
3601 }
3602
3603 spin_lock_init(&base->lcla_pool.lock);
3604
3605 base->irq = platform_get_irq(pdev, 0);
3606
3607 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3608 if (ret) {
3609 d40_err(&pdev->dev, "No IRQ defined\n");
3610 goto failure;
3611 }
3612
3613 if (base->plat_data->use_esram_lcla) {
3614
3615 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3616 if (IS_ERR(base->lcpa_regulator)) {
3617 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3618 ret = PTR_ERR(base->lcpa_regulator);
3619 base->lcpa_regulator = NULL;
3620 goto failure;
3621 }
3622
3623 ret = regulator_enable(base->lcpa_regulator);
3624 if (ret) {
3625 d40_err(&pdev->dev,
3626 "Failed to enable lcpa_regulator\n");
3627 regulator_put(base->lcpa_regulator);
3628 base->lcpa_regulator = NULL;
3629 goto failure;
3630 }
3631 }
3632
3633 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3634
3635 pm_runtime_irq_safe(base->dev);
3636 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3637 pm_runtime_use_autosuspend(base->dev);
3638 pm_runtime_mark_last_busy(base->dev);
3639 pm_runtime_set_active(base->dev);
3640 pm_runtime_enable(base->dev);
3641
3642 ret = d40_dmaengine_init(base, num_reserved_chans);
3643 if (ret)
3644 goto failure;
3645
3646 base->dev->dma_parms = &base->dma_parms;
3647 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3648 if (ret) {
3649 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3650 goto failure;
3651 }
3652
3653 d40_hw_init(base);
3654
3655 if (np) {
3656 ret = of_dma_controller_register(np, d40_xlate, NULL);
3657 if (ret)
3658 dev_err(&pdev->dev,
3659 "could not register of_dma_controller\n");
3660 }
3661
3662 dev_info(base->dev, "initialized\n");
3663 return 0;
3664
3665 failure:
3666 kmem_cache_destroy(base->desc_slab);
3667 if (base->virtbase)
3668 iounmap(base->virtbase);
3669
3670 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3671 iounmap(base->lcla_pool.base);
3672 base->lcla_pool.base = NULL;
3673 }
3674
3675 if (base->lcla_pool.dma_addr)
3676 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3677 SZ_1K * base->num_phy_chans,
3678 DMA_TO_DEVICE);
3679
3680 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3681 free_pages((unsigned long)base->lcla_pool.base,
3682 base->lcla_pool.pages);
3683
3684 kfree(base->lcla_pool.base_unaligned);
3685
3686 if (base->phy_lcpa)
3687 release_mem_region(base->phy_lcpa,
3688 base->lcpa_size);
3689 if (base->phy_start)
3690 release_mem_region(base->phy_start,
3691 base->phy_size);
3692 if (base->clk) {
3693 clk_disable_unprepare(base->clk);
3694 clk_put(base->clk);
3695 }
3696
3697 if (base->lcpa_regulator) {
3698 regulator_disable(base->lcpa_regulator);
3699 regulator_put(base->lcpa_regulator);
3700 }
3701
3702 kfree(base->lcla_pool.alloc_map);
3703 kfree(base->lookup_log_chans);
3704 kfree(base->lookup_phy_chans);
3705 kfree(base->phy_res);
3706 kfree(base);
3707 report_failure:
3708 d40_err(&pdev->dev, "probe failed\n");
3709 return ret;
3710 }
3711
3712 static const struct of_device_id d40_match[] = {
3713 { .compatible = "stericsson,dma40", },
3714 {}
3715 };
3716
3717 static struct platform_driver d40_driver = {
3718 .driver = {
3719 .name = D40_NAME,
3720 .pm = &dma40_pm_ops,
3721 .of_match_table = d40_match,
3722 },
3723 };
3724
3725 static int __init stedma40_init(void)
3726 {
3727 return platform_driver_probe(&d40_driver, d40_probe);
3728 }
3729 subsys_initcall(stedma40_init);
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