2 * Driver for STM32 DMA controller
4 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
6 * Copyright (C) M'boumba Cedric Madianga 2015
7 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
8 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
10 * License terms: GNU General Public License (GPL), version 2
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/jiffies.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/of_dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
32 #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
33 #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
34 #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
35 #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
36 #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
37 #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
38 #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
39 #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
40 #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
41 #define STM32_DMA_MASKI (STM32_DMA_TCI \
46 /* DMA Stream x Configuration Register */
47 #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
48 #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25)
49 #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)
50 #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23)
51 #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)
52 #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21)
53 #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)
54 #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16)
55 #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)
56 #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13)
57 #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)
58 #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11)
59 #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
60 #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)
61 #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6)
62 #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
63 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
64 #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */
65 #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
66 #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
67 #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
68 #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
69 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
71 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
72 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
73 #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
74 #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \
75 | STM32_DMA_SCR_MINC \
76 | STM32_DMA_SCR_PINCOS \
77 | STM32_DMA_SCR_PL_MASK)
78 #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \
79 | STM32_DMA_SCR_TEIE \
80 | STM32_DMA_SCR_DMEIE)
82 /* DMA Stream x number of data register */
83 #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x))
85 /* DMA stream peripheral address register */
86 #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x))
88 /* DMA stream x memory 0 address register */
89 #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x))
91 /* DMA stream x memory 1 address register */
92 #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x))
94 /* DMA stream x FIFO control register */
95 #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x))
96 #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)
97 #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK)
98 #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
99 #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */
100 #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \
101 | STM32_DMA_SFCR_DMDIS)
104 #define STM32_DMA_DEV_TO_MEM 0x00
105 #define STM32_DMA_MEM_TO_DEV 0x01
106 #define STM32_DMA_MEM_TO_MEM 0x02
108 /* DMA priority level */
109 #define STM32_DMA_PRIORITY_LOW 0x00
110 #define STM32_DMA_PRIORITY_MEDIUM 0x01
111 #define STM32_DMA_PRIORITY_HIGH 0x02
112 #define STM32_DMA_PRIORITY_VERY_HIGH 0x03
114 /* DMA FIFO threshold selection */
115 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00
116 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
117 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
118 #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
120 #define STM32_DMA_MAX_DATA_ITEMS 0xffff
122 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
123 * gather at boundary. Thus it's safer to round down this value on FIFO
126 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
127 ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
128 #define STM32_DMA_MAX_CHANNELS 0x08
129 #define STM32_DMA_MAX_REQUEST_ID 0x08
130 #define STM32_DMA_MAX_DATA_PARAM 0x03
131 #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
132 #define STM32_DMA_MIN_BURST 4
133 #define STM32_DMA_MAX_BURST 16
136 #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
137 #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
139 enum stm32_dma_width
{
145 enum stm32_dma_burst_size
{
146 STM32_DMA_BURST_SINGLE
,
147 STM32_DMA_BURST_INCR4
,
148 STM32_DMA_BURST_INCR8
,
149 STM32_DMA_BURST_INCR16
,
153 * struct stm32_dma_cfg - STM32 DMA custom configuration
154 * @channel_id: channel ID
155 * @request_line: DMA request
156 * @stream_config: 32bit mask specifying the DMA channel configuration
157 * @features: 32bit mask specifying the DMA Feature list
159 struct stm32_dma_cfg
{
166 struct stm32_dma_chan_reg
{
179 struct stm32_dma_sg_req
{
181 struct stm32_dma_chan_reg chan_reg
;
184 struct stm32_dma_desc
{
185 struct virt_dma_desc vdesc
;
188 struct stm32_dma_sg_req sg_req
[];
191 struct stm32_dma_chan
{
192 struct virt_dma_chan vchan
;
197 struct stm32_dma_desc
*desc
;
199 struct dma_slave_config dma_sconfig
;
200 struct stm32_dma_chan_reg chan_reg
;
206 struct stm32_dma_device
{
207 struct dma_device ddev
;
210 struct reset_control
*rst
;
212 struct stm32_dma_chan chan
[STM32_DMA_MAX_CHANNELS
];
215 static struct stm32_dma_device
*stm32_dma_get_dev(struct stm32_dma_chan
*chan
)
217 return container_of(chan
->vchan
.chan
.device
, struct stm32_dma_device
,
221 static struct stm32_dma_chan
*to_stm32_dma_chan(struct dma_chan
*c
)
223 return container_of(c
, struct stm32_dma_chan
, vchan
.chan
);
226 static struct stm32_dma_desc
*to_stm32_dma_desc(struct virt_dma_desc
*vdesc
)
228 return container_of(vdesc
, struct stm32_dma_desc
, vdesc
);
231 static struct device
*chan2dev(struct stm32_dma_chan
*chan
)
233 return &chan
->vchan
.chan
.dev
->device
;
236 static u32
stm32_dma_read(struct stm32_dma_device
*dmadev
, u32 reg
)
238 return readl_relaxed(dmadev
->base
+ reg
);
241 static void stm32_dma_write(struct stm32_dma_device
*dmadev
, u32 reg
, u32 val
)
243 writel_relaxed(val
, dmadev
->base
+ reg
);
246 static struct stm32_dma_desc
*stm32_dma_alloc_desc(u32 num_sgs
)
248 return kzalloc(sizeof(struct stm32_dma_desc
) +
249 sizeof(struct stm32_dma_sg_req
) * num_sgs
, GFP_NOWAIT
);
252 static int stm32_dma_get_width(struct stm32_dma_chan
*chan
,
253 enum dma_slave_buswidth width
)
256 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
257 return STM32_DMA_BYTE
;
258 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
259 return STM32_DMA_HALF_WORD
;
260 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
261 return STM32_DMA_WORD
;
263 dev_err(chan2dev(chan
), "Dma bus width not supported\n");
268 static enum dma_slave_buswidth
stm32_dma_get_max_width(u32 buf_len
,
271 enum dma_slave_buswidth max_width
;
273 if (threshold
== STM32_DMA_FIFO_THRESHOLD_FULL
)
274 max_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
276 max_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
278 while ((buf_len
< max_width
|| buf_len
% max_width
) &&
279 max_width
> DMA_SLAVE_BUSWIDTH_1_BYTE
)
280 max_width
= max_width
>> 1;
285 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst
, u32 threshold
,
286 enum dma_slave_buswidth width
)
290 if (width
!= DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
293 * If number of beats fit in several whole bursts
294 * this configuration is allowed.
296 remaining
= ((STM32_DMA_FIFO_SIZE
/ width
) *
297 (threshold
+ 1) / 4) % burst
;
309 static bool stm32_dma_is_burst_possible(u32 buf_len
, u32 threshold
)
312 case STM32_DMA_FIFO_THRESHOLD_FULL
:
313 if (buf_len
>= STM32_DMA_MAX_BURST
)
317 case STM32_DMA_FIFO_THRESHOLD_HALFFULL
:
318 if (buf_len
>= STM32_DMA_MAX_BURST
/ 2)
327 static u32
stm32_dma_get_best_burst(u32 buf_len
, u32 max_burst
, u32 threshold
,
328 enum dma_slave_buswidth width
)
330 u32 best_burst
= max_burst
;
332 if (best_burst
== 1 || !stm32_dma_is_burst_possible(buf_len
, threshold
))
335 while ((buf_len
< best_burst
* width
&& best_burst
> 1) ||
336 !stm32_dma_fifo_threshold_is_allowed(best_burst
, threshold
,
338 if (best_burst
> STM32_DMA_MIN_BURST
)
339 best_burst
= best_burst
>> 1;
347 static int stm32_dma_get_burst(struct stm32_dma_chan
*chan
, u32 maxburst
)
352 return STM32_DMA_BURST_SINGLE
;
354 return STM32_DMA_BURST_INCR4
;
356 return STM32_DMA_BURST_INCR8
;
358 return STM32_DMA_BURST_INCR16
;
360 dev_err(chan2dev(chan
), "Dma burst size not supported\n");
365 static void stm32_dma_set_fifo_config(struct stm32_dma_chan
*chan
,
366 u32 src_burst
, u32 dst_burst
)
368 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_MASK
;
369 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_DMEIE
;
371 if (!src_burst
&& !dst_burst
) {
372 /* Using direct mode */
373 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_DMEIE
;
375 /* Using FIFO mode */
376 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_MASK
;
380 static int stm32_dma_slave_config(struct dma_chan
*c
,
381 struct dma_slave_config
*config
)
383 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
385 memcpy(&chan
->dma_sconfig
, config
, sizeof(*config
));
387 chan
->config_init
= true;
392 static u32
stm32_dma_irq_status(struct stm32_dma_chan
*chan
)
394 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
398 * Read "flags" from DMA_xISR register corresponding to the selected
399 * DMA channel at the correct bit offset inside that register.
401 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
402 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
406 dma_isr
= stm32_dma_read(dmadev
, STM32_DMA_HISR
);
408 dma_isr
= stm32_dma_read(dmadev
, STM32_DMA_LISR
);
410 flags
= dma_isr
>> (((chan
->id
& 2) << 3) | ((chan
->id
& 1) * 6));
412 return flags
& STM32_DMA_MASKI
;
415 static void stm32_dma_irq_clear(struct stm32_dma_chan
*chan
, u32 flags
)
417 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
421 * Write "flags" to the DMA_xIFCR register corresponding to the selected
422 * DMA channel at the correct bit offset inside that register.
424 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
425 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
427 flags
&= STM32_DMA_MASKI
;
428 dma_ifcr
= flags
<< (((chan
->id
& 2) << 3) | ((chan
->id
& 1) * 6));
431 stm32_dma_write(dmadev
, STM32_DMA_HIFCR
, dma_ifcr
);
433 stm32_dma_write(dmadev
, STM32_DMA_LIFCR
, dma_ifcr
);
436 static int stm32_dma_disable_chan(struct stm32_dma_chan
*chan
)
438 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
439 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
443 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
445 if (dma_scr
& STM32_DMA_SCR_EN
) {
446 dma_scr
&= ~STM32_DMA_SCR_EN
;
447 stm32_dma_write(dmadev
, STM32_DMA_SCR(id
), dma_scr
);
450 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
451 dma_scr
&= STM32_DMA_SCR_EN
;
455 if (time_after_eq(jiffies
, timeout
)) {
456 dev_err(chan2dev(chan
), "%s: timeout!\n",
467 static void stm32_dma_stop(struct stm32_dma_chan
*chan
)
469 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
470 u32 dma_scr
, dma_sfcr
, status
;
473 /* Disable interrupts */
474 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
475 dma_scr
&= ~STM32_DMA_SCR_IRQ_MASK
;
476 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), dma_scr
);
477 dma_sfcr
= stm32_dma_read(dmadev
, STM32_DMA_SFCR(chan
->id
));
478 dma_sfcr
&= ~STM32_DMA_SFCR_FEIE
;
479 stm32_dma_write(dmadev
, STM32_DMA_SFCR(chan
->id
), dma_sfcr
);
482 ret
= stm32_dma_disable_chan(chan
);
486 /* Clear interrupt status if it is there */
487 status
= stm32_dma_irq_status(chan
);
489 dev_dbg(chan2dev(chan
), "%s(): clearing interrupt: 0x%08x\n",
491 stm32_dma_irq_clear(chan
, status
);
497 static int stm32_dma_terminate_all(struct dma_chan
*c
)
499 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
503 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
506 stm32_dma_stop(chan
);
510 vchan_get_all_descriptors(&chan
->vchan
, &head
);
511 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
512 vchan_dma_desc_free_list(&chan
->vchan
, &head
);
517 static void stm32_dma_synchronize(struct dma_chan
*c
)
519 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
521 vchan_synchronize(&chan
->vchan
);
524 static void stm32_dma_dump_reg(struct stm32_dma_chan
*chan
)
526 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
527 u32 scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
528 u32 ndtr
= stm32_dma_read(dmadev
, STM32_DMA_SNDTR(chan
->id
));
529 u32 spar
= stm32_dma_read(dmadev
, STM32_DMA_SPAR(chan
->id
));
530 u32 sm0ar
= stm32_dma_read(dmadev
, STM32_DMA_SM0AR(chan
->id
));
531 u32 sm1ar
= stm32_dma_read(dmadev
, STM32_DMA_SM1AR(chan
->id
));
532 u32 sfcr
= stm32_dma_read(dmadev
, STM32_DMA_SFCR(chan
->id
));
534 dev_dbg(chan2dev(chan
), "SCR: 0x%08x\n", scr
);
535 dev_dbg(chan2dev(chan
), "NDTR: 0x%08x\n", ndtr
);
536 dev_dbg(chan2dev(chan
), "SPAR: 0x%08x\n", spar
);
537 dev_dbg(chan2dev(chan
), "SM0AR: 0x%08x\n", sm0ar
);
538 dev_dbg(chan2dev(chan
), "SM1AR: 0x%08x\n", sm1ar
);
539 dev_dbg(chan2dev(chan
), "SFCR: 0x%08x\n", sfcr
);
542 static void stm32_dma_configure_next_sg(struct stm32_dma_chan
*chan
);
544 static void stm32_dma_start_transfer(struct stm32_dma_chan
*chan
)
546 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
547 struct virt_dma_desc
*vdesc
;
548 struct stm32_dma_sg_req
*sg_req
;
549 struct stm32_dma_chan_reg
*reg
;
553 ret
= stm32_dma_disable_chan(chan
);
558 vdesc
= vchan_next_desc(&chan
->vchan
);
562 chan
->desc
= to_stm32_dma_desc(vdesc
);
566 if (chan
->next_sg
== chan
->desc
->num_sgs
)
569 sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
570 reg
= &sg_req
->chan_reg
;
572 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), reg
->dma_scr
);
573 stm32_dma_write(dmadev
, STM32_DMA_SPAR(chan
->id
), reg
->dma_spar
);
574 stm32_dma_write(dmadev
, STM32_DMA_SM0AR(chan
->id
), reg
->dma_sm0ar
);
575 stm32_dma_write(dmadev
, STM32_DMA_SFCR(chan
->id
), reg
->dma_sfcr
);
576 stm32_dma_write(dmadev
, STM32_DMA_SM1AR(chan
->id
), reg
->dma_sm1ar
);
577 stm32_dma_write(dmadev
, STM32_DMA_SNDTR(chan
->id
), reg
->dma_sndtr
);
581 /* Clear interrupt status if it is there */
582 status
= stm32_dma_irq_status(chan
);
584 stm32_dma_irq_clear(chan
, status
);
586 if (chan
->desc
->cyclic
)
587 stm32_dma_configure_next_sg(chan
);
589 stm32_dma_dump_reg(chan
);
592 reg
->dma_scr
|= STM32_DMA_SCR_EN
;
593 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), reg
->dma_scr
);
597 dev_dbg(chan2dev(chan
), "vchan %pK: started\n", &chan
->vchan
);
600 static void stm32_dma_configure_next_sg(struct stm32_dma_chan
*chan
)
602 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
603 struct stm32_dma_sg_req
*sg_req
;
604 u32 dma_scr
, dma_sm0ar
, dma_sm1ar
, id
;
607 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
609 if (dma_scr
& STM32_DMA_SCR_DBM
) {
610 if (chan
->next_sg
== chan
->desc
->num_sgs
)
613 sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
615 if (dma_scr
& STM32_DMA_SCR_CT
) {
616 dma_sm0ar
= sg_req
->chan_reg
.dma_sm0ar
;
617 stm32_dma_write(dmadev
, STM32_DMA_SM0AR(id
), dma_sm0ar
);
618 dev_dbg(chan2dev(chan
), "CT=1 <=> SM0AR: 0x%08x\n",
619 stm32_dma_read(dmadev
, STM32_DMA_SM0AR(id
)));
621 dma_sm1ar
= sg_req
->chan_reg
.dma_sm1ar
;
622 stm32_dma_write(dmadev
, STM32_DMA_SM1AR(id
), dma_sm1ar
);
623 dev_dbg(chan2dev(chan
), "CT=0 <=> SM1AR: 0x%08x\n",
624 stm32_dma_read(dmadev
, STM32_DMA_SM1AR(id
)));
629 static void stm32_dma_handle_chan_done(struct stm32_dma_chan
*chan
)
632 if (chan
->desc
->cyclic
) {
633 vchan_cyclic_callback(&chan
->desc
->vdesc
);
635 stm32_dma_configure_next_sg(chan
);
638 if (chan
->next_sg
== chan
->desc
->num_sgs
) {
639 list_del(&chan
->desc
->vdesc
.node
);
640 vchan_cookie_complete(&chan
->desc
->vdesc
);
643 stm32_dma_start_transfer(chan
);
648 static irqreturn_t
stm32_dma_chan_irq(int irq
, void *devid
)
650 struct stm32_dma_chan
*chan
= devid
;
651 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
654 spin_lock(&chan
->vchan
.lock
);
656 status
= stm32_dma_irq_status(chan
);
657 scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
659 if (status
& STM32_DMA_TCI
) {
660 stm32_dma_irq_clear(chan
, STM32_DMA_TCI
);
661 if (scr
& STM32_DMA_SCR_TCIE
)
662 stm32_dma_handle_chan_done(chan
);
663 status
&= ~STM32_DMA_TCI
;
665 if (status
& STM32_DMA_HTI
) {
666 stm32_dma_irq_clear(chan
, STM32_DMA_HTI
);
667 status
&= ~STM32_DMA_HTI
;
669 if (status
& STM32_DMA_FEI
) {
670 stm32_dma_irq_clear(chan
, STM32_DMA_FEI
);
671 status
&= ~STM32_DMA_FEI
;
672 if (!(scr
& STM32_DMA_SCR_EN
))
673 dev_err(chan2dev(chan
), "FIFO Error\n");
675 dev_dbg(chan2dev(chan
), "FIFO over/underrun\n");
678 stm32_dma_irq_clear(chan
, status
);
679 dev_err(chan2dev(chan
), "DMA error: status=0x%08x\n", status
);
680 if (!(scr
& STM32_DMA_SCR_EN
))
681 dev_err(chan2dev(chan
), "chan disabled by HW\n");
684 spin_unlock(&chan
->vchan
.lock
);
689 static void stm32_dma_issue_pending(struct dma_chan
*c
)
691 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
694 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
695 if (vchan_issue_pending(&chan
->vchan
) && !chan
->desc
&& !chan
->busy
) {
696 dev_dbg(chan2dev(chan
), "vchan %pK: issued\n", &chan
->vchan
);
697 stm32_dma_start_transfer(chan
);
700 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
703 static int stm32_dma_set_xfer_param(struct stm32_dma_chan
*chan
,
704 enum dma_transfer_direction direction
,
705 enum dma_slave_buswidth
*buswidth
,
708 enum dma_slave_buswidth src_addr_width
, dst_addr_width
;
709 int src_bus_width
, dst_bus_width
;
710 int src_burst_size
, dst_burst_size
;
711 u32 src_maxburst
, dst_maxburst
, src_best_burst
, dst_best_burst
;
712 u32 dma_scr
, threshold
;
714 src_addr_width
= chan
->dma_sconfig
.src_addr_width
;
715 dst_addr_width
= chan
->dma_sconfig
.dst_addr_width
;
716 src_maxburst
= chan
->dma_sconfig
.src_maxburst
;
717 dst_maxburst
= chan
->dma_sconfig
.dst_maxburst
;
718 threshold
= chan
->threshold
;
722 /* Set device data size */
723 dst_bus_width
= stm32_dma_get_width(chan
, dst_addr_width
);
724 if (dst_bus_width
< 0)
725 return dst_bus_width
;
727 /* Set device burst size */
728 dst_best_burst
= stm32_dma_get_best_burst(buf_len
,
733 dst_burst_size
= stm32_dma_get_burst(chan
, dst_best_burst
);
734 if (dst_burst_size
< 0)
735 return dst_burst_size
;
737 /* Set memory data size */
738 src_addr_width
= stm32_dma_get_max_width(buf_len
, threshold
);
739 chan
->mem_width
= src_addr_width
;
740 src_bus_width
= stm32_dma_get_width(chan
, src_addr_width
);
741 if (src_bus_width
< 0)
742 return src_bus_width
;
744 /* Set memory burst size */
745 src_maxburst
= STM32_DMA_MAX_BURST
;
746 src_best_burst
= stm32_dma_get_best_burst(buf_len
,
750 src_burst_size
= stm32_dma_get_burst(chan
, src_best_burst
);
751 if (src_burst_size
< 0)
752 return src_burst_size
;
754 dma_scr
= STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV
) |
755 STM32_DMA_SCR_PSIZE(dst_bus_width
) |
756 STM32_DMA_SCR_MSIZE(src_bus_width
) |
757 STM32_DMA_SCR_PBURST(dst_burst_size
) |
758 STM32_DMA_SCR_MBURST(src_burst_size
);
760 /* Set FIFO threshold */
761 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_FTH_MASK
;
762 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_FTH(threshold
);
764 /* Set peripheral address */
765 chan
->chan_reg
.dma_spar
= chan
->dma_sconfig
.dst_addr
;
766 *buswidth
= dst_addr_width
;
770 /* Set device data size */
771 src_bus_width
= stm32_dma_get_width(chan
, src_addr_width
);
772 if (src_bus_width
< 0)
773 return src_bus_width
;
775 /* Set device burst size */
776 src_best_burst
= stm32_dma_get_best_burst(buf_len
,
780 chan
->mem_burst
= src_best_burst
;
781 src_burst_size
= stm32_dma_get_burst(chan
, src_best_burst
);
782 if (src_burst_size
< 0)
783 return src_burst_size
;
785 /* Set memory data size */
786 dst_addr_width
= stm32_dma_get_max_width(buf_len
, threshold
);
787 chan
->mem_width
= dst_addr_width
;
788 dst_bus_width
= stm32_dma_get_width(chan
, dst_addr_width
);
789 if (dst_bus_width
< 0)
790 return dst_bus_width
;
792 /* Set memory burst size */
793 dst_maxburst
= STM32_DMA_MAX_BURST
;
794 dst_best_burst
= stm32_dma_get_best_burst(buf_len
,
798 chan
->mem_burst
= dst_best_burst
;
799 dst_burst_size
= stm32_dma_get_burst(chan
, dst_best_burst
);
800 if (dst_burst_size
< 0)
801 return dst_burst_size
;
803 dma_scr
= STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM
) |
804 STM32_DMA_SCR_PSIZE(src_bus_width
) |
805 STM32_DMA_SCR_MSIZE(dst_bus_width
) |
806 STM32_DMA_SCR_PBURST(src_burst_size
) |
807 STM32_DMA_SCR_MBURST(dst_burst_size
);
809 /* Set FIFO threshold */
810 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_FTH_MASK
;
811 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_FTH(threshold
);
813 /* Set peripheral address */
814 chan
->chan_reg
.dma_spar
= chan
->dma_sconfig
.src_addr
;
815 *buswidth
= chan
->dma_sconfig
.src_addr_width
;
819 dev_err(chan2dev(chan
), "Dma direction is not supported\n");
823 stm32_dma_set_fifo_config(chan
, src_best_burst
, dst_best_burst
);
825 /* Set DMA control register */
826 chan
->chan_reg
.dma_scr
&= ~(STM32_DMA_SCR_DIR_MASK
|
827 STM32_DMA_SCR_PSIZE_MASK
| STM32_DMA_SCR_MSIZE_MASK
|
828 STM32_DMA_SCR_PBURST_MASK
| STM32_DMA_SCR_MBURST_MASK
);
829 chan
->chan_reg
.dma_scr
|= dma_scr
;
834 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg
*regs
)
836 memset(regs
, 0, sizeof(struct stm32_dma_chan_reg
));
839 static struct dma_async_tx_descriptor
*stm32_dma_prep_slave_sg(
840 struct dma_chan
*c
, struct scatterlist
*sgl
,
841 u32 sg_len
, enum dma_transfer_direction direction
,
842 unsigned long flags
, void *context
)
844 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
845 struct stm32_dma_desc
*desc
;
846 struct scatterlist
*sg
;
847 enum dma_slave_buswidth buswidth
;
851 if (!chan
->config_init
) {
852 dev_err(chan2dev(chan
), "dma channel is not configured\n");
857 dev_err(chan2dev(chan
), "Invalid segment length %d\n", sg_len
);
861 desc
= stm32_dma_alloc_desc(sg_len
);
865 /* Set peripheral flow controller */
866 if (chan
->dma_sconfig
.device_fc
)
867 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_PFCTRL
;
869 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_PFCTRL
;
871 for_each_sg(sgl
, sg
, sg_len
, i
) {
872 ret
= stm32_dma_set_xfer_param(chan
, direction
, &buswidth
,
877 desc
->sg_req
[i
].len
= sg_dma_len(sg
);
879 nb_data_items
= desc
->sg_req
[i
].len
/ buswidth
;
880 if (nb_data_items
> STM32_DMA_ALIGNED_MAX_DATA_ITEMS
) {
881 dev_err(chan2dev(chan
), "nb items not supported\n");
885 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
886 desc
->sg_req
[i
].chan_reg
.dma_scr
= chan
->chan_reg
.dma_scr
;
887 desc
->sg_req
[i
].chan_reg
.dma_sfcr
= chan
->chan_reg
.dma_sfcr
;
888 desc
->sg_req
[i
].chan_reg
.dma_spar
= chan
->chan_reg
.dma_spar
;
889 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= sg_dma_address(sg
);
890 desc
->sg_req
[i
].chan_reg
.dma_sm1ar
= sg_dma_address(sg
);
891 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= nb_data_items
;
894 desc
->num_sgs
= sg_len
;
895 desc
->cyclic
= false;
897 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
904 static struct dma_async_tx_descriptor
*stm32_dma_prep_dma_cyclic(
905 struct dma_chan
*c
, dma_addr_t buf_addr
, size_t buf_len
,
906 size_t period_len
, enum dma_transfer_direction direction
,
909 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
910 struct stm32_dma_desc
*desc
;
911 enum dma_slave_buswidth buswidth
;
912 u32 num_periods
, nb_data_items
;
915 if (!buf_len
|| !period_len
) {
916 dev_err(chan2dev(chan
), "Invalid buffer/period len\n");
920 if (!chan
->config_init
) {
921 dev_err(chan2dev(chan
), "dma channel is not configured\n");
925 if (buf_len
% period_len
) {
926 dev_err(chan2dev(chan
), "buf_len not multiple of period_len\n");
931 * We allow to take more number of requests till DMA is
932 * not started. The driver will loop over all requests.
933 * Once DMA is started then new requests can be queued only after
934 * terminating the DMA.
937 dev_err(chan2dev(chan
), "Request not allowed when dma busy\n");
941 ret
= stm32_dma_set_xfer_param(chan
, direction
, &buswidth
, period_len
);
945 nb_data_items
= period_len
/ buswidth
;
946 if (nb_data_items
> STM32_DMA_ALIGNED_MAX_DATA_ITEMS
) {
947 dev_err(chan2dev(chan
), "number of items not supported\n");
951 /* Enable Circular mode or double buffer mode */
952 if (buf_len
== period_len
)
953 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_CIRC
;
955 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_DBM
;
957 /* Clear periph ctrl if client set it */
958 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_PFCTRL
;
960 num_periods
= buf_len
/ period_len
;
962 desc
= stm32_dma_alloc_desc(num_periods
);
966 for (i
= 0; i
< num_periods
; i
++) {
967 desc
->sg_req
[i
].len
= period_len
;
969 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
970 desc
->sg_req
[i
].chan_reg
.dma_scr
= chan
->chan_reg
.dma_scr
;
971 desc
->sg_req
[i
].chan_reg
.dma_sfcr
= chan
->chan_reg
.dma_sfcr
;
972 desc
->sg_req
[i
].chan_reg
.dma_spar
= chan
->chan_reg
.dma_spar
;
973 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= buf_addr
;
974 desc
->sg_req
[i
].chan_reg
.dma_sm1ar
= buf_addr
;
975 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= nb_data_items
;
976 buf_addr
+= period_len
;
979 desc
->num_sgs
= num_periods
;
982 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
985 static struct dma_async_tx_descriptor
*stm32_dma_prep_dma_memcpy(
986 struct dma_chan
*c
, dma_addr_t dest
,
987 dma_addr_t src
, size_t len
, unsigned long flags
)
989 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
990 enum dma_slave_buswidth max_width
;
991 struct stm32_dma_desc
*desc
;
992 size_t xfer_count
, offset
;
993 u32 num_sgs
, best_burst
, dma_burst
, threshold
;
996 num_sgs
= DIV_ROUND_UP(len
, STM32_DMA_ALIGNED_MAX_DATA_ITEMS
);
997 desc
= stm32_dma_alloc_desc(num_sgs
);
1001 threshold
= chan
->threshold
;
1003 for (offset
= 0, i
= 0; offset
< len
; offset
+= xfer_count
, i
++) {
1004 xfer_count
= min_t(size_t, len
- offset
,
1005 STM32_DMA_ALIGNED_MAX_DATA_ITEMS
);
1007 /* Compute best burst size */
1008 max_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1009 best_burst
= stm32_dma_get_best_burst(len
, STM32_DMA_MAX_BURST
,
1010 threshold
, max_width
);
1011 dma_burst
= stm32_dma_get_burst(chan
, best_burst
);
1013 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
1014 desc
->sg_req
[i
].chan_reg
.dma_scr
=
1015 STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM
) |
1016 STM32_DMA_SCR_PBURST(dma_burst
) |
1017 STM32_DMA_SCR_MBURST(dma_burst
) |
1018 STM32_DMA_SCR_MINC
|
1019 STM32_DMA_SCR_PINC
|
1020 STM32_DMA_SCR_TCIE
|
1022 desc
->sg_req
[i
].chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_MASK
;
1023 desc
->sg_req
[i
].chan_reg
.dma_sfcr
|=
1024 STM32_DMA_SFCR_FTH(threshold
);
1025 desc
->sg_req
[i
].chan_reg
.dma_spar
= src
+ offset
;
1026 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= dest
+ offset
;
1027 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= xfer_count
;
1028 desc
->sg_req
[i
].len
= xfer_count
;
1031 desc
->num_sgs
= num_sgs
;
1032 desc
->cyclic
= false;
1034 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
1037 static u32
stm32_dma_get_remaining_bytes(struct stm32_dma_chan
*chan
)
1039 u32 dma_scr
, width
, ndtr
;
1040 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1042 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
1043 width
= STM32_DMA_SCR_PSIZE_GET(dma_scr
);
1044 ndtr
= stm32_dma_read(dmadev
, STM32_DMA_SNDTR(chan
->id
));
1046 return ndtr
<< width
;
1049 static size_t stm32_dma_desc_residue(struct stm32_dma_chan
*chan
,
1050 struct stm32_dma_desc
*desc
,
1053 u32 modulo
, burst_size
;
1058 * In cyclic mode, for the last period, residue = remaining bytes from
1061 if (chan
->desc
->cyclic
&& next_sg
== 0) {
1062 residue
= stm32_dma_get_remaining_bytes(chan
);
1067 * For all other periods in cyclic mode, and in sg mode,
1068 * residue = remaining bytes from NDTR + remaining periods/sg to be
1071 for (i
= next_sg
; i
< desc
->num_sgs
; i
++)
1072 residue
+= desc
->sg_req
[i
].len
;
1073 residue
+= stm32_dma_get_remaining_bytes(chan
);
1076 if (!chan
->mem_burst
)
1079 burst_size
= chan
->mem_burst
* chan
->mem_width
;
1080 modulo
= residue
% burst_size
;
1082 residue
= residue
- modulo
+ burst_size
;
1087 static enum dma_status
stm32_dma_tx_status(struct dma_chan
*c
,
1088 dma_cookie_t cookie
,
1089 struct dma_tx_state
*state
)
1091 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1092 struct virt_dma_desc
*vdesc
;
1093 enum dma_status status
;
1094 unsigned long flags
;
1097 status
= dma_cookie_status(c
, cookie
, state
);
1098 if (status
== DMA_COMPLETE
|| !state
)
1101 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
1102 vdesc
= vchan_find_desc(&chan
->vchan
, cookie
);
1103 if (chan
->desc
&& cookie
== chan
->desc
->vdesc
.tx
.cookie
)
1104 residue
= stm32_dma_desc_residue(chan
, chan
->desc
,
1107 residue
= stm32_dma_desc_residue(chan
,
1108 to_stm32_dma_desc(vdesc
), 0);
1109 dma_set_residue(state
, residue
);
1111 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
1116 static int stm32_dma_alloc_chan_resources(struct dma_chan
*c
)
1118 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1119 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1122 chan
->config_init
= false;
1123 ret
= clk_prepare_enable(dmadev
->clk
);
1125 dev_err(chan2dev(chan
), "clk_prepare_enable failed: %d\n", ret
);
1129 ret
= stm32_dma_disable_chan(chan
);
1131 clk_disable_unprepare(dmadev
->clk
);
1136 static void stm32_dma_free_chan_resources(struct dma_chan
*c
)
1138 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1139 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1140 unsigned long flags
;
1142 dev_dbg(chan2dev(chan
), "Freeing channel %d\n", chan
->id
);
1145 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
1146 stm32_dma_stop(chan
);
1148 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
1151 clk_disable_unprepare(dmadev
->clk
);
1153 vchan_free_chan_resources(to_virt_chan(c
));
1156 static void stm32_dma_desc_free(struct virt_dma_desc
*vdesc
)
1158 kfree(container_of(vdesc
, struct stm32_dma_desc
, vdesc
));
1161 static void stm32_dma_set_config(struct stm32_dma_chan
*chan
,
1162 struct stm32_dma_cfg
*cfg
)
1164 stm32_dma_clear_reg(&chan
->chan_reg
);
1166 chan
->chan_reg
.dma_scr
= cfg
->stream_config
& STM32_DMA_SCR_CFG_MASK
;
1167 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_REQ(cfg
->request_line
);
1169 /* Enable Interrupts */
1170 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_TEIE
| STM32_DMA_SCR_TCIE
;
1172 chan
->threshold
= STM32_DMA_THRESHOLD_FTR_GET(cfg
->features
);
1175 static struct dma_chan
*stm32_dma_of_xlate(struct of_phandle_args
*dma_spec
,
1176 struct of_dma
*ofdma
)
1178 struct stm32_dma_device
*dmadev
= ofdma
->of_dma_data
;
1179 struct device
*dev
= dmadev
->ddev
.dev
;
1180 struct stm32_dma_cfg cfg
;
1181 struct stm32_dma_chan
*chan
;
1184 if (dma_spec
->args_count
< 4) {
1185 dev_err(dev
, "Bad number of cells\n");
1189 cfg
.channel_id
= dma_spec
->args
[0];
1190 cfg
.request_line
= dma_spec
->args
[1];
1191 cfg
.stream_config
= dma_spec
->args
[2];
1192 cfg
.features
= dma_spec
->args
[3];
1194 if (cfg
.channel_id
>= STM32_DMA_MAX_CHANNELS
||
1195 cfg
.request_line
>= STM32_DMA_MAX_REQUEST_ID
) {
1196 dev_err(dev
, "Bad channel and/or request id\n");
1200 chan
= &dmadev
->chan
[cfg
.channel_id
];
1202 c
= dma_get_slave_channel(&chan
->vchan
.chan
);
1204 dev_err(dev
, "No more channels available\n");
1208 stm32_dma_set_config(chan
, &cfg
);
1213 static const struct of_device_id stm32_dma_of_match
[] = {
1214 { .compatible
= "st,stm32-dma", },
1217 MODULE_DEVICE_TABLE(of
, stm32_dma_of_match
);
1219 static int stm32_dma_probe(struct platform_device
*pdev
)
1221 struct stm32_dma_chan
*chan
;
1222 struct stm32_dma_device
*dmadev
;
1223 struct dma_device
*dd
;
1224 const struct of_device_id
*match
;
1225 struct resource
*res
;
1228 match
= of_match_device(stm32_dma_of_match
, &pdev
->dev
);
1230 dev_err(&pdev
->dev
, "Error: No device match found\n");
1234 dmadev
= devm_kzalloc(&pdev
->dev
, sizeof(*dmadev
), GFP_KERNEL
);
1240 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1241 dmadev
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1242 if (IS_ERR(dmadev
->base
))
1243 return PTR_ERR(dmadev
->base
);
1245 dmadev
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1246 if (IS_ERR(dmadev
->clk
)) {
1247 dev_err(&pdev
->dev
, "Error: Missing controller clock\n");
1248 return PTR_ERR(dmadev
->clk
);
1251 dmadev
->mem2mem
= of_property_read_bool(pdev
->dev
.of_node
,
1254 dmadev
->rst
= devm_reset_control_get(&pdev
->dev
, NULL
);
1255 if (!IS_ERR(dmadev
->rst
)) {
1256 reset_control_assert(dmadev
->rst
);
1258 reset_control_deassert(dmadev
->rst
);
1261 dma_cap_set(DMA_SLAVE
, dd
->cap_mask
);
1262 dma_cap_set(DMA_PRIVATE
, dd
->cap_mask
);
1263 dma_cap_set(DMA_CYCLIC
, dd
->cap_mask
);
1264 dd
->device_alloc_chan_resources
= stm32_dma_alloc_chan_resources
;
1265 dd
->device_free_chan_resources
= stm32_dma_free_chan_resources
;
1266 dd
->device_tx_status
= stm32_dma_tx_status
;
1267 dd
->device_issue_pending
= stm32_dma_issue_pending
;
1268 dd
->device_prep_slave_sg
= stm32_dma_prep_slave_sg
;
1269 dd
->device_prep_dma_cyclic
= stm32_dma_prep_dma_cyclic
;
1270 dd
->device_config
= stm32_dma_slave_config
;
1271 dd
->device_terminate_all
= stm32_dma_terminate_all
;
1272 dd
->device_synchronize
= stm32_dma_synchronize
;
1273 dd
->src_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1274 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1275 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
1276 dd
->dst_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1277 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1278 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
1279 dd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1280 dd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1281 dd
->max_burst
= STM32_DMA_MAX_BURST
;
1282 dd
->dev
= &pdev
->dev
;
1283 INIT_LIST_HEAD(&dd
->channels
);
1285 if (dmadev
->mem2mem
) {
1286 dma_cap_set(DMA_MEMCPY
, dd
->cap_mask
);
1287 dd
->device_prep_dma_memcpy
= stm32_dma_prep_dma_memcpy
;
1288 dd
->directions
|= BIT(DMA_MEM_TO_MEM
);
1291 for (i
= 0; i
< STM32_DMA_MAX_CHANNELS
; i
++) {
1292 chan
= &dmadev
->chan
[i
];
1294 chan
->vchan
.desc_free
= stm32_dma_desc_free
;
1295 vchan_init(&chan
->vchan
, dd
);
1298 ret
= dma_async_device_register(dd
);
1302 for (i
= 0; i
< STM32_DMA_MAX_CHANNELS
; i
++) {
1303 chan
= &dmadev
->chan
[i
];
1304 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
1307 dev_err(&pdev
->dev
, "No irq resource for chan %d\n", i
);
1308 goto err_unregister
;
1310 chan
->irq
= res
->start
;
1311 ret
= devm_request_irq(&pdev
->dev
, chan
->irq
,
1312 stm32_dma_chan_irq
, 0,
1313 dev_name(chan2dev(chan
)), chan
);
1316 "request_irq failed with err %d channel %d\n",
1318 goto err_unregister
;
1322 ret
= of_dma_controller_register(pdev
->dev
.of_node
,
1323 stm32_dma_of_xlate
, dmadev
);
1326 "STM32 DMA DMA OF registration failed %d\n", ret
);
1327 goto err_unregister
;
1330 platform_set_drvdata(pdev
, dmadev
);
1332 dev_info(&pdev
->dev
, "STM32 DMA driver registered\n");
1337 dma_async_device_unregister(dd
);
1342 static struct platform_driver stm32_dma_driver
= {
1344 .name
= "stm32-dma",
1345 .of_match_table
= stm32_dma_of_match
,
1349 static int __init
stm32_dma_init(void)
1351 return platform_driver_probe(&stm32_dma_driver
, stm32_dma_probe
);
1353 subsys_initcall(stm32_dma_init
);