1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for STM32 DMA controller
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
7 * Copyright (C) M'boumba Cedric Madianga 2015
8 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/init.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/of_dma.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
32 #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
33 #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
34 #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
35 #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
36 #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
37 #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
38 #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
39 #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
40 #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
41 #define STM32_DMA_MASKI (STM32_DMA_TCI \
46 /* DMA Stream x Configuration Register */
47 #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
48 #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25)
49 #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)
50 #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23)
51 #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)
52 #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21)
53 #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)
54 #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16)
55 #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)
56 #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13)
57 #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)
58 #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11)
59 #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
60 #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)
61 #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6)
62 #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
63 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
64 #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */
65 #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
66 #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
67 #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
68 #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
69 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
71 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
72 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
73 #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
74 #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \
75 | STM32_DMA_SCR_MINC \
76 | STM32_DMA_SCR_PINCOS \
77 | STM32_DMA_SCR_PL_MASK)
78 #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \
79 | STM32_DMA_SCR_TEIE \
80 | STM32_DMA_SCR_DMEIE)
82 /* DMA Stream x number of data register */
83 #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x))
85 /* DMA stream peripheral address register */
86 #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x))
88 /* DMA stream x memory 0 address register */
89 #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x))
91 /* DMA stream x memory 1 address register */
92 #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x))
94 /* DMA stream x FIFO control register */
95 #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x))
96 #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)
97 #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK)
98 #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
99 #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */
100 #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \
101 | STM32_DMA_SFCR_DMDIS)
104 #define STM32_DMA_DEV_TO_MEM 0x00
105 #define STM32_DMA_MEM_TO_DEV 0x01
106 #define STM32_DMA_MEM_TO_MEM 0x02
108 /* DMA priority level */
109 #define STM32_DMA_PRIORITY_LOW 0x00
110 #define STM32_DMA_PRIORITY_MEDIUM 0x01
111 #define STM32_DMA_PRIORITY_HIGH 0x02
112 #define STM32_DMA_PRIORITY_VERY_HIGH 0x03
114 /* DMA FIFO threshold selection */
115 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00
116 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
117 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
118 #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
120 #define STM32_DMA_MAX_DATA_ITEMS 0xffff
122 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
123 * gather at boundary. Thus it's safer to round down this value on FIFO
126 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
127 ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
128 #define STM32_DMA_MAX_CHANNELS 0x08
129 #define STM32_DMA_MAX_REQUEST_ID 0x08
130 #define STM32_DMA_MAX_DATA_PARAM 0x03
131 #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
132 #define STM32_DMA_MIN_BURST 4
133 #define STM32_DMA_MAX_BURST 16
136 #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
137 #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
139 enum stm32_dma_width
{
145 enum stm32_dma_burst_size
{
146 STM32_DMA_BURST_SINGLE
,
147 STM32_DMA_BURST_INCR4
,
148 STM32_DMA_BURST_INCR8
,
149 STM32_DMA_BURST_INCR16
,
153 * struct stm32_dma_cfg - STM32 DMA custom configuration
154 * @channel_id: channel ID
155 * @request_line: DMA request
156 * @stream_config: 32bit mask specifying the DMA channel configuration
157 * @features: 32bit mask specifying the DMA Feature list
159 struct stm32_dma_cfg
{
166 struct stm32_dma_chan_reg
{
179 struct stm32_dma_sg_req
{
181 struct stm32_dma_chan_reg chan_reg
;
184 struct stm32_dma_desc
{
185 struct virt_dma_desc vdesc
;
188 struct stm32_dma_sg_req sg_req
[];
191 struct stm32_dma_chan
{
192 struct virt_dma_chan vchan
;
197 struct stm32_dma_desc
*desc
;
199 struct dma_slave_config dma_sconfig
;
200 struct stm32_dma_chan_reg chan_reg
;
206 struct stm32_dma_device
{
207 struct dma_device ddev
;
210 struct reset_control
*rst
;
212 struct stm32_dma_chan chan
[STM32_DMA_MAX_CHANNELS
];
215 static struct stm32_dma_device
*stm32_dma_get_dev(struct stm32_dma_chan
*chan
)
217 return container_of(chan
->vchan
.chan
.device
, struct stm32_dma_device
,
221 static struct stm32_dma_chan
*to_stm32_dma_chan(struct dma_chan
*c
)
223 return container_of(c
, struct stm32_dma_chan
, vchan
.chan
);
226 static struct stm32_dma_desc
*to_stm32_dma_desc(struct virt_dma_desc
*vdesc
)
228 return container_of(vdesc
, struct stm32_dma_desc
, vdesc
);
231 static struct device
*chan2dev(struct stm32_dma_chan
*chan
)
233 return &chan
->vchan
.chan
.dev
->device
;
236 static u32
stm32_dma_read(struct stm32_dma_device
*dmadev
, u32 reg
)
238 return readl_relaxed(dmadev
->base
+ reg
);
241 static void stm32_dma_write(struct stm32_dma_device
*dmadev
, u32 reg
, u32 val
)
243 writel_relaxed(val
, dmadev
->base
+ reg
);
246 static int stm32_dma_get_width(struct stm32_dma_chan
*chan
,
247 enum dma_slave_buswidth width
)
250 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
251 return STM32_DMA_BYTE
;
252 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
253 return STM32_DMA_HALF_WORD
;
254 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
255 return STM32_DMA_WORD
;
257 dev_err(chan2dev(chan
), "Dma bus width not supported\n");
262 static enum dma_slave_buswidth
stm32_dma_get_max_width(u32 buf_len
,
265 enum dma_slave_buswidth max_width
;
267 if (threshold
== STM32_DMA_FIFO_THRESHOLD_FULL
)
268 max_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
270 max_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
272 while ((buf_len
< max_width
|| buf_len
% max_width
) &&
273 max_width
> DMA_SLAVE_BUSWIDTH_1_BYTE
)
274 max_width
= max_width
>> 1;
279 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst
, u32 threshold
,
280 enum dma_slave_buswidth width
)
284 if (width
!= DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
287 * If number of beats fit in several whole bursts
288 * this configuration is allowed.
290 remaining
= ((STM32_DMA_FIFO_SIZE
/ width
) *
291 (threshold
+ 1) / 4) % burst
;
303 static bool stm32_dma_is_burst_possible(u32 buf_len
, u32 threshold
)
306 * Buffer or period length has to be aligned on FIFO depth.
307 * Otherwise bytes may be stuck within FIFO at buffer or period
310 return ((buf_len
% ((threshold
+ 1) * 4)) == 0);
313 static u32
stm32_dma_get_best_burst(u32 buf_len
, u32 max_burst
, u32 threshold
,
314 enum dma_slave_buswidth width
)
316 u32 best_burst
= max_burst
;
318 if (best_burst
== 1 || !stm32_dma_is_burst_possible(buf_len
, threshold
))
321 while ((buf_len
< best_burst
* width
&& best_burst
> 1) ||
322 !stm32_dma_fifo_threshold_is_allowed(best_burst
, threshold
,
324 if (best_burst
> STM32_DMA_MIN_BURST
)
325 best_burst
= best_burst
>> 1;
333 static int stm32_dma_get_burst(struct stm32_dma_chan
*chan
, u32 maxburst
)
338 return STM32_DMA_BURST_SINGLE
;
340 return STM32_DMA_BURST_INCR4
;
342 return STM32_DMA_BURST_INCR8
;
344 return STM32_DMA_BURST_INCR16
;
346 dev_err(chan2dev(chan
), "Dma burst size not supported\n");
351 static void stm32_dma_set_fifo_config(struct stm32_dma_chan
*chan
,
352 u32 src_burst
, u32 dst_burst
)
354 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_MASK
;
355 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_DMEIE
;
357 if (!src_burst
&& !dst_burst
) {
358 /* Using direct mode */
359 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_DMEIE
;
361 /* Using FIFO mode */
362 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_MASK
;
366 static int stm32_dma_slave_config(struct dma_chan
*c
,
367 struct dma_slave_config
*config
)
369 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
371 memcpy(&chan
->dma_sconfig
, config
, sizeof(*config
));
373 chan
->config_init
= true;
378 static u32
stm32_dma_irq_status(struct stm32_dma_chan
*chan
)
380 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
384 * Read "flags" from DMA_xISR register corresponding to the selected
385 * DMA channel at the correct bit offset inside that register.
387 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
388 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
392 dma_isr
= stm32_dma_read(dmadev
, STM32_DMA_HISR
);
394 dma_isr
= stm32_dma_read(dmadev
, STM32_DMA_LISR
);
396 flags
= dma_isr
>> (((chan
->id
& 2) << 3) | ((chan
->id
& 1) * 6));
398 return flags
& STM32_DMA_MASKI
;
401 static void stm32_dma_irq_clear(struct stm32_dma_chan
*chan
, u32 flags
)
403 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
407 * Write "flags" to the DMA_xIFCR register corresponding to the selected
408 * DMA channel at the correct bit offset inside that register.
410 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
411 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
413 flags
&= STM32_DMA_MASKI
;
414 dma_ifcr
= flags
<< (((chan
->id
& 2) << 3) | ((chan
->id
& 1) * 6));
417 stm32_dma_write(dmadev
, STM32_DMA_HIFCR
, dma_ifcr
);
419 stm32_dma_write(dmadev
, STM32_DMA_LIFCR
, dma_ifcr
);
422 static int stm32_dma_disable_chan(struct stm32_dma_chan
*chan
)
424 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
425 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
429 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
431 if (dma_scr
& STM32_DMA_SCR_EN
) {
432 dma_scr
&= ~STM32_DMA_SCR_EN
;
433 stm32_dma_write(dmadev
, STM32_DMA_SCR(id
), dma_scr
);
436 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
437 dma_scr
&= STM32_DMA_SCR_EN
;
441 if (time_after_eq(jiffies
, timeout
)) {
442 dev_err(chan2dev(chan
), "%s: timeout!\n",
453 static void stm32_dma_stop(struct stm32_dma_chan
*chan
)
455 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
456 u32 dma_scr
, dma_sfcr
, status
;
459 /* Disable interrupts */
460 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
461 dma_scr
&= ~STM32_DMA_SCR_IRQ_MASK
;
462 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), dma_scr
);
463 dma_sfcr
= stm32_dma_read(dmadev
, STM32_DMA_SFCR(chan
->id
));
464 dma_sfcr
&= ~STM32_DMA_SFCR_FEIE
;
465 stm32_dma_write(dmadev
, STM32_DMA_SFCR(chan
->id
), dma_sfcr
);
468 ret
= stm32_dma_disable_chan(chan
);
472 /* Clear interrupt status if it is there */
473 status
= stm32_dma_irq_status(chan
);
475 dev_dbg(chan2dev(chan
), "%s(): clearing interrupt: 0x%08x\n",
477 stm32_dma_irq_clear(chan
, status
);
483 static int stm32_dma_terminate_all(struct dma_chan
*c
)
485 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
489 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
492 vchan_terminate_vdesc(&chan
->desc
->vdesc
);
494 stm32_dma_stop(chan
);
498 vchan_get_all_descriptors(&chan
->vchan
, &head
);
499 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
500 vchan_dma_desc_free_list(&chan
->vchan
, &head
);
505 static void stm32_dma_synchronize(struct dma_chan
*c
)
507 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
509 vchan_synchronize(&chan
->vchan
);
512 static void stm32_dma_dump_reg(struct stm32_dma_chan
*chan
)
514 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
515 u32 scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
516 u32 ndtr
= stm32_dma_read(dmadev
, STM32_DMA_SNDTR(chan
->id
));
517 u32 spar
= stm32_dma_read(dmadev
, STM32_DMA_SPAR(chan
->id
));
518 u32 sm0ar
= stm32_dma_read(dmadev
, STM32_DMA_SM0AR(chan
->id
));
519 u32 sm1ar
= stm32_dma_read(dmadev
, STM32_DMA_SM1AR(chan
->id
));
520 u32 sfcr
= stm32_dma_read(dmadev
, STM32_DMA_SFCR(chan
->id
));
522 dev_dbg(chan2dev(chan
), "SCR: 0x%08x\n", scr
);
523 dev_dbg(chan2dev(chan
), "NDTR: 0x%08x\n", ndtr
);
524 dev_dbg(chan2dev(chan
), "SPAR: 0x%08x\n", spar
);
525 dev_dbg(chan2dev(chan
), "SM0AR: 0x%08x\n", sm0ar
);
526 dev_dbg(chan2dev(chan
), "SM1AR: 0x%08x\n", sm1ar
);
527 dev_dbg(chan2dev(chan
), "SFCR: 0x%08x\n", sfcr
);
530 static void stm32_dma_configure_next_sg(struct stm32_dma_chan
*chan
);
532 static void stm32_dma_start_transfer(struct stm32_dma_chan
*chan
)
534 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
535 struct virt_dma_desc
*vdesc
;
536 struct stm32_dma_sg_req
*sg_req
;
537 struct stm32_dma_chan_reg
*reg
;
541 ret
= stm32_dma_disable_chan(chan
);
546 vdesc
= vchan_next_desc(&chan
->vchan
);
550 list_del(&vdesc
->node
);
552 chan
->desc
= to_stm32_dma_desc(vdesc
);
556 if (chan
->next_sg
== chan
->desc
->num_sgs
)
559 sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
560 reg
= &sg_req
->chan_reg
;
562 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), reg
->dma_scr
);
563 stm32_dma_write(dmadev
, STM32_DMA_SPAR(chan
->id
), reg
->dma_spar
);
564 stm32_dma_write(dmadev
, STM32_DMA_SM0AR(chan
->id
), reg
->dma_sm0ar
);
565 stm32_dma_write(dmadev
, STM32_DMA_SFCR(chan
->id
), reg
->dma_sfcr
);
566 stm32_dma_write(dmadev
, STM32_DMA_SM1AR(chan
->id
), reg
->dma_sm1ar
);
567 stm32_dma_write(dmadev
, STM32_DMA_SNDTR(chan
->id
), reg
->dma_sndtr
);
571 /* Clear interrupt status if it is there */
572 status
= stm32_dma_irq_status(chan
);
574 stm32_dma_irq_clear(chan
, status
);
576 if (chan
->desc
->cyclic
)
577 stm32_dma_configure_next_sg(chan
);
579 stm32_dma_dump_reg(chan
);
582 reg
->dma_scr
|= STM32_DMA_SCR_EN
;
583 stm32_dma_write(dmadev
, STM32_DMA_SCR(chan
->id
), reg
->dma_scr
);
587 dev_dbg(chan2dev(chan
), "vchan %pK: started\n", &chan
->vchan
);
590 static void stm32_dma_configure_next_sg(struct stm32_dma_chan
*chan
)
592 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
593 struct stm32_dma_sg_req
*sg_req
;
594 u32 dma_scr
, dma_sm0ar
, dma_sm1ar
, id
;
597 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
599 if (dma_scr
& STM32_DMA_SCR_DBM
) {
600 if (chan
->next_sg
== chan
->desc
->num_sgs
)
603 sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
605 if (dma_scr
& STM32_DMA_SCR_CT
) {
606 dma_sm0ar
= sg_req
->chan_reg
.dma_sm0ar
;
607 stm32_dma_write(dmadev
, STM32_DMA_SM0AR(id
), dma_sm0ar
);
608 dev_dbg(chan2dev(chan
), "CT=1 <=> SM0AR: 0x%08x\n",
609 stm32_dma_read(dmadev
, STM32_DMA_SM0AR(id
)));
611 dma_sm1ar
= sg_req
->chan_reg
.dma_sm1ar
;
612 stm32_dma_write(dmadev
, STM32_DMA_SM1AR(id
), dma_sm1ar
);
613 dev_dbg(chan2dev(chan
), "CT=0 <=> SM1AR: 0x%08x\n",
614 stm32_dma_read(dmadev
, STM32_DMA_SM1AR(id
)));
619 static void stm32_dma_handle_chan_done(struct stm32_dma_chan
*chan
)
622 if (chan
->desc
->cyclic
) {
623 vchan_cyclic_callback(&chan
->desc
->vdesc
);
625 stm32_dma_configure_next_sg(chan
);
628 if (chan
->next_sg
== chan
->desc
->num_sgs
) {
629 vchan_cookie_complete(&chan
->desc
->vdesc
);
632 stm32_dma_start_transfer(chan
);
637 static irqreturn_t
stm32_dma_chan_irq(int irq
, void *devid
)
639 struct stm32_dma_chan
*chan
= devid
;
640 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
641 u32 status
, scr
, sfcr
;
643 spin_lock(&chan
->vchan
.lock
);
645 status
= stm32_dma_irq_status(chan
);
646 scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
647 sfcr
= stm32_dma_read(dmadev
, STM32_DMA_SFCR(chan
->id
));
649 if (status
& STM32_DMA_TCI
) {
650 stm32_dma_irq_clear(chan
, STM32_DMA_TCI
);
651 if (scr
& STM32_DMA_SCR_TCIE
)
652 stm32_dma_handle_chan_done(chan
);
653 status
&= ~STM32_DMA_TCI
;
655 if (status
& STM32_DMA_HTI
) {
656 stm32_dma_irq_clear(chan
, STM32_DMA_HTI
);
657 status
&= ~STM32_DMA_HTI
;
659 if (status
& STM32_DMA_FEI
) {
660 stm32_dma_irq_clear(chan
, STM32_DMA_FEI
);
661 status
&= ~STM32_DMA_FEI
;
662 if (sfcr
& STM32_DMA_SFCR_FEIE
) {
663 if (!(scr
& STM32_DMA_SCR_EN
))
664 dev_err(chan2dev(chan
), "FIFO Error\n");
666 dev_dbg(chan2dev(chan
), "FIFO over/underrun\n");
670 stm32_dma_irq_clear(chan
, status
);
671 dev_err(chan2dev(chan
), "DMA error: status=0x%08x\n", status
);
672 if (!(scr
& STM32_DMA_SCR_EN
))
673 dev_err(chan2dev(chan
), "chan disabled by HW\n");
676 spin_unlock(&chan
->vchan
.lock
);
681 static void stm32_dma_issue_pending(struct dma_chan
*c
)
683 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
686 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
687 if (vchan_issue_pending(&chan
->vchan
) && !chan
->desc
&& !chan
->busy
) {
688 dev_dbg(chan2dev(chan
), "vchan %pK: issued\n", &chan
->vchan
);
689 stm32_dma_start_transfer(chan
);
692 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
695 static int stm32_dma_set_xfer_param(struct stm32_dma_chan
*chan
,
696 enum dma_transfer_direction direction
,
697 enum dma_slave_buswidth
*buswidth
,
700 enum dma_slave_buswidth src_addr_width
, dst_addr_width
;
701 int src_bus_width
, dst_bus_width
;
702 int src_burst_size
, dst_burst_size
;
703 u32 src_maxburst
, dst_maxburst
, src_best_burst
, dst_best_burst
;
704 u32 dma_scr
, threshold
;
706 src_addr_width
= chan
->dma_sconfig
.src_addr_width
;
707 dst_addr_width
= chan
->dma_sconfig
.dst_addr_width
;
708 src_maxburst
= chan
->dma_sconfig
.src_maxburst
;
709 dst_maxburst
= chan
->dma_sconfig
.dst_maxburst
;
710 threshold
= chan
->threshold
;
714 /* Set device data size */
715 dst_bus_width
= stm32_dma_get_width(chan
, dst_addr_width
);
716 if (dst_bus_width
< 0)
717 return dst_bus_width
;
719 /* Set device burst size */
720 dst_best_burst
= stm32_dma_get_best_burst(buf_len
,
725 dst_burst_size
= stm32_dma_get_burst(chan
, dst_best_burst
);
726 if (dst_burst_size
< 0)
727 return dst_burst_size
;
729 /* Set memory data size */
730 src_addr_width
= stm32_dma_get_max_width(buf_len
, threshold
);
731 chan
->mem_width
= src_addr_width
;
732 src_bus_width
= stm32_dma_get_width(chan
, src_addr_width
);
733 if (src_bus_width
< 0)
734 return src_bus_width
;
736 /* Set memory burst size */
737 src_maxburst
= STM32_DMA_MAX_BURST
;
738 src_best_burst
= stm32_dma_get_best_burst(buf_len
,
742 src_burst_size
= stm32_dma_get_burst(chan
, src_best_burst
);
743 if (src_burst_size
< 0)
744 return src_burst_size
;
746 dma_scr
= STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV
) |
747 STM32_DMA_SCR_PSIZE(dst_bus_width
) |
748 STM32_DMA_SCR_MSIZE(src_bus_width
) |
749 STM32_DMA_SCR_PBURST(dst_burst_size
) |
750 STM32_DMA_SCR_MBURST(src_burst_size
);
752 /* Set FIFO threshold */
753 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_FTH_MASK
;
754 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_FTH(threshold
);
756 /* Set peripheral address */
757 chan
->chan_reg
.dma_spar
= chan
->dma_sconfig
.dst_addr
;
758 *buswidth
= dst_addr_width
;
762 /* Set device data size */
763 src_bus_width
= stm32_dma_get_width(chan
, src_addr_width
);
764 if (src_bus_width
< 0)
765 return src_bus_width
;
767 /* Set device burst size */
768 src_best_burst
= stm32_dma_get_best_burst(buf_len
,
772 chan
->mem_burst
= src_best_burst
;
773 src_burst_size
= stm32_dma_get_burst(chan
, src_best_burst
);
774 if (src_burst_size
< 0)
775 return src_burst_size
;
777 /* Set memory data size */
778 dst_addr_width
= stm32_dma_get_max_width(buf_len
, threshold
);
779 chan
->mem_width
= dst_addr_width
;
780 dst_bus_width
= stm32_dma_get_width(chan
, dst_addr_width
);
781 if (dst_bus_width
< 0)
782 return dst_bus_width
;
784 /* Set memory burst size */
785 dst_maxburst
= STM32_DMA_MAX_BURST
;
786 dst_best_burst
= stm32_dma_get_best_burst(buf_len
,
790 chan
->mem_burst
= dst_best_burst
;
791 dst_burst_size
= stm32_dma_get_burst(chan
, dst_best_burst
);
792 if (dst_burst_size
< 0)
793 return dst_burst_size
;
795 dma_scr
= STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM
) |
796 STM32_DMA_SCR_PSIZE(src_bus_width
) |
797 STM32_DMA_SCR_MSIZE(dst_bus_width
) |
798 STM32_DMA_SCR_PBURST(src_burst_size
) |
799 STM32_DMA_SCR_MBURST(dst_burst_size
);
801 /* Set FIFO threshold */
802 chan
->chan_reg
.dma_sfcr
&= ~STM32_DMA_SFCR_FTH_MASK
;
803 chan
->chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_FTH(threshold
);
805 /* Set peripheral address */
806 chan
->chan_reg
.dma_spar
= chan
->dma_sconfig
.src_addr
;
807 *buswidth
= chan
->dma_sconfig
.src_addr_width
;
811 dev_err(chan2dev(chan
), "Dma direction is not supported\n");
815 stm32_dma_set_fifo_config(chan
, src_best_burst
, dst_best_burst
);
817 /* Set DMA control register */
818 chan
->chan_reg
.dma_scr
&= ~(STM32_DMA_SCR_DIR_MASK
|
819 STM32_DMA_SCR_PSIZE_MASK
| STM32_DMA_SCR_MSIZE_MASK
|
820 STM32_DMA_SCR_PBURST_MASK
| STM32_DMA_SCR_MBURST_MASK
);
821 chan
->chan_reg
.dma_scr
|= dma_scr
;
826 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg
*regs
)
828 memset(regs
, 0, sizeof(struct stm32_dma_chan_reg
));
831 static struct dma_async_tx_descriptor
*stm32_dma_prep_slave_sg(
832 struct dma_chan
*c
, struct scatterlist
*sgl
,
833 u32 sg_len
, enum dma_transfer_direction direction
,
834 unsigned long flags
, void *context
)
836 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
837 struct stm32_dma_desc
*desc
;
838 struct scatterlist
*sg
;
839 enum dma_slave_buswidth buswidth
;
843 if (!chan
->config_init
) {
844 dev_err(chan2dev(chan
), "dma channel is not configured\n");
849 dev_err(chan2dev(chan
), "Invalid segment length %d\n", sg_len
);
853 desc
= kzalloc(struct_size(desc
, sg_req
, sg_len
), GFP_NOWAIT
);
857 /* Set peripheral flow controller */
858 if (chan
->dma_sconfig
.device_fc
)
859 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_PFCTRL
;
861 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_PFCTRL
;
863 for_each_sg(sgl
, sg
, sg_len
, i
) {
864 ret
= stm32_dma_set_xfer_param(chan
, direction
, &buswidth
,
869 desc
->sg_req
[i
].len
= sg_dma_len(sg
);
871 nb_data_items
= desc
->sg_req
[i
].len
/ buswidth
;
872 if (nb_data_items
> STM32_DMA_ALIGNED_MAX_DATA_ITEMS
) {
873 dev_err(chan2dev(chan
), "nb items not supported\n");
877 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
878 desc
->sg_req
[i
].chan_reg
.dma_scr
= chan
->chan_reg
.dma_scr
;
879 desc
->sg_req
[i
].chan_reg
.dma_sfcr
= chan
->chan_reg
.dma_sfcr
;
880 desc
->sg_req
[i
].chan_reg
.dma_spar
= chan
->chan_reg
.dma_spar
;
881 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= sg_dma_address(sg
);
882 desc
->sg_req
[i
].chan_reg
.dma_sm1ar
= sg_dma_address(sg
);
883 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= nb_data_items
;
886 desc
->num_sgs
= sg_len
;
887 desc
->cyclic
= false;
889 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
896 static struct dma_async_tx_descriptor
*stm32_dma_prep_dma_cyclic(
897 struct dma_chan
*c
, dma_addr_t buf_addr
, size_t buf_len
,
898 size_t period_len
, enum dma_transfer_direction direction
,
901 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
902 struct stm32_dma_desc
*desc
;
903 enum dma_slave_buswidth buswidth
;
904 u32 num_periods
, nb_data_items
;
907 if (!buf_len
|| !period_len
) {
908 dev_err(chan2dev(chan
), "Invalid buffer/period len\n");
912 if (!chan
->config_init
) {
913 dev_err(chan2dev(chan
), "dma channel is not configured\n");
917 if (buf_len
% period_len
) {
918 dev_err(chan2dev(chan
), "buf_len not multiple of period_len\n");
923 * We allow to take more number of requests till DMA is
924 * not started. The driver will loop over all requests.
925 * Once DMA is started then new requests can be queued only after
926 * terminating the DMA.
929 dev_err(chan2dev(chan
), "Request not allowed when dma busy\n");
933 ret
= stm32_dma_set_xfer_param(chan
, direction
, &buswidth
, period_len
);
937 nb_data_items
= period_len
/ buswidth
;
938 if (nb_data_items
> STM32_DMA_ALIGNED_MAX_DATA_ITEMS
) {
939 dev_err(chan2dev(chan
), "number of items not supported\n");
943 /* Enable Circular mode or double buffer mode */
944 if (buf_len
== period_len
)
945 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_CIRC
;
947 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_DBM
;
949 /* Clear periph ctrl if client set it */
950 chan
->chan_reg
.dma_scr
&= ~STM32_DMA_SCR_PFCTRL
;
952 num_periods
= buf_len
/ period_len
;
954 desc
= kzalloc(struct_size(desc
, sg_req
, num_periods
), GFP_NOWAIT
);
958 for (i
= 0; i
< num_periods
; i
++) {
959 desc
->sg_req
[i
].len
= period_len
;
961 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
962 desc
->sg_req
[i
].chan_reg
.dma_scr
= chan
->chan_reg
.dma_scr
;
963 desc
->sg_req
[i
].chan_reg
.dma_sfcr
= chan
->chan_reg
.dma_sfcr
;
964 desc
->sg_req
[i
].chan_reg
.dma_spar
= chan
->chan_reg
.dma_spar
;
965 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= buf_addr
;
966 desc
->sg_req
[i
].chan_reg
.dma_sm1ar
= buf_addr
;
967 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= nb_data_items
;
968 buf_addr
+= period_len
;
971 desc
->num_sgs
= num_periods
;
974 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
977 static struct dma_async_tx_descriptor
*stm32_dma_prep_dma_memcpy(
978 struct dma_chan
*c
, dma_addr_t dest
,
979 dma_addr_t src
, size_t len
, unsigned long flags
)
981 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
982 enum dma_slave_buswidth max_width
;
983 struct stm32_dma_desc
*desc
;
984 size_t xfer_count
, offset
;
985 u32 num_sgs
, best_burst
, dma_burst
, threshold
;
988 num_sgs
= DIV_ROUND_UP(len
, STM32_DMA_ALIGNED_MAX_DATA_ITEMS
);
989 desc
= kzalloc(struct_size(desc
, sg_req
, num_sgs
), GFP_NOWAIT
);
993 threshold
= chan
->threshold
;
995 for (offset
= 0, i
= 0; offset
< len
; offset
+= xfer_count
, i
++) {
996 xfer_count
= min_t(size_t, len
- offset
,
997 STM32_DMA_ALIGNED_MAX_DATA_ITEMS
);
999 /* Compute best burst size */
1000 max_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1001 best_burst
= stm32_dma_get_best_burst(len
, STM32_DMA_MAX_BURST
,
1002 threshold
, max_width
);
1003 dma_burst
= stm32_dma_get_burst(chan
, best_burst
);
1005 stm32_dma_clear_reg(&desc
->sg_req
[i
].chan_reg
);
1006 desc
->sg_req
[i
].chan_reg
.dma_scr
=
1007 STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM
) |
1008 STM32_DMA_SCR_PBURST(dma_burst
) |
1009 STM32_DMA_SCR_MBURST(dma_burst
) |
1010 STM32_DMA_SCR_MINC
|
1011 STM32_DMA_SCR_PINC
|
1012 STM32_DMA_SCR_TCIE
|
1014 desc
->sg_req
[i
].chan_reg
.dma_sfcr
|= STM32_DMA_SFCR_MASK
;
1015 desc
->sg_req
[i
].chan_reg
.dma_sfcr
|=
1016 STM32_DMA_SFCR_FTH(threshold
);
1017 desc
->sg_req
[i
].chan_reg
.dma_spar
= src
+ offset
;
1018 desc
->sg_req
[i
].chan_reg
.dma_sm0ar
= dest
+ offset
;
1019 desc
->sg_req
[i
].chan_reg
.dma_sndtr
= xfer_count
;
1020 desc
->sg_req
[i
].len
= xfer_count
;
1023 desc
->num_sgs
= num_sgs
;
1024 desc
->cyclic
= false;
1026 return vchan_tx_prep(&chan
->vchan
, &desc
->vdesc
, flags
);
1029 static u32
stm32_dma_get_remaining_bytes(struct stm32_dma_chan
*chan
)
1031 u32 dma_scr
, width
, ndtr
;
1032 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1034 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(chan
->id
));
1035 width
= STM32_DMA_SCR_PSIZE_GET(dma_scr
);
1036 ndtr
= stm32_dma_read(dmadev
, STM32_DMA_SNDTR(chan
->id
));
1038 return ndtr
<< width
;
1042 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1043 * @chan: dma channel
1045 * This function called when IRQ are disable, checks that the hardware has not
1046 * switched on the next transfer in double buffer mode. The test is done by
1047 * comparing the next_sg memory address with the hardware related register
1048 * (based on CT bit value).
1050 * Returns true if expected current transfer is still running or double
1051 * buffer mode is not activated.
1053 static bool stm32_dma_is_current_sg(struct stm32_dma_chan
*chan
)
1055 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1056 struct stm32_dma_sg_req
*sg_req
;
1057 u32 dma_scr
, dma_smar
, id
;
1060 dma_scr
= stm32_dma_read(dmadev
, STM32_DMA_SCR(id
));
1062 if (!(dma_scr
& STM32_DMA_SCR_DBM
))
1065 sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
1067 if (dma_scr
& STM32_DMA_SCR_CT
) {
1068 dma_smar
= stm32_dma_read(dmadev
, STM32_DMA_SM0AR(id
));
1069 return (dma_smar
== sg_req
->chan_reg
.dma_sm0ar
);
1072 dma_smar
= stm32_dma_read(dmadev
, STM32_DMA_SM1AR(id
));
1074 return (dma_smar
== sg_req
->chan_reg
.dma_sm1ar
);
1077 static size_t stm32_dma_desc_residue(struct stm32_dma_chan
*chan
,
1078 struct stm32_dma_desc
*desc
,
1081 u32 modulo
, burst_size
;
1084 struct stm32_dma_sg_req
*sg_req
= &chan
->desc
->sg_req
[chan
->next_sg
];
1088 * Calculate the residue means compute the descriptors
1090 * - the sg_req currently transferred
1091 * - the Hardware remaining position in this sg (NDTR bits field).
1093 * A race condition may occur if DMA is running in cyclic or double
1094 * buffer mode, since the DMA register are automatically reloaded at end
1095 * of period transfer. The hardware may have switched to the next
1096 * transfer (CT bit updated) just before the position (SxNDTR reg) is
1098 * In this case the SxNDTR reg could (or not) correspond to the new
1099 * transfer position, and not the expected one.
1100 * The strategy implemented in the stm32 driver is to:
1101 * - read the SxNDTR register
1102 * - crosscheck that hardware is still in current transfer.
1103 * In case of switch, we can assume that the DMA is at the beginning of
1104 * the next transfer. So we approximate the residue in consequence, by
1105 * pointing on the beginning of next transfer.
1107 * This race condition doesn't apply for none cyclic mode, as double
1108 * buffer is not used. In such situation registers are updated by the
1112 residue
= stm32_dma_get_remaining_bytes(chan
);
1114 if (!stm32_dma_is_current_sg(chan
)) {
1116 if (n_sg
== chan
->desc
->num_sgs
)
1118 residue
= sg_req
->len
;
1122 * In cyclic mode, for the last period, residue = remaining bytes
1124 * else for all other periods in cyclic mode, and in sg mode,
1125 * residue = remaining bytes from NDTR + remaining
1126 * periods/sg to be transferred
1128 if (!chan
->desc
->cyclic
|| n_sg
!= 0)
1129 for (i
= n_sg
; i
< desc
->num_sgs
; i
++)
1130 residue
+= desc
->sg_req
[i
].len
;
1132 if (!chan
->mem_burst
)
1135 burst_size
= chan
->mem_burst
* chan
->mem_width
;
1136 modulo
= residue
% burst_size
;
1138 residue
= residue
- modulo
+ burst_size
;
1143 static enum dma_status
stm32_dma_tx_status(struct dma_chan
*c
,
1144 dma_cookie_t cookie
,
1145 struct dma_tx_state
*state
)
1147 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1148 struct virt_dma_desc
*vdesc
;
1149 enum dma_status status
;
1150 unsigned long flags
;
1153 status
= dma_cookie_status(c
, cookie
, state
);
1154 if (status
== DMA_COMPLETE
|| !state
)
1157 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
1158 vdesc
= vchan_find_desc(&chan
->vchan
, cookie
);
1159 if (chan
->desc
&& cookie
== chan
->desc
->vdesc
.tx
.cookie
)
1160 residue
= stm32_dma_desc_residue(chan
, chan
->desc
,
1163 residue
= stm32_dma_desc_residue(chan
,
1164 to_stm32_dma_desc(vdesc
), 0);
1165 dma_set_residue(state
, residue
);
1167 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
1172 static int stm32_dma_alloc_chan_resources(struct dma_chan
*c
)
1174 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1175 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1178 chan
->config_init
= false;
1180 ret
= pm_runtime_get_sync(dmadev
->ddev
.dev
);
1184 ret
= stm32_dma_disable_chan(chan
);
1186 pm_runtime_put(dmadev
->ddev
.dev
);
1191 static void stm32_dma_free_chan_resources(struct dma_chan
*c
)
1193 struct stm32_dma_chan
*chan
= to_stm32_dma_chan(c
);
1194 struct stm32_dma_device
*dmadev
= stm32_dma_get_dev(chan
);
1195 unsigned long flags
;
1197 dev_dbg(chan2dev(chan
), "Freeing channel %d\n", chan
->id
);
1200 spin_lock_irqsave(&chan
->vchan
.lock
, flags
);
1201 stm32_dma_stop(chan
);
1203 spin_unlock_irqrestore(&chan
->vchan
.lock
, flags
);
1206 pm_runtime_put(dmadev
->ddev
.dev
);
1208 vchan_free_chan_resources(to_virt_chan(c
));
1211 static void stm32_dma_desc_free(struct virt_dma_desc
*vdesc
)
1213 kfree(container_of(vdesc
, struct stm32_dma_desc
, vdesc
));
1216 static void stm32_dma_set_config(struct stm32_dma_chan
*chan
,
1217 struct stm32_dma_cfg
*cfg
)
1219 stm32_dma_clear_reg(&chan
->chan_reg
);
1221 chan
->chan_reg
.dma_scr
= cfg
->stream_config
& STM32_DMA_SCR_CFG_MASK
;
1222 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_REQ(cfg
->request_line
);
1224 /* Enable Interrupts */
1225 chan
->chan_reg
.dma_scr
|= STM32_DMA_SCR_TEIE
| STM32_DMA_SCR_TCIE
;
1227 chan
->threshold
= STM32_DMA_THRESHOLD_FTR_GET(cfg
->features
);
1230 static struct dma_chan
*stm32_dma_of_xlate(struct of_phandle_args
*dma_spec
,
1231 struct of_dma
*ofdma
)
1233 struct stm32_dma_device
*dmadev
= ofdma
->of_dma_data
;
1234 struct device
*dev
= dmadev
->ddev
.dev
;
1235 struct stm32_dma_cfg cfg
;
1236 struct stm32_dma_chan
*chan
;
1239 if (dma_spec
->args_count
< 4) {
1240 dev_err(dev
, "Bad number of cells\n");
1244 cfg
.channel_id
= dma_spec
->args
[0];
1245 cfg
.request_line
= dma_spec
->args
[1];
1246 cfg
.stream_config
= dma_spec
->args
[2];
1247 cfg
.features
= dma_spec
->args
[3];
1249 if (cfg
.channel_id
>= STM32_DMA_MAX_CHANNELS
||
1250 cfg
.request_line
>= STM32_DMA_MAX_REQUEST_ID
) {
1251 dev_err(dev
, "Bad channel and/or request id\n");
1255 chan
= &dmadev
->chan
[cfg
.channel_id
];
1257 c
= dma_get_slave_channel(&chan
->vchan
.chan
);
1259 dev_err(dev
, "No more channels available\n");
1263 stm32_dma_set_config(chan
, &cfg
);
1268 static const struct of_device_id stm32_dma_of_match
[] = {
1269 { .compatible
= "st,stm32-dma", },
1272 MODULE_DEVICE_TABLE(of
, stm32_dma_of_match
);
1274 static int stm32_dma_probe(struct platform_device
*pdev
)
1276 struct stm32_dma_chan
*chan
;
1277 struct stm32_dma_device
*dmadev
;
1278 struct dma_device
*dd
;
1279 const struct of_device_id
*match
;
1280 struct resource
*res
;
1283 match
= of_match_device(stm32_dma_of_match
, &pdev
->dev
);
1285 dev_err(&pdev
->dev
, "Error: No device match found\n");
1289 dmadev
= devm_kzalloc(&pdev
->dev
, sizeof(*dmadev
), GFP_KERNEL
);
1295 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1296 dmadev
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1297 if (IS_ERR(dmadev
->base
))
1298 return PTR_ERR(dmadev
->base
);
1300 dmadev
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1301 if (IS_ERR(dmadev
->clk
)) {
1302 dev_err(&pdev
->dev
, "Error: Missing controller clock\n");
1303 return PTR_ERR(dmadev
->clk
);
1306 ret
= clk_prepare_enable(dmadev
->clk
);
1308 dev_err(&pdev
->dev
, "clk_prep_enable error: %d\n", ret
);
1312 dmadev
->mem2mem
= of_property_read_bool(pdev
->dev
.of_node
,
1315 dmadev
->rst
= devm_reset_control_get(&pdev
->dev
, NULL
);
1316 if (!IS_ERR(dmadev
->rst
)) {
1317 reset_control_assert(dmadev
->rst
);
1319 reset_control_deassert(dmadev
->rst
);
1322 dma_cap_set(DMA_SLAVE
, dd
->cap_mask
);
1323 dma_cap_set(DMA_PRIVATE
, dd
->cap_mask
);
1324 dma_cap_set(DMA_CYCLIC
, dd
->cap_mask
);
1325 dd
->device_alloc_chan_resources
= stm32_dma_alloc_chan_resources
;
1326 dd
->device_free_chan_resources
= stm32_dma_free_chan_resources
;
1327 dd
->device_tx_status
= stm32_dma_tx_status
;
1328 dd
->device_issue_pending
= stm32_dma_issue_pending
;
1329 dd
->device_prep_slave_sg
= stm32_dma_prep_slave_sg
;
1330 dd
->device_prep_dma_cyclic
= stm32_dma_prep_dma_cyclic
;
1331 dd
->device_config
= stm32_dma_slave_config
;
1332 dd
->device_terminate_all
= stm32_dma_terminate_all
;
1333 dd
->device_synchronize
= stm32_dma_synchronize
;
1334 dd
->src_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1335 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1336 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
1337 dd
->dst_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1338 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1339 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
1340 dd
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1341 dd
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1342 dd
->max_burst
= STM32_DMA_MAX_BURST
;
1343 dd
->dev
= &pdev
->dev
;
1344 INIT_LIST_HEAD(&dd
->channels
);
1346 if (dmadev
->mem2mem
) {
1347 dma_cap_set(DMA_MEMCPY
, dd
->cap_mask
);
1348 dd
->device_prep_dma_memcpy
= stm32_dma_prep_dma_memcpy
;
1349 dd
->directions
|= BIT(DMA_MEM_TO_MEM
);
1352 for (i
= 0; i
< STM32_DMA_MAX_CHANNELS
; i
++) {
1353 chan
= &dmadev
->chan
[i
];
1355 chan
->vchan
.desc_free
= stm32_dma_desc_free
;
1356 vchan_init(&chan
->vchan
, dd
);
1359 ret
= dma_async_device_register(dd
);
1363 for (i
= 0; i
< STM32_DMA_MAX_CHANNELS
; i
++) {
1364 chan
= &dmadev
->chan
[i
];
1365 ret
= platform_get_irq(pdev
, i
);
1367 goto err_unregister
;
1370 ret
= devm_request_irq(&pdev
->dev
, chan
->irq
,
1371 stm32_dma_chan_irq
, 0,
1372 dev_name(chan2dev(chan
)), chan
);
1375 "request_irq failed with err %d channel %d\n",
1377 goto err_unregister
;
1381 ret
= of_dma_controller_register(pdev
->dev
.of_node
,
1382 stm32_dma_of_xlate
, dmadev
);
1385 "STM32 DMA DMA OF registration failed %d\n", ret
);
1386 goto err_unregister
;
1389 platform_set_drvdata(pdev
, dmadev
);
1391 pm_runtime_set_active(&pdev
->dev
);
1392 pm_runtime_enable(&pdev
->dev
);
1393 pm_runtime_get_noresume(&pdev
->dev
);
1394 pm_runtime_put(&pdev
->dev
);
1396 dev_info(&pdev
->dev
, "STM32 DMA driver registered\n");
1401 dma_async_device_unregister(dd
);
1403 clk_disable_unprepare(dmadev
->clk
);
1409 static int stm32_dma_runtime_suspend(struct device
*dev
)
1411 struct stm32_dma_device
*dmadev
= dev_get_drvdata(dev
);
1413 clk_disable_unprepare(dmadev
->clk
);
1418 static int stm32_dma_runtime_resume(struct device
*dev
)
1420 struct stm32_dma_device
*dmadev
= dev_get_drvdata(dev
);
1423 ret
= clk_prepare_enable(dmadev
->clk
);
1425 dev_err(dev
, "failed to prepare_enable clock\n");
1433 static const struct dev_pm_ops stm32_dma_pm_ops
= {
1434 SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend
,
1435 stm32_dma_runtime_resume
, NULL
)
1438 static struct platform_driver stm32_dma_driver
= {
1440 .name
= "stm32-dma",
1441 .of_match_table
= stm32_dma_of_match
,
1442 .pm
= &stm32_dma_pm_ops
,
1446 static int __init
stm32_dma_init(void)
1448 return platform_driver_probe(&stm32_dma_driver
, stm32_dma_probe
);
1450 subsys_initcall(stm32_dma_init
);