drivers/edac/Kconfig

   1 #
   2 #       EDAC Kconfig
   3 #       Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
   4 #       Licensed and distributed under the GPL
   5
   6 config EDAC_ATOMIC_SCRUB
   7         bool
   8
   9 config EDAC_SUPPORT
  10         bool
  11
  12 menuconfig EDAC
  13         tristate "EDAC (Error Detection And Correction) reporting"
  14         depends on HAS_IOMEM && EDAC_SUPPORT && RAS
  15         help
  16           EDAC is a subsystem along with hardware-specific drivers designed to
  17           report hardware errors. These are low-level errors that are reported
  18           in the CPU or supporting chipset or other subsystems:
  19           memory errors, cache errors, PCI errors, thermal throttling, etc..
  20           If unsure, select 'Y'.
  21
  22           The mailing list for the EDAC project is linux-edac@vger.kernel.org.
  23
  24 if EDAC
  25
  26 config EDAC_LEGACY_SYSFS
  27         bool "EDAC legacy sysfs"
  28         default y
  29         help
  30           Enable the compatibility sysfs nodes.
  31           Use 'Y' if your edac utilities aren't ported to work with the newer
  32           structures.
  33
  34 config EDAC_DEBUG
  35         bool "Debugging"
  36         select DEBUG_FS
  37         help
  38           This turns on debugging information for the entire EDAC subsystem.
  39           You do so by inserting edac_module with "edac_debug_level=x." Valid
  40           levels are 0-4 (from low to high) and by default it is set to 2.
  41           Usually you should select 'N' here.
  42
  43 config EDAC_DECODE_MCE
  44         tristate "Decode MCEs in human-readable form (only on AMD for now)"
  45         depends on CPU_SUP_AMD && X86_MCE_AMD
  46         default y
  47         ---help---
  48           Enable this option if you want to decode Machine Check Exceptions
  49           occurring on your machine in human-readable form.
  50
  51           You should definitely say Y here in case you want to decode MCEs
  52           which occur really early upon boot, before the module infrastructure
  53           has been initialized.
  54
  55 config EDAC_GHES
  56         bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
  57         depends on ACPI_APEI_GHES && (EDAC=y)
  58         default y
  59         help
  60           Not all machines support hardware-driven error report. Some of those
  61           provide a BIOS-driven error report mechanism via ACPI, using the
  62           APEI/GHES driver. By enabling this option, the error reports provided
  63           by GHES are sent to userspace via the EDAC API.
  64
  65           When this option is enabled, it will disable the hardware-driven
  66           mechanisms, if a GHES BIOS is detected, entering into the
  67           "Firmware First" mode.
  68
  69           It should be noticed that keeping both GHES and a hardware-driven
  70           error mechanism won't work well, as BIOS will race with OS, while
  71           reading the error registers. So, if you want to not use "Firmware
  72           first" GHES error mechanism, you should disable GHES either at
  73           compilation time or by passing "ghes.disable=1" Kernel parameter
  74           at boot time.
  75
  76           In doubt, say 'Y'.
  77
  78 config EDAC_AMD64
  79         tristate "AMD64 (Opteron, Athlon64)"
  80         depends on AMD_NB && EDAC_DECODE_MCE
  81         help
  82           Support for error detection and correction of DRAM ECC errors on
  83           the AMD64 families (>= K8) of memory controllers.
  84
  85 config EDAC_AMD64_ERROR_INJECTION
  86         bool "Sysfs HW Error injection facilities"
  87         depends on EDAC_AMD64
  88         help
  89           Recent Opterons (Family 10h and later) provide for Memory Error
  90           Injection into the ECC detection circuits. The amd64_edac module
  91           allows the operator/user to inject Uncorrectable and Correctable
  92           errors into DRAM.
  93
  94           When enabled, in each of the respective memory controller directories
  95           (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  96
  97           - inject_section (0..3, 16-byte section of 64-byte cacheline),
  98           - inject_word (0..8, 16-bit word of 16-byte section),
  99           - inject_ecc_vector (hex ecc vector: select bits of inject word)
 100
 101           In addition, there are two control files, inject_read and inject_write,
 102           which trigger the DRAM ECC Read and Write respectively.
 103
 104 config EDAC_AMD76X
 105         tristate "AMD 76x (760, 762, 768)"
 106         depends on PCI && X86_32
 107         help
 108           Support for error detection and correction on the AMD 76x
 109           series of chipsets used with the Athlon processor.
 110
 111 config EDAC_E7XXX
 112         tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
 113         depends on PCI && X86_32
 114         help
 115           Support for error detection and correction on the Intel
 116           E7205, E7500, E7501 and E7505 server chipsets.
 117
 118 config EDAC_E752X
 119         tristate "Intel e752x (e7520, e7525, e7320) and 3100"
 120         depends on PCI && X86
 121         help
 122           Support for error detection and correction on the Intel
 123           E7520, E7525, E7320 server chipsets.
 124
 125 config EDAC_I82443BXGX
 126         tristate "Intel 82443BX/GX (440BX/GX)"
 127         depends on PCI && X86_32
 128         depends on BROKEN
 129         help
 130           Support for error detection and correction on the Intel
 131           82443BX/GX memory controllers (440BX/GX chipsets).
 132
 133 config EDAC_I82875P
 134         tristate "Intel 82875p (D82875P, E7210)"
 135         depends on PCI && X86_32
 136         help
 137           Support for error detection and correction on the Intel
 138           DP82785P and E7210 server chipsets.
 139
 140 config EDAC_I82975X
 141         tristate "Intel 82975x (D82975x)"
 142         depends on PCI && X86
 143         help
 144           Support for error detection and correction on the Intel
 145           DP82975x server chipsets.
 146
 147 config EDAC_I3000
 148         tristate "Intel 3000/3010"
 149         depends on PCI && X86
 150         help
 151           Support for error detection and correction on the Intel
 152           3000 and 3010 server chipsets.
 153
 154 config EDAC_I3200
 155         tristate "Intel 3200"
 156         depends on PCI && X86
 157         help
 158           Support for error detection and correction on the Intel
 159           3200 and 3210 server chipsets.
 160
 161 config EDAC_IE31200
 162         tristate "Intel e312xx"
 163         depends on PCI && X86
 164         help
 165           Support for error detection and correction on the Intel
 166           E3-1200 based DRAM controllers.
 167
 168 config EDAC_X38
 169         tristate "Intel X38"
 170         depends on PCI && X86
 171         help
 172           Support for error detection and correction on the Intel
 173           X38 server chipsets.
 174
 175 config EDAC_I5400
 176         tristate "Intel 5400 (Seaburg) chipsets"
 177         depends on PCI && X86
 178         help
 179           Support for error detection and correction the Intel
 180           i5400 MCH chipset (Seaburg).
 181
 182 config EDAC_I7CORE
 183         tristate "Intel i7 Core (Nehalem) processors"
 184         depends on PCI && X86 && X86_MCE_INTEL
 185         help
 186           Support for error detection and correction the Intel
 187           i7 Core (Nehalem) Integrated Memory Controller that exists on
 188           newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
 189           and Xeon 55xx processors.
 190
 191 config EDAC_I82860
 192         tristate "Intel 82860"
 193         depends on PCI && X86_32
 194         help
 195           Support for error detection and correction on the Intel
 196           82860 chipset.
 197
 198 config EDAC_R82600
 199         tristate "Radisys 82600 embedded chipset"
 200         depends on PCI && X86_32
 201         help
 202           Support for error detection and correction on the Radisys
 203           82600 embedded chipset.
 204
 205 config EDAC_I5000
 206         tristate "Intel Greencreek/Blackford chipset"
 207         depends on X86 && PCI
 208         help
 209           Support for error detection and correction the Intel
 210           Greekcreek/Blackford chipsets.
 211
 212 config EDAC_I5100
 213         tristate "Intel San Clemente MCH"
 214         depends on X86 && PCI
 215         help
 216           Support for error detection and correction the Intel
 217           San Clemente MCH.
 218
 219 config EDAC_I7300
 220         tristate "Intel Clarksboro MCH"
 221         depends on X86 && PCI
 222         help
 223           Support for error detection and correction the Intel
 224           Clarksboro MCH (Intel 7300 chipset).
 225
 226 config EDAC_SBRIDGE
 227         tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
 228         depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
 229         help
 230           Support for error detection and correction the Intel
 231           Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
 232
 233 config EDAC_SKX
 234         tristate "Intel Skylake server Integrated MC"
 235         depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
 236         help
 237           Support for error detection and correction the Intel
 238           Skylake server Integrated Memory Controllers.
 239
 240 config EDAC_PND2
 241         tristate "Intel Pondicherry2"
 242         depends on PCI && X86_64 && X86_MCE_INTEL
 243         help
 244           Support for error detection and correction on the Intel
 245           Pondicherry2 Integrated Memory Controller. This SoC IP is
 246           first used on the Apollo Lake platform and Denverton
 247           micro-server but may appear on others in the future.
 248
 249 config EDAC_MPC85XX
 250         tristate "Freescale MPC83xx / MPC85xx"
 251         depends on FSL_SOC
 252         help
 253           Support for error detection and correction on the Freescale
 254           MPC8349, MPC8560, MPC8540, MPC8548, T4240
 255
 256 config EDAC_LAYERSCAPE
 257         tristate "Freescale Layerscape DDR"
 258         depends on ARCH_LAYERSCAPE
 259         help
 260           Support for error detection and correction on Freescale memory
 261           controllers on Layerscape SoCs.
 262
 263 config EDAC_MV64X60
 264         tristate "Marvell MV64x60"
 265         depends on MV64X60
 266         help
 267           Support for error detection and correction on the Marvell
 268           MV64360 and MV64460 chipsets.
 269
 270 config EDAC_PASEMI
 271         tristate "PA Semi PWRficient"
 272         depends on PPC_PASEMI && PCI
 273         help
 274           Support for error detection and correction on PA Semi
 275           PWRficient.
 276
 277 config EDAC_CELL
 278         tristate "Cell Broadband Engine memory controller"
 279         depends on PPC_CELL_COMMON
 280         help
 281           Support for error detection and correction on the
 282           Cell Broadband Engine internal memory controller
 283           on platform without a hypervisor
 284
 285 config EDAC_PPC4XX
 286         tristate "PPC4xx IBM DDR2 Memory Controller"
 287         depends on 4xx
 288         help
 289           This enables support for EDAC on the ECC memory used
 290           with the IBM DDR2 memory controller found in various
 291           PowerPC 4xx embedded processors such as the 405EX[r],
 292           440SP, 440SPe, 460EX, 460GT and 460SX.
 293
 294 config EDAC_AMD8131
 295         tristate "AMD8131 HyperTransport PCI-X Tunnel"
 296         depends on PCI && PPC_MAPLE
 297         help
 298           Support for error detection and correction on the
 299           AMD8131 HyperTransport PCI-X Tunnel chip.
 300           Note, add more Kconfig dependency if it's adopted
 301           on some machine other than Maple.
 302
 303 config EDAC_AMD8111
 304         tristate "AMD8111 HyperTransport I/O Hub"
 305         depends on PCI && PPC_MAPLE
 306         help
 307           Support for error detection and correction on the
 308           AMD8111 HyperTransport I/O Hub chip.
 309           Note, add more Kconfig dependency if it's adopted
 310           on some machine other than Maple.
 311
 312 config EDAC_CPC925
 313         tristate "IBM CPC925 Memory Controller (PPC970FX)"
 314         depends on PPC64
 315         help
 316           Support for error detection and correction on the
 317           IBM CPC925 Bridge and Memory Controller, which is
 318           a companion chip to the PowerPC 970 family of
 319           processors.
 320
 321 config EDAC_TILE
 322         tristate "Tilera Memory Controller"
 323         depends on TILE
 324         default y
 325         help
 326           Support for error detection and correction on the
 327           Tilera memory controller.
 328
 329 config EDAC_HIGHBANK_MC
 330         tristate "Highbank Memory Controller"
 331         depends on ARCH_HIGHBANK
 332         help
 333           Support for error detection and correction on the
 334           Calxeda Highbank memory controller.
 335
 336 config EDAC_HIGHBANK_L2
 337         tristate "Highbank L2 Cache"
 338         depends on ARCH_HIGHBANK
 339         help
 340           Support for error detection and correction on the
 341           Calxeda Highbank memory controller.
 342
 343 config EDAC_OCTEON_PC
 344         tristate "Cavium Octeon Primary Caches"
 345         depends on CPU_CAVIUM_OCTEON
 346         help
 347           Support for error detection and correction on the primary caches of
 348           the cnMIPS cores of Cavium Octeon family SOCs.
 349
 350 config EDAC_OCTEON_L2C
 351         tristate "Cavium Octeon Secondary Caches (L2C)"
 352         depends on CAVIUM_OCTEON_SOC
 353         help
 354           Support for error detection and correction on the
 355           Cavium Octeon family of SOCs.
 356
 357 config EDAC_OCTEON_LMC
 358         tristate "Cavium Octeon DRAM Memory Controller (LMC)"
 359         depends on CAVIUM_OCTEON_SOC
 360         help
 361           Support for error detection and correction on the
 362           Cavium Octeon family of SOCs.
 363
 364 config EDAC_OCTEON_PCI
 365         tristate "Cavium Octeon PCI Controller"
 366         depends on PCI && CAVIUM_OCTEON_SOC
 367         help
 368           Support for error detection and correction on the
 369           Cavium Octeon family of SOCs.
 370
 371 config EDAC_THUNDERX
 372         tristate "Cavium ThunderX EDAC"
 373         depends on ARM64
 374         depends on PCI
 375         help
 376           Support for error detection and correction on the
 377           Cavium ThunderX memory controllers (LMC), Cache
 378           Coherent Processor Interconnect (CCPI) and L2 cache
 379           blocks (TAD, CBC, MCI).
 380
 381 config EDAC_ALTERA
 382         bool "Altera SOCFPGA ECC"
 383         depends on EDAC=y && ARCH_SOCFPGA
 384         help
 385           Support for error detection and correction on the
 386           Altera SOCs. This must be selected for SDRAM ECC.
 387           Note that the preloader must initialize the SDRAM
 388           before loading the kernel.
 389
 390 config EDAC_ALTERA_L2C
 391         bool "Altera L2 Cache ECC"
 392         depends on EDAC_ALTERA=y && CACHE_L2X0
 393         help
 394           Support for error detection and correction on the
 395           Altera L2 cache Memory for Altera SoCs. This option
 396           requires L2 cache.
 397
 398 config EDAC_ALTERA_OCRAM
 399         bool "Altera On-Chip RAM ECC"
 400         depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
 401         help
 402           Support for error detection and correction on the
 403           Altera On-Chip RAM Memory for Altera SoCs.
 404
 405 config EDAC_ALTERA_ETHERNET
 406         bool "Altera Ethernet FIFO ECC"
 407         depends on EDAC_ALTERA=y
 408         help
 409           Support for error detection and correction on the
 410           Altera Ethernet FIFO Memory for Altera SoCs.
 411
 412 config EDAC_ALTERA_NAND
 413         bool "Altera NAND FIFO ECC"
 414         depends on EDAC_ALTERA=y && MTD_NAND_DENALI
 415         help
 416           Support for error detection and correction on the
 417           Altera NAND FIFO Memory for Altera SoCs.
 418
 419 config EDAC_ALTERA_DMA
 420         bool "Altera DMA FIFO ECC"
 421         depends on EDAC_ALTERA=y && PL330_DMA=y
 422         help
 423           Support for error detection and correction on the
 424           Altera DMA FIFO Memory for Altera SoCs.
 425
 426 config EDAC_ALTERA_USB
 427         bool "Altera USB FIFO ECC"
 428         depends on EDAC_ALTERA=y && USB_DWC2
 429         help
 430           Support for error detection and correction on the
 431           Altera USB FIFO Memory for Altera SoCs.
 432
 433 config EDAC_ALTERA_QSPI
 434         bool "Altera QSPI FIFO ECC"
 435         depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
 436         help
 437           Support for error detection and correction on the
 438           Altera QSPI FIFO Memory for Altera SoCs.
 439
 440 config EDAC_ALTERA_SDMMC
 441         bool "Altera SDMMC FIFO ECC"
 442         depends on EDAC_ALTERA=y && MMC_DW
 443         help
 444           Support for error detection and correction on the
 445           Altera SDMMC FIFO Memory for Altera SoCs.
 446
 447 config EDAC_SYNOPSYS
 448         tristate "Synopsys DDR Memory Controller"
 449         depends on ARCH_ZYNQ
 450         help
 451           Support for error detection and correction on the Synopsys DDR
 452           memory controller.
 453
 454 config EDAC_XGENE
 455         tristate "APM X-Gene SoC"
 456         depends on (ARM64 || COMPILE_TEST)
 457         help
 458           Support for error detection and correction on the
 459           APM X-Gene family of SOCs.
 460
 461 endif # EDAC