drivers/edac/Kconfig

   1 #
   2 #       EDAC Kconfig
   3 #       Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
   4 #       Licensed and distributed under the GPL
   5 #
   6
   7 config EDAC_SUPPORT
   8         bool
   9
  10 menuconfig EDAC
  11         bool "EDAC (Error Detection And Correction) reporting"
  12         depends on HAS_IOMEM
  13         depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
  14         help
  15           EDAC is designed to report errors in the core system.
  16           These are low-level errors that are reported in the CPU or
  17           supporting chipset or other subsystems:
  18           memory errors, cache errors, PCI errors, thermal throttling, etc..
  19           If unsure, select 'Y'.
  20
  21           If this code is reporting problems on your system, please
  22           see the EDAC project web pages for more information at:
  23
  24           <http://bluesmoke.sourceforge.net/>
  25
  26           and:
  27
  28           <http://buttersideup.com/edacwiki>
  29
  30           There is also a mailing list for the EDAC project, which can
  31           be found via the sourceforge page.
  32
  33 if EDAC
  34
  35 config EDAC_LEGACY_SYSFS
  36         bool "EDAC legacy sysfs"
  37         default y
  38         help
  39           Enable the compatibility sysfs nodes.
  40           Use 'Y' if your edac utilities aren't ported to work with the newer
  41           structures.
  42
  43 config EDAC_DEBUG
  44         bool "Debugging"
  45         help
  46           This turns on debugging information for the entire EDAC subsystem.
  47           You do so by inserting edac_module with "edac_debug_level=x." Valid
  48           levels are 0-4 (from low to high) and by default it is set to 2.
  49           Usually you should select 'N' here.
  50
  51 config EDAC_DECODE_MCE
  52         tristate "Decode MCEs in human-readable form (only on AMD for now)"
  53         depends on CPU_SUP_AMD && X86_MCE_AMD
  54         default y
  55         ---help---
  56           Enable this option if you want to decode Machine Check Exceptions
  57           occurring on your machine in human-readable form.
  58
  59           You should definitely say Y here in case you want to decode MCEs
  60           which occur really early upon boot, before the module infrastructure
  61           has been initialized.
  62
  63 config EDAC_MCE_INJ
  64         tristate "Simple MCE injection interface over /sysfs"
  65         depends on EDAC_DECODE_MCE
  66         default n
  67         help
  68           This is a simple interface to inject MCEs over /sysfs and test
  69           the MCE decoding code in EDAC.
  70
  71           This is currently AMD-only.
  72
  73 config EDAC_MM_EDAC
  74         tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  75         help
  76           Some systems are able to detect and correct errors in main
  77           memory.  EDAC can report statistics on memory error
  78           detection and correction (EDAC - or commonly referred to ECC
  79           errors).  EDAC will also try to decode where these errors
  80           occurred so that a particular failing memory module can be
  81           replaced.  If unsure, select 'Y'.
  82
  83 config EDAC_GHES
  84         bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
  85         depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
  86         default y
  87         help
  88           Not all machines support hardware-driven error report. Some of those
  89           provide a BIOS-driven error report mechanism via ACPI, using the
  90           APEI/GHES driver. By enabling this option, the error reports provided
  91           by GHES are sent to userspace via the EDAC API.
  92
  93           When this option is enabled, it will disable the hardware-driven
  94           mechanisms, if a GHES BIOS is detected, entering into the
  95           "Firmware First" mode.
  96
  97           It should be noticed that keeping both GHES and a hardware-driven
  98           error mechanism won't work well, as BIOS will race with OS, while
  99           reading the error registers. So, if you want to not use "Firmware
 100           first" GHES error mechanism, you should disable GHES either at
 101           compilation time or by passing "ghes.disable=1" Kernel parameter
 102           at boot time.
 103
 104           In doubt, say 'Y'.
 105
 106 config EDAC_AMD64
 107         tristate "AMD64 (Opteron, Athlon64) K8, F10h"
 108         depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
 109         help
 110           Support for error detection and correction of DRAM ECC errors on
 111           the AMD64 families of memory controllers (K8 and F10h)
 112
 113 config EDAC_AMD64_ERROR_INJECTION
 114         bool "Sysfs HW Error injection facilities"
 115         depends on EDAC_AMD64
 116         help
 117           Recent Opterons (Family 10h and later) provide for Memory Error
 118           Injection into the ECC detection circuits. The amd64_edac module
 119           allows the operator/user to inject Uncorrectable and Correctable
 120           errors into DRAM.
 121
 122           When enabled, in each of the respective memory controller directories
 123           (/sys/devices/system/edac/mc/mcX), there are 3 input files:
 124
 125           - inject_section (0..3, 16-byte section of 64-byte cacheline),
 126           - inject_word (0..8, 16-bit word of 16-byte section),
 127           - inject_ecc_vector (hex ecc vector: select bits of inject word)
 128
 129           In addition, there are two control files, inject_read and inject_write,
 130           which trigger the DRAM ECC Read and Write respectively.
 131
 132 config EDAC_AMD76X
 133         tristate "AMD 76x (760, 762, 768)"
 134         depends on EDAC_MM_EDAC && PCI && X86_32
 135         help
 136           Support for error detection and correction on the AMD 76x
 137           series of chipsets used with the Athlon processor.
 138
 139 config EDAC_E7XXX
 140         tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
 141         depends on EDAC_MM_EDAC && PCI && X86_32
 142         help
 143           Support for error detection and correction on the Intel
 144           E7205, E7500, E7501 and E7505 server chipsets.
 145
 146 config EDAC_E752X
 147         tristate "Intel e752x (e7520, e7525, e7320) and 3100"
 148         depends on EDAC_MM_EDAC && PCI && X86
 149         help
 150           Support for error detection and correction on the Intel
 151           E7520, E7525, E7320 server chipsets.
 152
 153 config EDAC_I82443BXGX
 154         tristate "Intel 82443BX/GX (440BX/GX)"
 155         depends on EDAC_MM_EDAC && PCI && X86_32
 156         depends on BROKEN
 157         help
 158           Support for error detection and correction on the Intel
 159           82443BX/GX memory controllers (440BX/GX chipsets).
 160
 161 config EDAC_I82875P
 162         tristate "Intel 82875p (D82875P, E7210)"
 163         depends on EDAC_MM_EDAC && PCI && X86_32
 164         help
 165           Support for error detection and correction on the Intel
 166           DP82785P and E7210 server chipsets.
 167
 168 config EDAC_I82975X
 169         tristate "Intel 82975x (D82975x)"
 170         depends on EDAC_MM_EDAC && PCI && X86
 171         help
 172           Support for error detection and correction on the Intel
 173           DP82975x server chipsets.
 174
 175 config EDAC_I3000
 176         tristate "Intel 3000/3010"
 177         depends on EDAC_MM_EDAC && PCI && X86
 178         help
 179           Support for error detection and correction on the Intel
 180           3000 and 3010 server chipsets.
 181
 182 config EDAC_I3200
 183         tristate "Intel 3200"
 184         depends on EDAC_MM_EDAC && PCI && X86
 185         help
 186           Support for error detection and correction on the Intel
 187           3200 and 3210 server chipsets.
 188
 189 config EDAC_X38
 190         tristate "Intel X38"
 191         depends on EDAC_MM_EDAC && PCI && X86
 192         help
 193           Support for error detection and correction on the Intel
 194           X38 server chipsets.
 195
 196 config EDAC_I5400
 197         tristate "Intel 5400 (Seaburg) chipsets"
 198         depends on EDAC_MM_EDAC && PCI && X86
 199         help
 200           Support for error detection and correction the Intel
 201           i5400 MCH chipset (Seaburg).
 202
 203 config EDAC_I7CORE
 204         tristate "Intel i7 Core (Nehalem) processors"
 205         depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
 206         help
 207           Support for error detection and correction the Intel
 208           i7 Core (Nehalem) Integrated Memory Controller that exists on
 209           newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
 210           and Xeon 55xx processors.
 211
 212 config EDAC_I82860
 213         tristate "Intel 82860"
 214         depends on EDAC_MM_EDAC && PCI && X86_32
 215         help
 216           Support for error detection and correction on the Intel
 217           82860 chipset.
 218
 219 config EDAC_R82600
 220         tristate "Radisys 82600 embedded chipset"
 221         depends on EDAC_MM_EDAC && PCI && X86_32
 222         help
 223           Support for error detection and correction on the Radisys
 224           82600 embedded chipset.
 225
 226 config EDAC_I5000
 227         tristate "Intel Greencreek/Blackford chipset"
 228         depends on EDAC_MM_EDAC && X86 && PCI
 229         help
 230           Support for error detection and correction the Intel
 231           Greekcreek/Blackford chipsets.
 232
 233 config EDAC_I5100
 234         tristate "Intel San Clemente MCH"
 235         depends on EDAC_MM_EDAC && X86 && PCI
 236         help
 237           Support for error detection and correction the Intel
 238           San Clemente MCH.
 239
 240 config EDAC_I7300
 241         tristate "Intel Clarksboro MCH"
 242         depends on EDAC_MM_EDAC && X86 && PCI
 243         help
 244           Support for error detection and correction the Intel
 245           Clarksboro MCH (Intel 7300 chipset).
 246
 247 config EDAC_SBRIDGE
 248         tristate "Intel Sandy-Bridge Integrated MC"
 249         depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
 250         depends on PCI_MMCONFIG
 251         help
 252           Support for error detection and correction the Intel
 253           Sandy Bridge Integrated Memory Controller.
 254
 255 config EDAC_MPC85XX
 256         tristate "Freescale MPC83xx / MPC85xx"
 257         depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
 258         help
 259           Support for error detection and correction on the Freescale
 260           MPC8349, MPC8560, MPC8540, MPC8548
 261
 262 config EDAC_MV64X60
 263         tristate "Marvell MV64x60"
 264         depends on EDAC_MM_EDAC && MV64X60
 265         help
 266           Support for error detection and correction on the Marvell
 267           MV64360 and MV64460 chipsets.
 268
 269 config EDAC_PASEMI
 270         tristate "PA Semi PWRficient"
 271         depends on EDAC_MM_EDAC && PCI
 272         depends on PPC_PASEMI
 273         help
 274           Support for error detection and correction on PA Semi
 275           PWRficient.
 276
 277 config EDAC_CELL
 278         tristate "Cell Broadband Engine memory controller"
 279         depends on EDAC_MM_EDAC && PPC_CELL_COMMON
 280         help
 281           Support for error detection and correction on the
 282           Cell Broadband Engine internal memory controller
 283           on platform without a hypervisor
 284
 285 config EDAC_PPC4XX
 286         tristate "PPC4xx IBM DDR2 Memory Controller"
 287         depends on EDAC_MM_EDAC && 4xx
 288         help
 289           This enables support for EDAC on the ECC memory used
 290           with the IBM DDR2 memory controller found in various
 291           PowerPC 4xx embedded processors such as the 405EX[r],
 292           440SP, 440SPe, 460EX, 460GT and 460SX.
 293
 294 config EDAC_AMD8131
 295         tristate "AMD8131 HyperTransport PCI-X Tunnel"
 296         depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
 297         help
 298           Support for error detection and correction on the
 299           AMD8131 HyperTransport PCI-X Tunnel chip.
 300           Note, add more Kconfig dependency if it's adopted
 301           on some machine other than Maple.
 302
 303 config EDAC_AMD8111
 304         tristate "AMD8111 HyperTransport I/O Hub"
 305         depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
 306         help
 307           Support for error detection and correction on the
 308           AMD8111 HyperTransport I/O Hub chip.
 309           Note, add more Kconfig dependency if it's adopted
 310           on some machine other than Maple.
 311
 312 config EDAC_CPC925
 313         tristate "IBM CPC925 Memory Controller (PPC970FX)"
 314         depends on EDAC_MM_EDAC && PPC64
 315         help
 316           Support for error detection and correction on the
 317           IBM CPC925 Bridge and Memory Controller, which is
 318           a companion chip to the PowerPC 970 family of
 319           processors.
 320
 321 config EDAC_TILE
 322         tristate "Tilera Memory Controller"
 323         depends on EDAC_MM_EDAC && TILE
 324         default y
 325         help
 326           Support for error detection and correction on the
 327           Tilera memory controller.
 328
 329 config EDAC_HIGHBANK_MC
 330         tristate "Highbank Memory Controller"
 331         depends on EDAC_MM_EDAC && ARCH_HIGHBANK
 332         help
 333           Support for error detection and correction on the
 334           Calxeda Highbank memory controller.
 335
 336 config EDAC_HIGHBANK_L2
 337         tristate "Highbank L2 Cache"
 338         depends on EDAC_MM_EDAC && ARCH_HIGHBANK
 339         help
 340           Support for error detection and correction on the
 341           Calxeda Highbank memory controller.
 342
 343 config EDAC_OCTEON_PC
 344         tristate "Cavium Octeon Primary Caches"
 345         depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 346         help
 347           Support for error detection and correction on the primary caches of
 348           the cnMIPS cores of Cavium Octeon family SOCs.
 349
 350 config EDAC_OCTEON_L2C
 351         tristate "Cavium Octeon Secondary Caches (L2C)"
 352         depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 353         help
 354           Support for error detection and correction on the
 355           Cavium Octeon family of SOCs.
 356
 357 config EDAC_OCTEON_LMC
 358         tristate "Cavium Octeon DRAM Memory Controller (LMC)"
 359         depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
 360         help
 361           Support for error detection and correction on the
 362           Cavium Octeon family of SOCs.
 363
 364 config EDAC_OCTEON_PCI
 365         tristate "Cavium Octeon PCI Controller"
 366         depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
 367         help
 368           Support for error detection and correction on the
 369           Cavium Octeon family of SOCs.
 370
 371 endif # EDAC