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1 #
2 # EDAC Kconfig
3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
5 #
6
7 menuconfig EDAC
8 bool "EDAC (Error Detection And Correction) reporting"
9 depends on HAS_IOMEM
10 depends on X86 || PPC || TILE
11 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
17
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
30 if EDAC
31
32 comment "Reporting subsystems"
33
34 config EDAC_DEBUG
35 bool "Debugging"
36 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
42 config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
45 default y
46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions
48 occurring on your machine in human-readable form.
49
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
52 has been initialized.
53
54 config EDAC_MCE_INJ
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
57 default n
58 help
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
61
62 This is currently AMD-only.
63
64 config EDAC_MM_EDAC
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
66 help
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
73
74 config EDAC_MCE
75 bool
76
77 config EDAC_AMD64
78 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
79 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
80 help
81 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families of memory controllers (K8 and F10h)
83
84 config EDAC_AMD64_ERROR_INJECTION
85 bool "Sysfs HW Error injection facilities"
86 depends on EDAC_AMD64
87 help
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
91 errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103 config EDAC_AMD76X
104 tristate "AMD 76x (760, 762, 768)"
105 depends on EDAC_MM_EDAC && PCI && X86_32
106 help
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
109
110 config EDAC_E7XXX
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
112 depends on EDAC_MM_EDAC && PCI && X86_32
113 help
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
116
117 config EDAC_E752X
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
119 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
120 help
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
123
124 config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on EDAC_MM_EDAC && PCI && X86_32
127 depends on BROKEN
128 help
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
131
132 config EDAC_I82875P
133 tristate "Intel 82875p (D82875P, E7210)"
134 depends on EDAC_MM_EDAC && PCI && X86_32
135 help
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
138
139 config EDAC_I82975X
140 tristate "Intel 82975x (D82975x)"
141 depends on EDAC_MM_EDAC && PCI && X86
142 help
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
145
146 config EDAC_I3000
147 tristate "Intel 3000/3010"
148 depends on EDAC_MM_EDAC && PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
152
153 config EDAC_I3200
154 tristate "Intel 3200"
155 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
156 help
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
159
160 config EDAC_X38
161 tristate "Intel X38"
162 depends on EDAC_MM_EDAC && PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 X38 server chipsets.
166
167 config EDAC_I5400
168 tristate "Intel 5400 (Seaburg) chipsets"
169 depends on EDAC_MM_EDAC && PCI && X86
170 help
171 Support for error detection and correction the Intel
172 i5400 MCH chipset (Seaburg).
173
174 config EDAC_I7CORE
175 tristate "Intel i7 Core (Nehalem) processors"
176 depends on EDAC_MM_EDAC && PCI && X86
177 select EDAC_MCE
178 help
179 Support for error detection and correction the Intel
180 i7 Core (Nehalem) Integrated Memory Controller that exists on
181 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
182 and Xeon 55xx processors.
183
184 config EDAC_I82860
185 tristate "Intel 82860"
186 depends on EDAC_MM_EDAC && PCI && X86_32
187 help
188 Support for error detection and correction on the Intel
189 82860 chipset.
190
191 config EDAC_R82600
192 tristate "Radisys 82600 embedded chipset"
193 depends on EDAC_MM_EDAC && PCI && X86_32
194 help
195 Support for error detection and correction on the Radisys
196 82600 embedded chipset.
197
198 config EDAC_I5000
199 tristate "Intel Greencreek/Blackford chipset"
200 depends on EDAC_MM_EDAC && X86 && PCI
201 help
202 Support for error detection and correction the Intel
203 Greekcreek/Blackford chipsets.
204
205 config EDAC_I5100
206 tristate "Intel San Clemente MCH"
207 depends on EDAC_MM_EDAC && X86 && PCI
208 help
209 Support for error detection and correction the Intel
210 San Clemente MCH.
211
212 config EDAC_I7300
213 tristate "Intel Clarksboro MCH"
214 depends on EDAC_MM_EDAC && X86 && PCI
215 help
216 Support for error detection and correction the Intel
217 Clarksboro MCH (Intel 7300 chipset).
218
219 config EDAC_MPC85XX
220 tristate "Freescale MPC83xx / MPC85xx"
221 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
222 help
223 Support for error detection and correction on the Freescale
224 MPC8349, MPC8560, MPC8540, MPC8548
225
226 config EDAC_MV64X60
227 tristate "Marvell MV64x60"
228 depends on EDAC_MM_EDAC && MV64X60
229 help
230 Support for error detection and correction on the Marvell
231 MV64360 and MV64460 chipsets.
232
233 config EDAC_PASEMI
234 tristate "PA Semi PWRficient"
235 depends on EDAC_MM_EDAC && PCI
236 depends on PPC_PASEMI
237 help
238 Support for error detection and correction on PA Semi
239 PWRficient.
240
241 config EDAC_CELL
242 tristate "Cell Broadband Engine memory controller"
243 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
244 help
245 Support for error detection and correction on the
246 Cell Broadband Engine internal memory controller
247 on platform without a hypervisor
248
249 config EDAC_PPC4XX
250 tristate "PPC4xx IBM DDR2 Memory Controller"
251 depends on EDAC_MM_EDAC && 4xx
252 help
253 This enables support for EDAC on the ECC memory used
254 with the IBM DDR2 memory controller found in various
255 PowerPC 4xx embedded processors such as the 405EX[r],
256 440SP, 440SPe, 460EX, 460GT and 460SX.
257
258 config EDAC_AMD8131
259 tristate "AMD8131 HyperTransport PCI-X Tunnel"
260 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
261 help
262 Support for error detection and correction on the
263 AMD8131 HyperTransport PCI-X Tunnel chip.
264 Note, add more Kconfig dependency if it's adopted
265 on some machine other than Maple.
266
267 config EDAC_AMD8111
268 tristate "AMD8111 HyperTransport I/O Hub"
269 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
270 help
271 Support for error detection and correction on the
272 AMD8111 HyperTransport I/O Hub chip.
273 Note, add more Kconfig dependency if it's adopted
274 on some machine other than Maple.
275
276 config EDAC_CPC925
277 tristate "IBM CPC925 Memory Controller (PPC970FX)"
278 depends on EDAC_MM_EDAC && PPC64
279 help
280 Support for error detection and correction on the
281 IBM CPC925 Bridge and Memory Controller, which is
282 a companion chip to the PowerPC 970 family of
283 processors.
284
285 config EDAC_TILE
286 tristate "Tilera Memory Controller"
287 depends on EDAC_MM_EDAC && TILE
288 default y
289 help
290 Support for error detection and correction on the
291 Tilera memory controller.
292
293 endif # EDAC